tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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drm/amdgpu: Add lsdma v7_0_0 ip headers (v3)

v1: Add lsdma v7_0_0 register offset and shift masks
header files (Hawking)
v2: Update lsdma v7_0_0 register offset and shift masks
header files for RE2.5 (Likun)
v3: Clean up lsdma v7_0_0 ip headers (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher f902bf5d f579c06b

+1799
+388
drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_0_0_offset.h
··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _lsdma_7_0_0_OFFSET_HEADER 24 + #define _lsdma_7_0_0_OFFSET_HEADER 25 + 26 + 27 + 28 + // addressBlock: lsdma0_lsdma0dec 29 + // base address: 0x45000 30 + #define regLSDMA_UCODE_ADDR 0x0000 31 + #define regLSDMA_UCODE_ADDR_BASE_IDX 0 32 + #define regLSDMA_UCODE_DATA 0x0001 33 + #define regLSDMA_UCODE_DATA_BASE_IDX 0 34 + #define regLSDMA_ERROR_INJECT_CNTL 0x0004 35 + #define regLSDMA_ERROR_INJECT_CNTL_BASE_IDX 0 36 + #define regLSDMA_ERROR_INJECT_SELECT 0x0005 37 + #define regLSDMA_ERROR_INJECT_SELECT_BASE_IDX 0 38 + #define regLSDMA_CONTEXT_GROUP_BOUNDARY 0x001f 39 + #define regLSDMA_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 40 + #define regLSDMA_RB_RPTR_FETCH_HI 0x0020 41 + #define regLSDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 42 + #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 43 + #define regLSDMA_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 44 + #define regLSDMA_RB_RPTR_FETCH 0x0022 45 + #define regLSDMA_RB_RPTR_FETCH_BASE_IDX 0 46 + #define regLSDMA_IB_OFFSET_FETCH 0x0023 47 + #define regLSDMA_IB_OFFSET_FETCH_BASE_IDX 0 48 + #define regLSDMA_PROGRAM 0x0024 49 + #define regLSDMA_PROGRAM_BASE_IDX 0 50 + #define regLSDMA_STATUS_REG 0x0025 51 + #define regLSDMA_STATUS_REG_BASE_IDX 0 52 + #define regLSDMA_STATUS1_REG 0x0026 53 + #define regLSDMA_STATUS1_REG_BASE_IDX 0 54 + #define regLSDMA_RD_BURST_CNTL 0x0027 55 + #define regLSDMA_RD_BURST_CNTL_BASE_IDX 0 56 + #define regLSDMA_HBM_PAGE_CONFIG 0x0028 57 + #define regLSDMA_HBM_PAGE_CONFIG_BASE_IDX 0 58 + #define regLSDMA_UCODE_CHECKSUM 0x0029 59 + #define regLSDMA_UCODE_CHECKSUM_BASE_IDX 0 60 + #define regLSDMA_FREEZE 0x002b 61 + #define regLSDMA_FREEZE_BASE_IDX 0 62 + #define regLSDMA_DCC_CNTL 0x002d 63 + #define regLSDMA_DCC_CNTL_BASE_IDX 0 64 + #define regLSDMA_POWER_GATING 0x002e 65 + #define regLSDMA_POWER_GATING_BASE_IDX 0 66 + #define regLSDMA_PGFSM_CONFIG 0x002f 67 + #define regLSDMA_PGFSM_CONFIG_BASE_IDX 0 68 + #define regLSDMA_PGFSM_WRITE 0x0030 69 + #define regLSDMA_PGFSM_WRITE_BASE_IDX 0 70 + #define regLSDMA_PGFSM_READ 0x0031 71 + #define regLSDMA_PGFSM_READ_BASE_IDX 0 72 + #define regLSDMA_BA_THRESHOLD 0x0033 73 + #define regLSDMA_BA_THRESHOLD_BASE_IDX 0 74 + #define regLSDMA_ID 0x0034 75 + #define regLSDMA_ID_BASE_IDX 0 76 + #define regLSDMA_VERSION 0x0035 77 + #define regLSDMA_VERSION_BASE_IDX 0 78 + #define regLSDMA_EDC_COUNTER 0x0036 79 + #define regLSDMA_EDC_COUNTER_BASE_IDX 0 80 + #define regLSDMA_EDC_COUNTER2 0x0037 81 + #define regLSDMA_EDC_COUNTER2_BASE_IDX 0 82 + #define regLSDMA_STATUS2_REG 0x0038 83 + #define regLSDMA_STATUS2_REG_BASE_IDX 0 84 + #define regLSDMA_ATOMIC_CNTL 0x0039 85 + #define regLSDMA_ATOMIC_CNTL_BASE_IDX 0 86 + #define regLSDMA_ATOMIC_PREOP_LO 0x003a 87 + #define regLSDMA_ATOMIC_PREOP_LO_BASE_IDX 0 88 + #define regLSDMA_ATOMIC_PREOP_HI 0x003b 89 + #define regLSDMA_ATOMIC_PREOP_HI_BASE_IDX 0 90 + #define regLSDMA_UTCL1_CNTL 0x003c 91 + #define regLSDMA_UTCL1_CNTL_BASE_IDX 0 92 + #define regLSDMA_UTCL1_WATERMK 0x003d 93 + #define regLSDMA_UTCL1_WATERMK_BASE_IDX 0 94 + #define regLSDMA_UTCL1_RD_STATUS 0x003e 95 + #define regLSDMA_UTCL1_RD_STATUS_BASE_IDX 0 96 + #define regLSDMA_UTCL1_WR_STATUS 0x003f 97 + #define regLSDMA_UTCL1_WR_STATUS_BASE_IDX 0 98 + #define regLSDMA_UTCL1_INV0 0x0040 99 + #define regLSDMA_UTCL1_INV0_BASE_IDX 0 100 + #define regLSDMA_UTCL1_INV1 0x0041 101 + #define regLSDMA_UTCL1_INV1_BASE_IDX 0 102 + #define regLSDMA_UTCL1_INV2 0x0042 103 + #define regLSDMA_UTCL1_INV2_BASE_IDX 0 104 + #define regLSDMA_UTCL1_RD_XNACK0 0x0043 105 + #define regLSDMA_UTCL1_RD_XNACK0_BASE_IDX 0 106 + #define regLSDMA_UTCL1_RD_XNACK1 0x0044 107 + #define regLSDMA_UTCL1_RD_XNACK1_BASE_IDX 0 108 + #define regLSDMA_UTCL1_WR_XNACK0 0x0045 109 + #define regLSDMA_UTCL1_WR_XNACK0_BASE_IDX 0 110 + #define regLSDMA_UTCL1_WR_XNACK1 0x0046 111 + #define regLSDMA_UTCL1_WR_XNACK1_BASE_IDX 0 112 + #define regLSDMA_UTCL1_TIMEOUT 0x0047 113 + #define regLSDMA_UTCL1_TIMEOUT_BASE_IDX 0 114 + #define regLSDMA_UTCL1_PAGE 0x0048 115 + #define regLSDMA_UTCL1_PAGE_BASE_IDX 0 116 + #define regLSDMA_RELAX_ORDERING_LUT 0x004a 117 + #define regLSDMA_RELAX_ORDERING_LUT_BASE_IDX 0 118 + #define regLSDMA_CHICKEN_BITS_2 0x004b 119 + #define regLSDMA_CHICKEN_BITS_2_BASE_IDX 0 120 + #define regLSDMA_STATUS3_REG 0x004c 121 + #define regLSDMA_STATUS3_REG_BASE_IDX 0 122 + #define regLSDMA_PHYSICAL_ADDR_LO 0x004d 123 + #define regLSDMA_PHYSICAL_ADDR_LO_BASE_IDX 0 124 + #define regLSDMA_PHYSICAL_ADDR_HI 0x004e 125 + #define regLSDMA_PHYSICAL_ADDR_HI_BASE_IDX 0 126 + #define regLSDMA_ECC_CNTL 0x004f 127 + #define regLSDMA_ECC_CNTL_BASE_IDX 0 128 + #define regLSDMA_ERROR_LOG 0x0050 129 + #define regLSDMA_ERROR_LOG_BASE_IDX 0 130 + #define regLSDMA_PUB_DUMMY0 0x0051 131 + #define regLSDMA_PUB_DUMMY0_BASE_IDX 0 132 + #define regLSDMA_PUB_DUMMY1 0x0052 133 + #define regLSDMA_PUB_DUMMY1_BASE_IDX 0 134 + #define regLSDMA_PUB_DUMMY2 0x0053 135 + #define regLSDMA_PUB_DUMMY2_BASE_IDX 0 136 + #define regLSDMA_PUB_DUMMY3 0x0054 137 + #define regLSDMA_PUB_DUMMY3_BASE_IDX 0 138 + #define regLSDMA_F32_COUNTER 0x0055 139 + #define regLSDMA_F32_COUNTER_BASE_IDX 0 140 + #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG 0x0057 141 + #define regLSDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 0 142 + #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG 0x0058 143 + #define regLSDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 0 144 + #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x0059 145 + #define regLSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 146 + #define regLSDMA_PERFCNT_MISC_CNTL 0x005a 147 + #define regLSDMA_PERFCNT_MISC_CNTL_BASE_IDX 0 148 + #define regLSDMA_PERFCNT_PERFCOUNTER_LO 0x005b 149 + #define regLSDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 0 150 + #define regLSDMA_PERFCNT_PERFCOUNTER_HI 0x005c 151 + #define regLSDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 0 152 + #define regLSDMA_CRD_CNTL 0x005d 153 + #define regLSDMA_CRD_CNTL_BASE_IDX 0 154 + #define regLSDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 155 + #define regLSDMA_ULV_CNTL 0x005f 156 + #define regLSDMA_ULV_CNTL_BASE_IDX 0 157 + #define regLSDMA_EA_DBIT_ADDR_DATA 0x0060 158 + #define regLSDMA_EA_DBIT_ADDR_DATA_BASE_IDX 0 159 + #define regLSDMA_EA_DBIT_ADDR_INDEX 0x0061 160 + #define regLSDMA_EA_DBIT_ADDR_INDEX_BASE_IDX 0 161 + #define regLSDMA_STATUS4_REG 0x0063 162 + #define regLSDMA_STATUS4_REG_BASE_IDX 0 163 + #define regLSDMA_CE_CTRL 0x0066 164 + #define regLSDMA_CE_CTRL_BASE_IDX 0 165 + #define regLSDMA_EXCEPTION_STATUS 0x0067 166 + #define regLSDMA_EXCEPTION_STATUS_BASE_IDX 0 167 + #define regLSDMA_INT_CNTL 0x0069 168 + #define regLSDMA_INT_CNTL_BASE_IDX 0 169 + #define regLSDMA_MEM_POWER_CTRL 0x006a 170 + #define regLSDMA_MEM_POWER_CTRL_BASE_IDX 0 171 + #define regLSDMA_CLK_CTRL 0x006b 172 + #define regLSDMA_CLK_CTRL_BASE_IDX 0 173 + #define regLSDMA_CNTL 0x006c 174 + #define regLSDMA_CNTL_BASE_IDX 0 175 + #define regLSDMA_CHICKEN_BITS 0x006d 176 + #define regLSDMA_CHICKEN_BITS_BASE_IDX 0 177 + #define regLSDMA_PIO_SRC_ADDR_LO 0x0070 178 + #define regLSDMA_PIO_SRC_ADDR_LO_BASE_IDX 0 179 + #define regLSDMA_PIO_SRC_ADDR_HI 0x0071 180 + #define regLSDMA_PIO_SRC_ADDR_HI_BASE_IDX 0 181 + #define regLSDMA_PIO_DST_ADDR_LO 0x0072 182 + #define regLSDMA_PIO_DST_ADDR_LO_BASE_IDX 0 183 + #define regLSDMA_PIO_DST_ADDR_HI 0x0073 184 + #define regLSDMA_PIO_DST_ADDR_HI_BASE_IDX 0 185 + #define regLSDMA_PIO_COMMAND 0x0074 186 + #define regLSDMA_PIO_COMMAND_BASE_IDX 0 187 + #define regLSDMA_PIO_CONSTFILL_DATA 0x0075 188 + #define regLSDMA_PIO_CONSTFILL_DATA_BASE_IDX 0 189 + #define regLSDMA_PIO_CONTROL 0x0076 190 + #define regLSDMA_PIO_CONTROL_BASE_IDX 0 191 + #define regLSDMA_PIO_STATUS 0x007a 192 + #define regLSDMA_PIO_STATUS_BASE_IDX 0 193 + #define regLSDMA_PF_PIO_STATUS 0x007b 194 + #define regLSDMA_PF_PIO_STATUS_BASE_IDX 0 195 + #define regLSDMA_QUEUE0_RB_CNTL 0x0080 196 + #define regLSDMA_QUEUE0_RB_CNTL_BASE_IDX 0 197 + #define regLSDMA_QUEUE0_RB_BASE 0x0081 198 + #define regLSDMA_QUEUE0_RB_BASE_BASE_IDX 0 199 + #define regLSDMA_QUEUE0_RB_BASE_HI 0x0082 200 + #define regLSDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 201 + #define regLSDMA_QUEUE0_RB_RPTR 0x0083 202 + #define regLSDMA_QUEUE0_RB_RPTR_BASE_IDX 0 203 + #define regLSDMA_QUEUE0_RB_RPTR_HI 0x0084 204 + #define regLSDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 205 + #define regLSDMA_QUEUE0_RB_WPTR 0x0085 206 + #define regLSDMA_QUEUE0_RB_WPTR_BASE_IDX 0 207 + #define regLSDMA_QUEUE0_RB_WPTR_HI 0x0086 208 + #define regLSDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 209 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL 0x0087 210 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_CNTL_BASE_IDX 0 211 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0088 212 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 213 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x0089 214 + #define regLSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 215 + #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI 0x008a 216 + #define regLSDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 217 + #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO 0x008b 218 + #define regLSDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 219 + #define regLSDMA_QUEUE0_IB_CNTL 0x008c 220 + #define regLSDMA_QUEUE0_IB_CNTL_BASE_IDX 0 221 + #define regLSDMA_QUEUE0_IB_RPTR 0x008d 222 + #define regLSDMA_QUEUE0_IB_RPTR_BASE_IDX 0 223 + #define regLSDMA_QUEUE0_IB_OFFSET 0x008e 224 + #define regLSDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 225 + #define regLSDMA_QUEUE0_IB_BASE_LO 0x008f 226 + #define regLSDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 227 + #define regLSDMA_QUEUE0_IB_BASE_HI 0x0090 228 + #define regLSDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 229 + #define regLSDMA_QUEUE0_IB_SIZE 0x0091 230 + #define regLSDMA_QUEUE0_IB_SIZE_BASE_IDX 0 231 + #define regLSDMA_QUEUE0_SKIP_CNTL 0x0092 232 + #define regLSDMA_QUEUE0_SKIP_CNTL_BASE_IDX 0 233 + #define regLSDMA_QUEUE0_CSA_ADDR_LO 0x0093 234 + #define regLSDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 235 + #define regLSDMA_QUEUE0_CSA_ADDR_HI 0x0094 236 + #define regLSDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 237 + #define regLSDMA_QUEUE0_RB_AQL_CNTL 0x0095 238 + #define regLSDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 239 + #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE 0x0096 240 + #define regLSDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 241 + #define regLSDMA_QUEUE0_CNTL 0x0097 242 + #define regLSDMA_QUEUE0_CNTL_BASE_IDX 0 243 + #define regLSDMA_QUEUE0_RB_PREEMPT 0x0098 244 + #define regLSDMA_QUEUE0_RB_PREEMPT_BASE_IDX 0 245 + #define regLSDMA_QUEUE0_IB_SUB_REMAIN 0x0099 246 + #define regLSDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 247 + #define regLSDMA_QUEUE0_PREEMPT 0x009a 248 + #define regLSDMA_QUEUE0_PREEMPT_BASE_IDX 0 249 + #define regLSDMA_QUEUE0_CONTEXT_STATUS 0x009b 250 + #define regLSDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 251 + #define regLSDMA_QUEUE0_STATUS 0x009c 252 + #define regLSDMA_QUEUE0_STATUS_BASE_IDX 0 253 + #define regLSDMA_QUEUE0_DOORBELL 0x009d 254 + #define regLSDMA_QUEUE0_DOORBELL_BASE_IDX 0 255 + #define regLSDMA_QUEUE0_DOORBELL_OFFSET 0x009e 256 + #define regLSDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 257 + #define regLSDMA_QUEUE0_DOORBELL_LOG 0x009f 258 + #define regLSDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 259 + #define regLSDMA_QUEUE0_WATERMARK 0x00a0 260 + #define regLSDMA_QUEUE0_WATERMARK_BASE_IDX 0 261 + #define regLSDMA_QUEUE0_DUMMY0 0x00a1 262 + #define regLSDMA_QUEUE0_DUMMY0_BASE_IDX 0 263 + #define regLSDMA_QUEUE0_DUMMY1 0x00a2 264 + #define regLSDMA_QUEUE0_DUMMY1_BASE_IDX 0 265 + #define regLSDMA_QUEUE0_DUMMY2 0x00a3 266 + #define regLSDMA_QUEUE0_DUMMY2_BASE_IDX 0 267 + #define regLSDMA_QUEUE0_MIDCMD_DATA0 0x00c0 268 + #define regLSDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 269 + #define regLSDMA_QUEUE0_MIDCMD_DATA1 0x00c1 270 + #define regLSDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 271 + #define regLSDMA_QUEUE0_MIDCMD_DATA2 0x00c2 272 + #define regLSDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 273 + #define regLSDMA_QUEUE0_MIDCMD_DATA3 0x00c3 274 + #define regLSDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 275 + #define regLSDMA_QUEUE0_MIDCMD_DATA4 0x00c4 276 + #define regLSDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 277 + #define regLSDMA_QUEUE0_MIDCMD_DATA5 0x00c5 278 + #define regLSDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 279 + #define regLSDMA_QUEUE0_MIDCMD_DATA6 0x00c6 280 + #define regLSDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 281 + #define regLSDMA_QUEUE0_MIDCMD_DATA7 0x00c7 282 + #define regLSDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 283 + #define regLSDMA_QUEUE0_MIDCMD_DATA8 0x00c8 284 + #define regLSDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 285 + #define regLSDMA_QUEUE0_MIDCMD_DATA9 0x00c9 286 + #define regLSDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 287 + #define regLSDMA_QUEUE0_MIDCMD_DATA10 0x00ca 288 + #define regLSDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 289 + #define regLSDMA_QUEUE0_MIDCMD_CNTL 0x00cb 290 + #define regLSDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 291 + #define regLSDMA_QUEUE1_RB_CNTL 0x00d8 292 + #define regLSDMA_QUEUE1_RB_CNTL_BASE_IDX 0 293 + #define regLSDMA_QUEUE1_RB_BASE 0x00d9 294 + #define regLSDMA_QUEUE1_RB_BASE_BASE_IDX 0 295 + #define regLSDMA_QUEUE1_RB_BASE_HI 0x00da 296 + #define regLSDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 297 + #define regLSDMA_QUEUE1_RB_RPTR 0x00db 298 + #define regLSDMA_QUEUE1_RB_RPTR_BASE_IDX 0 299 + #define regLSDMA_QUEUE1_RB_RPTR_HI 0x00dc 300 + #define regLSDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 301 + #define regLSDMA_QUEUE1_RB_WPTR 0x00dd 302 + #define regLSDMA_QUEUE1_RB_WPTR_BASE_IDX 0 303 + #define regLSDMA_QUEUE1_RB_WPTR_HI 0x00de 304 + #define regLSDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 305 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL 0x00df 306 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_CNTL_BASE_IDX 0 307 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x00e0 308 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 309 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x00e1 310 + #define regLSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 311 + #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI 0x00e2 312 + #define regLSDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 313 + #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO 0x00e3 314 + #define regLSDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 315 + #define regLSDMA_QUEUE1_IB_CNTL 0x00e4 316 + #define regLSDMA_QUEUE1_IB_CNTL_BASE_IDX 0 317 + #define regLSDMA_QUEUE1_IB_RPTR 0x00e5 318 + #define regLSDMA_QUEUE1_IB_RPTR_BASE_IDX 0 319 + #define regLSDMA_QUEUE1_IB_OFFSET 0x00e6 320 + #define regLSDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 321 + #define regLSDMA_QUEUE1_IB_BASE_LO 0x00e7 322 + #define regLSDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 323 + #define regLSDMA_QUEUE1_IB_BASE_HI 0x00e8 324 + #define regLSDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 325 + #define regLSDMA_QUEUE1_IB_SIZE 0x00e9 326 + #define regLSDMA_QUEUE1_IB_SIZE_BASE_IDX 0 327 + #define regLSDMA_QUEUE1_SKIP_CNTL 0x00ea 328 + #define regLSDMA_QUEUE1_SKIP_CNTL_BASE_IDX 0 329 + #define regLSDMA_QUEUE1_CSA_ADDR_LO 0x00eb 330 + #define regLSDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 331 + #define regLSDMA_QUEUE1_CSA_ADDR_HI 0x00ec 332 + #define regLSDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 333 + #define regLSDMA_QUEUE1_RB_AQL_CNTL 0x00ed 334 + #define regLSDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 335 + #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE 0x00ee 336 + #define regLSDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 337 + #define regLSDMA_QUEUE1_CNTL 0x00ef 338 + #define regLSDMA_QUEUE1_CNTL_BASE_IDX 0 339 + #define regLSDMA_QUEUE1_RB_PREEMPT 0x00f0 340 + #define regLSDMA_QUEUE1_RB_PREEMPT_BASE_IDX 0 341 + #define regLSDMA_QUEUE1_IB_SUB_REMAIN 0x00f1 342 + #define regLSDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 343 + #define regLSDMA_QUEUE1_PREEMPT 0x00f2 344 + #define regLSDMA_QUEUE1_PREEMPT_BASE_IDX 0 345 + #define regLSDMA_QUEUE1_CONTEXT_STATUS 0x00f3 346 + #define regLSDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 347 + #define regLSDMA_QUEUE1_STATUS 0x00f4 348 + #define regLSDMA_QUEUE1_STATUS_BASE_IDX 0 349 + #define regLSDMA_QUEUE1_DOORBELL 0x00f5 350 + #define regLSDMA_QUEUE1_DOORBELL_BASE_IDX 0 351 + #define regLSDMA_QUEUE1_DOORBELL_OFFSET 0x00f6 352 + #define regLSDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 353 + #define regLSDMA_QUEUE1_DOORBELL_LOG 0x00f7 354 + #define regLSDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 355 + #define regLSDMA_QUEUE1_WATERMARK 0x00f8 356 + #define regLSDMA_QUEUE1_WATERMARK_BASE_IDX 0 357 + #define regLSDMA_QUEUE1_DUMMY0 0x00f9 358 + #define regLSDMA_QUEUE1_DUMMY0_BASE_IDX 0 359 + #define regLSDMA_QUEUE1_DUMMY1 0x00fa 360 + #define regLSDMA_QUEUE1_DUMMY1_BASE_IDX 0 361 + #define regLSDMA_QUEUE1_DUMMY2 0x00fb 362 + #define regLSDMA_QUEUE1_DUMMY2_BASE_IDX 0 363 + #define regLSDMA_QUEUE1_MIDCMD_DATA0 0x0118 364 + #define regLSDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 365 + #define regLSDMA_QUEUE1_MIDCMD_DATA1 0x0119 366 + #define regLSDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 367 + #define regLSDMA_QUEUE1_MIDCMD_DATA2 0x011a 368 + #define regLSDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 369 + #define regLSDMA_QUEUE1_MIDCMD_DATA3 0x011b 370 + #define regLSDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 371 + #define regLSDMA_QUEUE1_MIDCMD_DATA4 0x011c 372 + #define regLSDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 373 + #define regLSDMA_QUEUE1_MIDCMD_DATA5 0x011d 374 + #define regLSDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 375 + #define regLSDMA_QUEUE1_MIDCMD_DATA6 0x011e 376 + #define regLSDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 377 + #define regLSDMA_QUEUE1_MIDCMD_DATA7 0x011f 378 + #define regLSDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 379 + #define regLSDMA_QUEUE1_MIDCMD_DATA8 0x0120 380 + #define regLSDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 381 + #define regLSDMA_QUEUE1_MIDCMD_DATA9 0x0121 382 + #define regLSDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 383 + #define regLSDMA_QUEUE1_MIDCMD_DATA10 0x0122 384 + #define regLSDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 385 + #define regLSDMA_QUEUE1_MIDCMD_CNTL 0x0123 386 + #define regLSDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 387 + 388 + #endif
+1411
drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_0_0_sh_mask.h
··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _lsdma_7_0_0_SH_MASK_HEADER 24 + #define _lsdma_7_0_0_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: lsdma0_lsdma0dec 28 + //LSDMA_UCODE_ADDR 29 + #define LSDMA_UCODE_ADDR__VALUE__SHIFT 0x0 30 + #define LSDMA_UCODE_ADDR__VALUE_MASK 0x00001FFFL 31 + //LSDMA_UCODE_DATA 32 + #define LSDMA_UCODE_DATA__VALUE__SHIFT 0x0 33 + #define LSDMA_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 34 + //LSDMA_ERROR_INJECT_CNTL 35 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION__SHIFT 0x0 36 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x1 37 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x2 38 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_MEMHUB_READ_POISON_INJECT__SHIFT 0x8 39 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_MEMHUB_ATOMIC_POISON_INJECT__SHIFT 0x9 40 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_IRRITATION_MASK 0x00000001L 41 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000002L 42 + #define LSDMA_ERROR_INJECT_CNTL__ENABLE_ERROR_INJECT_MASK 0x0000000CL 43 + //LSDMA_ERROR_INJECT_SELECT 44 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0__SHIFT 0x0 45 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1__SHIFT 0x1 46 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2__SHIFT 0x2 47 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3__SHIFT 0x3 48 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4__SHIFT 0x4 49 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5__SHIFT 0x5 50 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6__SHIFT 0x6 51 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7__SHIFT 0x7 52 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8__SHIFT 0x8 53 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9__SHIFT 0x9 54 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10__SHIFT 0xa 55 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11__SHIFT 0xb 56 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12__SHIFT 0xc 57 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13__SHIFT 0xd 58 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14__SHIFT 0xe 59 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15__SHIFT 0xf 60 + #define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF__SHIFT 0x10 61 + #define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF__SHIFT 0x11 62 + #define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF__SHIFT 0x12 63 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO__SHIFT 0x13 64 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO__SHIFT 0x14 65 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO__SHIFT 0x15 66 + #define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO__SHIFT 0x16 67 + #define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO__SHIFT 0x17 68 + #define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO__SHIFT 0x18 69 + #define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF__SHIFT 0x19 70 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF0_MASK 0x00000001L 71 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF1_MASK 0x00000002L 72 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF2_MASK 0x00000004L 73 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF3_MASK 0x00000008L 74 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF4_MASK 0x00000010L 75 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF5_MASK 0x00000020L 76 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF6_MASK 0x00000040L 77 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF7_MASK 0x00000080L 78 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF8_MASK 0x00000100L 79 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF9_MASK 0x00000200L 80 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF10_MASK 0x00000400L 81 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF11_MASK 0x00000800L 82 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF12_MASK 0x00001000L 83 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF13_MASK 0x00002000L 84 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF14_MASK 0x00004000L 85 + #define LSDMA_ERROR_INJECT_SELECT__MBANK_DATA_BUF15_MASK 0x00008000L 86 + #define LSDMA_ERROR_INJECT_SELECT__UCODE_BUF_MASK 0x00010000L 87 + #define LSDMA_ERROR_INJECT_SELECT__RB_CMD_BUF_MASK 0x00020000L 88 + #define LSDMA_ERROR_INJECT_SELECT__IB_CMD_BUF_MASK 0x00040000L 89 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RD_FIFO_MASK 0x00080000L 90 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_RDBST_FIFO_MASK 0x00100000L 91 + #define LSDMA_ERROR_INJECT_SELECT__UTCL1_WR_FIFO_MASK 0x00200000L 92 + #define LSDMA_ERROR_INJECT_SELECT__DATA_LUT_FIFO_MASK 0x00400000L 93 + #define LSDMA_ERROR_INJECT_SELECT__SPLIT_DATA_FIFO_MASK 0x00800000L 94 + #define LSDMA_ERROR_INJECT_SELECT__MC_WR_ADDR_FIFO_MASK 0x01000000L 95 + #define LSDMA_ERROR_INJECT_SELECT__MC_RDRET_BUF_MASK 0x02000000L 96 + #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR__SHIFT 0x0 97 + #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA__SHIFT 0x1 98 + #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_ADDR_MASK 0x00000001L 99 + #define LSDMA_PUB_REG_TYPE0__LSDMA_UCODE_DATA_MASK 0x00000002L 100 + #define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL__SHIFT 0xb 101 + #define LSDMA_PUB_REG_TYPE3__LSDMA_CLK_CTRL_MASK 0x00000800L 102 + //LSDMA_CONTEXT_GROUP_BOUNDARY 103 + #define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 104 + #define LSDMA_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 105 + //LSDMA_RB_RPTR_FETCH_HI 106 + #define LSDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 107 + #define LSDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 108 + //LSDMA_SEM_WAIT_FAIL_TIMER_CNTL 109 + #define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 110 + #define LSDMA_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 111 + //LSDMA_RB_RPTR_FETCH 112 + #define LSDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 113 + #define LSDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 114 + //LSDMA_IB_OFFSET_FETCH 115 + #define LSDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 116 + #define LSDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 117 + //LSDMA_PROGRAM 118 + #define LSDMA_PROGRAM__STREAM__SHIFT 0x0 119 + #define LSDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL 120 + //LSDMA_STATUS_REG 121 + #define LSDMA_STATUS_REG__IDLE__SHIFT 0x0 122 + #define LSDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 123 + #define LSDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 124 + #define LSDMA_STATUS_REG__RB_FULL__SHIFT 0x3 125 + #define LSDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 126 + #define LSDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 127 + #define LSDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 128 + #define LSDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 129 + #define LSDMA_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 130 + #define LSDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 131 + #define LSDMA_STATUS_REG__EX_IDLE__SHIFT 0xa 132 + #define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 133 + #define LSDMA_STATUS_REG__PACKET_READY__SHIFT 0xc 134 + #define LSDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 135 + #define LSDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe 136 + #define LSDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 137 + #define LSDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 138 + #define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 139 + #define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 140 + #define LSDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 141 + #define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 142 + #define LSDMA_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 143 + #define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 144 + #define LSDMA_STATUS_REG__DRM_IDLE__SHIFT 0x17 145 + #define LSDMA_STATUS_REG__Reserved__SHIFT 0x18 146 + #define LSDMA_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 147 + #define LSDMA_STATUS_REG__SEM_IDLE__SHIFT 0x1a 148 + #define LSDMA_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 149 + #define LSDMA_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 150 + #define LSDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e 151 + #define LSDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 152 + #define LSDMA_STATUS_REG__IDLE_MASK 0x00000001L 153 + #define LSDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L 154 + #define LSDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L 155 + #define LSDMA_STATUS_REG__RB_FULL_MASK 0x00000008L 156 + #define LSDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 157 + #define LSDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 158 + #define LSDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 159 + #define LSDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 160 + #define LSDMA_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 161 + #define LSDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L 162 + #define LSDMA_STATUS_REG__EX_IDLE_MASK 0x00000400L 163 + #define LSDMA_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 164 + #define LSDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L 165 + #define LSDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 166 + #define LSDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 167 + #define LSDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 168 + #define LSDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 169 + #define LSDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 170 + #define LSDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 171 + #define LSDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 172 + #define LSDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 173 + #define LSDMA_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 174 + #define LSDMA_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 175 + #define LSDMA_STATUS_REG__Reserved_MASK 0x01000000L 176 + #define LSDMA_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 177 + #define LSDMA_STATUS_REG__SEM_IDLE_MASK 0x04000000L 178 + #define LSDMA_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 179 + #define LSDMA_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 180 + #define LSDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L 181 + #define LSDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 182 + //LSDMA_STATUS1_REG 183 + #define LSDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 184 + #define LSDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 185 + #define LSDMA_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 186 + #define LSDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 187 + #define LSDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 188 + #define LSDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 189 + #define LSDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 190 + #define LSDMA_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x7 191 + #define LSDMA_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x8 192 + #define LSDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 193 + #define LSDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 194 + #define LSDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb 195 + #define LSDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc 196 + #define LSDMA_STATUS1_REG__EX_START__SHIFT 0xd 197 + #define LSDMA_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0xe 198 + #define LSDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf 199 + #define LSDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 200 + #define LSDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 201 + #define LSDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 202 + #define LSDMA_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 203 + #define LSDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 204 + #define LSDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 205 + #define LSDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 206 + #define LSDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 207 + #define LSDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 208 + #define LSDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 209 + #define LSDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L 210 + #define LSDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L 211 + #define LSDMA_STATUS1_REG__EX_START_MASK 0x00002000L 212 + #define LSDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L 213 + #define LSDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L 214 + //LSDMA_RD_BURST_CNTL 215 + #define LSDMA_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 216 + #define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 217 + #define LSDMA_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 218 + #define LSDMA_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL 219 + //LSDMA_HBM_PAGE_CONFIG 220 + #define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 221 + #define LSDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 222 + //LSDMA_UCODE_CHECKSUM 223 + #define LSDMA_UCODE_CHECKSUM__DATA__SHIFT 0x0 224 + #define LSDMA_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 225 + //LSDMA_FREEZE 226 + #define LSDMA_FREEZE__PREEMPT__SHIFT 0x0 227 + #define LSDMA_FREEZE__FREEZE__SHIFT 0x4 228 + #define LSDMA_FREEZE__FROZEN__SHIFT 0x5 229 + #define LSDMA_FREEZE__F32_FREEZE__SHIFT 0x6 230 + #define LSDMA_FREEZE__PREEMPT_MASK 0x00000001L 231 + #define LSDMA_FREEZE__FREEZE_MASK 0x00000010L 232 + #define LSDMA_FREEZE__FROZEN_MASK 0x00000020L 233 + #define LSDMA_FREEZE__F32_FREEZE_MASK 0x00000040L 234 + //LSDMA_DCC_CNTL 235 + #define LSDMA_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 236 + #define LSDMA_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L 237 + //LSDMA_POWER_GATING 238 + #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION__SHIFT 0x0 239 + #define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION__SHIFT 0x1 240 + #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ__SHIFT 0x2 241 + #define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ__SHIFT 0x3 242 + #define LSDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 243 + #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_CONDITION_MASK 0x00000001L 244 + #define LSDMA_POWER_GATING__LSDMA_POWER_ON_CONDITION_MASK 0x00000002L 245 + #define LSDMA_POWER_GATING__LSDMA_POWER_OFF_REQ_MASK 0x00000004L 246 + #define LSDMA_POWER_GATING__LSDMA_POWER_ON_REQ_MASK 0x00000008L 247 + #define LSDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 248 + //LSDMA_PGFSM_CONFIG 249 + #define LSDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 250 + #define LSDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 251 + #define LSDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 252 + #define LSDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 253 + #define LSDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 254 + #define LSDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 255 + #define LSDMA_PGFSM_CONFIG__READ__SHIFT 0xd 256 + #define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 257 + #define LSDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 258 + #define LSDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 259 + #define LSDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 260 + #define LSDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 261 + #define LSDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 262 + #define LSDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 263 + #define LSDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 264 + #define LSDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 265 + #define LSDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 266 + #define LSDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 267 + //LSDMA_PGFSM_WRITE 268 + #define LSDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 269 + #define LSDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 270 + //LSDMA_PGFSM_READ 271 + #define LSDMA_PGFSM_READ__VALUE__SHIFT 0x0 272 + #define LSDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 273 + //LSDMA_BA_THRESHOLD 274 + #define LSDMA_BA_THRESHOLD__READ_THRES__SHIFT 0x0 275 + #define LSDMA_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 276 + #define LSDMA_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 277 + #define LSDMA_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 278 + //LSDMA_ID 279 + #define LSDMA_ID__DEVICE_ID__SHIFT 0x0 280 + #define LSDMA_ID__DEVICE_ID_MASK 0x000000FFL 281 + //LSDMA_VERSION 282 + #define LSDMA_VERSION__MINVER__SHIFT 0x0 283 + #define LSDMA_VERSION__MAJVER__SHIFT 0x8 284 + #define LSDMA_VERSION__REV__SHIFT 0x10 285 + #define LSDMA_VERSION__MINVER_MASK 0x0000007FL 286 + #define LSDMA_VERSION__MAJVER_MASK 0x00007F00L 287 + #define LSDMA_VERSION__REV_MASK 0x003F0000L 288 + //LSDMA_EDC_COUNTER 289 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED__SHIFT 0x0 290 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED__SHIFT 0x2 291 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED__SHIFT 0x4 292 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED__SHIFT 0x6 293 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED__SHIFT 0x8 294 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa 295 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED__SHIFT 0xc 296 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 297 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED__SHIFT 0x10 298 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED__SHIFT 0x12 299 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED__SHIFT 0x14 300 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED__SHIFT 0x16 301 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED__SHIFT 0x18 302 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED__SHIFT 0x1a 303 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED__SHIFT 0x1c 304 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED__SHIFT 0x1e 305 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF0_SED_MASK 0x00000003L 306 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF1_SED_MASK 0x0000000CL 307 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF2_SED_MASK 0x00000030L 308 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF3_SED_MASK 0x000000C0L 309 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF4_SED_MASK 0x00000300L 310 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF5_SED_MASK 0x00000C00L 311 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF6_SED_MASK 0x00003000L 312 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF7_SED_MASK 0x0000C000L 313 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF8_SED_MASK 0x00030000L 314 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF9_SED_MASK 0x000C0000L 315 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF10_SED_MASK 0x00300000L 316 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF11_SED_MASK 0x00C00000L 317 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF12_SED_MASK 0x03000000L 318 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF13_SED_MASK 0x0C000000L 319 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF14_SED_MASK 0x30000000L 320 + #define LSDMA_EDC_COUNTER__LSDMA_MBANK_DATA_BUF15_SED_MASK 0xC0000000L 321 + //LSDMA_EDC_COUNTER2 322 + #define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED__SHIFT 0x0 323 + #define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED__SHIFT 0x2 324 + #define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED__SHIFT 0x4 325 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED__SHIFT 0x6 326 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x8 327 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED__SHIFT 0xa 328 + #define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED__SHIFT 0xc 329 + #define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED__SHIFT 0xe 330 + #define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 331 + #define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED__SHIFT 0x12 332 + #define LSDMA_EDC_COUNTER2__LSDMA_UCODE_BUF_SED_MASK 0x00000003L 333 + #define LSDMA_EDC_COUNTER2__LSDMA_RB_CMD_BUF_SED_MASK 0x0000000CL 334 + #define LSDMA_EDC_COUNTER2__LSDMA_IB_CMD_BUF_SED_MASK 0x00000030L 335 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RD_FIFO_SED_MASK 0x000000C0L 336 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000300L 337 + #define LSDMA_EDC_COUNTER2__LSDMA_UTCL1_WR_FIFO_SED_MASK 0x00000C00L 338 + #define LSDMA_EDC_COUNTER2__LSDMA_DATA_LUT_FIFO_SED_MASK 0x00003000L 339 + #define LSDMA_EDC_COUNTER2__LSDMA_SPLIT_DATA_BUF_SED_MASK 0x0000C000L 340 + #define LSDMA_EDC_COUNTER2__LSDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00030000L 341 + #define LSDMA_EDC_COUNTER2__LSDMA_MC_RDRET_BUF_SED_MASK 0x000C0000L 342 + //LSDMA_STATUS2_REG 343 + #define LSDMA_STATUS2_REG__ID__SHIFT 0x0 344 + #define LSDMA_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x3 345 + #define LSDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 346 + #define LSDMA_STATUS2_REG__ID_MASK 0x00000007L 347 + #define LSDMA_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFF8L 348 + #define LSDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 349 + //LSDMA_ATOMIC_CNTL 350 + #define LSDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 351 + #define LSDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 352 + //LSDMA_ATOMIC_PREOP_LO 353 + #define LSDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 354 + #define LSDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 355 + //LSDMA_ATOMIC_PREOP_HI 356 + #define LSDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 357 + #define LSDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 358 + //LSDMA_UTCL1_CNTL 359 + #define LSDMA_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 360 + #define LSDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 361 + #define LSDMA_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 362 + #define LSDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 363 + #define LSDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 364 + #define LSDMA_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 365 + #define LSDMA_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 366 + #define LSDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 367 + #define LSDMA_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 368 + #define LSDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 369 + #define LSDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 370 + #define LSDMA_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 371 + //LSDMA_UTCL1_WATERMK 372 + #define LSDMA_UTCL1_WATERMK__REQ_WATERMK__SHIFT 0x0 373 + #define LSDMA_UTCL1_WATERMK__REQ_DEPTH__SHIFT 0x3 374 + #define LSDMA_UTCL1_WATERMK__PAGE_WATERMK__SHIFT 0x5 375 + #define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x8 376 + #define LSDMA_UTCL1_WATERMK__RESERVED__SHIFT 0x10 377 + #define LSDMA_UTCL1_WATERMK__REQ_WATERMK_MASK 0x00000007L 378 + #define LSDMA_UTCL1_WATERMK__REQ_DEPTH_MASK 0x00000018L 379 + #define LSDMA_UTCL1_WATERMK__PAGE_WATERMK_MASK 0x000000E0L 380 + #define LSDMA_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x0000FF00L 381 + #define LSDMA_UTCL1_WATERMK__RESERVED_MASK 0xFFFF0000L 382 + //LSDMA_UTCL1_RD_STATUS 383 + #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 384 + #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 385 + #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 386 + #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 387 + #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 388 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 389 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 390 + #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 391 + #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 392 + #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 393 + #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 394 + #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 395 + #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 396 + #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 397 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 398 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 399 + #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 400 + #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 401 + #define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 402 + #define LSDMA_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 403 + #define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 404 + #define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 405 + #define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 406 + #define LSDMA_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 407 + #define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 408 + #define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 409 + #define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 410 + #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 411 + #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 412 + #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 413 + #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 414 + #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 415 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 416 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 417 + #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 418 + #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 419 + #define LSDMA_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 420 + #define LSDMA_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 421 + #define LSDMA_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 422 + #define LSDMA_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 423 + #define LSDMA_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 424 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 425 + #define LSDMA_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 426 + #define LSDMA_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 427 + #define LSDMA_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 428 + #define LSDMA_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 429 + #define LSDMA_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 430 + #define LSDMA_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 431 + #define LSDMA_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 432 + #define LSDMA_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 433 + #define LSDMA_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 434 + #define LSDMA_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 435 + #define LSDMA_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 436 + #define LSDMA_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 437 + //LSDMA_UTCL1_WR_STATUS 438 + #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 439 + #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 440 + #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 441 + #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 442 + #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 443 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 444 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 445 + #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 446 + #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 447 + #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 448 + #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 449 + #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 450 + #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 451 + #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 452 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 453 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 454 + #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 455 + #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 456 + #define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 457 + #define LSDMA_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 458 + #define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 459 + #define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 460 + #define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 461 + #define LSDMA_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 462 + #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 463 + #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 464 + #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 465 + #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 466 + #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 467 + #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 468 + #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 469 + #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 470 + #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 471 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 472 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 473 + #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 474 + #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 475 + #define LSDMA_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 476 + #define LSDMA_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 477 + #define LSDMA_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 478 + #define LSDMA_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 479 + #define LSDMA_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 480 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 481 + #define LSDMA_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 482 + #define LSDMA_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 483 + #define LSDMA_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 484 + #define LSDMA_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 485 + #define LSDMA_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 486 + #define LSDMA_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 487 + #define LSDMA_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 488 + #define LSDMA_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 489 + #define LSDMA_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 490 + #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 491 + #define LSDMA_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 492 + #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 493 + #define LSDMA_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 494 + //LSDMA_UTCL1_INV0 495 + #define LSDMA_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 496 + #define LSDMA_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 497 + #define LSDMA_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 498 + #define LSDMA_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 499 + #define LSDMA_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 500 + #define LSDMA_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 501 + #define LSDMA_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 502 + #define LSDMA_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 503 + #define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 504 + #define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 505 + #define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 506 + #define LSDMA_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 507 + #define LSDMA_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 508 + #define LSDMA_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 509 + #define LSDMA_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 510 + #define LSDMA_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 511 + #define LSDMA_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 512 + #define LSDMA_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 513 + #define LSDMA_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 514 + #define LSDMA_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 515 + #define LSDMA_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 516 + #define LSDMA_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 517 + #define LSDMA_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 518 + #define LSDMA_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 519 + #define LSDMA_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 520 + #define LSDMA_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 521 + #define LSDMA_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 522 + #define LSDMA_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 523 + //LSDMA_UTCL1_INV1 524 + #define LSDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 525 + #define LSDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 526 + //LSDMA_UTCL1_INV2 527 + #define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 528 + #define LSDMA_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 529 + //LSDMA_UTCL1_RD_XNACK0 530 + #define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 531 + #define LSDMA_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 532 + //LSDMA_UTCL1_RD_XNACK1 533 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 534 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 535 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 536 + #define LSDMA_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 537 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 538 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 539 + #define LSDMA_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 540 + #define LSDMA_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 541 + //LSDMA_UTCL1_WR_XNACK0 542 + #define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 543 + #define LSDMA_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 544 + //LSDMA_UTCL1_WR_XNACK1 545 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 546 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 547 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 548 + #define LSDMA_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 549 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 550 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 551 + #define LSDMA_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 552 + #define LSDMA_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 553 + //LSDMA_UTCL1_TIMEOUT 554 + #define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 555 + #define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 556 + #define LSDMA_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 557 + #define LSDMA_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 558 + //LSDMA_UTCL1_PAGE 559 + #define LSDMA_UTCL1_PAGE__INVALID_ADDR__SHIFT 0x0 560 + #define LSDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 561 + #define LSDMA_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5 562 + #define LSDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 563 + #define LSDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 564 + #define LSDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 565 + #define LSDMA_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L 566 + #define LSDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 567 + #define LSDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 568 + //LSDMA_RELAX_ORDERING_LUT 569 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 570 + #define LSDMA_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 571 + #define LSDMA_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 572 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 573 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 574 + #define LSDMA_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 575 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 576 + #define LSDMA_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 577 + #define LSDMA_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 578 + #define LSDMA_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 579 + #define LSDMA_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 580 + #define LSDMA_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 581 + #define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 582 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 583 + #define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 584 + #define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 585 + #define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 586 + #define LSDMA_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 587 + #define LSDMA_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 588 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 589 + #define LSDMA_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 590 + #define LSDMA_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 591 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 592 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 593 + #define LSDMA_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 594 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 595 + #define LSDMA_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 596 + #define LSDMA_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 597 + #define LSDMA_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 598 + #define LSDMA_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 599 + #define LSDMA_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 600 + #define LSDMA_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 601 + #define LSDMA_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 602 + #define LSDMA_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 603 + #define LSDMA_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 604 + #define LSDMA_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 605 + #define LSDMA_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 606 + #define LSDMA_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 607 + //LSDMA_CHICKEN_BITS_2 608 + #define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 609 + #define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 610 + #define LSDMA_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 611 + #define LSDMA_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L 612 + //LSDMA_STATUS3_REG 613 + #define LSDMA_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 614 + #define LSDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 615 + #define LSDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 616 + #define LSDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 617 + #define LSDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 618 + #define LSDMA_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 619 + #define LSDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 620 + #define LSDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 621 + #define LSDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L 622 + #define LSDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L 623 + //LSDMA_PHYSICAL_ADDR_LO 624 + #define LSDMA_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 625 + #define LSDMA_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 626 + #define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 627 + #define LSDMA_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 628 + #define LSDMA_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 629 + #define LSDMA_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 630 + #define LSDMA_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 631 + #define LSDMA_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 632 + //LSDMA_PHYSICAL_ADDR_HI 633 + #define LSDMA_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 634 + #define LSDMA_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 635 + //LSDMA_ECC_CNTL 636 + #define LSDMA_ECC_CNTL__ECC_DISABLE__SHIFT 0x0 637 + #define LSDMA_ECC_CNTL__ECC_DISABLE_MASK 0x00000001L 638 + //LSDMA_ERROR_LOG 639 + #define LSDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 640 + #define LSDMA_ERROR_LOG__STATUS__SHIFT 0x10 641 + #define LSDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 642 + #define LSDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L 643 + //LSDMA_PUB_DUMMY0 644 + #define LSDMA_PUB_DUMMY0__DUMMY__SHIFT 0x0 645 + #define LSDMA_PUB_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 646 + //LSDMA_PUB_DUMMY1 647 + #define LSDMA_PUB_DUMMY1__DUMMY__SHIFT 0x0 648 + #define LSDMA_PUB_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 649 + //LSDMA_PUB_DUMMY2 650 + #define LSDMA_PUB_DUMMY2__DUMMY__SHIFT 0x0 651 + #define LSDMA_PUB_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 652 + //LSDMA_PUB_DUMMY3 653 + #define LSDMA_PUB_DUMMY3__DUMMY__SHIFT 0x0 654 + #define LSDMA_PUB_DUMMY3__DUMMY_MASK 0xFFFFFFFFL 655 + //LSDMA_F32_COUNTER 656 + #define LSDMA_F32_COUNTER__VALUE__SHIFT 0x0 657 + #define LSDMA_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 658 + //LSDMA_PERFCNT_PERFCOUNTER0_CFG 659 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 660 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 661 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 662 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 663 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 664 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 665 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 666 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 667 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 668 + #define LSDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 669 + //LSDMA_PERFCNT_PERFCOUNTER1_CFG 670 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 671 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 672 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 673 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 674 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 675 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 676 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 677 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 678 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 679 + #define LSDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 680 + //LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 681 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 682 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 683 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 684 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 685 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 686 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 687 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 688 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 689 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 690 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 691 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 692 + #define LSDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 693 + //LSDMA_PERFCNT_MISC_CNTL 694 + #define LSDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 695 + #define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT__SHIFT 0x10 696 + #define LSDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL 697 + #define LSDMA_PERFCNT_MISC_CNTL__MMHUB_REQ_EVENT_SELECT_MASK 0x00010000L 698 + //LSDMA_PERFCNT_PERFCOUNTER_LO 699 + #define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 700 + #define LSDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 701 + //LSDMA_PERFCNT_PERFCOUNTER_HI 702 + #define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 703 + #define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 704 + #define LSDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 705 + #define LSDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 706 + //LSDMA_CRD_CNTL 707 + #define LSDMA_CRD_CNTL__DRM_CREDIT__SHIFT 0x0 708 + #define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 709 + #define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 710 + #define LSDMA_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 711 + #define LSDMA_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 712 + //LSDMA_ULV_CNTL 713 + #define LSDMA_ULV_CNTL__HYSTERESIS__SHIFT 0x0 714 + #define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b 715 + #define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c 716 + #define LSDMA_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 717 + #define LSDMA_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 718 + #define LSDMA_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 719 + #define LSDMA_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 720 + #define LSDMA_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L 721 + #define LSDMA_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L 722 + #define LSDMA_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 723 + #define LSDMA_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 724 + #define LSDMA_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 725 + //LSDMA_EA_DBIT_ADDR_DATA 726 + #define LSDMA_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 727 + #define LSDMA_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 728 + //LSDMA_EA_DBIT_ADDR_INDEX 729 + #define LSDMA_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 730 + #define LSDMA_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 731 + //LSDMA_STATUS4_REG 732 + #define LSDMA_STATUS4_REG__IDLE__SHIFT 0x0 733 + #define LSDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 734 + #define LSDMA_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 735 + #define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING__SHIFT 0x4 736 + #define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING__SHIFT 0x5 737 + #define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x6 738 + #define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x7 739 + #define LSDMA_STATUS4_REG__REG_POLLING__SHIFT 0x8 740 + #define LSDMA_STATUS4_REG__MEM_POLLING__SHIFT 0x9 741 + #define LSDMA_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xa 742 + #define LSDMA_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xc 743 + #define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0xe 744 + #define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x12 745 + #define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD__SHIFT 0x13 746 + #define LSDMA_STATUS4_REG__IDLE_MASK 0x00000001L 747 + #define LSDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L 748 + #define LSDMA_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L 749 + #define LSDMA_STATUS4_REG__MMHUB_RD_OUTSTANDING_MASK 0x00000010L 750 + #define LSDMA_STATUS4_REG__MMHUB_WR_OUTSTANDING_MASK 0x00000020L 751 + #define LSDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000040L 752 + #define LSDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000080L 753 + #define LSDMA_STATUS4_REG__REG_POLLING_MASK 0x00000100L 754 + #define LSDMA_STATUS4_REG__MEM_POLLING_MASK 0x00000200L 755 + #define LSDMA_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00000C00L 756 + #define LSDMA_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x00003000L 757 + #define LSDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x0003C000L 758 + #define LSDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00040000L 759 + #define LSDMA_STATUS4_REG__SRIOV_LSDMA_EXECUTING_CMD_MASK 0x00080000L 760 + //LSDMA_CE_CTRL 761 + #define LSDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 762 + #define LSDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 763 + #define LSDMA_CE_CTRL__RESERVED_7_5__SHIFT 0x5 764 + #define LSDMA_CE_CTRL__RESERVED__SHIFT 0x8 765 + #define LSDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L 766 + #define LSDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L 767 + #define LSDMA_CE_CTRL__RESERVED_7_5_MASK 0x000000E0L 768 + #define LSDMA_CE_CTRL__RESERVED_MASK 0xFFFFFF00L 769 + //LSDMA_EXCEPTION_STATUS 770 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC__SHIFT 0x0 771 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC__SHIFT 0x1 772 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC__SHIFT 0x2 773 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC__SHIFT 0x3 774 + #define LSDMA_EXCEPTION_STATUS__SRAM_ECC__SHIFT 0x6 775 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR__SHIFT 0x8 776 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR__SHIFT 0x9 777 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR__SHIFT 0xa 778 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR__SHIFT 0xb 779 + #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR__SHIFT 0xd 780 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT__SHIFT 0x10 781 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT__SHIFT 0x11 782 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT__SHIFT 0x12 783 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT__SHIFT 0x13 784 + #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT__SHIFT 0x15 785 + #define LSDMA_EXCEPTION_STATUS__INVALID_ADDR__SHIFT 0x18 786 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_ECC_MASK 0x00000001L 787 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_ECC_MASK 0x00000002L 788 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_ECC_MASK 0x00000004L 789 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_ECC_MASK 0x00000008L 790 + #define LSDMA_EXCEPTION_STATUS__SRAM_ECC_MASK 0x00000040L 791 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_GEN_ERR_MASK 0x00000100L 792 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_GEN_ERR_MASK 0x00000200L 793 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_GEN_ERR_MASK 0x00000400L 794 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_GEN_ERR_MASK 0x00000800L 795 + #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_GEN_ERR_MASK 0x00002000L 796 + #define LSDMA_EXCEPTION_STATUS__RB_FETCH_NACK_PRT_MASK 0x00010000L 797 + #define LSDMA_EXCEPTION_STATUS__IB_FETCH_NACK_PRT_MASK 0x00020000L 798 + #define LSDMA_EXCEPTION_STATUS__COPY_CMD_NACK_PRT_MASK 0x00040000L 799 + #define LSDMA_EXCEPTION_STATUS__NON_COPY_CMD_NACK_PRT_MASK 0x00080000L 800 + #define LSDMA_EXCEPTION_STATUS__RPTR_WB_NACK_PRT_MASK 0x00200000L 801 + //LSDMA_INT_CNTL 802 + #define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE__SHIFT 0x0 803 + #define LSDMA_INT_CNTL__TRAP_INT_ENABLE__SHIFT 0x1 804 + #define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE__SHIFT 0x2 805 + #define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE__SHIFT 0x3 806 + #define LSDMA_INT_CNTL__FROZEN_INT_ENABLE__SHIFT 0x4 807 + #define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE__SHIFT 0x5 808 + #define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x6 809 + #define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE__SHIFT 0x7 810 + #define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE__SHIFT 0x8 811 + #define LSDMA_INT_CNTL__INVALID_ADDR_INT_ENABLE__SHIFT 0x9 812 + #define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xa 813 + #define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xb 814 + #define LSDMA_INT_CNTL__ECC_INT_ENABLE__SHIFT 0xc 815 + #define LSDMA_INT_CNTL__ATOMIC_RTN_DONE_INT_ENABLE_MASK 0x00000001L 816 + #define LSDMA_INT_CNTL__TRAP_INT_ENABLE_MASK 0x00000002L 817 + #define LSDMA_INT_CNTL__SRBM_WRITE_INT_ENABLE_MASK 0x00000004L 818 + #define LSDMA_INT_CNTL__CTX_EMPTY_INT_ENABLE_MASK 0x00000008L 819 + #define LSDMA_INT_CNTL__FROZEN_INT_ENABLE_MASK 0x00000010L 820 + #define LSDMA_INT_CNTL__PREEMPT_INT_ENABLE_MASK 0x00000020L 821 + #define LSDMA_INT_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x00000040L 822 + #define LSDMA_INT_CNTL__ATOMIC_TIMEOUT_INT_ENABLE_MASK 0x00000080L 823 + #define LSDMA_INT_CNTL__POLL_TIMEOUT_INT_ENABLE_MASK 0x00000100L 824 + #define LSDMA_INT_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00000400L 825 + #define LSDMA_INT_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00000800L 826 + #define LSDMA_INT_CNTL__ECC_INT_ENABLE_MASK 0x00001000L 827 + //LSDMA_MEM_POWER_CTRL 828 + #define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN__SHIFT 0x0 829 + #define LSDMA_MEM_POWER_CTRL__MEM_POWER_CTRL_EN_MASK 0x00000001L 830 + //LSDMA_CLK_CTRL 831 + #define LSDMA_CLK_CTRL__RESERVED__SHIFT 0x1 832 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 833 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 834 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 835 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 836 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 837 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 838 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 839 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 840 + #define LSDMA_CLK_CTRL__RESERVED_MASK 0x00FFFFFEL 841 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 842 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 843 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 844 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 845 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 846 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 847 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 848 + #define LSDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 849 + //LSDMA_CNTL 850 + #define LSDMA_CNTL__UTC_L1_ENABLE__SHIFT 0x1 851 + #define LSDMA_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 852 + #define LSDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 853 + #define LSDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 854 + #define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 855 + #define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x6 856 + #define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 857 + #define LSDMA_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 858 + #define LSDMA_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x13 859 + #define LSDMA_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 860 + #define LSDMA_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 861 + #define LSDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 862 + #define LSDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 863 + #define LSDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 864 + #define LSDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000040L 865 + #define LSDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 866 + #define LSDMA_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 867 + //LSDMA_CHICKEN_BITS 868 + #define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 869 + #define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 870 + #define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE__SHIFT 0x3 871 + #define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 872 + #define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 873 + #define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 874 + #define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 875 + #define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 876 + #define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 877 + #define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 878 + #define LSDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x18 879 + #define LSDMA_CHICKEN_BITS__DRAM_ECC_NACK_F32_RESET_ENABLE__SHIFT 0x19 880 + #define LSDMA_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 881 + #define LSDMA_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 882 + #define LSDMA_CHICKEN_BITS__F32_MGCG_ENABLE_MASK 0x00000008L 883 + #define LSDMA_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 884 + #define LSDMA_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 885 + #define LSDMA_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 886 + #define LSDMA_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 887 + #define LSDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L 888 + #define LSDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 889 + #define LSDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 890 + //LSDMA_PIO_SRC_ADDR_LO 891 + #define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO__SHIFT 0x0 892 + #define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO_MASK 0xFFFFFFFFL 893 + //LSDMA_PIO_SRC_ADDR_HI 894 + #define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 895 + #define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xFFFFFFFFL 896 + //LSDMA_PIO_DST_ADDR_LO 897 + #define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO__SHIFT 0x0 898 + #define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO_MASK 0xFFFFFFFFL 899 + //LSDMA_PIO_DST_ADDR_HI 900 + #define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 901 + #define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0xFFFFFFFFL 902 + //LSDMA_PIO_COMMAND 903 + #define LSDMA_PIO_COMMAND__BYTE_COUNT__SHIFT 0x0 904 + #define LSDMA_PIO_COMMAND__SRC_LOCATION__SHIFT 0x1a 905 + #define LSDMA_PIO_COMMAND__DST_LOCATION__SHIFT 0x1b 906 + #define LSDMA_PIO_COMMAND__SRC_ADDR_INC__SHIFT 0x1c 907 + #define LSDMA_PIO_COMMAND__DST_ADDR_INC__SHIFT 0x1d 908 + #define LSDMA_PIO_COMMAND__OVERLAP_DISABLE__SHIFT 0x1e 909 + #define LSDMA_PIO_COMMAND__CONSTANT_FILL__SHIFT 0x1f 910 + #define LSDMA_PIO_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL 911 + #define LSDMA_PIO_COMMAND__SRC_LOCATION_MASK 0x04000000L 912 + #define LSDMA_PIO_COMMAND__DST_LOCATION_MASK 0x08000000L 913 + #define LSDMA_PIO_COMMAND__SRC_ADDR_INC_MASK 0x10000000L 914 + #define LSDMA_PIO_COMMAND__DST_ADDR_INC_MASK 0x20000000L 915 + #define LSDMA_PIO_COMMAND__OVERLAP_DISABLE_MASK 0x40000000L 916 + #define LSDMA_PIO_COMMAND__CONSTANT_FILL_MASK 0x80000000L 917 + //LSDMA_PIO_CONSTFILL_DATA 918 + #define LSDMA_PIO_CONSTFILL_DATA__DATA__SHIFT 0x0 919 + #define LSDMA_PIO_CONSTFILL_DATA__DATA_MASK 0xFFFFFFFFL 920 + //LSDMA_PIO_CONTROL 921 + #define LSDMA_PIO_CONTROL__VMID__SHIFT 0x0 922 + #define LSDMA_PIO_CONTROL__DST_GPA__SHIFT 0x4 923 + #define LSDMA_PIO_CONTROL__DST_SYS__SHIFT 0x5 924 + #define LSDMA_PIO_CONTROL__DST_GCC__SHIFT 0x6 925 + #define LSDMA_PIO_CONTROL__DST_SNOOP__SHIFT 0x7 926 + #define LSDMA_PIO_CONTROL__DST_REUSE_HINT__SHIFT 0x8 927 + #define LSDMA_PIO_CONTROL__DST_COMP_EN__SHIFT 0xa 928 + #define LSDMA_PIO_CONTROL__SRC_GPA__SHIFT 0x14 929 + #define LSDMA_PIO_CONTROL__SRC_SYS__SHIFT 0x15 930 + #define LSDMA_PIO_CONTROL__SRC_SNOOP__SHIFT 0x17 931 + #define LSDMA_PIO_CONTROL__SRC_REUSE_HINT__SHIFT 0x18 932 + #define LSDMA_PIO_CONTROL__SRC_COMP_EN__SHIFT 0x1a 933 + #define LSDMA_PIO_CONTROL__VMID_MASK 0x0000000FL 934 + #define LSDMA_PIO_CONTROL__DST_GPA_MASK 0x00000010L 935 + #define LSDMA_PIO_CONTROL__DST_SYS_MASK 0x00000020L 936 + #define LSDMA_PIO_CONTROL__DST_GCC_MASK 0x00000040L 937 + #define LSDMA_PIO_CONTROL__DST_SNOOP_MASK 0x00000080L 938 + #define LSDMA_PIO_CONTROL__DST_REUSE_HINT_MASK 0x00000300L 939 + #define LSDMA_PIO_CONTROL__DST_COMP_EN_MASK 0x00000400L 940 + #define LSDMA_PIO_CONTROL__SRC_GPA_MASK 0x00100000L 941 + #define LSDMA_PIO_CONTROL__SRC_SYS_MASK 0x00200000L 942 + #define LSDMA_PIO_CONTROL__SRC_SNOOP_MASK 0x00800000L 943 + #define LSDMA_PIO_CONTROL__SRC_REUSE_HINT_MASK 0x03000000L 944 + #define LSDMA_PIO_CONTROL__SRC_COMP_EN_MASK 0x04000000L 945 + //LSDMA_PIO_STATUS 946 + #define LSDMA_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 947 + #define LSDMA_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 948 + #define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR__SHIFT 0x8 949 + #define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9 950 + #define LSDMA_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa 951 + #define LSDMA_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb 952 + #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf 953 + #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 954 + #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 955 + #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 956 + #define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c 957 + #define LSDMA_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d 958 + #define LSDMA_PIO_STATUS__PIO_IDLE__SHIFT 0x1f 959 + #define LSDMA_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L 960 + #define LSDMA_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L 961 + #define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR_MASK 0x00000100L 962 + #define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L 963 + #define LSDMA_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L 964 + #define LSDMA_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L 965 + #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L 966 + #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L 967 + #define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L 968 + #define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L 969 + #define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L 970 + #define LSDMA_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L 971 + #define LSDMA_PIO_STATUS__PIO_IDLE_MASK 0x80000000L 972 + //LSDMA_PF_PIO_STATUS 973 + #define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 974 + #define LSDMA_PF_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 975 + #define LSDMA_PF_PIO_STATUS__ERROR_INVALID_ADDR__SHIFT 0x8 976 + #define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0x9 977 + #define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xa 978 + #define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xb 979 + #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf 980 + #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 981 + #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 982 + #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 983 + #define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c 984 + #define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d 985 + #define LSDMA_PF_PIO_STATUS__PIO_IDLE__SHIFT 0x1f 986 + #define LSDMA_PF_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L 987 + #define LSDMA_PF_PIO_STATUS__CMD_PROCESSING_MASK 0x000000F8L 988 + #define LSDMA_PF_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00000200L 989 + #define LSDMA_PF_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00000400L 990 + #define LSDMA_PF_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00000800L 991 + #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L 992 + #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L 993 + #define LSDMA_PF_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L 994 + #define LSDMA_PF_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L 995 + #define LSDMA_PF_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L 996 + #define LSDMA_PF_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L 997 + #define LSDMA_PF_PIO_STATUS__PIO_IDLE_MASK 0x80000000L 998 + //LSDMA_QUEUE0_RB_CNTL 999 + #define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1000 + #define LSDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 1001 + #define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1002 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1003 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1004 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1005 + #define LSDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 1006 + #define LSDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 1007 + #define LSDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1008 + #define LSDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1009 + #define LSDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1010 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1011 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1012 + #define LSDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1013 + #define LSDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1014 + //LSDMA_QUEUE0_RB_BASE 1015 + #define LSDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 1016 + #define LSDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1017 + //LSDMA_QUEUE0_RB_BASE_HI 1018 + #define LSDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 1019 + #define LSDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1020 + //LSDMA_QUEUE0_RB_RPTR 1021 + #define LSDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 1022 + #define LSDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1023 + //LSDMA_QUEUE0_RB_RPTR_HI 1024 + #define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1025 + #define LSDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1026 + //LSDMA_QUEUE0_RB_WPTR 1027 + #define LSDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 1028 + #define LSDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1029 + //LSDMA_QUEUE0_RB_WPTR_HI 1030 + #define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1031 + #define LSDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1032 + //LSDMA_QUEUE0_RB_WPTR_POLL_CNTL 1033 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1034 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1035 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1036 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1037 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1038 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1039 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1040 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1041 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1042 + #define LSDMA_QUEUE0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1043 + //LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 1044 + #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1045 + #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1046 + //LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 1047 + #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1048 + #define LSDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1049 + //LSDMA_QUEUE0_RB_RPTR_ADDR_HI 1050 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1051 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1052 + //LSDMA_QUEUE0_RB_RPTR_ADDR_LO 1053 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1054 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1055 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1056 + #define LSDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1057 + //LSDMA_QUEUE0_IB_CNTL 1058 + #define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1059 + #define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1060 + #define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1061 + #define LSDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 1062 + #define LSDMA_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f 1063 + #define LSDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1064 + #define LSDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1065 + #define LSDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1066 + #define LSDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1067 + //LSDMA_QUEUE0_IB_RPTR 1068 + #define LSDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 1069 + #define LSDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1070 + //LSDMA_QUEUE0_IB_OFFSET 1071 + #define LSDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 1072 + #define LSDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1073 + //LSDMA_QUEUE0_IB_BASE_LO 1074 + #define LSDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 1075 + #define LSDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1076 + //LSDMA_QUEUE0_IB_BASE_HI 1077 + #define LSDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 1078 + #define LSDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1079 + //LSDMA_QUEUE0_IB_SIZE 1080 + #define LSDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 1081 + #define LSDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1082 + //LSDMA_QUEUE0_SKIP_CNTL 1083 + #define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1084 + #define LSDMA_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1085 + //LSDMA_QUEUE0_CSA_ADDR_LO 1086 + #define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1087 + #define LSDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1088 + //LSDMA_QUEUE0_CSA_ADDR_HI 1089 + #define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1090 + #define LSDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1091 + //LSDMA_QUEUE0_RB_AQL_CNTL 1092 + #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1093 + #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1094 + #define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1095 + #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1096 + #define LSDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1097 + #define LSDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1098 + //LSDMA_QUEUE0_MINOR_PTR_UPDATE 1099 + #define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1100 + #define LSDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1101 + //LSDMA_QUEUE0_CNTL 1102 + #define LSDMA_QUEUE0_CNTL__QUANTUM__SHIFT 0x0 1103 + #define LSDMA_QUEUE0_CNTL__QUANTUM_MASK 0x000000FFL 1104 + //LSDMA_QUEUE0_RB_PREEMPT 1105 + #define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1106 + #define LSDMA_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1107 + //LSDMA_QUEUE0_IB_SUB_REMAIN 1108 + #define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1109 + #define LSDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1110 + //LSDMA_QUEUE0_PREEMPT 1111 + #define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1112 + #define LSDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1113 + //LSDMA_QUEUE0_CONTEXT_STATUS 1114 + #define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1115 + #define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1116 + #define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1117 + #define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1118 + #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1119 + #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1120 + #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1121 + #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1122 + #define LSDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1123 + #define LSDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1124 + #define LSDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1125 + #define LSDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1126 + #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1127 + #define LSDMA_QUEUE0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1128 + #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1129 + #define LSDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1130 + //LSDMA_QUEUE0_STATUS 1131 + #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1132 + #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1133 + #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1134 + #define LSDMA_QUEUE0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1135 + //LSDMA_QUEUE0_DOORBELL 1136 + #define LSDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c 1137 + #define LSDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e 1138 + #define LSDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L 1139 + #define LSDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L 1140 + //LSDMA_QUEUE0_DOORBELL_OFFSET 1141 + #define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1142 + #define LSDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1143 + //LSDMA_QUEUE0_DOORBELL_LOG 1144 + #define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1145 + #define LSDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 1146 + #define LSDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1147 + #define LSDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1148 + //LSDMA_QUEUE0_WATERMARK 1149 + #define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1150 + #define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1151 + #define LSDMA_QUEUE0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1152 + #define LSDMA_QUEUE0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1153 + //LSDMA_QUEUE0_DUMMY0 1154 + #define LSDMA_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 1155 + #define LSDMA_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1156 + //LSDMA_QUEUE0_DUMMY1 1157 + #define LSDMA_QUEUE0_DUMMY1__DUMMY__SHIFT 0x0 1158 + #define LSDMA_QUEUE0_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 1159 + //LSDMA_QUEUE0_DUMMY2 1160 + #define LSDMA_QUEUE0_DUMMY2__DUMMY__SHIFT 0x0 1161 + #define LSDMA_QUEUE0_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 1162 + //LSDMA_QUEUE0_MIDCMD_DATA0 1163 + #define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1164 + #define LSDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1165 + //LSDMA_QUEUE0_MIDCMD_DATA1 1166 + #define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1167 + #define LSDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1168 + //LSDMA_QUEUE0_MIDCMD_DATA2 1169 + #define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1170 + #define LSDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1171 + //LSDMA_QUEUE0_MIDCMD_DATA3 1172 + #define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1173 + #define LSDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1174 + //LSDMA_QUEUE0_MIDCMD_DATA4 1175 + #define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1176 + #define LSDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1177 + //LSDMA_QUEUE0_MIDCMD_DATA5 1178 + #define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1179 + #define LSDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1180 + //LSDMA_QUEUE0_MIDCMD_DATA6 1181 + #define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1182 + #define LSDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1183 + //LSDMA_QUEUE0_MIDCMD_DATA7 1184 + #define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1185 + #define LSDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1186 + //LSDMA_QUEUE0_MIDCMD_DATA8 1187 + #define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1188 + #define LSDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1189 + //LSDMA_QUEUE0_MIDCMD_DATA9 1190 + #define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 1191 + #define LSDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1192 + //LSDMA_QUEUE0_MIDCMD_DATA10 1193 + #define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 1194 + #define LSDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1195 + //LSDMA_QUEUE0_MIDCMD_CNTL 1196 + #define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1197 + #define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1198 + #define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1199 + #define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1200 + #define LSDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1201 + #define LSDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1202 + #define LSDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1203 + #define LSDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1204 + //LSDMA_QUEUE1_RB_CNTL 1205 + #define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1206 + #define LSDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 1207 + #define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1208 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1209 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1210 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1211 + #define LSDMA_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 1212 + #define LSDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 1213 + #define LSDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1214 + #define LSDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL 1215 + #define LSDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1216 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1217 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1218 + #define LSDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1219 + #define LSDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1220 + //LSDMA_QUEUE1_RB_BASE 1221 + #define LSDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 1222 + #define LSDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1223 + //LSDMA_QUEUE1_RB_BASE_HI 1224 + #define LSDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 1225 + #define LSDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1226 + //LSDMA_QUEUE1_RB_RPTR 1227 + #define LSDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 1228 + #define LSDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1229 + //LSDMA_QUEUE1_RB_RPTR_HI 1230 + #define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1231 + #define LSDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1232 + //LSDMA_QUEUE1_RB_WPTR 1233 + #define LSDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 1234 + #define LSDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1235 + //LSDMA_QUEUE1_RB_WPTR_HI 1236 + #define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1237 + #define LSDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1238 + //LSDMA_QUEUE1_RB_WPTR_POLL_CNTL 1239 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1240 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1241 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1242 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1243 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1244 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1245 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1246 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1247 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1248 + #define LSDMA_QUEUE1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1249 + //LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 1250 + #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1251 + #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1252 + //LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 1253 + #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1254 + #define LSDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1255 + //LSDMA_QUEUE1_RB_RPTR_ADDR_HI 1256 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1257 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1258 + //LSDMA_QUEUE1_RB_RPTR_ADDR_LO 1259 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 1260 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1261 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L 1262 + #define LSDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1263 + //LSDMA_QUEUE1_IB_CNTL 1264 + #define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1265 + #define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1266 + #define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1267 + #define LSDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 1268 + #define LSDMA_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f 1269 + #define LSDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1270 + #define LSDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1271 + #define LSDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1272 + #define LSDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1273 + //LSDMA_QUEUE1_IB_RPTR 1274 + #define LSDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 1275 + #define LSDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1276 + //LSDMA_QUEUE1_IB_OFFSET 1277 + #define LSDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 1278 + #define LSDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1279 + //LSDMA_QUEUE1_IB_BASE_LO 1280 + #define LSDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 1281 + #define LSDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1282 + //LSDMA_QUEUE1_IB_BASE_HI 1283 + #define LSDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 1284 + #define LSDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1285 + //LSDMA_QUEUE1_IB_SIZE 1286 + #define LSDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 1287 + #define LSDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1288 + //LSDMA_QUEUE1_SKIP_CNTL 1289 + #define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1290 + #define LSDMA_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL 1291 + //LSDMA_QUEUE1_CSA_ADDR_LO 1292 + #define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1293 + #define LSDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1294 + //LSDMA_QUEUE1_CSA_ADDR_HI 1295 + #define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1296 + #define LSDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1297 + //LSDMA_QUEUE1_RB_AQL_CNTL 1298 + #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1299 + #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1300 + #define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1301 + #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1302 + #define LSDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1303 + #define LSDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1304 + //LSDMA_QUEUE1_MINOR_PTR_UPDATE 1305 + #define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1306 + #define LSDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1307 + //LSDMA_QUEUE1_CNTL 1308 + #define LSDMA_QUEUE1_CNTL__QUANTUM__SHIFT 0x0 1309 + #define LSDMA_QUEUE1_CNTL__QUANTUM_MASK 0x000000FFL 1310 + //LSDMA_QUEUE1_RB_PREEMPT 1311 + #define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 1312 + #define LSDMA_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L 1313 + //LSDMA_QUEUE1_IB_SUB_REMAIN 1314 + #define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1315 + #define LSDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL 1316 + //LSDMA_QUEUE1_PREEMPT 1317 + #define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1318 + #define LSDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1319 + //LSDMA_QUEUE1_CONTEXT_STATUS 1320 + #define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1321 + #define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1322 + #define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1323 + #define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1324 + #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1325 + #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1326 + #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1327 + #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1328 + #define LSDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1329 + #define LSDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1330 + #define LSDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1331 + #define LSDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1332 + #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1333 + #define LSDMA_QUEUE1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1334 + #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1335 + #define LSDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1336 + //LSDMA_QUEUE1_STATUS 1337 + #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1338 + #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1339 + #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1340 + #define LSDMA_QUEUE1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1341 + //LSDMA_QUEUE1_DOORBELL 1342 + #define LSDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c 1343 + #define LSDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e 1344 + #define LSDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L 1345 + #define LSDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L 1346 + //LSDMA_QUEUE1_DOORBELL_OFFSET 1347 + #define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1348 + #define LSDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1349 + //LSDMA_QUEUE1_DOORBELL_LOG 1350 + #define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1351 + #define LSDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 1352 + #define LSDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1353 + #define LSDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1354 + //LSDMA_QUEUE1_WATERMARK 1355 + #define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1356 + #define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1357 + #define LSDMA_QUEUE1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1358 + #define LSDMA_QUEUE1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1359 + //LSDMA_QUEUE1_DUMMY0 1360 + #define LSDMA_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 1361 + #define LSDMA_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL 1362 + //LSDMA_QUEUE1_DUMMY1 1363 + #define LSDMA_QUEUE1_DUMMY1__DUMMY__SHIFT 0x0 1364 + #define LSDMA_QUEUE1_DUMMY1__DUMMY_MASK 0xFFFFFFFFL 1365 + //LSDMA_QUEUE1_DUMMY2 1366 + #define LSDMA_QUEUE1_DUMMY2__DUMMY__SHIFT 0x0 1367 + #define LSDMA_QUEUE1_DUMMY2__DUMMY_MASK 0xFFFFFFFFL 1368 + //LSDMA_QUEUE1_MIDCMD_DATA0 1369 + #define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1370 + #define LSDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1371 + //LSDMA_QUEUE1_MIDCMD_DATA1 1372 + #define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1373 + #define LSDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1374 + //LSDMA_QUEUE1_MIDCMD_DATA2 1375 + #define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1376 + #define LSDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1377 + //LSDMA_QUEUE1_MIDCMD_DATA3 1378 + #define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1379 + #define LSDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1380 + //LSDMA_QUEUE1_MIDCMD_DATA4 1381 + #define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1382 + #define LSDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1383 + //LSDMA_QUEUE1_MIDCMD_DATA5 1384 + #define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1385 + #define LSDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1386 + //LSDMA_QUEUE1_MIDCMD_DATA6 1387 + #define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1388 + #define LSDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1389 + //LSDMA_QUEUE1_MIDCMD_DATA7 1390 + #define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1391 + #define LSDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1392 + //LSDMA_QUEUE1_MIDCMD_DATA8 1393 + #define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1394 + #define LSDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1395 + //LSDMA_QUEUE1_MIDCMD_DATA9 1396 + #define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 1397 + #define LSDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL 1398 + //LSDMA_QUEUE1_MIDCMD_DATA10 1399 + #define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 1400 + #define LSDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL 1401 + //LSDMA_QUEUE1_MIDCMD_CNTL 1402 + #define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1403 + #define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1404 + #define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1405 + #define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1406 + #define LSDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1407 + #define LSDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1408 + #define LSDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1409 + #define LSDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1410 + 1411 + #endif