tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: dispcc-sc7180: use parent_hws where possible

Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-18-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Dmitry Baryshkov and committed by
Stephen Boyd f8fae78c 789ab2c2

+34 -34
+34 -34
drivers/clk/qcom/dispcc-sc7180.c
··· 63 63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], 64 64 .clkr.hw.init = &(struct clk_init_data){ 65 65 .name = "disp_cc_pll0_out_even", 66 - .parent_data = &(const struct clk_parent_data){ 67 - .hw = &disp_cc_pll0.clkr.hw, 66 + .parent_hws = (const struct clk_hw*[]){ 67 + &disp_cc_pll0.clkr.hw, 68 68 }, 69 69 .num_parents = 1, 70 70 .flags = CLK_SET_RATE_PARENT, ··· 317 317 .enable_mask = BIT(0), 318 318 .hw.init = &(struct clk_init_data){ 319 319 .name = "disp_cc_mdss_ahb_clk", 320 - .parent_data = &(const struct clk_parent_data){ 321 - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, 320 + .parent_hws = (const struct clk_hw*[]){ 321 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 322 322 }, 323 323 .num_parents = 1, 324 324 .flags = CLK_SET_RATE_PARENT, ··· 335 335 .enable_mask = BIT(0), 336 336 .hw.init = &(struct clk_init_data){ 337 337 .name = "disp_cc_mdss_byte0_clk", 338 - .parent_data = &(const struct clk_parent_data){ 339 - .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, 338 + .parent_hws = (const struct clk_hw*[]){ 339 + &disp_cc_mdss_byte0_clk_src.clkr.hw, 340 340 }, 341 341 .num_parents = 1, 342 342 .flags = CLK_SET_RATE_PARENT, ··· 381 381 .enable_mask = BIT(0), 382 382 .hw.init = &(struct clk_init_data){ 383 383 .name = "disp_cc_mdss_byte0_intf_clk", 384 - .parent_data = &(const struct clk_parent_data){ 385 - .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 384 + .parent_hws = (const struct clk_hw*[]){ 385 + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 386 386 }, 387 387 .num_parents = 1, 388 388 .flags = CLK_SET_RATE_PARENT, ··· 399 399 .enable_mask = BIT(0), 400 400 .hw.init = &(struct clk_init_data){ 401 401 .name = "disp_cc_mdss_dp_aux_clk", 402 - .parent_data = &(const struct clk_parent_data){ 403 - .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 402 + .parent_hws = (const struct clk_hw*[]){ 403 + &disp_cc_mdss_dp_aux_clk_src.clkr.hw, 404 404 }, 405 405 .num_parents = 1, 406 406 .flags = CLK_SET_RATE_PARENT, ··· 417 417 .enable_mask = BIT(0), 418 418 .hw.init = &(struct clk_init_data){ 419 419 .name = "disp_cc_mdss_dp_crypto_clk", 420 - .parent_data = &(const struct clk_parent_data){ 421 - .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, 420 + .parent_hws = (const struct clk_hw*[]){ 421 + &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, 422 422 }, 423 423 .num_parents = 1, 424 424 .flags = CLK_SET_RATE_PARENT, ··· 435 435 .enable_mask = BIT(0), 436 436 .hw.init = &(struct clk_init_data){ 437 437 .name = "disp_cc_mdss_dp_link_clk", 438 - .parent_data = &(const struct clk_parent_data){ 439 - .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, 438 + .parent_hws = (const struct clk_hw*[]){ 439 + &disp_cc_mdss_dp_link_clk_src.clkr.hw, 440 440 }, 441 441 .num_parents = 1, 442 442 .flags = CLK_SET_RATE_PARENT, ··· 453 453 .enable_mask = BIT(0), 454 454 .hw.init = &(struct clk_init_data){ 455 455 .name = "disp_cc_mdss_dp_link_intf_clk", 456 - .parent_data = &(const struct clk_parent_data){ 457 - .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 456 + .parent_hws = (const struct clk_hw*[]){ 457 + &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, 458 458 }, 459 459 .num_parents = 1, 460 460 .ops = &clk_branch2_ops, ··· 470 470 .enable_mask = BIT(0), 471 471 .hw.init = &(struct clk_init_data){ 472 472 .name = "disp_cc_mdss_dp_pixel_clk", 473 - .parent_data = &(const struct clk_parent_data){ 474 - .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 473 + .parent_hws = (const struct clk_hw*[]){ 474 + &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, 475 475 }, 476 476 .num_parents = 1, 477 477 .flags = CLK_SET_RATE_PARENT, ··· 488 488 .enable_mask = BIT(0), 489 489 .hw.init = &(struct clk_init_data){ 490 490 .name = "disp_cc_mdss_esc0_clk", 491 - .parent_data = &(const struct clk_parent_data){ 492 - .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, 491 + .parent_hws = (const struct clk_hw*[]){ 492 + &disp_cc_mdss_esc0_clk_src.clkr.hw, 493 493 }, 494 494 .num_parents = 1, 495 495 .flags = CLK_SET_RATE_PARENT, ··· 506 506 .enable_mask = BIT(0), 507 507 .hw.init = &(struct clk_init_data){ 508 508 .name = "disp_cc_mdss_mdp_clk", 509 - .parent_data = &(const struct clk_parent_data){ 510 - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, 509 + .parent_hws = (const struct clk_hw*[]){ 510 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 511 511 }, 512 512 .num_parents = 1, 513 513 .flags = CLK_SET_RATE_PARENT, ··· 524 524 .enable_mask = BIT(0), 525 525 .hw.init = &(struct clk_init_data){ 526 526 .name = "disp_cc_mdss_mdp_lut_clk", 527 - .parent_data = &(const struct clk_parent_data){ 528 - .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, 527 + .parent_hws = (const struct clk_hw*[]){ 528 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 529 529 }, 530 530 .num_parents = 1, 531 531 .ops = &clk_branch2_ops, ··· 541 541 .enable_mask = BIT(0), 542 542 .hw.init = &(struct clk_init_data){ 543 543 .name = "disp_cc_mdss_non_gdsc_ahb_clk", 544 - .parent_data = &(const struct clk_parent_data){ 545 - .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, 544 + .parent_hws = (const struct clk_hw*[]){ 545 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 546 546 }, 547 547 .num_parents = 1, 548 548 .flags = CLK_SET_RATE_PARENT, ··· 559 559 .enable_mask = BIT(0), 560 560 .hw.init = &(struct clk_init_data){ 561 561 .name = "disp_cc_mdss_pclk0_clk", 562 - .parent_data = &(const struct clk_parent_data){ 563 - .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, 562 + .parent_hws = (const struct clk_hw*[]){ 563 + &disp_cc_mdss_pclk0_clk_src.clkr.hw, 564 564 }, 565 565 .num_parents = 1, 566 566 .flags = CLK_SET_RATE_PARENT, ··· 577 577 .enable_mask = BIT(0), 578 578 .hw.init = &(struct clk_init_data){ 579 579 .name = "disp_cc_mdss_rot_clk", 580 - .parent_data = &(const struct clk_parent_data){ 581 - .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, 580 + .parent_hws = (const struct clk_hw*[]){ 581 + &disp_cc_mdss_rot_clk_src.clkr.hw, 582 582 }, 583 583 .num_parents = 1, 584 584 .flags = CLK_SET_RATE_PARENT, ··· 595 595 .enable_mask = BIT(0), 596 596 .hw.init = &(struct clk_init_data){ 597 597 .name = "disp_cc_mdss_rscc_vsync_clk", 598 - .parent_data = &(const struct clk_parent_data){ 599 - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, 598 + .parent_hws = (const struct clk_hw*[]){ 599 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 600 600 }, 601 601 .num_parents = 1, 602 602 .flags = CLK_SET_RATE_PARENT, ··· 613 613 .enable_mask = BIT(0), 614 614 .hw.init = &(struct clk_init_data){ 615 615 .name = "disp_cc_mdss_vsync_clk", 616 - .parent_data = &(const struct clk_parent_data){ 617 - .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, 616 + .parent_hws = (const struct clk_hw*[]){ 617 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 618 618 }, 619 619 .num_parents = 1, 620 620 .flags = CLK_SET_RATE_PARENT,