tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'late-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC i.MX DT changes from Olof Johansson:
"This branch contains of devicetree changes for the Freescale i.MX
platform.
The base patch of the branch changes the format of the dts files to a
slightly different format that makes it easier to do derivative board
definitions, but it also introduces a lot of churn in the process
since every line of the file is touched.
On top of that are a handful of the regular changes; enabling more
boards as DT-based instead of legacy board files (mx25pdk), enabling
another driver for devicetree and thus adding bindings (onewire), etc.
I'm not happy about the churn, and will likely not take it for other
platforms in the future."
* tag 'late-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (21 commits)
ARM: dts: add dtsi for imx6q and imx6dl
ARM: dts: rename imx6q.dtsi to imx6qdl.dtsi
ARM: dts: i.MX6: Add regulator delay support
ARM: dts: Add device tree entry for onewire master on i.MX53
ARM: i.MX53: Add clocks for i.mx53 onewire master.
W1: Add device tree support to MXC onewire master.
ARM: imx: enable imx6q-cpufreq support
ARM: dts: Add apf51 basic support
ARM i.MX6: change mxs usbphy clock usage
ARM: dts: imx6q: Remove silicon version from SDMA firmware
ARM i.MX53: dts: add oftree for MBa53 baseboard
ARM i.MX53: add dts for the TQ tqma53 module
ARM: dts: imx53: pinctrl update
ARM i.MX51 babbage: Add keypad support
ARM: dts: imx: Add imx51 KPP entry
ARM: dts: imx25-karo-tx25: Put status entry in the end
ARM: mx25pdk: Add device tree support
ARM: dts: imx: use nodes label in board dts
ARM: dts: add missing imx dtb targets
ARM: boot: dts: Add an entry for imx27-pdk.dtb
...
+2562
-1886
+6
Documentation/devicetree/bindings/arm/armadeus.txt
+6
Documentation/devicetree/bindings/arm/armadeus.txt
+8
Documentation/devicetree/bindings/arm/fsl.txt
+8
Documentation/devicetree/bindings/arm/fsl.txt
···
5
5
Required root node properties:
6
6
- compatible = "fsl,imx23-evk", "fsl,imx23";
7
7
8
+
i.MX25 Product Development Kit
9
+
Required root node properties:
10
+
- compatible = "fsl,imx25-pdk", "fsl,imx25";
11
+
12
+
i.MX27 Product Development Kit
13
+
Required root node properties:
14
+
- compatible = "fsl,imx27-pdk", "fsl,imx27";
15
+
8
16
i.MX28 Evaluation Kit
9
17
Required root node properties:
10
18
- compatible = "fsl,imx28-evk", "fsl,imx28";
+1
Documentation/devicetree/bindings/clock/imx5-clock.txt
+1
Documentation/devicetree/bindings/clock/imx5-clock.txt
+2
Documentation/devicetree/bindings/clock/imx6q-clock.txt
+2
Documentation/devicetree/bindings/clock/imx6q-clock.txt
+19
Documentation/devicetree/bindings/w1/fsl-imx-owire.txt
+19
Documentation/devicetree/bindings/w1/fsl-imx-owire.txt
···
1
+
* Freescale i.MX One wire bus master controller
2
+
3
+
Required properties:
4
+
- compatible : should be "fsl,imx21-owire"
5
+
- reg : Address and length of the register set for the device
6
+
7
+
Optional properties:
8
+
- clocks : phandle of clock that supplies the module (required if platform
9
+
clock bindings use device tree)
10
+
11
+
Example:
12
+
13
+
- From imx53.dtsi:
14
+
owire: owire@63fa4000 {
15
+
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
16
+
reg = <0x63fa4000 0x4000>;
17
+
clocks = <&clks 159>;
18
+
status = "disabled";
19
+
};
+9
-1
arch/arm/boot/dts/Makefile
+9
-1
arch/arm/boot/dts/Makefile
···
80
80
armada-370-mirabox.dtb \
81
81
armada-xp-db.dtb \
82
82
armada-xp-openblocks-ax3-4.dtb
83
-
dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \
83
+
dtb-$(CONFIG_ARCH_MXC) += \
84
+
imx25-karo-tx25.dtb \
85
+
imx25-pdk.dtb \
86
+
imx27-apf27.dtb \
87
+
imx27-pdk.dtb \
88
+
imx31-bug.dtb \
89
+
imx51-apf51.dtb \
90
+
imx51-babbage.dtb \
84
91
imx53-ard.dtb \
85
92
imx53-evk.dtb \
93
+
imx53-mba53.dtb \
86
94
imx53-qsb.dtb \
87
95
imx53-smd.dtb \
88
96
imx6q-arm2.dtb \
+11
-19
arch/arm/boot/dts/imx25-karo-tx25.dts
+11
-19
arch/arm/boot/dts/imx25-karo-tx25.dts
···
19
19
memory {
20
20
reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21
21
};
22
+
};
22
23
23
-
soc {
24
-
aips@43f00000 {
25
-
uart1: serial@43f90000 {
26
-
status = "okay";
27
-
};
28
-
};
24
+
&uart1 {
25
+
status = "okay";
26
+
};
29
27
30
-
spba@50000000 {
31
-
fec: ethernet@50038000 {
32
-
status = "okay";
33
-
phy-mode = "rmii";
34
-
};
35
-
};
28
+
&fec {
29
+
phy-mode = "rmii";
30
+
status = "okay";
31
+
};
36
32
37
-
emi@80000000 {
38
-
nand@bb000000 {
39
-
nand-on-flash-bbt;
40
-
status = "okay";
41
-
};
42
-
};
43
-
};
33
+
&nfc {
34
+
nand-on-flash-bbt;
35
+
status = "okay";
44
36
};
+36
arch/arm/boot/dts/imx25-pdk.dts
+36
arch/arm/boot/dts/imx25-pdk.dts
···
1
+
/*
2
+
* Copyright 2013 Freescale Semiconductor, Inc.
3
+
*
4
+
* The code contained herein is licensed under the GNU General Public
5
+
* License. You may obtain a copy of the GNU General Public License
6
+
* Version 2 or later at the following locations:
7
+
*
8
+
* http://www.opensource.org/licenses/gpl-license.html
9
+
* http://www.gnu.org/copyleft/gpl.html
10
+
*/
11
+
12
+
/dts-v1/;
13
+
/include/ "imx25.dtsi"
14
+
15
+
/ {
16
+
model = "Freescale i.MX25 Product Development Kit";
17
+
compatible = "fsl,imx25-pdk", "fsl,imx25";
18
+
19
+
memory {
20
+
reg = <0x80000000 0x4000000>;
21
+
};
22
+
};
23
+
24
+
&uart1 {
25
+
status = "okay";
26
+
};
27
+
28
+
&fec {
29
+
phy-mode = "rmii";
30
+
status = "okay";
31
+
};
32
+
33
+
&nfc {
34
+
nand-on-flash-bbt;
35
+
status = "okay";
36
+
};
+1
-1
arch/arm/boot/dts/imx25.dtsi
+1
-1
arch/arm/boot/dts/imx25.dtsi
+9
-15
arch/arm/boot/dts/imx27-3ds.dts
arch/arm/boot/dts/imx27-pdk.dts
+9
-15
arch/arm/boot/dts/imx27-3ds.dts
arch/arm/boot/dts/imx27-pdk.dts
···
13
13
/include/ "imx27.dtsi"
14
14
15
15
/ {
16
-
model = "mx27_3ds";
17
-
compatible = "freescale,imx27-3ds", "fsl,imx27";
16
+
model = "Freescale i.MX27 Product Development Kit";
17
+
compatible = "fsl,imx27-pdk", "fsl,imx27";
18
18
19
19
memory {
20
20
reg = <0x0 0x0>;
21
21
};
22
+
};
22
23
23
-
soc {
24
-
aipi@10000000 { /* aipi1 */
25
-
uart1: serial@1000a000 {
26
-
fsl,uart-has-rtscts;
27
-
status = "okay";
28
-
};
29
-
};
24
+
&uart1 {
25
+
fsl,uart-has-rtscts;
26
+
status = "okay";
27
+
};
30
28
31
-
aipi@10020000 { /* aipi2 */
32
-
ethernet@1002b000 {
33
-
status = "okay";
34
-
};
35
-
};
36
-
};
29
+
&fec {
30
+
status = "okay";
37
31
};
+39
-43
arch/arm/boot/dts/imx27-apf27.dts
+39
-43
arch/arm/boot/dts/imx27-apf27.dts
···
32
32
clock-frequency = <0>;
33
33
};
34
34
};
35
+
};
35
36
36
-
soc {
37
-
aipi@10000000 {
38
-
serial@1000a000 {
39
-
status = "okay";
40
-
};
37
+
&uart1 {
38
+
status = "okay";
39
+
};
41
40
42
-
ethernet@1002b000 {
43
-
status = "okay";
44
-
};
45
-
};
41
+
&fec {
42
+
status = "okay";
43
+
};
46
44
47
-
nand@d8000000 {
48
-
status = "okay";
49
-
nand-bus-width = <16>;
50
-
nand-ecc-mode = "hw";
51
-
nand-on-flash-bbt;
45
+
&nfc {
46
+
status = "okay";
47
+
nand-bus-width = <16>;
48
+
nand-ecc-mode = "hw";
49
+
nand-on-flash-bbt;
52
50
53
-
partition@0 {
54
-
label = "u-boot";
55
-
reg = <0x0 0x100000>;
56
-
};
51
+
partition@0 {
52
+
label = "u-boot";
53
+
reg = <0x0 0x100000>;
54
+
};
57
55
58
-
partition@100000 {
59
-
label = "env";
60
-
reg = <0x100000 0x80000>;
61
-
};
56
+
partition@100000 {
57
+
label = "env";
58
+
reg = <0x100000 0x80000>;
59
+
};
62
60
63
-
partition@180000 {
64
-
label = "env2";
65
-
reg = <0x180000 0x80000>;
66
-
};
61
+
partition@180000 {
62
+
label = "env2";
63
+
reg = <0x180000 0x80000>;
64
+
};
67
65
68
-
partition@200000 {
69
-
label = "firmware";
70
-
reg = <0x200000 0x80000>;
71
-
};
66
+
partition@200000 {
67
+
label = "firmware";
68
+
reg = <0x200000 0x80000>;
69
+
};
72
70
73
-
partition@280000 {
74
-
label = "dtb";
75
-
reg = <0x280000 0x80000>;
76
-
};
71
+
partition@280000 {
72
+
label = "dtb";
73
+
reg = <0x280000 0x80000>;
74
+
};
77
75
78
-
partition@300000 {
79
-
label = "kernel";
80
-
reg = <0x300000 0x500000>;
81
-
};
76
+
partition@300000 {
77
+
label = "kernel";
78
+
reg = <0x300000 0x500000>;
79
+
};
82
80
83
-
partition@800000 {
84
-
label = "rootfs";
85
-
reg = <0x800000 0xf800000>;
86
-
};
87
-
};
81
+
partition@800000 {
82
+
label = "rootfs";
83
+
reg = <0x800000 0xf800000>;
88
84
};
89
85
};
+4
-8
arch/arm/boot/dts/imx31-bug.dts
+4
-8
arch/arm/boot/dts/imx31-bug.dts
···
19
19
memory {
20
20
reg = <0x80000000 0x8000000>; /* 128M */
21
21
};
22
+
};
22
23
23
-
soc {
24
-
aips@43f00000 { /* AIPS1 */
25
-
uart5: serial@43fb4000 {
26
-
fsl,uart-has-rtscts;
27
-
status = "okay";
28
-
};
29
-
};
30
-
};
24
+
&uart5 {
25
+
fsl,uart-has-rtscts;
26
+
status = "okay";
31
27
};
+52
arch/arm/boot/dts/imx51-apf51.dts
+52
arch/arm/boot/dts/imx51-apf51.dts
···
1
+
/*
2
+
* Copyright 2012 Armadeus Systems - <support@armadeus.com>
3
+
* Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
4
+
*
5
+
* Based on mx51-babbage.dts
6
+
* Copyright 2011 Freescale Semiconductor, Inc.
7
+
* Copyright 2011 Linaro Ltd.
8
+
*
9
+
* The code contained herein is licensed under the GNU General Public
10
+
* License. You may obtain a copy of the GNU General Public License
11
+
* Version 2 or later at the following locations:
12
+
*
13
+
* http://www.opensource.org/licenses/gpl-license.html
14
+
* http://www.gnu.org/copyleft/gpl.html
15
+
*/
16
+
17
+
/dts-v1/;
18
+
/include/ "imx51.dtsi"
19
+
20
+
/ {
21
+
model = "Armadeus Systems APF51 module";
22
+
compatible = "armadeus,imx51-apf51", "fsl,imx51";
23
+
24
+
memory {
25
+
reg = <0x90000000 0x20000000>;
26
+
};
27
+
28
+
clocks {
29
+
ckih1 {
30
+
clock-frequency = <0>;
31
+
};
32
+
33
+
osc {
34
+
clock-frequency = <33554432>;
35
+
};
36
+
};
37
+
};
38
+
39
+
&fec {
40
+
pinctrl-names = "default";
41
+
pinctrl-0 = <&pinctrl_fec_2>;
42
+
phy-mode = "mii";
43
+
phy-reset-gpios = <&gpio3 0 0>;
44
+
phy-reset-duration = <1>;
45
+
status = "okay";
46
+
};
47
+
48
+
&uart3 {
49
+
pinctrl-names = "default";
50
+
pinctrl-0 = <&pinctrl_uart3_2>;
51
+
status = "okay";
52
+
};
+246
-232
arch/arm/boot/dts/imx51-babbage.dts
+246
-232
arch/arm/boot/dts/imx51-babbage.dts
···
21
21
reg = <0x90000000 0x20000000>;
22
22
};
23
23
24
-
soc {
25
-
display@di0 {
26
-
compatible = "fsl,imx-parallel-display";
27
-
crtcs = <&ipu 0>;
28
-
interface-pix-fmt = "rgb24";
29
-
pinctrl-names = "default";
30
-
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
31
-
};
24
+
display@di0 {
25
+
compatible = "fsl,imx-parallel-display";
26
+
crtcs = <&ipu 0>;
27
+
interface-pix-fmt = "rgb24";
28
+
pinctrl-names = "default";
29
+
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
30
+
};
32
31
33
-
display@di1 {
34
-
compatible = "fsl,imx-parallel-display";
35
-
crtcs = <&ipu 1>;
36
-
interface-pix-fmt = "rgb565";
37
-
pinctrl-names = "default";
38
-
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
39
-
};
40
-
41
-
aips@70000000 { /* aips-1 */
42
-
spba@70000000 {
43
-
esdhc@70004000 { /* ESDHC1 */
44
-
pinctrl-names = "default";
45
-
pinctrl-0 = <&pinctrl_esdhc1_1>;
46
-
fsl,cd-controller;
47
-
fsl,wp-controller;
48
-
status = "okay";
49
-
};
50
-
51
-
esdhc@70008000 { /* ESDHC2 */
52
-
pinctrl-names = "default";
53
-
pinctrl-0 = <&pinctrl_esdhc2_1>;
54
-
cd-gpios = <&gpio1 6 0>;
55
-
wp-gpios = <&gpio1 5 0>;
56
-
status = "okay";
57
-
};
58
-
59
-
uart3: serial@7000c000 {
60
-
pinctrl-names = "default";
61
-
pinctrl-0 = <&pinctrl_uart3_1>;
62
-
fsl,uart-has-rtscts;
63
-
status = "okay";
64
-
};
65
-
66
-
ecspi@70010000 { /* ECSPI1 */
67
-
pinctrl-names = "default";
68
-
pinctrl-0 = <&pinctrl_ecspi1_1>;
69
-
fsl,spi-num-chipselects = <2>;
70
-
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
71
-
status = "okay";
72
-
73
-
pmic: mc13892@0 {
74
-
#address-cells = <1>;
75
-
#size-cells = <0>;
76
-
compatible = "fsl,mc13892";
77
-
spi-max-frequency = <6000000>;
78
-
reg = <0>;
79
-
interrupt-parent = <&gpio1>;
80
-
interrupts = <8 0x4>;
81
-
82
-
regulators {
83
-
sw1_reg: sw1 {
84
-
regulator-min-microvolt = <600000>;
85
-
regulator-max-microvolt = <1375000>;
86
-
regulator-boot-on;
87
-
regulator-always-on;
88
-
};
89
-
90
-
sw2_reg: sw2 {
91
-
regulator-min-microvolt = <900000>;
92
-
regulator-max-microvolt = <1850000>;
93
-
regulator-boot-on;
94
-
regulator-always-on;
95
-
};
96
-
97
-
sw3_reg: sw3 {
98
-
regulator-min-microvolt = <1100000>;
99
-
regulator-max-microvolt = <1850000>;
100
-
regulator-boot-on;
101
-
regulator-always-on;
102
-
};
103
-
104
-
sw4_reg: sw4 {
105
-
regulator-min-microvolt = <1100000>;
106
-
regulator-max-microvolt = <1850000>;
107
-
regulator-boot-on;
108
-
regulator-always-on;
109
-
};
110
-
111
-
vpll_reg: vpll {
112
-
regulator-min-microvolt = <1050000>;
113
-
regulator-max-microvolt = <1800000>;
114
-
regulator-boot-on;
115
-
regulator-always-on;
116
-
};
117
-
118
-
vdig_reg: vdig {
119
-
regulator-min-microvolt = <1650000>;
120
-
regulator-max-microvolt = <1650000>;
121
-
regulator-boot-on;
122
-
};
123
-
124
-
vsd_reg: vsd {
125
-
regulator-min-microvolt = <1800000>;
126
-
regulator-max-microvolt = <3150000>;
127
-
};
128
-
129
-
vusb2_reg: vusb2 {
130
-
regulator-min-microvolt = <2400000>;
131
-
regulator-max-microvolt = <2775000>;
132
-
regulator-boot-on;
133
-
regulator-always-on;
134
-
};
135
-
136
-
vvideo_reg: vvideo {
137
-
regulator-min-microvolt = <2775000>;
138
-
regulator-max-microvolt = <2775000>;
139
-
};
140
-
141
-
vaudio_reg: vaudio {
142
-
regulator-min-microvolt = <2300000>;
143
-
regulator-max-microvolt = <3000000>;
144
-
};
145
-
146
-
vcam_reg: vcam {
147
-
regulator-min-microvolt = <2500000>;
148
-
regulator-max-microvolt = <3000000>;
149
-
};
150
-
151
-
vgen1_reg: vgen1 {
152
-
regulator-min-microvolt = <1200000>;
153
-
regulator-max-microvolt = <1200000>;
154
-
};
155
-
156
-
vgen2_reg: vgen2 {
157
-
regulator-min-microvolt = <1200000>;
158
-
regulator-max-microvolt = <3150000>;
159
-
regulator-always-on;
160
-
};
161
-
162
-
vgen3_reg: vgen3 {
163
-
regulator-min-microvolt = <1800000>;
164
-
regulator-max-microvolt = <2900000>;
165
-
regulator-always-on;
166
-
};
167
-
};
168
-
};
169
-
170
-
flash: at45db321d@1 {
171
-
#address-cells = <1>;
172
-
#size-cells = <1>;
173
-
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
174
-
spi-max-frequency = <25000000>;
175
-
reg = <1>;
176
-
177
-
partition@0 {
178
-
label = "U-Boot";
179
-
reg = <0x0 0x40000>;
180
-
read-only;
181
-
};
182
-
183
-
partition@40000 {
184
-
label = "Kernel";
185
-
reg = <0x40000 0x3c0000>;
186
-
};
187
-
};
188
-
};
189
-
190
-
ssi2: ssi@70014000 {
191
-
fsl,mode = "i2s-slave";
192
-
status = "okay";
193
-
};
194
-
};
195
-
196
-
iomuxc@73fa8000 {
197
-
pinctrl-names = "default";
198
-
pinctrl-0 = <&pinctrl_hog>;
199
-
200
-
hog {
201
-
pinctrl_hog: hoggrp {
202
-
fsl,pins = <
203
-
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
204
-
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
205
-
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
206
-
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
207
-
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
208
-
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
209
-
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
210
-
>;
211
-
};
212
-
};
213
-
};
214
-
215
-
uart1: serial@73fbc000 {
216
-
pinctrl-names = "default";
217
-
pinctrl-0 = <&pinctrl_uart1_1>;
218
-
fsl,uart-has-rtscts;
219
-
status = "okay";
220
-
};
221
-
222
-
uart2: serial@73fc0000 {
223
-
pinctrl-names = "default";
224
-
pinctrl-0 = <&pinctrl_uart2_1>;
225
-
status = "okay";
226
-
};
227
-
};
228
-
229
-
aips@80000000 { /* aips-2 */
230
-
i2c@83fc4000 { /* I2C2 */
231
-
pinctrl-names = "default";
232
-
pinctrl-0 = <&pinctrl_i2c2_1>;
233
-
status = "okay";
234
-
235
-
sgtl5000: codec@0a {
236
-
compatible = "fsl,sgtl5000";
237
-
reg = <0x0a>;
238
-
clock-frequency = <26000000>;
239
-
VDDA-supply = <&vdig_reg>;
240
-
VDDIO-supply = <&vvideo_reg>;
241
-
};
242
-
};
243
-
244
-
audmux@83fd0000 {
245
-
pinctrl-names = "default";
246
-
pinctrl-0 = <&pinctrl_audmux_1>;
247
-
status = "okay";
248
-
};
249
-
250
-
ethernet@83fec000 {
251
-
pinctrl-names = "default";
252
-
pinctrl-0 = <&pinctrl_fec_1>;
253
-
phy-mode = "mii";
254
-
status = "okay";
255
-
};
256
-
};
32
+
display@di1 {
33
+
compatible = "fsl,imx-parallel-display";
34
+
crtcs = <&ipu 1>;
35
+
interface-pix-fmt = "rgb565";
36
+
pinctrl-names = "default";
37
+
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
257
38
};
258
39
259
40
gpio-keys {
···
61
280
mux-int-port = <2>;
62
281
mux-ext-port = <3>;
63
282
};
283
+
};
284
+
285
+
&esdhc1 {
286
+
pinctrl-names = "default";
287
+
pinctrl-0 = <&pinctrl_esdhc1_1>;
288
+
fsl,cd-controller;
289
+
fsl,wp-controller;
290
+
status = "okay";
291
+
};
292
+
293
+
&esdhc2 {
294
+
pinctrl-names = "default";
295
+
pinctrl-0 = <&pinctrl_esdhc2_1>;
296
+
cd-gpios = <&gpio1 6 0>;
297
+
wp-gpios = <&gpio1 5 0>;
298
+
status = "okay";
299
+
};
300
+
301
+
&uart3 {
302
+
pinctrl-names = "default";
303
+
pinctrl-0 = <&pinctrl_uart3_1>;
304
+
fsl,uart-has-rtscts;
305
+
status = "okay";
306
+
};
307
+
308
+
&ecspi1 {
309
+
pinctrl-names = "default";
310
+
pinctrl-0 = <&pinctrl_ecspi1_1>;
311
+
fsl,spi-num-chipselects = <2>;
312
+
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
313
+
status = "okay";
314
+
315
+
pmic: mc13892@0 {
316
+
#address-cells = <1>;
317
+
#size-cells = <0>;
318
+
compatible = "fsl,mc13892";
319
+
spi-max-frequency = <6000000>;
320
+
reg = <0>;
321
+
interrupt-parent = <&gpio1>;
322
+
interrupts = <8 0x4>;
323
+
324
+
regulators {
325
+
sw1_reg: sw1 {
326
+
regulator-min-microvolt = <600000>;
327
+
regulator-max-microvolt = <1375000>;
328
+
regulator-boot-on;
329
+
regulator-always-on;
330
+
};
331
+
332
+
sw2_reg: sw2 {
333
+
regulator-min-microvolt = <900000>;
334
+
regulator-max-microvolt = <1850000>;
335
+
regulator-boot-on;
336
+
regulator-always-on;
337
+
};
338
+
339
+
sw3_reg: sw3 {
340
+
regulator-min-microvolt = <1100000>;
341
+
regulator-max-microvolt = <1850000>;
342
+
regulator-boot-on;
343
+
regulator-always-on;
344
+
};
345
+
346
+
sw4_reg: sw4 {
347
+
regulator-min-microvolt = <1100000>;
348
+
regulator-max-microvolt = <1850000>;
349
+
regulator-boot-on;
350
+
regulator-always-on;
351
+
};
352
+
353
+
vpll_reg: vpll {
354
+
regulator-min-microvolt = <1050000>;
355
+
regulator-max-microvolt = <1800000>;
356
+
regulator-boot-on;
357
+
regulator-always-on;
358
+
};
359
+
360
+
vdig_reg: vdig {
361
+
regulator-min-microvolt = <1650000>;
362
+
regulator-max-microvolt = <1650000>;
363
+
regulator-boot-on;
364
+
};
365
+
366
+
vsd_reg: vsd {
367
+
regulator-min-microvolt = <1800000>;
368
+
regulator-max-microvolt = <3150000>;
369
+
};
370
+
371
+
vusb2_reg: vusb2 {
372
+
regulator-min-microvolt = <2400000>;
373
+
regulator-max-microvolt = <2775000>;
374
+
regulator-boot-on;
375
+
regulator-always-on;
376
+
};
377
+
378
+
vvideo_reg: vvideo {
379
+
regulator-min-microvolt = <2775000>;
380
+
regulator-max-microvolt = <2775000>;
381
+
};
382
+
383
+
vaudio_reg: vaudio {
384
+
regulator-min-microvolt = <2300000>;
385
+
regulator-max-microvolt = <3000000>;
386
+
};
387
+
388
+
vcam_reg: vcam {
389
+
regulator-min-microvolt = <2500000>;
390
+
regulator-max-microvolt = <3000000>;
391
+
};
392
+
393
+
vgen1_reg: vgen1 {
394
+
regulator-min-microvolt = <1200000>;
395
+
regulator-max-microvolt = <1200000>;
396
+
};
397
+
398
+
vgen2_reg: vgen2 {
399
+
regulator-min-microvolt = <1200000>;
400
+
regulator-max-microvolt = <3150000>;
401
+
regulator-always-on;
402
+
};
403
+
404
+
vgen3_reg: vgen3 {
405
+
regulator-min-microvolt = <1800000>;
406
+
regulator-max-microvolt = <2900000>;
407
+
regulator-always-on;
408
+
};
409
+
};
410
+
};
411
+
412
+
flash: at45db321d@1 {
413
+
#address-cells = <1>;
414
+
#size-cells = <1>;
415
+
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
416
+
spi-max-frequency = <25000000>;
417
+
reg = <1>;
418
+
419
+
partition@0 {
420
+
label = "U-Boot";
421
+
reg = <0x0 0x40000>;
422
+
read-only;
423
+
};
424
+
425
+
partition@40000 {
426
+
label = "Kernel";
427
+
reg = <0x40000 0x3c0000>;
428
+
};
429
+
};
430
+
};
431
+
432
+
&ssi2 {
433
+
fsl,mode = "i2s-slave";
434
+
status = "okay";
435
+
};
436
+
437
+
&iomuxc {
438
+
pinctrl-names = "default";
439
+
pinctrl-0 = <&pinctrl_hog>;
440
+
441
+
hog {
442
+
pinctrl_hog: hoggrp {
443
+
fsl,pins = <
444
+
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
445
+
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
446
+
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
447
+
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
448
+
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
449
+
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
450
+
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
451
+
>;
452
+
};
453
+
};
454
+
};
455
+
456
+
&uart1 {
457
+
pinctrl-names = "default";
458
+
pinctrl-0 = <&pinctrl_uart1_1>;
459
+
fsl,uart-has-rtscts;
460
+
status = "okay";
461
+
};
462
+
463
+
&uart2 {
464
+
pinctrl-names = "default";
465
+
pinctrl-0 = <&pinctrl_uart2_1>;
466
+
status = "okay";
467
+
};
468
+
469
+
&i2c2 {
470
+
pinctrl-names = "default";
471
+
pinctrl-0 = <&pinctrl_i2c2_1>;
472
+
status = "okay";
473
+
474
+
sgtl5000: codec@0a {
475
+
compatible = "fsl,sgtl5000";
476
+
reg = <0x0a>;
477
+
clock-frequency = <26000000>;
478
+
VDDA-supply = <&vdig_reg>;
479
+
VDDIO-supply = <&vvideo_reg>;
480
+
};
481
+
};
482
+
483
+
&audmux {
484
+
pinctrl-names = "default";
485
+
pinctrl-0 = <&pinctrl_audmux_1>;
486
+
status = "okay";
487
+
};
488
+
489
+
&fec {
490
+
pinctrl-names = "default";
491
+
pinctrl-0 = <&pinctrl_fec_1>;
492
+
phy-mode = "mii";
493
+
status = "okay";
494
+
};
495
+
496
+
&kpp {
497
+
pinctrl-names = "default";
498
+
pinctrl-0 = <&pinctrl_kpp_1>;
499
+
linux,keymap = <0x00000067 /* KEY_UP */
500
+
0x0001006c /* KEY_DOWN */
501
+
0x00020072 /* KEY_VOLUMEDOWN */
502
+
0x00030066 /* KEY_HOME */
503
+
0x0100006a /* KEY_RIGHT */
504
+
0x01010069 /* KEY_LEFT */
505
+
0x0102001c /* KEY_ENTER */
506
+
0x01030073 /* KEY_VOLUMEUP */
507
+
0x02000040 /* KEY_F6 */
508
+
0x02010042 /* KEY_F8 */
509
+
0x02020043 /* KEY_F9 */
510
+
0x02030044 /* KEY_F10 */
511
+
0x0300003b /* KEY_F1 */
512
+
0x0301003c /* KEY_F2 */
513
+
0x0302003d /* KEY_F3 */
514
+
0x03030074>; /* KEY_POWER */
515
+
status = "okay";
64
516
};
+53
arch/arm/boot/dts/imx51.dtsi
+53
arch/arm/boot/dts/imx51.dtsi
···
221
221
#interrupt-cells = <2>;
222
222
};
223
223
224
+
kpp: kpp@73f94000 {
225
+
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
226
+
reg = <0x73f94000 0x4000>;
227
+
interrupts = <60>;
228
+
clocks = <&clks 0>;
229
+
status = "disabled";
230
+
};
231
+
224
232
wdog1: wdog@73f98000 {
225
233
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
226
234
reg = <0x73f98000 0x4000>;
···
279
271
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
280
272
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
281
273
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
274
+
>;
275
+
};
276
+
277
+
pinctrl_fec_2: fecgrp-2 {
278
+
fsl,pins = <
279
+
589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
280
+
592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
281
+
594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
282
+
596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
283
+
598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
284
+
602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
285
+
604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
286
+
609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
287
+
618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
288
+
623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
289
+
628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
290
+
634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
291
+
639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
292
+
644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
293
+
649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
294
+
653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
295
+
657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
296
+
662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
282
297
>;
283
298
};
284
299
};
···
438
407
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
439
408
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
440
409
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
410
+
>;
411
+
};
412
+
413
+
pinctrl_uart3_2: uart3grp-2 {
414
+
fsl,pins = <
415
+
434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
416
+
430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
417
+
>;
418
+
};
419
+
};
420
+
421
+
kpp {
422
+
pinctrl_kpp_1: kppgrp-1 {
423
+
fsl,pins = <
424
+
438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
425
+
439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
426
+
440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
427
+
441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
428
+
442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
429
+
444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
430
+
446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
431
+
448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
441
432
>;
442
433
};
443
434
};
+60
-66
arch/arm/boot/dts/imx53-ard.dts
+60
-66
arch/arm/boot/dts/imx53-ard.dts
···
21
21
reg = <0x70000000 0x40000000>;
22
22
};
23
23
24
-
soc {
25
-
aips@50000000 { /* AIPS1 */
26
-
spba@50000000 {
27
-
esdhc@50004000 { /* ESDHC1 */
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&pinctrl_esdhc1_2>;
30
-
cd-gpios = <&gpio1 1 0>;
31
-
wp-gpios = <&gpio1 9 0>;
32
-
status = "okay";
33
-
};
34
-
};
35
-
36
-
iomuxc@53fa8000 {
37
-
pinctrl-names = "default";
38
-
pinctrl-0 = <&pinctrl_hog>;
39
-
40
-
hog {
41
-
pinctrl_hog: hoggrp {
42
-
fsl,pins = <
43
-
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
44
-
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
45
-
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
46
-
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
47
-
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
48
-
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
49
-
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
50
-
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
51
-
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
52
-
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
53
-
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
54
-
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
55
-
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
56
-
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
57
-
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
58
-
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
59
-
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
60
-
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
61
-
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
62
-
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
63
-
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
64
-
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
65
-
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
66
-
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
67
-
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
68
-
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
69
-
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
70
-
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
71
-
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
72
-
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
73
-
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
74
-
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
75
-
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
76
-
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
77
-
>;
78
-
};
79
-
};
80
-
};
81
-
82
-
uart1: serial@53fbc000 {
83
-
pinctrl-names = "default";
84
-
pinctrl-0 = <&pinctrl_uart1_2>;
85
-
status = "okay";
86
-
};
87
-
};
88
-
};
89
-
90
24
eim-cs1@f4000000 {
91
25
#address-cells = <1>;
92
26
#size-cells = <1>;
···
95
161
linux,code = <114>; /* KEY_VOLUMEDOWN */
96
162
};
97
163
};
164
+
};
165
+
166
+
&esdhc1 {
167
+
pinctrl-names = "default";
168
+
pinctrl-0 = <&pinctrl_esdhc1_2>;
169
+
cd-gpios = <&gpio1 1 0>;
170
+
wp-gpios = <&gpio1 9 0>;
171
+
status = "okay";
172
+
};
173
+
174
+
&iomuxc {
175
+
pinctrl-names = "default";
176
+
pinctrl-0 = <&pinctrl_hog>;
177
+
178
+
hog {
179
+
pinctrl_hog: hoggrp {
180
+
fsl,pins = <
181
+
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
182
+
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
183
+
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
184
+
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
185
+
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
186
+
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
187
+
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
188
+
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
189
+
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
190
+
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
191
+
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
192
+
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
193
+
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
194
+
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
195
+
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
196
+
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
197
+
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
198
+
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
199
+
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
200
+
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
201
+
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
202
+
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
203
+
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
204
+
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
205
+
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
206
+
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
207
+
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
208
+
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
209
+
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
210
+
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
211
+
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
212
+
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
213
+
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
214
+
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
215
+
>;
216
+
};
217
+
};
218
+
};
219
+
220
+
&uart1 {
221
+
pinctrl-names = "default";
222
+
pinctrl-0 = <&pinctrl_uart1_2>;
223
+
status = "okay";
98
224
};
+93
-101
arch/arm/boot/dts/imx53-evk.dts
+93
-101
arch/arm/boot/dts/imx53-evk.dts
···
21
21
reg = <0x70000000 0x80000000>;
22
22
};
23
23
24
-
soc {
25
-
aips@50000000 { /* AIPS1 */
26
-
spba@50000000 {
27
-
esdhc@50004000 { /* ESDHC1 */
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&pinctrl_esdhc1_1>;
30
-
cd-gpios = <&gpio3 13 0>;
31
-
wp-gpios = <&gpio3 14 0>;
32
-
status = "okay";
33
-
};
34
-
35
-
ecspi@50010000 { /* ECSPI1 */
36
-
pinctrl-names = "default";
37
-
pinctrl-0 = <&pinctrl_ecspi1_1>;
38
-
fsl,spi-num-chipselects = <2>;
39
-
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
40
-
status = "okay";
41
-
42
-
flash: at45db321d@1 {
43
-
#address-cells = <1>;
44
-
#size-cells = <1>;
45
-
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
46
-
spi-max-frequency = <25000000>;
47
-
reg = <1>;
48
-
49
-
partition@0 {
50
-
label = "U-Boot";
51
-
reg = <0x0 0x40000>;
52
-
read-only;
53
-
};
54
-
55
-
partition@40000 {
56
-
label = "Kernel";
57
-
reg = <0x40000 0x3c0000>;
58
-
};
59
-
};
60
-
};
61
-
62
-
esdhc@50020000 { /* ESDHC3 */
63
-
pinctrl-names = "default";
64
-
pinctrl-0 = <&pinctrl_esdhc3_1>;
65
-
cd-gpios = <&gpio3 11 0>;
66
-
wp-gpios = <&gpio3 12 0>;
67
-
status = "okay";
68
-
};
69
-
};
70
-
71
-
iomuxc@53fa8000 {
72
-
pinctrl-names = "default";
73
-
pinctrl-0 = <&pinctrl_hog>;
74
-
75
-
hog {
76
-
pinctrl_hog: hoggrp {
77
-
fsl,pins = <
78
-
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
79
-
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
80
-
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
81
-
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
82
-
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
83
-
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
84
-
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
85
-
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
86
-
>;
87
-
};
88
-
};
89
-
};
90
-
91
-
uart1: serial@53fbc000 {
92
-
pinctrl-names = "default";
93
-
pinctrl-0 = <&pinctrl_uart1_1>;
94
-
status = "okay";
95
-
};
96
-
};
97
-
98
-
aips@60000000 { /* AIPS2 */
99
-
i2c@63fc4000 { /* I2C2 */
100
-
pinctrl-names = "default";
101
-
pinctrl-0 = <&pinctrl_i2c2_1>;
102
-
status = "okay";
103
-
104
-
pmic: mc13892@08 {
105
-
compatible = "fsl,mc13892", "fsl,mc13xxx";
106
-
reg = <0x08>;
107
-
};
108
-
109
-
codec: sgtl5000@0a {
110
-
compatible = "fsl,sgtl5000";
111
-
reg = <0x0a>;
112
-
};
113
-
};
114
-
115
-
ethernet@63fec000 {
116
-
pinctrl-names = "default";
117
-
pinctrl-0 = <&pinctrl_fec_1>;
118
-
phy-mode = "rmii";
119
-
phy-reset-gpios = <&gpio7 6 0>;
120
-
status = "okay";
121
-
};
122
-
};
123
-
};
124
-
125
24
leds {
126
25
compatible = "gpio-leds";
127
26
···
30
131
linux,default-trigger = "heartbeat";
31
132
};
32
133
};
134
+
};
135
+
136
+
&esdhc1 {
137
+
pinctrl-names = "default";
138
+
pinctrl-0 = <&pinctrl_esdhc1_1>;
139
+
cd-gpios = <&gpio3 13 0>;
140
+
wp-gpios = <&gpio3 14 0>;
141
+
status = "okay";
142
+
};
143
+
144
+
&ecspi1 {
145
+
pinctrl-names = "default";
146
+
pinctrl-0 = <&pinctrl_ecspi1_1>;
147
+
fsl,spi-num-chipselects = <2>;
148
+
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
149
+
status = "okay";
150
+
151
+
flash: at45db321d@1 {
152
+
#address-cells = <1>;
153
+
#size-cells = <1>;
154
+
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
155
+
spi-max-frequency = <25000000>;
156
+
reg = <1>;
157
+
158
+
partition@0 {
159
+
label = "U-Boot";
160
+
reg = <0x0 0x40000>;
161
+
read-only;
162
+
};
163
+
164
+
partition@40000 {
165
+
label = "Kernel";
166
+
reg = <0x40000 0x3c0000>;
167
+
};
168
+
};
169
+
};
170
+
171
+
&esdhc3 {
172
+
pinctrl-names = "default";
173
+
pinctrl-0 = <&pinctrl_esdhc3_1>;
174
+
cd-gpios = <&gpio3 11 0>;
175
+
wp-gpios = <&gpio3 12 0>;
176
+
status = "okay";
177
+
};
178
+
179
+
&iomuxc {
180
+
pinctrl-names = "default";
181
+
pinctrl-0 = <&pinctrl_hog>;
182
+
183
+
hog {
184
+
pinctrl_hog: hoggrp {
185
+
fsl,pins = <
186
+
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
187
+
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
188
+
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
189
+
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
190
+
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
191
+
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
192
+
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
193
+
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
194
+
>;
195
+
};
196
+
};
197
+
};
198
+
199
+
&uart1 {
200
+
pinctrl-names = "default";
201
+
pinctrl-0 = <&pinctrl_uart1_1>;
202
+
status = "okay";
203
+
};
204
+
205
+
&i2c2 {
206
+
pinctrl-names = "default";
207
+
pinctrl-0 = <&pinctrl_i2c2_1>;
208
+
status = "okay";
209
+
210
+
pmic: mc13892@08 {
211
+
compatible = "fsl,mc13892", "fsl,mc13xxx";
212
+
reg = <0x08>;
213
+
};
214
+
215
+
codec: sgtl5000@0a {
216
+
compatible = "fsl,sgtl5000";
217
+
reg = <0x0a>;
218
+
};
219
+
};
220
+
221
+
&fec {
222
+
pinctrl-names = "default";
223
+
pinctrl-0 = <&pinctrl_fec_1>;
224
+
phy-mode = "rmii";
225
+
phy-reset-gpios = <&gpio7 6 0>;
226
+
status = "okay";
33
227
};
+130
arch/arm/boot/dts/imx53-mba53.dts
+130
arch/arm/boot/dts/imx53-mba53.dts
···
1
+
/*
2
+
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3
+
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4
+
*
5
+
* The code contained herein is licensed under the GNU General Public
6
+
* License. You may obtain a copy of the GNU General Public License
7
+
* Version 2 or later at the following locations:
8
+
*
9
+
* http://www.opensource.org/licenses/gpl-license.html
10
+
* http://www.gnu.org/copyleft/gpl.html
11
+
*/
12
+
13
+
/dts-v1/;
14
+
/include/ "imx53-tqma53.dtsi"
15
+
16
+
/ {
17
+
model = "TQ MBa53 starter kit";
18
+
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
19
+
};
20
+
21
+
&iomuxc {
22
+
lvds1 {
23
+
pinctrl_lvds1_1: lvds1-grp1 {
24
+
fsl,pins = <730 0x10000 /* LVDS0_TX3 */
25
+
732 0x10000 /* LVDS0_CLK */
26
+
734 0x10000 /* LVDS0_TX2 */
27
+
736 0x10000 /* LVDS0_TX1 */
28
+
738 0x10000>; /* LVDS0_TX0 */
29
+
};
30
+
31
+
pinctrl_lvds1_2: lvds1-grp2 {
32
+
fsl,pins = <720 0x10000 /* LVDS1_TX3 */
33
+
722 0x10000 /* LVDS1_TX2 */
34
+
724 0x10000 /* LVDS1_CLK */
35
+
726 0x10000 /* LVDS1_TX1 */
36
+
728 0x10000>; /* LVDS1_TX0 */
37
+
};
38
+
};
39
+
40
+
disp1 {
41
+
pinctrl_disp1_1: disp1-grp1 {
42
+
fsl,pins = <689 0x10000 /* DISP1_DRDY */
43
+
482 0x10000 /* DISP1_HSYNC */
44
+
489 0x10000 /* DISP1_VSYNC */
45
+
684 0x10000 /* DISP1_DAT_0 */
46
+
515 0x10000 /* DISP1_DAT_22 */
47
+
523 0x10000 /* DISP1_DAT_23 */
48
+
543 0x10000 /* DISP1_DAT_21 */
49
+
553 0x10000 /* DISP1_DAT_20 */
50
+
558 0x10000 /* DISP1_DAT_19 */
51
+
564 0x10000 /* DISP1_DAT_18 */
52
+
570 0x10000 /* DISP1_DAT_17 */
53
+
575 0x10000 /* DISP1_DAT_16 */
54
+
580 0x10000 /* DISP1_DAT_15 */
55
+
585 0x10000 /* DISP1_DAT_14 */
56
+
590 0x10000 /* DISP1_DAT_13 */
57
+
595 0x10000 /* DISP1_DAT_12 */
58
+
628 0x10000 /* DISP1_DAT_11 */
59
+
634 0x10000 /* DISP1_DAT_10 */
60
+
639 0x10000 /* DISP1_DAT_9 */
61
+
644 0x10000 /* DISP1_DAT_8 */
62
+
649 0x10000 /* DISP1_DAT_7 */
63
+
654 0x10000 /* DISP1_DAT_6 */
64
+
659 0x10000 /* DISP1_DAT_5 */
65
+
664 0x10000 /* DISP1_DAT_4 */
66
+
669 0x10000 /* DISP1_DAT_3 */
67
+
674 0x10000 /* DISP1_DAT_2 */
68
+
679 0x10000 /* DISP1_DAT_1 */
69
+
684 0x10000>; /* DISP1_DAT_0 */
70
+
};
71
+
};
72
+
};
73
+
74
+
&cspi {
75
+
status = "okay";
76
+
};
77
+
78
+
&i2c2 {
79
+
codec: sgtl5000@a {
80
+
compatible = "fsl,sgtl5000";
81
+
reg = <0x0a>;
82
+
};
83
+
84
+
expander: pca9554@20 {
85
+
compatible = "pca9554";
86
+
reg = <0x20>;
87
+
interrupts = <109>;
88
+
};
89
+
90
+
sensor2: lm75@49 {
91
+
compatible = "lm75";
92
+
reg = <0x49>;
93
+
};
94
+
};
95
+
96
+
&fec {
97
+
status = "okay";
98
+
};
99
+
100
+
&esdhc2 {
101
+
status = "okay";
102
+
};
103
+
104
+
&uart3 {
105
+
status = "okay";
106
+
};
107
+
108
+
&ecspi1 {
109
+
status = "okay";
110
+
};
111
+
112
+
&uart1 {
113
+
status = "okay";
114
+
};
115
+
116
+
&uart2 {
117
+
status = "okay";
118
+
};
119
+
120
+
&can1 {
121
+
status = "okay";
122
+
};
123
+
124
+
&can2 {
125
+
status = "okay";
126
+
};
127
+
128
+
&i2c3 {
129
+
status = "okay";
130
+
};
+186
-194
arch/arm/boot/dts/imx53-qsb.dts
+186
-194
arch/arm/boot/dts/imx53-qsb.dts
···
21
21
reg = <0x70000000 0x40000000>;
22
22
};
23
23
24
-
soc {
25
-
aips@50000000 { /* AIPS1 */
26
-
spba@50000000 {
27
-
esdhc@50004000 { /* ESDHC1 */
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&pinctrl_esdhc1_1>;
30
-
cd-gpios = <&gpio3 13 0>;
31
-
status = "okay";
32
-
};
33
-
34
-
ssi2: ssi@50014000 {
35
-
fsl,mode = "i2s-slave";
36
-
status = "okay";
37
-
};
38
-
39
-
esdhc@50020000 { /* ESDHC3 */
40
-
pinctrl-names = "default";
41
-
pinctrl-0 = <&pinctrl_esdhc3_1>;
42
-
cd-gpios = <&gpio3 11 0>;
43
-
wp-gpios = <&gpio3 12 0>;
44
-
status = "okay";
45
-
};
46
-
};
47
-
48
-
iomuxc@53fa8000 {
49
-
pinctrl-names = "default";
50
-
pinctrl-0 = <&pinctrl_hog>;
51
-
52
-
hog {
53
-
pinctrl_hog: hoggrp {
54
-
fsl,pins = <
55
-
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
56
-
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
57
-
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
58
-
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
59
-
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
60
-
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61
-
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62
-
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63
-
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64
-
>;
65
-
};
66
-
67
-
led_pin_gpio7_7: led_gpio7_7@0 {
68
-
fsl,pins = <
69
-
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
70
-
>;
71
-
};
72
-
};
73
-
74
-
};
75
-
76
-
uart1: serial@53fbc000 {
77
-
pinctrl-names = "default";
78
-
pinctrl-0 = <&pinctrl_uart1_1>;
79
-
status = "okay";
80
-
};
81
-
};
82
-
83
-
aips@60000000 { /* AIPS2 */
84
-
i2c@63fc4000 { /* I2C2 */
85
-
pinctrl-names = "default";
86
-
pinctrl-0 = <&pinctrl_i2c2_1>;
87
-
status = "okay";
88
-
89
-
sgtl5000: codec@0a {
90
-
compatible = "fsl,sgtl5000";
91
-
reg = <0x0a>;
92
-
VDDA-supply = <®_3p2v>;
93
-
VDDIO-supply = <®_3p2v>;
94
-
};
95
-
};
96
-
97
-
i2c@63fc8000 { /* I2C1 */
98
-
pinctrl-names = "default";
99
-
pinctrl-0 = <&pinctrl_i2c1_1>;
100
-
status = "okay";
101
-
102
-
accelerometer: mma8450@1c {
103
-
compatible = "fsl,mma8450";
104
-
reg = <0x1c>;
105
-
};
106
-
107
-
pmic: dialog@48 {
108
-
compatible = "dlg,da9053-aa", "dlg,da9052";
109
-
reg = <0x48>;
110
-
interrupt-parent = <&gpio7>;
111
-
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
112
-
113
-
regulators {
114
-
buck1_reg: buck1 {
115
-
regulator-min-microvolt = <500000>;
116
-
regulator-max-microvolt = <2075000>;
117
-
regulator-always-on;
118
-
};
119
-
120
-
buck2_reg: buck2 {
121
-
regulator-min-microvolt = <500000>;
122
-
regulator-max-microvolt = <2075000>;
123
-
regulator-always-on;
124
-
};
125
-
126
-
buck3_reg: buck3 {
127
-
regulator-min-microvolt = <925000>;
128
-
regulator-max-microvolt = <2500000>;
129
-
regulator-always-on;
130
-
};
131
-
132
-
buck4_reg: buck4 {
133
-
regulator-min-microvolt = <925000>;
134
-
regulator-max-microvolt = <2500000>;
135
-
regulator-always-on;
136
-
};
137
-
138
-
ldo1_reg: ldo1 {
139
-
regulator-min-microvolt = <600000>;
140
-
regulator-max-microvolt = <1800000>;
141
-
regulator-boot-on;
142
-
regulator-always-on;
143
-
};
144
-
145
-
ldo2_reg: ldo2 {
146
-
regulator-min-microvolt = <600000>;
147
-
regulator-max-microvolt = <1800000>;
148
-
regulator-always-on;
149
-
};
150
-
151
-
ldo3_reg: ldo3 {
152
-
regulator-min-microvolt = <600000>;
153
-
regulator-max-microvolt = <1800000>;
154
-
regulator-always-on;
155
-
};
156
-
157
-
ldo4_reg: ldo4 {
158
-
regulator-min-microvolt = <1725000>;
159
-
regulator-max-microvolt = <3300000>;
160
-
regulator-always-on;
161
-
};
162
-
163
-
ldo5_reg: ldo5 {
164
-
regulator-min-microvolt = <1725000>;
165
-
regulator-max-microvolt = <3300000>;
166
-
regulator-always-on;
167
-
};
168
-
169
-
ldo6_reg: ldo6 {
170
-
regulator-min-microvolt = <1200000>;
171
-
regulator-max-microvolt = <3600000>;
172
-
regulator-always-on;
173
-
};
174
-
175
-
ldo7_reg: ldo7 {
176
-
regulator-min-microvolt = <1200000>;
177
-
regulator-max-microvolt = <3600000>;
178
-
regulator-always-on;
179
-
};
180
-
181
-
ldo8_reg: ldo8 {
182
-
regulator-min-microvolt = <1200000>;
183
-
regulator-max-microvolt = <3600000>;
184
-
regulator-always-on;
185
-
};
186
-
187
-
ldo9_reg: ldo9 {
188
-
regulator-min-microvolt = <1200000>;
189
-
regulator-max-microvolt = <3600000>;
190
-
regulator-always-on;
191
-
};
192
-
193
-
ldo10_reg: ldo10 {
194
-
regulator-min-microvolt = <1250000>;
195
-
regulator-max-microvolt = <3650000>;
196
-
regulator-always-on;
197
-
};
198
-
};
199
-
};
200
-
};
201
-
202
-
audmux@63fd0000 {
203
-
pinctrl-names = "default";
204
-
pinctrl-0 = <&pinctrl_audmux_1>;
205
-
status = "okay";
206
-
};
207
-
208
-
ethernet@63fec000 {
209
-
pinctrl-names = "default";
210
-
pinctrl-0 = <&pinctrl_fec_1>;
211
-
phy-mode = "rmii";
212
-
phy-reset-gpios = <&gpio7 6 0>;
213
-
status = "okay";
214
-
};
215
-
};
216
-
};
217
-
218
24
gpio-keys {
219
25
compatible = "gpio-keys";
220
26
···
81
275
mux-int-port = <2>;
82
276
mux-ext-port = <5>;
83
277
};
278
+
};
279
+
280
+
&esdhc1 {
281
+
pinctrl-names = "default";
282
+
pinctrl-0 = <&pinctrl_esdhc1_1>;
283
+
cd-gpios = <&gpio3 13 0>;
284
+
status = "okay";
285
+
};
286
+
287
+
&ssi2 {
288
+
fsl,mode = "i2s-slave";
289
+
status = "okay";
290
+
};
291
+
292
+
&esdhc3 {
293
+
pinctrl-names = "default";
294
+
pinctrl-0 = <&pinctrl_esdhc3_1>;
295
+
cd-gpios = <&gpio3 11 0>;
296
+
wp-gpios = <&gpio3 12 0>;
297
+
status = "okay";
298
+
};
299
+
300
+
&iomuxc {
301
+
pinctrl-names = "default";
302
+
pinctrl-0 = <&pinctrl_hog>;
303
+
304
+
hog {
305
+
pinctrl_hog: hoggrp {
306
+
fsl,pins = <
307
+
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
308
+
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
309
+
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
310
+
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
311
+
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
312
+
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
313
+
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
314
+
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
315
+
1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
316
+
>;
317
+
};
318
+
319
+
led_pin_gpio7_7: led_gpio7_7@0 {
320
+
fsl,pins = <
321
+
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
322
+
>;
323
+
};
324
+
};
325
+
326
+
};
327
+
328
+
&uart1 {
329
+
pinctrl-names = "default";
330
+
pinctrl-0 = <&pinctrl_uart1_1>;
331
+
status = "okay";
332
+
};
333
+
334
+
&i2c2 {
335
+
pinctrl-names = "default";
336
+
pinctrl-0 = <&pinctrl_i2c2_1>;
337
+
status = "okay";
338
+
339
+
sgtl5000: codec@0a {
340
+
compatible = "fsl,sgtl5000";
341
+
reg = <0x0a>;
342
+
VDDA-supply = <®_3p2v>;
343
+
VDDIO-supply = <®_3p2v>;
344
+
};
345
+
};
346
+
347
+
&i2c1 {
348
+
pinctrl-names = "default";
349
+
pinctrl-0 = <&pinctrl_i2c1_1>;
350
+
status = "okay";
351
+
352
+
accelerometer: mma8450@1c {
353
+
compatible = "fsl,mma8450";
354
+
reg = <0x1c>;
355
+
};
356
+
357
+
pmic: dialog@48 {
358
+
compatible = "dlg,da9053-aa", "dlg,da9052";
359
+
reg = <0x48>;
360
+
interrupt-parent = <&gpio7>;
361
+
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
362
+
363
+
regulators {
364
+
buck1_reg: buck1 {
365
+
regulator-min-microvolt = <500000>;
366
+
regulator-max-microvolt = <2075000>;
367
+
regulator-always-on;
368
+
};
369
+
370
+
buck2_reg: buck2 {
371
+
regulator-min-microvolt = <500000>;
372
+
regulator-max-microvolt = <2075000>;
373
+
regulator-always-on;
374
+
};
375
+
376
+
buck3_reg: buck3 {
377
+
regulator-min-microvolt = <925000>;
378
+
regulator-max-microvolt = <2500000>;
379
+
regulator-always-on;
380
+
};
381
+
382
+
buck4_reg: buck4 {
383
+
regulator-min-microvolt = <925000>;
384
+
regulator-max-microvolt = <2500000>;
385
+
regulator-always-on;
386
+
};
387
+
388
+
ldo1_reg: ldo1 {
389
+
regulator-min-microvolt = <600000>;
390
+
regulator-max-microvolt = <1800000>;
391
+
regulator-boot-on;
392
+
regulator-always-on;
393
+
};
394
+
395
+
ldo2_reg: ldo2 {
396
+
regulator-min-microvolt = <600000>;
397
+
regulator-max-microvolt = <1800000>;
398
+
regulator-always-on;
399
+
};
400
+
401
+
ldo3_reg: ldo3 {
402
+
regulator-min-microvolt = <600000>;
403
+
regulator-max-microvolt = <1800000>;
404
+
regulator-always-on;
405
+
};
406
+
407
+
ldo4_reg: ldo4 {
408
+
regulator-min-microvolt = <1725000>;
409
+
regulator-max-microvolt = <3300000>;
410
+
regulator-always-on;
411
+
};
412
+
413
+
ldo5_reg: ldo5 {
414
+
regulator-min-microvolt = <1725000>;
415
+
regulator-max-microvolt = <3300000>;
416
+
regulator-always-on;
417
+
};
418
+
419
+
ldo6_reg: ldo6 {
420
+
regulator-min-microvolt = <1200000>;
421
+
regulator-max-microvolt = <3600000>;
422
+
regulator-always-on;
423
+
};
424
+
425
+
ldo7_reg: ldo7 {
426
+
regulator-min-microvolt = <1200000>;
427
+
regulator-max-microvolt = <3600000>;
428
+
regulator-always-on;
429
+
};
430
+
431
+
ldo8_reg: ldo8 {
432
+
regulator-min-microvolt = <1200000>;
433
+
regulator-max-microvolt = <3600000>;
434
+
regulator-always-on;
435
+
};
436
+
437
+
ldo9_reg: ldo9 {
438
+
regulator-min-microvolt = <1200000>;
439
+
regulator-max-microvolt = <3600000>;
440
+
regulator-always-on;
441
+
};
442
+
443
+
ldo10_reg: ldo10 {
444
+
regulator-min-microvolt = <1250000>;
445
+
regulator-max-microvolt = <3650000>;
446
+
regulator-always-on;
447
+
};
448
+
};
449
+
};
450
+
};
451
+
452
+
&audmux {
453
+
pinctrl-names = "default";
454
+
pinctrl-0 = <&pinctrl_audmux_1>;
455
+
status = "okay";
456
+
};
457
+
458
+
&fec {
459
+
pinctrl-names = "default";
460
+
pinctrl-0 = <&pinctrl_fec_1>;
461
+
phy-mode = "rmii";
462
+
phy-reset-gpios = <&gpio7 6 0>;
463
+
status = "okay";
84
464
};
+143
-151
arch/arm/boot/dts/imx53-smd.dts
+143
-151
arch/arm/boot/dts/imx53-smd.dts
···
21
21
reg = <0x70000000 0x40000000>;
22
22
};
23
23
24
-
soc {
25
-
aips@50000000 { /* AIPS1 */
26
-
spba@50000000 {
27
-
esdhc@50004000 { /* ESDHC1 */
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&pinctrl_esdhc1_1>;
30
-
cd-gpios = <&gpio3 13 0>;
31
-
wp-gpios = <&gpio4 11 0>;
32
-
status = "okay";
33
-
};
34
-
35
-
esdhc@50008000 { /* ESDHC2 */
36
-
pinctrl-names = "default";
37
-
pinctrl-0 = <&pinctrl_esdhc2_1>;
38
-
non-removable;
39
-
status = "okay";
40
-
};
41
-
42
-
uart3: serial@5000c000 {
43
-
pinctrl-names = "default";
44
-
pinctrl-0 = <&pinctrl_uart3_1>;
45
-
fsl,uart-has-rtscts;
46
-
status = "okay";
47
-
};
48
-
49
-
ecspi@50010000 { /* ECSPI1 */
50
-
pinctrl-names = "default";
51
-
pinctrl-0 = <&pinctrl_ecspi1_1>;
52
-
fsl,spi-num-chipselects = <2>;
53
-
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
54
-
status = "okay";
55
-
56
-
zigbee: mc1323@0 {
57
-
compatible = "fsl,mc1323";
58
-
spi-max-frequency = <8000000>;
59
-
reg = <0>;
60
-
};
61
-
62
-
flash: m25p32@1 {
63
-
#address-cells = <1>;
64
-
#size-cells = <1>;
65
-
compatible = "st,m25p32", "st,m25p";
66
-
spi-max-frequency = <20000000>;
67
-
reg = <1>;
68
-
69
-
partition@0 {
70
-
label = "U-Boot";
71
-
reg = <0x0 0x40000>;
72
-
read-only;
73
-
};
74
-
75
-
partition@40000 {
76
-
label = "Kernel";
77
-
reg = <0x40000 0x3c0000>;
78
-
};
79
-
};
80
-
};
81
-
82
-
esdhc@50020000 { /* ESDHC3 */
83
-
pinctrl-names = "default";
84
-
pinctrl-0 = <&pinctrl_esdhc3_1>;
85
-
non-removable;
86
-
status = "okay";
87
-
};
88
-
};
89
-
90
-
iomuxc@53fa8000 {
91
-
pinctrl-names = "default";
92
-
pinctrl-0 = <&pinctrl_hog>;
93
-
94
-
hog {
95
-
pinctrl_hog: hoggrp {
96
-
fsl,pins = <
97
-
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
98
-
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
99
-
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
100
-
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
101
-
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
102
-
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
103
-
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
104
-
>;
105
-
};
106
-
};
107
-
};
108
-
109
-
uart1: serial@53fbc000 {
110
-
pinctrl-names = "default";
111
-
pinctrl-0 = <&pinctrl_uart1_1>;
112
-
status = "okay";
113
-
};
114
-
115
-
uart2: serial@53fc0000 {
116
-
pinctrl-names = "default";
117
-
pinctrl-0 = <&pinctrl_uart2_1>;
118
-
status = "okay";
119
-
};
120
-
};
121
-
122
-
aips@60000000 { /* AIPS2 */
123
-
i2c@63fc4000 { /* I2C2 */
124
-
pinctrl-names = "default";
125
-
pinctrl-0 = <&pinctrl_i2c2_1>;
126
-
status = "okay";
127
-
128
-
codec: sgtl5000@0a {
129
-
compatible = "fsl,sgtl5000";
130
-
reg = <0x0a>;
131
-
};
132
-
133
-
magnetometer: mag3110@0e {
134
-
compatible = "fsl,mag3110";
135
-
reg = <0x0e>;
136
-
};
137
-
138
-
touchkey: mpr121@5a {
139
-
compatible = "fsl,mpr121";
140
-
reg = <0x5a>;
141
-
};
142
-
};
143
-
144
-
i2c@63fc8000 { /* I2C1 */
145
-
pinctrl-names = "default";
146
-
pinctrl-0 = <&pinctrl_i2c1_1>;
147
-
status = "okay";
148
-
149
-
accelerometer: mma8450@1c {
150
-
compatible = "fsl,mma8450";
151
-
reg = <0x1c>;
152
-
};
153
-
154
-
camera: ov5642@3c {
155
-
compatible = "ovti,ov5642";
156
-
reg = <0x3c>;
157
-
};
158
-
159
-
pmic: dialog@48 {
160
-
compatible = "dialog,da9053", "dialog,da9052";
161
-
reg = <0x48>;
162
-
};
163
-
};
164
-
165
-
ethernet@63fec000 {
166
-
pinctrl-names = "default";
167
-
pinctrl-0 = <&pinctrl_fec_1>;
168
-
phy-mode = "rmii";
169
-
phy-reset-gpios = <&gpio7 6 0>;
170
-
status = "okay";
171
-
};
172
-
};
173
-
};
174
-
175
24
gpio-keys {
176
25
compatible = "gpio-keys";
177
26
···
36
187
linux,code = <114>; /* KEY_VOLUMEDOWN */
37
188
};
38
189
};
190
+
};
191
+
192
+
&esdhc1 {
193
+
pinctrl-names = "default";
194
+
pinctrl-0 = <&pinctrl_esdhc1_1>;
195
+
cd-gpios = <&gpio3 13 0>;
196
+
wp-gpios = <&gpio4 11 0>;
197
+
status = "okay";
198
+
};
199
+
200
+
&esdhc2 {
201
+
pinctrl-names = "default";
202
+
pinctrl-0 = <&pinctrl_esdhc2_1>;
203
+
non-removable;
204
+
status = "okay";
205
+
};
206
+
207
+
&uart3 {
208
+
pinctrl-names = "default";
209
+
pinctrl-0 = <&pinctrl_uart3_1>;
210
+
fsl,uart-has-rtscts;
211
+
status = "okay";
212
+
};
213
+
214
+
&ecspi1 {
215
+
pinctrl-names = "default";
216
+
pinctrl-0 = <&pinctrl_ecspi1_1>;
217
+
fsl,spi-num-chipselects = <2>;
218
+
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
219
+
status = "okay";
220
+
221
+
zigbee: mc1323@0 {
222
+
compatible = "fsl,mc1323";
223
+
spi-max-frequency = <8000000>;
224
+
reg = <0>;
225
+
};
226
+
227
+
flash: m25p32@1 {
228
+
#address-cells = <1>;
229
+
#size-cells = <1>;
230
+
compatible = "st,m25p32", "st,m25p";
231
+
spi-max-frequency = <20000000>;
232
+
reg = <1>;
233
+
234
+
partition@0 {
235
+
label = "U-Boot";
236
+
reg = <0x0 0x40000>;
237
+
read-only;
238
+
};
239
+
240
+
partition@40000 {
241
+
label = "Kernel";
242
+
reg = <0x40000 0x3c0000>;
243
+
};
244
+
};
245
+
};
246
+
247
+
&esdhc3 {
248
+
pinctrl-names = "default";
249
+
pinctrl-0 = <&pinctrl_esdhc3_1>;
250
+
non-removable;
251
+
status = "okay";
252
+
};
253
+
254
+
&iomuxc {
255
+
pinctrl-names = "default";
256
+
pinctrl-0 = <&pinctrl_hog>;
257
+
258
+
hog {
259
+
pinctrl_hog: hoggrp {
260
+
fsl,pins = <
261
+
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
262
+
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
263
+
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
264
+
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
265
+
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
266
+
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
267
+
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
268
+
>;
269
+
};
270
+
};
271
+
};
272
+
273
+
&uart1 {
274
+
pinctrl-names = "default";
275
+
pinctrl-0 = <&pinctrl_uart1_1>;
276
+
status = "okay";
277
+
};
278
+
279
+
&uart2 {
280
+
pinctrl-names = "default";
281
+
pinctrl-0 = <&pinctrl_uart2_1>;
282
+
status = "okay";
283
+
};
284
+
285
+
&i2c2 {
286
+
pinctrl-names = "default";
287
+
pinctrl-0 = <&pinctrl_i2c2_1>;
288
+
status = "okay";
289
+
290
+
codec: sgtl5000@0a {
291
+
compatible = "fsl,sgtl5000";
292
+
reg = <0x0a>;
293
+
};
294
+
295
+
magnetometer: mag3110@0e {
296
+
compatible = "fsl,mag3110";
297
+
reg = <0x0e>;
298
+
};
299
+
300
+
touchkey: mpr121@5a {
301
+
compatible = "fsl,mpr121";
302
+
reg = <0x5a>;
303
+
};
304
+
};
305
+
306
+
&i2c1 {
307
+
pinctrl-names = "default";
308
+
pinctrl-0 = <&pinctrl_i2c1_1>;
309
+
status = "okay";
310
+
311
+
accelerometer: mma8450@1c {
312
+
compatible = "fsl,mma8450";
313
+
reg = <0x1c>;
314
+
};
315
+
316
+
camera: ov5642@3c {
317
+
compatible = "ovti,ov5642";
318
+
reg = <0x3c>;
319
+
};
320
+
321
+
pmic: dialog@48 {
322
+
compatible = "dialog,da9053", "dialog,da9052";
323
+
reg = <0x48>;
324
+
};
325
+
};
326
+
327
+
&fec {
328
+
pinctrl-names = "default";
329
+
pinctrl-0 = <&pinctrl_fec_1>;
330
+
phy-mode = "rmii";
331
+
phy-reset-gpios = <&gpio7 6 0>;
332
+
status = "okay";
39
333
};
+172
arch/arm/boot/dts/imx53-tqma53.dtsi
+172
arch/arm/boot/dts/imx53-tqma53.dtsi
···
1
+
/*
2
+
* Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3
+
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4
+
*
5
+
* The code contained herein is licensed under the GNU General Public
6
+
* License. You may obtain a copy of the GNU General Public License
7
+
* Version 2 or later at the following locations:
8
+
*
9
+
* http://www.opensource.org/licenses/gpl-license.html
10
+
* http://www.gnu.org/copyleft/gpl.html
11
+
*/
12
+
13
+
/include/ "imx53.dtsi"
14
+
15
+
/ {
16
+
model = "TQ TQMa53";
17
+
compatible = "tq,tqma53", "fsl,imx53";
18
+
19
+
memory {
20
+
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
21
+
};
22
+
23
+
regulators {
24
+
compatible = "simple-bus";
25
+
26
+
reg_3p3v: 3p3v {
27
+
compatible = "regulator-fixed";
28
+
regulator-name = "3P3V";
29
+
regulator-min-microvolt = <3300000>;
30
+
regulator-max-microvolt = <3300000>;
31
+
regulator-always-on;
32
+
};
33
+
};
34
+
};
35
+
36
+
&esdhc2 {
37
+
pinctrl-names = "default";
38
+
pinctrl-0 = <&pinctrl_esdhc2_1>;
39
+
wp-gpios = <&gpio1 2 0>;
40
+
cd-gpios = <&gpio1 4 0>;
41
+
status = "disabled";
42
+
};
43
+
44
+
&uart3 {
45
+
pinctrl-names = "default";
46
+
pinctrl-0 = <&pinctrl_uart3_2>;
47
+
status = "disabled";
48
+
};
49
+
50
+
&ecspi1 {
51
+
pinctrl-names = "default";
52
+
pinctrl-0 = <&pinctrl_ecspi1_1>;
53
+
fsl,spi-num-chipselects = <4>;
54
+
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
55
+
<&gpio3 24 0>, <&gpio3 25 0>;
56
+
status = "disabled";
57
+
};
58
+
59
+
&esdhc3 { /* EMMC */
60
+
pinctrl-names = "default";
61
+
pinctrl-0 = <&pinctrl_esdhc3_1>;
62
+
vmmc-supply = <®_3p3v>;
63
+
non-removable;
64
+
bus-width = <8>;
65
+
status = "okay";
66
+
};
67
+
68
+
&iomuxc {
69
+
pinctrl-names = "default";
70
+
pinctrl-0 = <&pinctrl_hog>;
71
+
72
+
i2s {
73
+
pinctrl_i2s_1: i2s-grp1 {
74
+
fsl,pins = <
75
+
1 0x10000 /* I2S_MCLK */
76
+
10 0x10000 /* I2S_SCLK */
77
+
17 0x10000 /* I2S_DOUT */
78
+
23 0x10000 /* I2S_LRCLK*/
79
+
30 0x10000 /* I2S_DIN */
80
+
>;
81
+
};
82
+
};
83
+
84
+
hog {
85
+
pinctrl_hog: hoggrp {
86
+
fsl,pins = <
87
+
610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
88
+
711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
89
+
873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
90
+
878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
91
+
922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
92
+
928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
93
+
982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
94
+
989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
95
+
1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
96
+
1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */
97
+
>;
98
+
};
99
+
};
100
+
};
101
+
102
+
&uart1 {
103
+
pinctrl-names = "default";
104
+
pinctrl-0 = <&pinctrl_uart1_2>;
105
+
fsl,uart-has-rtscts;
106
+
status = "disabled";
107
+
};
108
+
109
+
&uart2 {
110
+
pinctrl-names = "default";
111
+
pinctrl-0 = <&pinctrl_uart2_1>;
112
+
status = "disabled";
113
+
};
114
+
115
+
&can1 {
116
+
pinctrl-names = "default";
117
+
pinctrl-0 = <&pinctrl_can1_2>;
118
+
status = "disabled";
119
+
};
120
+
121
+
&can2 {
122
+
pinctrl-names = "default";
123
+
pinctrl-0 = <&pinctrl_can2_1>;
124
+
status = "disabled";
125
+
};
126
+
127
+
&i2c3 {
128
+
pinctrl-names = "default";
129
+
pinctrl-0 = <&pinctrl_i2c3_1>;
130
+
status = "disabled";
131
+
};
132
+
133
+
&cspi {
134
+
pinctrl-names = "default";
135
+
pinctrl-0 = <&pinctrl_cspi_1>;
136
+
fsl,spi-num-chipselects = <3>;
137
+
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
138
+
<&gpio1 21 0>;
139
+
status = "disabled";
140
+
};
141
+
142
+
&i2c2 {
143
+
pinctrl-names = "default";
144
+
pinctrl-0 = <&pinctrl_i2c2_1>;
145
+
status = "okay";
146
+
147
+
pmic: mc34708@8 {
148
+
compatible = "fsl,mc34708";
149
+
reg = <0x8>;
150
+
fsl,mc13xxx-uses-rtc;
151
+
interrupt-parent = <&gpio2>;
152
+
interrupts = <6 8>; /* PDATA_DATA6, low active */
153
+
};
154
+
155
+
sensor1: lm75@48 {
156
+
compatible = "lm75";
157
+
reg = <0x48>;
158
+
};
159
+
160
+
eeprom: 24c64@50 {
161
+
compatible = "at,24c64";
162
+
pagesize = <32>;
163
+
reg = <0x50>;
164
+
};
165
+
};
166
+
167
+
&fec {
168
+
pinctrl-names = "default";
169
+
pinctrl-0 = <&pinctrl_fec_1>;
170
+
phy-mode = "rmii";
171
+
status = "disabled";
172
+
};
+68
arch/arm/boot/dts/imx53.dtsi
+68
arch/arm/boot/dts/imx53.dtsi
···
274
274
};
275
275
};
276
276
277
+
csi {
278
+
pinctrl_csi_1: csigrp-1 {
279
+
fsl,pins = <
280
+
286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
281
+
291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
282
+
280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
283
+
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
284
+
409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
285
+
402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
286
+
395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
287
+
388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
288
+
381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
289
+
374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
290
+
367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
291
+
360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
292
+
352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
293
+
344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
294
+
336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
295
+
328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
296
+
320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
297
+
312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
298
+
304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
299
+
296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
300
+
276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
301
+
>;
302
+
};
303
+
};
304
+
305
+
cspi {
306
+
pinctrl_cspi_1: cspigrp-1 {
307
+
fsl,pins = <
308
+
998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
309
+
1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
310
+
1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
311
+
>;
312
+
};
313
+
};
314
+
277
315
ecspi1 {
278
316
pinctrl_ecspi1_1: ecspi1grp-1 {
279
317
fsl,pins = <
···
387
349
853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
388
350
>;
389
351
};
352
+
353
+
pinctrl_can1_2: can1grp-2 {
354
+
fsl,pins = <
355
+
37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
356
+
44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
357
+
>;
358
+
};
390
359
};
391
360
392
361
can2 {
···
432
387
};
433
388
};
434
389
390
+
owire {
391
+
pinctrl_owire_1: owiregrp-1 {
392
+
fsl,pins = <
393
+
1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
394
+
>;
395
+
};
396
+
};
397
+
435
398
uart1 {
436
399
pinctrl_uart1_1: uart1grp-1 {
437
400
fsl,pins = <
···
474
421
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
475
422
>;
476
423
};
424
+
425
+
pinctrl_uart3_2: uart3grp-2 {
426
+
fsl,pins = <
427
+
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
428
+
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
429
+
>;
430
+
};
431
+
477
432
};
478
433
479
434
uart4 {
···
628
567
interrupts = <86>;
629
568
clocks = <&clks 67>, <&clks 68>;
630
569
clock-names = "ipg", "per";
570
+
status = "disabled";
571
+
};
572
+
573
+
owire: owire@63fa4000 {
574
+
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
575
+
reg = <0x63fa4000 0x4000>;
576
+
clocks = <&clks 159>;
631
577
status = "disabled";
632
578
};
633
579
+59
arch/arm/boot/dts/imx6dl.dtsi
+59
arch/arm/boot/dts/imx6dl.dtsi
···
1
+
/*
2
+
* Copyright 2013 Freescale Semiconductor, Inc.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*
8
+
*/
9
+
10
+
/include/ "imx6qdl.dtsi"
11
+
12
+
/ {
13
+
cpus {
14
+
#address-cells = <1>;
15
+
#size-cells = <0>;
16
+
17
+
cpu@0 {
18
+
compatible = "arm,cortex-a9";
19
+
reg = <0>;
20
+
next-level-cache = <&L2>;
21
+
};
22
+
23
+
cpu@1 {
24
+
compatible = "arm,cortex-a9";
25
+
reg = <1>;
26
+
next-level-cache = <&L2>;
27
+
};
28
+
};
29
+
30
+
soc {
31
+
aips1: aips-bus@02000000 {
32
+
pxp: pxp@020f0000 {
33
+
reg = <0x020f0000 0x4000>;
34
+
interrupts = <0 98 0x04>;
35
+
};
36
+
37
+
epdc: epdc@020f4000 {
38
+
reg = <0x020f4000 0x4000>;
39
+
interrupts = <0 97 0x04>;
40
+
};
41
+
42
+
lcdif: lcdif@020f8000 {
43
+
reg = <0x020f8000 0x4000>;
44
+
interrupts = <0 39 0x04>;
45
+
};
46
+
};
47
+
48
+
aips2: aips-bus@02100000 {
49
+
i2c4: i2c@021f8000 {
50
+
#address-cells = <1>;
51
+
#size-cells = <0>;
52
+
compatible = "fsl,imx1-i2c";
53
+
reg = <0x021f8000 0x4000>;
54
+
interrupts = <0 35 0x04>;
55
+
status = "disabled";
56
+
};
57
+
};
58
+
};
59
+
};
+59
-65
arch/arm/boot/dts/imx6q-arm2.dts
+59
-65
arch/arm/boot/dts/imx6q-arm2.dts
···
21
21
reg = <0x10000000 0x80000000>;
22
22
};
23
23
24
-
soc {
25
-
gpmi-nand@00112000 {
26
-
pinctrl-names = "default";
27
-
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
28
-
status = "disabled"; /* gpmi nand conflicts with SD */
29
-
};
30
-
31
-
aips-bus@02000000 { /* AIPS1 */
32
-
iomuxc@020e0000 {
33
-
pinctrl-names = "default";
34
-
pinctrl-0 = <&pinctrl_hog>;
35
-
36
-
hog {
37
-
pinctrl_hog: hoggrp {
38
-
fsl,pins = <
39
-
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
40
-
>;
41
-
};
42
-
};
43
-
44
-
arm2 {
45
-
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
46
-
fsl,pins = <
47
-
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
48
-
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
49
-
>;
50
-
};
51
-
};
52
-
};
53
-
};
54
-
55
-
aips-bus@02100000 { /* AIPS2 */
56
-
ethernet@02188000 {
57
-
pinctrl-names = "default";
58
-
pinctrl-0 = <&pinctrl_enet_2>;
59
-
phy-mode = "rgmii";
60
-
status = "okay";
61
-
};
62
-
63
-
usdhc@02198000 { /* uSDHC3 */
64
-
cd-gpios = <&gpio6 11 0>;
65
-
wp-gpios = <&gpio6 14 0>;
66
-
vmmc-supply = <®_3p3v>;
67
-
pinctrl-names = "default";
68
-
pinctrl-0 = <&pinctrl_usdhc3_1
69
-
&pinctrl_usdhc3_arm2>;
70
-
status = "okay";
71
-
};
72
-
73
-
usdhc@0219c000 { /* uSDHC4 */
74
-
non-removable;
75
-
vmmc-supply = <®_3p3v>;
76
-
pinctrl-names = "default";
77
-
pinctrl-0 = <&pinctrl_usdhc4_1>;
78
-
status = "okay";
79
-
};
80
-
81
-
uart4: serial@021f0000 {
82
-
pinctrl-names = "default";
83
-
pinctrl-0 = <&pinctrl_uart4_1>;
84
-
status = "okay";
85
-
};
86
-
};
87
-
};
88
-
89
24
regulators {
90
25
compatible = "simple-bus";
91
26
···
42
107
linux,default-trigger = "heartbeat";
43
108
};
44
109
};
110
+
};
111
+
112
+
&gpmi {
113
+
pinctrl-names = "default";
114
+
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
115
+
status = "disabled"; /* gpmi nand conflicts with SD */
116
+
};
117
+
118
+
&iomuxc {
119
+
pinctrl-names = "default";
120
+
pinctrl-0 = <&pinctrl_hog>;
121
+
122
+
hog {
123
+
pinctrl_hog: hoggrp {
124
+
fsl,pins = <
125
+
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
126
+
>;
127
+
};
128
+
};
129
+
130
+
arm2 {
131
+
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
132
+
fsl,pins = <
133
+
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
134
+
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
135
+
>;
136
+
};
137
+
};
138
+
};
139
+
140
+
&fec {
141
+
pinctrl-names = "default";
142
+
pinctrl-0 = <&pinctrl_enet_2>;
143
+
phy-mode = "rgmii";
144
+
status = "okay";
145
+
};
146
+
147
+
&usdhc3 {
148
+
cd-gpios = <&gpio6 11 0>;
149
+
wp-gpios = <&gpio6 14 0>;
150
+
vmmc-supply = <®_3p3v>;
151
+
pinctrl-names = "default";
152
+
pinctrl-0 = <&pinctrl_usdhc3_1
153
+
&pinctrl_usdhc3_arm2>;
154
+
status = "okay";
155
+
};
156
+
157
+
&usdhc4 {
158
+
non-removable;
159
+
vmmc-supply = <®_3p3v>;
160
+
pinctrl-names = "default";
161
+
pinctrl-0 = <&pinctrl_usdhc4_1>;
162
+
status = "okay";
163
+
};
164
+
165
+
&uart4 {
166
+
pinctrl-names = "default";
167
+
pinctrl-0 = <&pinctrl_uart4_1>;
168
+
status = "okay";
45
169
};
+31
-37
arch/arm/boot/dts/imx6q-sabreauto.dts
+31
-37
arch/arm/boot/dts/imx6q-sabreauto.dts
···
20
20
memory {
21
21
reg = <0x10000000 0x80000000>;
22
22
};
23
+
};
23
24
24
-
soc {
25
-
aips-bus@02000000 { /* AIPS1 */
26
-
iomuxc@020e0000 {
27
-
pinctrl-names = "default";
28
-
pinctrl-0 = <&pinctrl_hog>;
25
+
&iomuxc {
26
+
pinctrl-names = "default";
27
+
pinctrl-0 = <&pinctrl_hog>;
29
28
30
-
hog {
31
-
pinctrl_hog: hoggrp {
32
-
fsl,pins = <
33
-
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34
-
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35
-
>;
36
-
};
37
-
};
38
-
};
39
-
};
40
-
41
-
aips-bus@02100000 { /* AIPS2 */
42
-
uart4: serial@021f0000 {
43
-
pinctrl-names = "default";
44
-
pinctrl-0 = <&pinctrl_uart4_1>;
45
-
status = "okay";
46
-
};
47
-
48
-
ethernet@02188000 {
49
-
pinctrl-names = "default";
50
-
pinctrl-0 = <&pinctrl_enet_2>;
51
-
phy-mode = "rgmii";
52
-
status = "okay";
53
-
};
54
-
55
-
usdhc@02198000 { /* uSDHC3 */
56
-
pinctrl-names = "default";
57
-
pinctrl-0 = <&pinctrl_usdhc3_1>;
58
-
cd-gpios = <&gpio6 15 0>;
59
-
wp-gpios = <&gpio1 13 0>;
60
-
status = "okay";
61
-
};
29
+
hog {
30
+
pinctrl_hog: hoggrp {
31
+
fsl,pins = <
32
+
1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
33
+
13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
34
+
>;
62
35
};
63
36
};
37
+
};
38
+
39
+
&uart4 {
40
+
pinctrl-names = "default";
41
+
pinctrl-0 = <&pinctrl_uart4_1>;
42
+
status = "okay";
43
+
};
44
+
45
+
&fec {
46
+
pinctrl-names = "default";
47
+
pinctrl-0 = <&pinctrl_enet_2>;
48
+
phy-mode = "rgmii";
49
+
status = "okay";
50
+
};
51
+
52
+
&usdhc3 {
53
+
pinctrl-names = "default";
54
+
pinctrl-0 = <&pinctrl_usdhc3_1>;
55
+
cd-gpios = <&gpio6 15 0>;
56
+
wp-gpios = <&gpio1 13 0>;
57
+
status = "okay";
64
58
};
+104
-112
arch/arm/boot/dts/imx6q-sabrelite.dts
+104
-112
arch/arm/boot/dts/imx6q-sabrelite.dts
···
21
21
reg = <0x10000000 0x40000000>;
22
22
};
23
23
24
-
soc {
25
-
aips-bus@02000000 { /* AIPS1 */
26
-
spba-bus@02000000 {
27
-
ecspi@02008000 { /* eCSPI1 */
28
-
fsl,spi-num-chipselects = <1>;
29
-
cs-gpios = <&gpio3 19 0>;
30
-
pinctrl-names = "default";
31
-
pinctrl-0 = <&pinctrl_ecspi1_1>;
32
-
status = "okay";
33
-
34
-
flash: m25p80@0 {
35
-
compatible = "sst,sst25vf016b";
36
-
spi-max-frequency = <20000000>;
37
-
reg = <0>;
38
-
};
39
-
};
40
-
41
-
ssi1: ssi@02028000 {
42
-
fsl,mode = "i2s-slave";
43
-
status = "okay";
44
-
};
45
-
};
46
-
47
-
iomuxc@020e0000 {
48
-
pinctrl-names = "default";
49
-
pinctrl-0 = <&pinctrl_hog>;
50
-
51
-
hog {
52
-
pinctrl_hog: hoggrp {
53
-
fsl,pins = <
54
-
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
55
-
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
56
-
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
57
-
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
58
-
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
59
-
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
60
-
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
61
-
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
62
-
>;
63
-
};
64
-
};
65
-
};
66
-
};
67
-
68
-
aips-bus@02100000 { /* AIPS2 */
69
-
usb@02184000 { /* USB OTG */
70
-
vbus-supply = <®_usb_otg_vbus>;
71
-
pinctrl-names = "default";
72
-
pinctrl-0 = <&pinctrl_usbotg_1>;
73
-
disable-over-current;
74
-
status = "okay";
75
-
};
76
-
77
-
usb@02184200 { /* USB1 */
78
-
status = "okay";
79
-
};
80
-
81
-
ethernet@02188000 {
82
-
pinctrl-names = "default";
83
-
pinctrl-0 = <&pinctrl_enet_1>;
84
-
phy-mode = "rgmii";
85
-
phy-reset-gpios = <&gpio3 23 0>;
86
-
status = "okay";
87
-
};
88
-
89
-
usdhc@02198000 { /* uSDHC3 */
90
-
pinctrl-names = "default";
91
-
pinctrl-0 = <&pinctrl_usdhc3_2>;
92
-
cd-gpios = <&gpio7 0 0>;
93
-
wp-gpios = <&gpio7 1 0>;
94
-
vmmc-supply = <®_3p3v>;
95
-
status = "okay";
96
-
};
97
-
98
-
usdhc@0219c000 { /* uSDHC4 */
99
-
pinctrl-names = "default";
100
-
pinctrl-0 = <&pinctrl_usdhc4_2>;
101
-
cd-gpios = <&gpio2 6 0>;
102
-
wp-gpios = <&gpio2 7 0>;
103
-
vmmc-supply = <®_3p3v>;
104
-
status = "okay";
105
-
};
106
-
107
-
audmux@021d8000 {
108
-
status = "okay";
109
-
pinctrl-names = "default";
110
-
pinctrl-0 = <&pinctrl_audmux_1>;
111
-
};
112
-
113
-
uart2: serial@021e8000 {
114
-
status = "okay";
115
-
pinctrl-names = "default";
116
-
pinctrl-0 = <&pinctrl_uart2_1>;
117
-
};
118
-
119
-
i2c@021a0000 { /* I2C1 */
120
-
status = "okay";
121
-
clock-frequency = <100000>;
122
-
pinctrl-names = "default";
123
-
pinctrl-0 = <&pinctrl_i2c1_1>;
124
-
125
-
codec: sgtl5000@0a {
126
-
compatible = "fsl,sgtl5000";
127
-
reg = <0x0a>;
128
-
clocks = <&clks 169>;
129
-
VDDA-supply = <®_2p5v>;
130
-
VDDIO-supply = <®_3p3v>;
131
-
};
132
-
};
133
-
};
134
-
};
135
-
136
24
regulators {
137
25
compatible = "simple-bus";
138
26
···
62
174
"Headphone Jack", "HP_OUT";
63
175
mux-int-port = <1>;
64
176
mux-ext-port = <4>;
177
+
};
178
+
};
179
+
180
+
&ecspi1 {
181
+
fsl,spi-num-chipselects = <1>;
182
+
cs-gpios = <&gpio3 19 0>;
183
+
pinctrl-names = "default";
184
+
pinctrl-0 = <&pinctrl_ecspi1_1>;
185
+
status = "okay";
186
+
187
+
flash: m25p80@0 {
188
+
compatible = "sst,sst25vf016b";
189
+
spi-max-frequency = <20000000>;
190
+
reg = <0>;
191
+
};
192
+
};
193
+
194
+
&ssi1 {
195
+
fsl,mode = "i2s-slave";
196
+
status = "okay";
197
+
};
198
+
199
+
&iomuxc {
200
+
pinctrl-names = "default";
201
+
pinctrl-0 = <&pinctrl_hog>;
202
+
203
+
hog {
204
+
pinctrl_hog: hoggrp {
205
+
fsl,pins = <
206
+
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
207
+
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
208
+
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
209
+
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
210
+
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
211
+
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
212
+
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
213
+
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
214
+
>;
215
+
};
216
+
};
217
+
};
218
+
219
+
&usbotg {
220
+
vbus-supply = <®_usb_otg_vbus>;
221
+
pinctrl-names = "default";
222
+
pinctrl-0 = <&pinctrl_usbotg_1>;
223
+
disable-over-current;
224
+
status = "okay";
225
+
};
226
+
227
+
&usbh1 {
228
+
status = "okay";
229
+
};
230
+
231
+
&fec {
232
+
pinctrl-names = "default";
233
+
pinctrl-0 = <&pinctrl_enet_1>;
234
+
phy-mode = "rgmii";
235
+
phy-reset-gpios = <&gpio3 23 0>;
236
+
status = "okay";
237
+
};
238
+
239
+
&usdhc3 {
240
+
pinctrl-names = "default";
241
+
pinctrl-0 = <&pinctrl_usdhc3_2>;
242
+
cd-gpios = <&gpio7 0 0>;
243
+
wp-gpios = <&gpio7 1 0>;
244
+
vmmc-supply = <®_3p3v>;
245
+
status = "okay";
246
+
};
247
+
248
+
&usdhc4 {
249
+
pinctrl-names = "default";
250
+
pinctrl-0 = <&pinctrl_usdhc4_2>;
251
+
cd-gpios = <&gpio2 6 0>;
252
+
wp-gpios = <&gpio2 7 0>;
253
+
vmmc-supply = <®_3p3v>;
254
+
status = "okay";
255
+
};
256
+
257
+
&audmux {
258
+
status = "okay";
259
+
pinctrl-names = "default";
260
+
pinctrl-0 = <&pinctrl_audmux_1>;
261
+
};
262
+
263
+
&uart2 {
264
+
status = "okay";
265
+
pinctrl-names = "default";
266
+
pinctrl-0 = <&pinctrl_uart2_1>;
267
+
};
268
+
269
+
&i2c1 {
270
+
status = "okay";
271
+
clock-frequency = <100000>;
272
+
pinctrl-names = "default";
273
+
pinctrl-0 = <&pinctrl_i2c1_1>;
274
+
275
+
codec: sgtl5000@0a {
276
+
compatible = "fsl,sgtl5000";
277
+
reg = <0x0a>;
278
+
clocks = <&clks 169>;
279
+
VDDA-supply = <®_2p5v>;
280
+
VDDIO-supply = <®_3p3v>;
65
281
};
66
282
};
+47
-55
arch/arm/boot/dts/imx6q-sabresd.dts
+47
-55
arch/arm/boot/dts/imx6q-sabresd.dts
···
21
21
reg = <0x10000000 0x40000000>;
22
22
};
23
23
24
-
soc {
25
-
aips-bus@02000000 { /* AIPS1 */
26
-
spba-bus@02000000 {
27
-
uart1: serial@02020000 {
28
-
pinctrl-names = "default";
29
-
pinctrl-0 = <&pinctrl_uart1_1>;
30
-
status = "okay";
31
-
};
32
-
};
33
-
34
-
iomuxc@020e0000 {
35
-
pinctrl-names = "default";
36
-
pinctrl-0 = <&pinctrl_hog>;
37
-
38
-
hog {
39
-
pinctrl_hog: hoggrp {
40
-
fsl,pins = <
41
-
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42
-
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
43
-
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
44
-
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
45
-
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
46
-
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
47
-
>;
48
-
};
49
-
};
50
-
};
51
-
};
52
-
53
-
aips-bus@02100000 { /* AIPS2 */
54
-
ethernet@02188000 {
55
-
pinctrl-names = "default";
56
-
pinctrl-0 = <&pinctrl_enet_1>;
57
-
phy-mode = "rgmii";
58
-
status = "okay";
59
-
};
60
-
61
-
usdhc@02194000 { /* uSDHC2 */
62
-
pinctrl-names = "default";
63
-
pinctrl-0 = <&pinctrl_usdhc2_1>;
64
-
cd-gpios = <&gpio2 2 0>;
65
-
wp-gpios = <&gpio2 3 0>;
66
-
status = "okay";
67
-
};
68
-
69
-
usdhc@02198000 { /* uSDHC3 */
70
-
pinctrl-names = "default";
71
-
pinctrl-0 = <&pinctrl_usdhc3_1>;
72
-
cd-gpios = <&gpio2 0 0>;
73
-
wp-gpios = <&gpio2 1 0>;
74
-
status = "okay";
75
-
};
76
-
};
77
-
};
78
-
79
24
gpio-keys {
80
25
compatible = "gpio-keys";
81
26
···
36
91
linux,code = <114>; /* KEY_VOLUMEDOWN */
37
92
};
38
93
};
94
+
};
95
+
96
+
&uart1 {
97
+
pinctrl-names = "default";
98
+
pinctrl-0 = <&pinctrl_uart1_1>;
99
+
status = "okay";
100
+
};
101
+
102
+
&iomuxc {
103
+
pinctrl-names = "default";
104
+
pinctrl-0 = <&pinctrl_hog>;
105
+
106
+
hog {
107
+
pinctrl_hog: hoggrp {
108
+
fsl,pins = <
109
+
1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
110
+
1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
111
+
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
112
+
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
113
+
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
114
+
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
115
+
>;
116
+
};
117
+
};
118
+
};
119
+
120
+
&fec {
121
+
pinctrl-names = "default";
122
+
pinctrl-0 = <&pinctrl_enet_1>;
123
+
phy-mode = "rgmii";
124
+
status = "okay";
125
+
};
126
+
127
+
&usdhc2 {
128
+
pinctrl-names = "default";
129
+
pinctrl-0 = <&pinctrl_usdhc2_1>;
130
+
cd-gpios = <&gpio2 2 0>;
131
+
wp-gpios = <&gpio2 3 0>;
132
+
status = "okay";
133
+
};
134
+
135
+
&usdhc3 {
136
+
pinctrl-names = "default";
137
+
pinctrl-0 = <&pinctrl_usdhc3_1>;
138
+
cd-gpios = <&gpio2 0 0>;
139
+
wp-gpios = <&gpio2 1 0>;
140
+
status = "okay";
39
141
};
+16
-780
arch/arm/boot/dts/imx6q.dtsi
+16
-780
arch/arm/boot/dts/imx6q.dtsi
···
1
+
1
2
/*
2
-
* Copyright 2011 Freescale Semiconductor, Inc.
3
-
* Copyright 2011 Linaro Ltd.
3
+
* Copyright 2013 Freescale Semiconductor, Inc.
4
4
*
5
-
* The code contained herein is licensed under the GNU General Public
6
-
* License. You may obtain a copy of the GNU General Public License
7
-
* Version 2 or later at the following locations:
5
+
* This program is free software; you can redistribute it and/or modify
6
+
* it under the terms of the GNU General Public License version 2 as
7
+
* published by the Free Software Foundation.
8
8
*
9
-
* http://www.opensource.org/licenses/gpl-license.html
10
-
* http://www.gnu.org/copyleft/gpl.html
11
9
*/
12
10
13
-
/include/ "skeleton.dtsi"
11
+
/include/ "imx6qdl.dtsi"
14
12
15
13
/ {
16
-
aliases {
17
-
serial0 = &uart1;
18
-
serial1 = &uart2;
19
-
serial2 = &uart3;
20
-
serial3 = &uart4;
21
-
serial4 = &uart5;
22
-
gpio0 = &gpio1;
23
-
gpio1 = &gpio2;
24
-
gpio2 = &gpio3;
25
-
gpio3 = &gpio4;
26
-
gpio4 = &gpio5;
27
-
gpio5 = &gpio6;
28
-
gpio6 = &gpio7;
29
-
};
30
-
31
14
cpus {
32
15
#address-cells = <1>;
33
16
#size-cells = <0>;
···
21
38
next-level-cache = <&L2>;
22
39
operating-points = <
23
40
/* kHz uV */
24
-
792000 1100000
41
+
1200000 1275000
42
+
996000 1250000
43
+
792000 1150000
25
44
396000 950000
26
-
198000 850000
27
45
>;
28
46
clock-latency = <61036>; /* two CLK32 periods */
29
-
cpu0-supply = <®_cpu>;
47
+
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
48
+
<&clks 17>, <&clks 170>;
49
+
clock-names = "arm", "pll2_pfd2_396m", "step",
50
+
"pll1_sw", "pll1_sys";
51
+
arm-supply = <®_arm>;
52
+
pu-supply = <®_pu>;
53
+
soc-supply = <®_soc>;
30
54
};
31
55
32
56
cpu@1 {
···
55
65
};
56
66
};
57
67
58
-
intc: interrupt-controller@00a01000 {
59
-
compatible = "arm,cortex-a9-gic";
60
-
#interrupt-cells = <3>;
61
-
#address-cells = <1>;
62
-
#size-cells = <1>;
63
-
interrupt-controller;
64
-
reg = <0x00a01000 0x1000>,
65
-
<0x00a00100 0x100>;
66
-
};
67
-
68
-
clocks {
69
-
#address-cells = <1>;
70
-
#size-cells = <0>;
71
-
72
-
ckil {
73
-
compatible = "fsl,imx-ckil", "fixed-clock";
74
-
clock-frequency = <32768>;
75
-
};
76
-
77
-
ckih1 {
78
-
compatible = "fsl,imx-ckih1", "fixed-clock";
79
-
clock-frequency = <0>;
80
-
};
81
-
82
-
osc {
83
-
compatible = "fsl,imx-osc", "fixed-clock";
84
-
clock-frequency = <24000000>;
85
-
};
86
-
};
87
-
88
68
soc {
89
-
#address-cells = <1>;
90
-
#size-cells = <1>;
91
-
compatible = "simple-bus";
92
-
interrupt-parent = <&intc>;
93
-
ranges;
94
-
95
-
dma-apbh@00110000 {
96
-
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
97
-
reg = <0x00110000 0x2000>;
98
-
clocks = <&clks 106>;
99
-
};
100
-
101
-
nfc: gpmi-nand@00112000 {
102
-
compatible = "fsl,imx6q-gpmi-nand";
103
-
#address-cells = <1>;
104
-
#size-cells = <1>;
105
-
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106
-
reg-names = "gpmi-nand", "bch";
107
-
interrupts = <0 13 0x04>, <0 15 0x04>;
108
-
interrupt-names = "gpmi-dma", "bch";
109
-
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
110
-
<&clks 150>, <&clks 149>;
111
-
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
112
-
"gpmi_bch_apb", "per1_bch";
113
-
fsl,gpmi-dma-channel = <0>;
114
-
status = "disabled";
115
-
};
116
-
117
-
timer@00a00600 {
118
-
compatible = "arm,cortex-a9-twd-timer";
119
-
reg = <0x00a00600 0x20>;
120
-
interrupts = <1 13 0xf01>;
121
-
};
122
-
123
-
L2: l2-cache@00a02000 {
124
-
compatible = "arm,pl310-cache";
125
-
reg = <0x00a02000 0x1000>;
126
-
interrupts = <0 92 0x04>;
127
-
cache-unified;
128
-
cache-level = <2>;
129
-
};
130
-
131
69
aips-bus@02000000 { /* AIPS1 */
132
-
compatible = "fsl,aips-bus", "simple-bus";
133
-
#address-cells = <1>;
134
-
#size-cells = <1>;
135
-
reg = <0x02000000 0x100000>;
136
-
ranges;
137
-
138
70
spba-bus@02000000 {
139
-
compatible = "fsl,spba-bus", "simple-bus";
140
-
#address-cells = <1>;
141
-
#size-cells = <1>;
142
-
reg = <0x02000000 0x40000>;
143
-
ranges;
144
-
145
-
spdif: spdif@02004000 {
146
-
reg = <0x02004000 0x4000>;
147
-
interrupts = <0 52 0x04>;
148
-
};
149
-
150
-
ecspi1: ecspi@02008000 {
151
-
#address-cells = <1>;
152
-
#size-cells = <0>;
153
-
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154
-
reg = <0x02008000 0x4000>;
155
-
interrupts = <0 31 0x04>;
156
-
clocks = <&clks 112>, <&clks 112>;
157
-
clock-names = "ipg", "per";
158
-
status = "disabled";
159
-
};
160
-
161
-
ecspi2: ecspi@0200c000 {
162
-
#address-cells = <1>;
163
-
#size-cells = <0>;
164
-
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
165
-
reg = <0x0200c000 0x4000>;
166
-
interrupts = <0 32 0x04>;
167
-
clocks = <&clks 113>, <&clks 113>;
168
-
clock-names = "ipg", "per";
169
-
status = "disabled";
170
-
};
171
-
172
-
ecspi3: ecspi@02010000 {
173
-
#address-cells = <1>;
174
-
#size-cells = <0>;
175
-
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
176
-
reg = <0x02010000 0x4000>;
177
-
interrupts = <0 33 0x04>;
178
-
clocks = <&clks 114>, <&clks 114>;
179
-
clock-names = "ipg", "per";
180
-
status = "disabled";
181
-
};
182
-
183
-
ecspi4: ecspi@02014000 {
184
-
#address-cells = <1>;
185
-
#size-cells = <0>;
186
-
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187
-
reg = <0x02014000 0x4000>;
188
-
interrupts = <0 34 0x04>;
189
-
clocks = <&clks 115>, <&clks 115>;
190
-
clock-names = "ipg", "per";
191
-
status = "disabled";
192
-
};
193
-
194
71
ecspi5: ecspi@02018000 {
195
72
#address-cells = <1>;
196
73
#size-cells = <0>;
···
68
211
clock-names = "ipg", "per";
69
212
status = "disabled";
70
213
};
71
-
72
-
uart1: serial@02020000 {
73
-
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
74
-
reg = <0x02020000 0x4000>;
75
-
interrupts = <0 26 0x04>;
76
-
clocks = <&clks 160>, <&clks 161>;
77
-
clock-names = "ipg", "per";
78
-
status = "disabled";
79
-
};
80
-
81
-
esai: esai@02024000 {
82
-
reg = <0x02024000 0x4000>;
83
-
interrupts = <0 51 0x04>;
84
-
};
85
-
86
-
ssi1: ssi@02028000 {
87
-
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
88
-
reg = <0x02028000 0x4000>;
89
-
interrupts = <0 46 0x04>;
90
-
clocks = <&clks 178>;
91
-
fsl,fifo-depth = <15>;
92
-
fsl,ssi-dma-events = <38 37>;
93
-
status = "disabled";
94
-
};
95
-
96
-
ssi2: ssi@0202c000 {
97
-
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
98
-
reg = <0x0202c000 0x4000>;
99
-
interrupts = <0 47 0x04>;
100
-
clocks = <&clks 179>;
101
-
fsl,fifo-depth = <15>;
102
-
fsl,ssi-dma-events = <42 41>;
103
-
status = "disabled";
104
-
};
105
-
106
-
ssi3: ssi@02030000 {
107
-
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
108
-
reg = <0x02030000 0x4000>;
109
-
interrupts = <0 48 0x04>;
110
-
clocks = <&clks 180>;
111
-
fsl,fifo-depth = <15>;
112
-
fsl,ssi-dma-events = <46 45>;
113
-
status = "disabled";
114
-
};
115
-
116
-
asrc: asrc@02034000 {
117
-
reg = <0x02034000 0x4000>;
118
-
interrupts = <0 50 0x04>;
119
-
};
120
-
121
-
spba@0203c000 {
122
-
reg = <0x0203c000 0x4000>;
123
-
};
124
-
};
125
-
126
-
vpu: vpu@02040000 {
127
-
reg = <0x02040000 0x3c000>;
128
-
interrupts = <0 3 0x04 0 12 0x04>;
129
-
};
130
-
131
-
aipstz@0207c000 { /* AIPSTZ1 */
132
-
reg = <0x0207c000 0x4000>;
133
-
};
134
-
135
-
pwm1: pwm@02080000 {
136
-
#pwm-cells = <2>;
137
-
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
138
-
reg = <0x02080000 0x4000>;
139
-
interrupts = <0 83 0x04>;
140
-
clocks = <&clks 62>, <&clks 145>;
141
-
clock-names = "ipg", "per";
142
-
};
143
-
144
-
pwm2: pwm@02084000 {
145
-
#pwm-cells = <2>;
146
-
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
147
-
reg = <0x02084000 0x4000>;
148
-
interrupts = <0 84 0x04>;
149
-
clocks = <&clks 62>, <&clks 146>;
150
-
clock-names = "ipg", "per";
151
-
};
152
-
153
-
pwm3: pwm@02088000 {
154
-
#pwm-cells = <2>;
155
-
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
156
-
reg = <0x02088000 0x4000>;
157
-
interrupts = <0 85 0x04>;
158
-
clocks = <&clks 62>, <&clks 147>;
159
-
clock-names = "ipg", "per";
160
-
};
161
-
162
-
pwm4: pwm@0208c000 {
163
-
#pwm-cells = <2>;
164
-
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
165
-
reg = <0x0208c000 0x4000>;
166
-
interrupts = <0 86 0x04>;
167
-
clocks = <&clks 62>, <&clks 148>;
168
-
clock-names = "ipg", "per";
169
-
};
170
-
171
-
can1: flexcan@02090000 {
172
-
reg = <0x02090000 0x4000>;
173
-
interrupts = <0 110 0x04>;
174
-
};
175
-
176
-
can2: flexcan@02094000 {
177
-
reg = <0x02094000 0x4000>;
178
-
interrupts = <0 111 0x04>;
179
-
};
180
-
181
-
gpt: gpt@02098000 {
182
-
compatible = "fsl,imx6q-gpt";
183
-
reg = <0x02098000 0x4000>;
184
-
interrupts = <0 55 0x04>;
185
-
};
186
-
187
-
gpio1: gpio@0209c000 {
188
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
189
-
reg = <0x0209c000 0x4000>;
190
-
interrupts = <0 66 0x04 0 67 0x04>;
191
-
gpio-controller;
192
-
#gpio-cells = <2>;
193
-
interrupt-controller;
194
-
#interrupt-cells = <2>;
195
-
};
196
-
197
-
gpio2: gpio@020a0000 {
198
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
199
-
reg = <0x020a0000 0x4000>;
200
-
interrupts = <0 68 0x04 0 69 0x04>;
201
-
gpio-controller;
202
-
#gpio-cells = <2>;
203
-
interrupt-controller;
204
-
#interrupt-cells = <2>;
205
-
};
206
-
207
-
gpio3: gpio@020a4000 {
208
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
209
-
reg = <0x020a4000 0x4000>;
210
-
interrupts = <0 70 0x04 0 71 0x04>;
211
-
gpio-controller;
212
-
#gpio-cells = <2>;
213
-
interrupt-controller;
214
-
#interrupt-cells = <2>;
215
-
};
216
-
217
-
gpio4: gpio@020a8000 {
218
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
219
-
reg = <0x020a8000 0x4000>;
220
-
interrupts = <0 72 0x04 0 73 0x04>;
221
-
gpio-controller;
222
-
#gpio-cells = <2>;
223
-
interrupt-controller;
224
-
#interrupt-cells = <2>;
225
-
};
226
-
227
-
gpio5: gpio@020ac000 {
228
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
229
-
reg = <0x020ac000 0x4000>;
230
-
interrupts = <0 74 0x04 0 75 0x04>;
231
-
gpio-controller;
232
-
#gpio-cells = <2>;
233
-
interrupt-controller;
234
-
#interrupt-cells = <2>;
235
-
};
236
-
237
-
gpio6: gpio@020b0000 {
238
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
239
-
reg = <0x020b0000 0x4000>;
240
-
interrupts = <0 76 0x04 0 77 0x04>;
241
-
gpio-controller;
242
-
#gpio-cells = <2>;
243
-
interrupt-controller;
244
-
#interrupt-cells = <2>;
245
-
};
246
-
247
-
gpio7: gpio@020b4000 {
248
-
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
249
-
reg = <0x020b4000 0x4000>;
250
-
interrupts = <0 78 0x04 0 79 0x04>;
251
-
gpio-controller;
252
-
#gpio-cells = <2>;
253
-
interrupt-controller;
254
-
#interrupt-cells = <2>;
255
-
};
256
-
257
-
kpp: kpp@020b8000 {
258
-
reg = <0x020b8000 0x4000>;
259
-
interrupts = <0 82 0x04>;
260
-
};
261
-
262
-
wdog1: wdog@020bc000 {
263
-
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
264
-
reg = <0x020bc000 0x4000>;
265
-
interrupts = <0 80 0x04>;
266
-
clocks = <&clks 0>;
267
-
};
268
-
269
-
wdog2: wdog@020c0000 {
270
-
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
271
-
reg = <0x020c0000 0x4000>;
272
-
interrupts = <0 81 0x04>;
273
-
clocks = <&clks 0>;
274
-
status = "disabled";
275
-
};
276
-
277
-
clks: ccm@020c4000 {
278
-
compatible = "fsl,imx6q-ccm";
279
-
reg = <0x020c4000 0x4000>;
280
-
interrupts = <0 87 0x04 0 88 0x04>;
281
-
#clock-cells = <1>;
282
-
};
283
-
284
-
anatop: anatop@020c8000 {
285
-
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
286
-
reg = <0x020c8000 0x1000>;
287
-
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
288
-
289
-
regulator-1p1@110 {
290
-
compatible = "fsl,anatop-regulator";
291
-
regulator-name = "vdd1p1";
292
-
regulator-min-microvolt = <800000>;
293
-
regulator-max-microvolt = <1375000>;
294
-
regulator-always-on;
295
-
anatop-reg-offset = <0x110>;
296
-
anatop-vol-bit-shift = <8>;
297
-
anatop-vol-bit-width = <5>;
298
-
anatop-min-bit-val = <4>;
299
-
anatop-min-voltage = <800000>;
300
-
anatop-max-voltage = <1375000>;
301
-
};
302
-
303
-
regulator-3p0@120 {
304
-
compatible = "fsl,anatop-regulator";
305
-
regulator-name = "vdd3p0";
306
-
regulator-min-microvolt = <2800000>;
307
-
regulator-max-microvolt = <3150000>;
308
-
regulator-always-on;
309
-
anatop-reg-offset = <0x120>;
310
-
anatop-vol-bit-shift = <8>;
311
-
anatop-vol-bit-width = <5>;
312
-
anatop-min-bit-val = <0>;
313
-
anatop-min-voltage = <2625000>;
314
-
anatop-max-voltage = <3400000>;
315
-
};
316
-
317
-
regulator-2p5@130 {
318
-
compatible = "fsl,anatop-regulator";
319
-
regulator-name = "vdd2p5";
320
-
regulator-min-microvolt = <2000000>;
321
-
regulator-max-microvolt = <2750000>;
322
-
regulator-always-on;
323
-
anatop-reg-offset = <0x130>;
324
-
anatop-vol-bit-shift = <8>;
325
-
anatop-vol-bit-width = <5>;
326
-
anatop-min-bit-val = <0>;
327
-
anatop-min-voltage = <2000000>;
328
-
anatop-max-voltage = <2750000>;
329
-
};
330
-
331
-
reg_cpu: regulator-vddcore@140 {
332
-
compatible = "fsl,anatop-regulator";
333
-
regulator-name = "cpu";
334
-
regulator-min-microvolt = <725000>;
335
-
regulator-max-microvolt = <1450000>;
336
-
regulator-always-on;
337
-
anatop-reg-offset = <0x140>;
338
-
anatop-vol-bit-shift = <0>;
339
-
anatop-vol-bit-width = <5>;
340
-
anatop-min-bit-val = <1>;
341
-
anatop-min-voltage = <725000>;
342
-
anatop-max-voltage = <1450000>;
343
-
};
344
-
345
-
regulator-vddpu@140 {
346
-
compatible = "fsl,anatop-regulator";
347
-
regulator-name = "vddpu";
348
-
regulator-min-microvolt = <725000>;
349
-
regulator-max-microvolt = <1450000>;
350
-
regulator-always-on;
351
-
anatop-reg-offset = <0x140>;
352
-
anatop-vol-bit-shift = <9>;
353
-
anatop-vol-bit-width = <5>;
354
-
anatop-min-bit-val = <1>;
355
-
anatop-min-voltage = <725000>;
356
-
anatop-max-voltage = <1450000>;
357
-
};
358
-
359
-
regulator-vddsoc@140 {
360
-
compatible = "fsl,anatop-regulator";
361
-
regulator-name = "vddsoc";
362
-
regulator-min-microvolt = <725000>;
363
-
regulator-max-microvolt = <1450000>;
364
-
regulator-always-on;
365
-
anatop-reg-offset = <0x140>;
366
-
anatop-vol-bit-shift = <18>;
367
-
anatop-vol-bit-width = <5>;
368
-
anatop-min-bit-val = <1>;
369
-
anatop-min-voltage = <725000>;
370
-
anatop-max-voltage = <1450000>;
371
-
};
372
-
};
373
-
374
-
usbphy1: usbphy@020c9000 {
375
-
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
376
-
reg = <0x020c9000 0x1000>;
377
-
interrupts = <0 44 0x04>;
378
-
clocks = <&clks 182>;
379
-
};
380
-
381
-
usbphy2: usbphy@020ca000 {
382
-
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
383
-
reg = <0x020ca000 0x1000>;
384
-
interrupts = <0 45 0x04>;
385
-
clocks = <&clks 183>;
386
-
};
387
-
388
-
snvs@020cc000 {
389
-
compatible = "fsl,sec-v4.0-mon", "simple-bus";
390
-
#address-cells = <1>;
391
-
#size-cells = <1>;
392
-
ranges = <0 0x020cc000 0x4000>;
393
-
394
-
snvs-rtc-lp@34 {
395
-
compatible = "fsl,sec-v4.0-mon-rtc-lp";
396
-
reg = <0x34 0x58>;
397
-
interrupts = <0 19 0x04 0 20 0x04>;
398
-
};
399
-
};
400
-
401
-
epit1: epit@020d0000 { /* EPIT1 */
402
-
reg = <0x020d0000 0x4000>;
403
-
interrupts = <0 56 0x04>;
404
-
};
405
-
406
-
epit2: epit@020d4000 { /* EPIT2 */
407
-
reg = <0x020d4000 0x4000>;
408
-
interrupts = <0 57 0x04>;
409
-
};
410
-
411
-
src: src@020d8000 {
412
-
compatible = "fsl,imx6q-src";
413
-
reg = <0x020d8000 0x4000>;
414
-
interrupts = <0 91 0x04 0 96 0x04>;
415
-
};
416
-
417
-
gpc: gpc@020dc000 {
418
-
compatible = "fsl,imx6q-gpc";
419
-
reg = <0x020dc000 0x4000>;
420
-
interrupts = <0 89 0x04 0 90 0x04>;
421
-
};
422
-
423
-
gpr: iomuxc-gpr@020e0000 {
424
-
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
425
-
reg = <0x020e0000 0x38>;
426
214
};
427
215
428
216
iomuxc: iomuxc@020e0000 {
···
282
780
};
283
781
};
284
782
};
285
-
286
-
dcic1: dcic@020e4000 {
287
-
reg = <0x020e4000 0x4000>;
288
-
interrupts = <0 124 0x04>;
289
-
};
290
-
291
-
dcic2: dcic@020e8000 {
292
-
reg = <0x020e8000 0x4000>;
293
-
interrupts = <0 125 0x04>;
294
-
};
295
-
296
-
sdma: sdma@020ec000 {
297
-
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
298
-
reg = <0x020ec000 0x4000>;
299
-
interrupts = <0 2 0x04>;
300
-
clocks = <&clks 155>, <&clks 155>;
301
-
clock-names = "ipg", "ahb";
302
-
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
303
-
};
304
-
};
305
-
306
-
aips-bus@02100000 { /* AIPS2 */
307
-
compatible = "fsl,aips-bus", "simple-bus";
308
-
#address-cells = <1>;
309
-
#size-cells = <1>;
310
-
reg = <0x02100000 0x100000>;
311
-
ranges;
312
-
313
-
caam@02100000 {
314
-
reg = <0x02100000 0x40000>;
315
-
interrupts = <0 105 0x04 0 106 0x04>;
316
-
};
317
-
318
-
aipstz@0217c000 { /* AIPSTZ2 */
319
-
reg = <0x0217c000 0x4000>;
320
-
};
321
-
322
-
usbotg: usb@02184000 {
323
-
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
324
-
reg = <0x02184000 0x200>;
325
-
interrupts = <0 43 0x04>;
326
-
clocks = <&clks 162>;
327
-
fsl,usbphy = <&usbphy1>;
328
-
fsl,usbmisc = <&usbmisc 0>;
329
-
status = "disabled";
330
-
};
331
-
332
-
usbh1: usb@02184200 {
333
-
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
334
-
reg = <0x02184200 0x200>;
335
-
interrupts = <0 40 0x04>;
336
-
clocks = <&clks 162>;
337
-
fsl,usbphy = <&usbphy2>;
338
-
fsl,usbmisc = <&usbmisc 1>;
339
-
status = "disabled";
340
-
};
341
-
342
-
usbh2: usb@02184400 {
343
-
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
344
-
reg = <0x02184400 0x200>;
345
-
interrupts = <0 41 0x04>;
346
-
clocks = <&clks 162>;
347
-
fsl,usbmisc = <&usbmisc 2>;
348
-
status = "disabled";
349
-
};
350
-
351
-
usbh3: usb@02184600 {
352
-
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
353
-
reg = <0x02184600 0x200>;
354
-
interrupts = <0 42 0x04>;
355
-
clocks = <&clks 162>;
356
-
fsl,usbmisc = <&usbmisc 3>;
357
-
status = "disabled";
358
-
};
359
-
360
-
usbmisc: usbmisc: usbmisc@02184800 {
361
-
#index-cells = <1>;
362
-
compatible = "fsl,imx6q-usbmisc";
363
-
reg = <0x02184800 0x200>;
364
-
clocks = <&clks 162>;
365
-
};
366
-
367
-
fec: ethernet@02188000 {
368
-
compatible = "fsl,imx6q-fec";
369
-
reg = <0x02188000 0x4000>;
370
-
interrupts = <0 118 0x04 0 119 0x04>;
371
-
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
372
-
clock-names = "ipg", "ahb", "ptp";
373
-
status = "disabled";
374
-
};
375
-
376
-
mlb@0218c000 {
377
-
reg = <0x0218c000 0x4000>;
378
-
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
379
-
};
380
-
381
-
usdhc1: usdhc@02190000 {
382
-
compatible = "fsl,imx6q-usdhc";
383
-
reg = <0x02190000 0x4000>;
384
-
interrupts = <0 22 0x04>;
385
-
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
386
-
clock-names = "ipg", "ahb", "per";
387
-
bus-width = <4>;
388
-
status = "disabled";
389
-
};
390
-
391
-
usdhc2: usdhc@02194000 {
392
-
compatible = "fsl,imx6q-usdhc";
393
-
reg = <0x02194000 0x4000>;
394
-
interrupts = <0 23 0x04>;
395
-
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
396
-
clock-names = "ipg", "ahb", "per";
397
-
bus-width = <4>;
398
-
status = "disabled";
399
-
};
400
-
401
-
usdhc3: usdhc@02198000 {
402
-
compatible = "fsl,imx6q-usdhc";
403
-
reg = <0x02198000 0x4000>;
404
-
interrupts = <0 24 0x04>;
405
-
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
406
-
clock-names = "ipg", "ahb", "per";
407
-
bus-width = <4>;
408
-
status = "disabled";
409
-
};
410
-
411
-
usdhc4: usdhc@0219c000 {
412
-
compatible = "fsl,imx6q-usdhc";
413
-
reg = <0x0219c000 0x4000>;
414
-
interrupts = <0 25 0x04>;
415
-
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
416
-
clock-names = "ipg", "ahb", "per";
417
-
bus-width = <4>;
418
-
status = "disabled";
419
-
};
420
-
421
-
i2c1: i2c@021a0000 {
422
-
#address-cells = <1>;
423
-
#size-cells = <0>;
424
-
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
425
-
reg = <0x021a0000 0x4000>;
426
-
interrupts = <0 36 0x04>;
427
-
clocks = <&clks 125>;
428
-
status = "disabled";
429
-
};
430
-
431
-
i2c2: i2c@021a4000 {
432
-
#address-cells = <1>;
433
-
#size-cells = <0>;
434
-
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
435
-
reg = <0x021a4000 0x4000>;
436
-
interrupts = <0 37 0x04>;
437
-
clocks = <&clks 126>;
438
-
status = "disabled";
439
-
};
440
-
441
-
i2c3: i2c@021a8000 {
442
-
#address-cells = <1>;
443
-
#size-cells = <0>;
444
-
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
445
-
reg = <0x021a8000 0x4000>;
446
-
interrupts = <0 38 0x04>;
447
-
clocks = <&clks 127>;
448
-
status = "disabled";
449
-
};
450
-
451
-
romcp@021ac000 {
452
-
reg = <0x021ac000 0x4000>;
453
-
};
454
-
455
-
mmdc0: mmdc@021b0000 { /* MMDC0 */
456
-
compatible = "fsl,imx6q-mmdc";
457
-
reg = <0x021b0000 0x4000>;
458
-
};
459
-
460
-
mmdc1: mmdc@021b4000 { /* MMDC1 */
461
-
reg = <0x021b4000 0x4000>;
462
-
};
463
-
464
-
weim@021b8000 {
465
-
reg = <0x021b8000 0x4000>;
466
-
interrupts = <0 14 0x04>;
467
-
};
468
-
469
-
ocotp@021bc000 {
470
-
reg = <0x021bc000 0x4000>;
471
-
};
472
-
473
-
ocotp@021c0000 {
474
-
reg = <0x021c0000 0x4000>;
475
-
interrupts = <0 21 0x04>;
476
-
};
477
-
478
-
tzasc@021d0000 { /* TZASC1 */
479
-
reg = <0x021d0000 0x4000>;
480
-
interrupts = <0 108 0x04>;
481
-
};
482
-
483
-
tzasc@021d4000 { /* TZASC2 */
484
-
reg = <0x021d4000 0x4000>;
485
-
interrupts = <0 109 0x04>;
486
-
};
487
-
488
-
audmux: audmux@021d8000 {
489
-
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
490
-
reg = <0x021d8000 0x4000>;
491
-
status = "disabled";
492
-
};
493
-
494
-
mipi@021dc000 { /* MIPI-CSI */
495
-
reg = <0x021dc000 0x4000>;
496
-
};
497
-
498
-
mipi@021e0000 { /* MIPI-DSI */
499
-
reg = <0x021e0000 0x4000>;
500
-
};
501
-
502
-
vdoa@021e4000 {
503
-
reg = <0x021e4000 0x4000>;
504
-
interrupts = <0 18 0x04>;
505
-
};
506
-
507
-
uart2: serial@021e8000 {
508
-
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
509
-
reg = <0x021e8000 0x4000>;
510
-
interrupts = <0 27 0x04>;
511
-
clocks = <&clks 160>, <&clks 161>;
512
-
clock-names = "ipg", "per";
513
-
status = "disabled";
514
-
};
515
-
516
-
uart3: serial@021ec000 {
517
-
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
518
-
reg = <0x021ec000 0x4000>;
519
-
interrupts = <0 28 0x04>;
520
-
clocks = <&clks 160>, <&clks 161>;
521
-
clock-names = "ipg", "per";
522
-
status = "disabled";
523
-
};
524
-
525
-
uart4: serial@021f0000 {
526
-
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
527
-
reg = <0x021f0000 0x4000>;
528
-
interrupts = <0 29 0x04>;
529
-
clocks = <&clks 160>, <&clks 161>;
530
-
clock-names = "ipg", "per";
531
-
status = "disabled";
532
-
};
533
-
534
-
uart5: serial@021f4000 {
535
-
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
536
-
reg = <0x021f4000 0x4000>;
537
-
interrupts = <0 30 0x04>;
538
-
clocks = <&clks 160>, <&clks 161>;
539
-
clock-names = "ipg", "per";
540
-
status = "disabled";
541
-
};
542
-
};
543
-
544
-
ipu1: ipu@02400000 {
545
-
#crtc-cells = <1>;
546
-
compatible = "fsl,imx6q-ipu";
547
-
reg = <0x02400000 0x400000>;
548
-
interrupts = <0 6 0x4 0 5 0x4>;
549
-
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
550
-
clock-names = "bus", "di0", "di1";
551
783
};
552
784
553
785
ipu2: ipu@02800000 {
+800
arch/arm/boot/dts/imx6qdl.dtsi
+800
arch/arm/boot/dts/imx6qdl.dtsi
···
1
+
/*
2
+
* Copyright 2011 Freescale Semiconductor, Inc.
3
+
* Copyright 2011 Linaro Ltd.
4
+
*
5
+
* The code contained herein is licensed under the GNU General Public
6
+
* License. You may obtain a copy of the GNU General Public License
7
+
* Version 2 or later at the following locations:
8
+
*
9
+
* http://www.opensource.org/licenses/gpl-license.html
10
+
* http://www.gnu.org/copyleft/gpl.html
11
+
*/
12
+
13
+
/include/ "skeleton.dtsi"
14
+
15
+
/ {
16
+
aliases {
17
+
serial0 = &uart1;
18
+
serial1 = &uart2;
19
+
serial2 = &uart3;
20
+
serial3 = &uart4;
21
+
serial4 = &uart5;
22
+
gpio0 = &gpio1;
23
+
gpio1 = &gpio2;
24
+
gpio2 = &gpio3;
25
+
gpio3 = &gpio4;
26
+
gpio4 = &gpio5;
27
+
gpio5 = &gpio6;
28
+
gpio6 = &gpio7;
29
+
};
30
+
31
+
intc: interrupt-controller@00a01000 {
32
+
compatible = "arm,cortex-a9-gic";
33
+
#interrupt-cells = <3>;
34
+
#address-cells = <1>;
35
+
#size-cells = <1>;
36
+
interrupt-controller;
37
+
reg = <0x00a01000 0x1000>,
38
+
<0x00a00100 0x100>;
39
+
};
40
+
41
+
clocks {
42
+
#address-cells = <1>;
43
+
#size-cells = <0>;
44
+
45
+
ckil {
46
+
compatible = "fsl,imx-ckil", "fixed-clock";
47
+
clock-frequency = <32768>;
48
+
};
49
+
50
+
ckih1 {
51
+
compatible = "fsl,imx-ckih1", "fixed-clock";
52
+
clock-frequency = <0>;
53
+
};
54
+
55
+
osc {
56
+
compatible = "fsl,imx-osc", "fixed-clock";
57
+
clock-frequency = <24000000>;
58
+
};
59
+
};
60
+
61
+
soc {
62
+
#address-cells = <1>;
63
+
#size-cells = <1>;
64
+
compatible = "simple-bus";
65
+
interrupt-parent = <&intc>;
66
+
ranges;
67
+
68
+
dma-apbh@00110000 {
69
+
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70
+
reg = <0x00110000 0x2000>;
71
+
clocks = <&clks 106>;
72
+
};
73
+
74
+
gpmi: gpmi-nand@00112000 {
75
+
compatible = "fsl,imx6q-gpmi-nand";
76
+
#address-cells = <1>;
77
+
#size-cells = <1>;
78
+
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
79
+
reg-names = "gpmi-nand", "bch";
80
+
interrupts = <0 13 0x04>, <0 15 0x04>;
81
+
interrupt-names = "gpmi-dma", "bch";
82
+
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
83
+
<&clks 150>, <&clks 149>;
84
+
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
85
+
"gpmi_bch_apb", "per1_bch";
86
+
fsl,gpmi-dma-channel = <0>;
87
+
status = "disabled";
88
+
};
89
+
90
+
timer@00a00600 {
91
+
compatible = "arm,cortex-a9-twd-timer";
92
+
reg = <0x00a00600 0x20>;
93
+
interrupts = <1 13 0xf01>;
94
+
};
95
+
96
+
L2: l2-cache@00a02000 {
97
+
compatible = "arm,pl310-cache";
98
+
reg = <0x00a02000 0x1000>;
99
+
interrupts = <0 92 0x04>;
100
+
cache-unified;
101
+
cache-level = <2>;
102
+
};
103
+
104
+
aips-bus@02000000 { /* AIPS1 */
105
+
compatible = "fsl,aips-bus", "simple-bus";
106
+
#address-cells = <1>;
107
+
#size-cells = <1>;
108
+
reg = <0x02000000 0x100000>;
109
+
ranges;
110
+
111
+
spba-bus@02000000 {
112
+
compatible = "fsl,spba-bus", "simple-bus";
113
+
#address-cells = <1>;
114
+
#size-cells = <1>;
115
+
reg = <0x02000000 0x40000>;
116
+
ranges;
117
+
118
+
spdif: spdif@02004000 {
119
+
reg = <0x02004000 0x4000>;
120
+
interrupts = <0 52 0x04>;
121
+
};
122
+
123
+
ecspi1: ecspi@02008000 {
124
+
#address-cells = <1>;
125
+
#size-cells = <0>;
126
+
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
127
+
reg = <0x02008000 0x4000>;
128
+
interrupts = <0 31 0x04>;
129
+
clocks = <&clks 112>, <&clks 112>;
130
+
clock-names = "ipg", "per";
131
+
status = "disabled";
132
+
};
133
+
134
+
ecspi2: ecspi@0200c000 {
135
+
#address-cells = <1>;
136
+
#size-cells = <0>;
137
+
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
138
+
reg = <0x0200c000 0x4000>;
139
+
interrupts = <0 32 0x04>;
140
+
clocks = <&clks 113>, <&clks 113>;
141
+
clock-names = "ipg", "per";
142
+
status = "disabled";
143
+
};
144
+
145
+
ecspi3: ecspi@02010000 {
146
+
#address-cells = <1>;
147
+
#size-cells = <0>;
148
+
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
149
+
reg = <0x02010000 0x4000>;
150
+
interrupts = <0 33 0x04>;
151
+
clocks = <&clks 114>, <&clks 114>;
152
+
clock-names = "ipg", "per";
153
+
status = "disabled";
154
+
};
155
+
156
+
ecspi4: ecspi@02014000 {
157
+
#address-cells = <1>;
158
+
#size-cells = <0>;
159
+
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160
+
reg = <0x02014000 0x4000>;
161
+
interrupts = <0 34 0x04>;
162
+
clocks = <&clks 115>, <&clks 115>;
163
+
clock-names = "ipg", "per";
164
+
status = "disabled";
165
+
};
166
+
167
+
uart1: serial@02020000 {
168
+
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
169
+
reg = <0x02020000 0x4000>;
170
+
interrupts = <0 26 0x04>;
171
+
clocks = <&clks 160>, <&clks 161>;
172
+
clock-names = "ipg", "per";
173
+
status = "disabled";
174
+
};
175
+
176
+
esai: esai@02024000 {
177
+
reg = <0x02024000 0x4000>;
178
+
interrupts = <0 51 0x04>;
179
+
};
180
+
181
+
ssi1: ssi@02028000 {
182
+
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
183
+
reg = <0x02028000 0x4000>;
184
+
interrupts = <0 46 0x04>;
185
+
clocks = <&clks 178>;
186
+
fsl,fifo-depth = <15>;
187
+
fsl,ssi-dma-events = <38 37>;
188
+
status = "disabled";
189
+
};
190
+
191
+
ssi2: ssi@0202c000 {
192
+
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
193
+
reg = <0x0202c000 0x4000>;
194
+
interrupts = <0 47 0x04>;
195
+
clocks = <&clks 179>;
196
+
fsl,fifo-depth = <15>;
197
+
fsl,ssi-dma-events = <42 41>;
198
+
status = "disabled";
199
+
};
200
+
201
+
ssi3: ssi@02030000 {
202
+
compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
203
+
reg = <0x02030000 0x4000>;
204
+
interrupts = <0 48 0x04>;
205
+
clocks = <&clks 180>;
206
+
fsl,fifo-depth = <15>;
207
+
fsl,ssi-dma-events = <46 45>;
208
+
status = "disabled";
209
+
};
210
+
211
+
asrc: asrc@02034000 {
212
+
reg = <0x02034000 0x4000>;
213
+
interrupts = <0 50 0x04>;
214
+
};
215
+
216
+
spba@0203c000 {
217
+
reg = <0x0203c000 0x4000>;
218
+
};
219
+
};
220
+
221
+
vpu: vpu@02040000 {
222
+
reg = <0x02040000 0x3c000>;
223
+
interrupts = <0 3 0x04 0 12 0x04>;
224
+
};
225
+
226
+
aipstz@0207c000 { /* AIPSTZ1 */
227
+
reg = <0x0207c000 0x4000>;
228
+
};
229
+
230
+
pwm1: pwm@02080000 {
231
+
#pwm-cells = <2>;
232
+
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
233
+
reg = <0x02080000 0x4000>;
234
+
interrupts = <0 83 0x04>;
235
+
clocks = <&clks 62>, <&clks 145>;
236
+
clock-names = "ipg", "per";
237
+
};
238
+
239
+
pwm2: pwm@02084000 {
240
+
#pwm-cells = <2>;
241
+
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
242
+
reg = <0x02084000 0x4000>;
243
+
interrupts = <0 84 0x04>;
244
+
clocks = <&clks 62>, <&clks 146>;
245
+
clock-names = "ipg", "per";
246
+
};
247
+
248
+
pwm3: pwm@02088000 {
249
+
#pwm-cells = <2>;
250
+
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
251
+
reg = <0x02088000 0x4000>;
252
+
interrupts = <0 85 0x04>;
253
+
clocks = <&clks 62>, <&clks 147>;
254
+
clock-names = "ipg", "per";
255
+
};
256
+
257
+
pwm4: pwm@0208c000 {
258
+
#pwm-cells = <2>;
259
+
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
260
+
reg = <0x0208c000 0x4000>;
261
+
interrupts = <0 86 0x04>;
262
+
clocks = <&clks 62>, <&clks 148>;
263
+
clock-names = "ipg", "per";
264
+
};
265
+
266
+
can1: flexcan@02090000 {
267
+
reg = <0x02090000 0x4000>;
268
+
interrupts = <0 110 0x04>;
269
+
};
270
+
271
+
can2: flexcan@02094000 {
272
+
reg = <0x02094000 0x4000>;
273
+
interrupts = <0 111 0x04>;
274
+
};
275
+
276
+
gpt: gpt@02098000 {
277
+
compatible = "fsl,imx6q-gpt";
278
+
reg = <0x02098000 0x4000>;
279
+
interrupts = <0 55 0x04>;
280
+
};
281
+
282
+
gpio1: gpio@0209c000 {
283
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
284
+
reg = <0x0209c000 0x4000>;
285
+
interrupts = <0 66 0x04 0 67 0x04>;
286
+
gpio-controller;
287
+
#gpio-cells = <2>;
288
+
interrupt-controller;
289
+
#interrupt-cells = <2>;
290
+
};
291
+
292
+
gpio2: gpio@020a0000 {
293
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
294
+
reg = <0x020a0000 0x4000>;
295
+
interrupts = <0 68 0x04 0 69 0x04>;
296
+
gpio-controller;
297
+
#gpio-cells = <2>;
298
+
interrupt-controller;
299
+
#interrupt-cells = <2>;
300
+
};
301
+
302
+
gpio3: gpio@020a4000 {
303
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
304
+
reg = <0x020a4000 0x4000>;
305
+
interrupts = <0 70 0x04 0 71 0x04>;
306
+
gpio-controller;
307
+
#gpio-cells = <2>;
308
+
interrupt-controller;
309
+
#interrupt-cells = <2>;
310
+
};
311
+
312
+
gpio4: gpio@020a8000 {
313
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
314
+
reg = <0x020a8000 0x4000>;
315
+
interrupts = <0 72 0x04 0 73 0x04>;
316
+
gpio-controller;
317
+
#gpio-cells = <2>;
318
+
interrupt-controller;
319
+
#interrupt-cells = <2>;
320
+
};
321
+
322
+
gpio5: gpio@020ac000 {
323
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
324
+
reg = <0x020ac000 0x4000>;
325
+
interrupts = <0 74 0x04 0 75 0x04>;
326
+
gpio-controller;
327
+
#gpio-cells = <2>;
328
+
interrupt-controller;
329
+
#interrupt-cells = <2>;
330
+
};
331
+
332
+
gpio6: gpio@020b0000 {
333
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
334
+
reg = <0x020b0000 0x4000>;
335
+
interrupts = <0 76 0x04 0 77 0x04>;
336
+
gpio-controller;
337
+
#gpio-cells = <2>;
338
+
interrupt-controller;
339
+
#interrupt-cells = <2>;
340
+
};
341
+
342
+
gpio7: gpio@020b4000 {
343
+
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
344
+
reg = <0x020b4000 0x4000>;
345
+
interrupts = <0 78 0x04 0 79 0x04>;
346
+
gpio-controller;
347
+
#gpio-cells = <2>;
348
+
interrupt-controller;
349
+
#interrupt-cells = <2>;
350
+
};
351
+
352
+
kpp: kpp@020b8000 {
353
+
reg = <0x020b8000 0x4000>;
354
+
interrupts = <0 82 0x04>;
355
+
};
356
+
357
+
wdog1: wdog@020bc000 {
358
+
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
359
+
reg = <0x020bc000 0x4000>;
360
+
interrupts = <0 80 0x04>;
361
+
clocks = <&clks 0>;
362
+
};
363
+
364
+
wdog2: wdog@020c0000 {
365
+
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
366
+
reg = <0x020c0000 0x4000>;
367
+
interrupts = <0 81 0x04>;
368
+
clocks = <&clks 0>;
369
+
status = "disabled";
370
+
};
371
+
372
+
clks: ccm@020c4000 {
373
+
compatible = "fsl,imx6q-ccm";
374
+
reg = <0x020c4000 0x4000>;
375
+
interrupts = <0 87 0x04 0 88 0x04>;
376
+
#clock-cells = <1>;
377
+
};
378
+
379
+
anatop: anatop@020c8000 {
380
+
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
381
+
reg = <0x020c8000 0x1000>;
382
+
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
383
+
384
+
regulator-1p1@110 {
385
+
compatible = "fsl,anatop-regulator";
386
+
regulator-name = "vdd1p1";
387
+
regulator-min-microvolt = <800000>;
388
+
regulator-max-microvolt = <1375000>;
389
+
regulator-always-on;
390
+
anatop-reg-offset = <0x110>;
391
+
anatop-vol-bit-shift = <8>;
392
+
anatop-vol-bit-width = <5>;
393
+
anatop-min-bit-val = <4>;
394
+
anatop-min-voltage = <800000>;
395
+
anatop-max-voltage = <1375000>;
396
+
};
397
+
398
+
regulator-3p0@120 {
399
+
compatible = "fsl,anatop-regulator";
400
+
regulator-name = "vdd3p0";
401
+
regulator-min-microvolt = <2800000>;
402
+
regulator-max-microvolt = <3150000>;
403
+
regulator-always-on;
404
+
anatop-reg-offset = <0x120>;
405
+
anatop-vol-bit-shift = <8>;
406
+
anatop-vol-bit-width = <5>;
407
+
anatop-min-bit-val = <0>;
408
+
anatop-min-voltage = <2625000>;
409
+
anatop-max-voltage = <3400000>;
410
+
};
411
+
412
+
regulator-2p5@130 {
413
+
compatible = "fsl,anatop-regulator";
414
+
regulator-name = "vdd2p5";
415
+
regulator-min-microvolt = <2000000>;
416
+
regulator-max-microvolt = <2750000>;
417
+
regulator-always-on;
418
+
anatop-reg-offset = <0x130>;
419
+
anatop-vol-bit-shift = <8>;
420
+
anatop-vol-bit-width = <5>;
421
+
anatop-min-bit-val = <0>;
422
+
anatop-min-voltage = <2000000>;
423
+
anatop-max-voltage = <2750000>;
424
+
};
425
+
426
+
reg_arm: regulator-vddcore@140 {
427
+
compatible = "fsl,anatop-regulator";
428
+
regulator-name = "cpu";
429
+
regulator-min-microvolt = <725000>;
430
+
regulator-max-microvolt = <1450000>;
431
+
regulator-always-on;
432
+
anatop-reg-offset = <0x140>;
433
+
anatop-vol-bit-shift = <0>;
434
+
anatop-vol-bit-width = <5>;
435
+
anatop-delay-reg-offset = <0x170>;
436
+
anatop-delay-bit-shift = <24>;
437
+
anatop-delay-bit-width = <2>;
438
+
anatop-min-bit-val = <1>;
439
+
anatop-min-voltage = <725000>;
440
+
anatop-max-voltage = <1450000>;
441
+
};
442
+
443
+
reg_pu: regulator-vddpu@140 {
444
+
compatible = "fsl,anatop-regulator";
445
+
regulator-name = "vddpu";
446
+
regulator-min-microvolt = <725000>;
447
+
regulator-max-microvolt = <1450000>;
448
+
regulator-always-on;
449
+
anatop-reg-offset = <0x140>;
450
+
anatop-vol-bit-shift = <9>;
451
+
anatop-vol-bit-width = <5>;
452
+
anatop-delay-reg-offset = <0x170>;
453
+
anatop-delay-bit-shift = <26>;
454
+
anatop-delay-bit-width = <2>;
455
+
anatop-min-bit-val = <1>;
456
+
anatop-min-voltage = <725000>;
457
+
anatop-max-voltage = <1450000>;
458
+
};
459
+
460
+
reg_soc: regulator-vddsoc@140 {
461
+
compatible = "fsl,anatop-regulator";
462
+
regulator-name = "vddsoc";
463
+
regulator-min-microvolt = <725000>;
464
+
regulator-max-microvolt = <1450000>;
465
+
regulator-always-on;
466
+
anatop-reg-offset = <0x140>;
467
+
anatop-vol-bit-shift = <18>;
468
+
anatop-vol-bit-width = <5>;
469
+
anatop-delay-reg-offset = <0x170>;
470
+
anatop-delay-bit-shift = <28>;
471
+
anatop-delay-bit-width = <2>;
472
+
anatop-min-bit-val = <1>;
473
+
anatop-min-voltage = <725000>;
474
+
anatop-max-voltage = <1450000>;
475
+
};
476
+
};
477
+
478
+
usbphy1: usbphy@020c9000 {
479
+
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
480
+
reg = <0x020c9000 0x1000>;
481
+
interrupts = <0 44 0x04>;
482
+
clocks = <&clks 182>;
483
+
};
484
+
485
+
usbphy2: usbphy@020ca000 {
486
+
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
487
+
reg = <0x020ca000 0x1000>;
488
+
interrupts = <0 45 0x04>;
489
+
clocks = <&clks 183>;
490
+
};
491
+
492
+
snvs@020cc000 {
493
+
compatible = "fsl,sec-v4.0-mon", "simple-bus";
494
+
#address-cells = <1>;
495
+
#size-cells = <1>;
496
+
ranges = <0 0x020cc000 0x4000>;
497
+
498
+
snvs-rtc-lp@34 {
499
+
compatible = "fsl,sec-v4.0-mon-rtc-lp";
500
+
reg = <0x34 0x58>;
501
+
interrupts = <0 19 0x04 0 20 0x04>;
502
+
};
503
+
};
504
+
505
+
epit1: epit@020d0000 { /* EPIT1 */
506
+
reg = <0x020d0000 0x4000>;
507
+
interrupts = <0 56 0x04>;
508
+
};
509
+
510
+
epit2: epit@020d4000 { /* EPIT2 */
511
+
reg = <0x020d4000 0x4000>;
512
+
interrupts = <0 57 0x04>;
513
+
};
514
+
515
+
src: src@020d8000 {
516
+
compatible = "fsl,imx6q-src";
517
+
reg = <0x020d8000 0x4000>;
518
+
interrupts = <0 91 0x04 0 96 0x04>;
519
+
};
520
+
521
+
gpc: gpc@020dc000 {
522
+
compatible = "fsl,imx6q-gpc";
523
+
reg = <0x020dc000 0x4000>;
524
+
interrupts = <0 89 0x04 0 90 0x04>;
525
+
};
526
+
527
+
gpr: iomuxc-gpr@020e0000 {
528
+
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
529
+
reg = <0x020e0000 0x38>;
530
+
};
531
+
532
+
dcic1: dcic@020e4000 {
533
+
reg = <0x020e4000 0x4000>;
534
+
interrupts = <0 124 0x04>;
535
+
};
536
+
537
+
dcic2: dcic@020e8000 {
538
+
reg = <0x020e8000 0x4000>;
539
+
interrupts = <0 125 0x04>;
540
+
};
541
+
542
+
sdma: sdma@020ec000 {
543
+
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
544
+
reg = <0x020ec000 0x4000>;
545
+
interrupts = <0 2 0x04>;
546
+
clocks = <&clks 155>, <&clks 155>;
547
+
clock-names = "ipg", "ahb";
548
+
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
549
+
};
550
+
};
551
+
552
+
aips-bus@02100000 { /* AIPS2 */
553
+
compatible = "fsl,aips-bus", "simple-bus";
554
+
#address-cells = <1>;
555
+
#size-cells = <1>;
556
+
reg = <0x02100000 0x100000>;
557
+
ranges;
558
+
559
+
caam@02100000 {
560
+
reg = <0x02100000 0x40000>;
561
+
interrupts = <0 105 0x04 0 106 0x04>;
562
+
};
563
+
564
+
aipstz@0217c000 { /* AIPSTZ2 */
565
+
reg = <0x0217c000 0x4000>;
566
+
};
567
+
568
+
usbotg: usb@02184000 {
569
+
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
570
+
reg = <0x02184000 0x200>;
571
+
interrupts = <0 43 0x04>;
572
+
clocks = <&clks 162>;
573
+
fsl,usbphy = <&usbphy1>;
574
+
fsl,usbmisc = <&usbmisc 0>;
575
+
status = "disabled";
576
+
};
577
+
578
+
usbh1: usb@02184200 {
579
+
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
580
+
reg = <0x02184200 0x200>;
581
+
interrupts = <0 40 0x04>;
582
+
clocks = <&clks 162>;
583
+
fsl,usbphy = <&usbphy2>;
584
+
fsl,usbmisc = <&usbmisc 1>;
585
+
status = "disabled";
586
+
};
587
+
588
+
usbh2: usb@02184400 {
589
+
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
590
+
reg = <0x02184400 0x200>;
591
+
interrupts = <0 41 0x04>;
592
+
clocks = <&clks 162>;
593
+
fsl,usbmisc = <&usbmisc 2>;
594
+
status = "disabled";
595
+
};
596
+
597
+
usbh3: usb@02184600 {
598
+
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
599
+
reg = <0x02184600 0x200>;
600
+
interrupts = <0 42 0x04>;
601
+
clocks = <&clks 162>;
602
+
fsl,usbmisc = <&usbmisc 3>;
603
+
status = "disabled";
604
+
};
605
+
606
+
usbmisc: usbmisc: usbmisc@02184800 {
607
+
#index-cells = <1>;
608
+
compatible = "fsl,imx6q-usbmisc";
609
+
reg = <0x02184800 0x200>;
610
+
clocks = <&clks 162>;
611
+
};
612
+
613
+
fec: ethernet@02188000 {
614
+
compatible = "fsl,imx6q-fec";
615
+
reg = <0x02188000 0x4000>;
616
+
interrupts = <0 118 0x04 0 119 0x04>;
617
+
clocks = <&clks 117>, <&clks 117>, <&clks 190>;
618
+
clock-names = "ipg", "ahb", "ptp";
619
+
status = "disabled";
620
+
};
621
+
622
+
mlb@0218c000 {
623
+
reg = <0x0218c000 0x4000>;
624
+
interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
625
+
};
626
+
627
+
usdhc1: usdhc@02190000 {
628
+
compatible = "fsl,imx6q-usdhc";
629
+
reg = <0x02190000 0x4000>;
630
+
interrupts = <0 22 0x04>;
631
+
clocks = <&clks 163>, <&clks 163>, <&clks 163>;
632
+
clock-names = "ipg", "ahb", "per";
633
+
bus-width = <4>;
634
+
status = "disabled";
635
+
};
636
+
637
+
usdhc2: usdhc@02194000 {
638
+
compatible = "fsl,imx6q-usdhc";
639
+
reg = <0x02194000 0x4000>;
640
+
interrupts = <0 23 0x04>;
641
+
clocks = <&clks 164>, <&clks 164>, <&clks 164>;
642
+
clock-names = "ipg", "ahb", "per";
643
+
bus-width = <4>;
644
+
status = "disabled";
645
+
};
646
+
647
+
usdhc3: usdhc@02198000 {
648
+
compatible = "fsl,imx6q-usdhc";
649
+
reg = <0x02198000 0x4000>;
650
+
interrupts = <0 24 0x04>;
651
+
clocks = <&clks 165>, <&clks 165>, <&clks 165>;
652
+
clock-names = "ipg", "ahb", "per";
653
+
bus-width = <4>;
654
+
status = "disabled";
655
+
};
656
+
657
+
usdhc4: usdhc@0219c000 {
658
+
compatible = "fsl,imx6q-usdhc";
659
+
reg = <0x0219c000 0x4000>;
660
+
interrupts = <0 25 0x04>;
661
+
clocks = <&clks 166>, <&clks 166>, <&clks 166>;
662
+
clock-names = "ipg", "ahb", "per";
663
+
bus-width = <4>;
664
+
status = "disabled";
665
+
};
666
+
667
+
i2c1: i2c@021a0000 {
668
+
#address-cells = <1>;
669
+
#size-cells = <0>;
670
+
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
671
+
reg = <0x021a0000 0x4000>;
672
+
interrupts = <0 36 0x04>;
673
+
clocks = <&clks 125>;
674
+
status = "disabled";
675
+
};
676
+
677
+
i2c2: i2c@021a4000 {
678
+
#address-cells = <1>;
679
+
#size-cells = <0>;
680
+
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
681
+
reg = <0x021a4000 0x4000>;
682
+
interrupts = <0 37 0x04>;
683
+
clocks = <&clks 126>;
684
+
status = "disabled";
685
+
};
686
+
687
+
i2c3: i2c@021a8000 {
688
+
#address-cells = <1>;
689
+
#size-cells = <0>;
690
+
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
691
+
reg = <0x021a8000 0x4000>;
692
+
interrupts = <0 38 0x04>;
693
+
clocks = <&clks 127>;
694
+
status = "disabled";
695
+
};
696
+
697
+
romcp@021ac000 {
698
+
reg = <0x021ac000 0x4000>;
699
+
};
700
+
701
+
mmdc0: mmdc@021b0000 { /* MMDC0 */
702
+
compatible = "fsl,imx6q-mmdc";
703
+
reg = <0x021b0000 0x4000>;
704
+
};
705
+
706
+
mmdc1: mmdc@021b4000 { /* MMDC1 */
707
+
reg = <0x021b4000 0x4000>;
708
+
};
709
+
710
+
weim@021b8000 {
711
+
reg = <0x021b8000 0x4000>;
712
+
interrupts = <0 14 0x04>;
713
+
};
714
+
715
+
ocotp@021bc000 {
716
+
compatible = "fsl,imx6q-ocotp";
717
+
reg = <0x021bc000 0x4000>;
718
+
};
719
+
720
+
ocotp@021c0000 {
721
+
reg = <0x021c0000 0x4000>;
722
+
interrupts = <0 21 0x04>;
723
+
};
724
+
725
+
tzasc@021d0000 { /* TZASC1 */
726
+
reg = <0x021d0000 0x4000>;
727
+
interrupts = <0 108 0x04>;
728
+
};
729
+
730
+
tzasc@021d4000 { /* TZASC2 */
731
+
reg = <0x021d4000 0x4000>;
732
+
interrupts = <0 109 0x04>;
733
+
};
734
+
735
+
audmux: audmux@021d8000 {
736
+
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
737
+
reg = <0x021d8000 0x4000>;
738
+
status = "disabled";
739
+
};
740
+
741
+
mipi@021dc000 { /* MIPI-CSI */
742
+
reg = <0x021dc000 0x4000>;
743
+
};
744
+
745
+
mipi@021e0000 { /* MIPI-DSI */
746
+
reg = <0x021e0000 0x4000>;
747
+
};
748
+
749
+
vdoa@021e4000 {
750
+
reg = <0x021e4000 0x4000>;
751
+
interrupts = <0 18 0x04>;
752
+
};
753
+
754
+
uart2: serial@021e8000 {
755
+
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
756
+
reg = <0x021e8000 0x4000>;
757
+
interrupts = <0 27 0x04>;
758
+
clocks = <&clks 160>, <&clks 161>;
759
+
clock-names = "ipg", "per";
760
+
status = "disabled";
761
+
};
762
+
763
+
uart3: serial@021ec000 {
764
+
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
765
+
reg = <0x021ec000 0x4000>;
766
+
interrupts = <0 28 0x04>;
767
+
clocks = <&clks 160>, <&clks 161>;
768
+
clock-names = "ipg", "per";
769
+
status = "disabled";
770
+
};
771
+
772
+
uart4: serial@021f0000 {
773
+
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
774
+
reg = <0x021f0000 0x4000>;
775
+
interrupts = <0 29 0x04>;
776
+
clocks = <&clks 160>, <&clks 161>;
777
+
clock-names = "ipg", "per";
778
+
status = "disabled";
779
+
};
780
+
781
+
uart5: serial@021f4000 {
782
+
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
783
+
reg = <0x021f4000 0x4000>;
784
+
interrupts = <0 30 0x04>;
785
+
clocks = <&clks 160>, <&clks 161>;
786
+
clock-names = "ipg", "per";
787
+
status = "disabled";
788
+
};
789
+
};
790
+
791
+
ipu1: ipu@02400000 {
792
+
#crtc-cells = <1>;
793
+
compatible = "fsl,imx6q-ipu";
794
+
reg = <0x02400000 0x400000>;
795
+
interrupts = <0 6 0x4 0 5 0x4>;
796
+
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
797
+
clock-names = "bus", "di0", "di1";
798
+
};
799
+
};
800
+
};
+3
-1
arch/arm/mach-imx/clk-imx51-imx53.c
+3
-1
arch/arm/mach-imx/clk-imx51-imx53.c
···
83
83
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84
84
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
85
85
can_sel, can1_serial_gate, can1_ipg_gate,
86
+
owire_gate,
86
87
clk_max
87
88
};
88
89
···
234
233
clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
235
234
clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
236
235
clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
236
+
clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
237
237
238
238
for (i = 0; i < ARRAY_SIZE(clk); i++)
239
239
if (IS_ERR(clk[i]))
240
240
pr_err("i.MX5 clk %d: register failed with %ld\n",
241
241
i, PTR_ERR(clk[i]));
242
-
242
+
243
243
clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
244
244
clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
245
245
clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
+22
-4
arch/arm/mach-imx/clk-imx6q.c
+22
-4
arch/arm/mach-imx/clk-imx6q.c
···
164
164
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
165
165
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
166
166
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
167
-
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
168
-
clk_max
167
+
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
168
+
usbphy2_gate, clk_max
169
169
};
170
170
171
171
static struct clk *clk[clk_max];
···
218
218
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
219
219
clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
220
220
221
-
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
222
-
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
221
+
/*
222
+
* Bit 20 is the reserved and read-only bit, we do this only for:
223
+
* - Do nothing for usbphy clk_enable/disable
224
+
* - Keep refcount when do usbphy clk_enable/disable, in that case,
225
+
* the clk framework may need to enable/disable usbphy's parent
226
+
*/
227
+
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
228
+
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
229
+
230
+
/*
231
+
* usbphy*_gate needs to be on after system boots up, and software
232
+
* never needs to control it anymore.
233
+
*/
234
+
clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
235
+
clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
223
236
224
237
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
225
238
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
···
458
445
459
446
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
460
447
clk_prepare_enable(clk[clks_init_on[i]]);
448
+
449
+
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
450
+
clk_prepare_enable(clk[usbphy1_gate]);
451
+
clk_prepare_enable(clk[usbphy2_gate]);
452
+
}
461
453
462
454
/* Set initial power mode */
463
455
imx6q_set_lpm(WAIT_CLOCKED);
+65
arch/arm/mach-imx/mach-imx6q.c
+65
arch/arm/mach-imx/mach-imx6q.c
···
12
12
13
13
#include <linux/clk.h>
14
14
#include <linux/clkdev.h>
15
+
#include <linux/cpu.h>
15
16
#include <linux/delay.h>
16
17
#include <linux/export.h>
17
18
#include <linux/init.h>
···
23
22
#include <linux/of_address.h>
24
23
#include <linux/of_irq.h>
25
24
#include <linux/of_platform.h>
25
+
#include <linux/opp.h>
26
26
#include <linux/phy.h>
27
27
#include <linux/regmap.h>
28
28
#include <linux/micrel_phy.h>
···
202
200
imx6q_1588_init();
203
201
}
204
202
203
+
#define OCOTP_CFG3 0x440
204
+
#define OCOTP_CFG3_SPEED_SHIFT 16
205
+
#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
206
+
207
+
static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
208
+
{
209
+
struct device_node *np;
210
+
void __iomem *base;
211
+
u32 val;
212
+
213
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
214
+
if (!np) {
215
+
pr_warn("failed to find ocotp node\n");
216
+
return;
217
+
}
218
+
219
+
base = of_iomap(np, 0);
220
+
if (!base) {
221
+
pr_warn("failed to map ocotp\n");
222
+
goto put_node;
223
+
}
224
+
225
+
val = readl_relaxed(base + OCOTP_CFG3);
226
+
val >>= OCOTP_CFG3_SPEED_SHIFT;
227
+
if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
228
+
if (opp_disable(cpu_dev, 1200000000))
229
+
pr_warn("failed to disable 1.2 GHz OPP\n");
230
+
231
+
put_node:
232
+
of_node_put(np);
233
+
}
234
+
235
+
static void __init imx6q_opp_init(struct device *cpu_dev)
236
+
{
237
+
struct device_node *np;
238
+
239
+
np = of_find_node_by_path("/cpus/cpu@0");
240
+
if (!np) {
241
+
pr_warn("failed to find cpu0 node\n");
242
+
return;
243
+
}
244
+
245
+
cpu_dev->of_node = np;
246
+
if (of_init_opp_table(cpu_dev)) {
247
+
pr_warn("failed to init OPP table\n");
248
+
goto put_node;
249
+
}
250
+
251
+
imx6q_opp_check_1p2ghz(cpu_dev);
252
+
253
+
put_node:
254
+
of_node_put(np);
255
+
}
256
+
257
+
struct platform_device imx6q_cpufreq_pdev = {
258
+
.name = "imx6q-cpufreq",
259
+
};
260
+
205
261
static void __init imx6q_init_late(void)
206
262
{
207
263
/*
···
268
208
*/
269
209
if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
270
210
imx6q_cpuidle_init();
211
+
212
+
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
213
+
imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
214
+
platform_device_register(&imx6q_cpufreq_pdev);
215
+
}
271
216
}
272
217
273
218
static void __init imx6q_map_io(void)
+8
-1
drivers/w1/masters/mxc_w1.c
+8
-1
drivers/w1/masters/mxc_w1.c
···
157
157
return 0;
158
158
}
159
159
160
+
static struct of_device_id mxc_w1_dt_ids[] = {
161
+
{ .compatible = "fsl,imx21-owire" },
162
+
{ /* sentinel */ }
163
+
};
164
+
MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
165
+
160
166
static struct platform_driver mxc_w1_driver = {
161
167
.driver = {
162
-
.name = "mxc_w1",
168
+
.name = "mxc_w1",
169
+
.of_match_table = mxc_w1_dt_ids,
163
170
},
164
171
.probe = mxc_w1_probe,
165
172
.remove = mxc_w1_remove,