Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: soc: fsl: cpm_qe: Add TSA controller

Add support for the time slot assigner (TSA)
available in some PowerQUICC SoC such as MPC885
or MPC866.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20230217145645.1768659-2-herve.codina@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Herve Codina and committed by
Mark Brown
f8c760e8 fe15c26e

+228
+215
Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: PowerQUICC CPM Time-slot assigner (TSA) controller 8 + 9 + maintainers: 10 + - Herve Codina <herve.codina@bootlin.com> 11 + 12 + description: 13 + The TSA is the time-slot assigner that can be found on some PowerQUICC SoC. 14 + Its purpose is to route some TDM time-slots to other internal serial 15 + controllers. 16 + 17 + properties: 18 + compatible: 19 + items: 20 + - enum: 21 + - fsl,mpc885-tsa 22 + - fsl,mpc866-tsa 23 + - const: fsl,cpm1-tsa 24 + 25 + reg: 26 + items: 27 + - description: SI (Serial Interface) register base 28 + - description: SI RAM base 29 + 30 + reg-names: 31 + items: 32 + - const: si_regs 33 + - const: si_ram 34 + 35 + '#address-cells': 36 + const: 1 37 + 38 + '#size-cells': 39 + const: 0 40 + 41 + '#fsl,serial-cells': 42 + $ref: /schemas/types.yaml#/definitions/uint32 43 + const: 1 44 + description: 45 + TSA consumers that use a phandle to TSA need to pass the serial identifier 46 + with this phandle (defined in dt-bindings/soc/fsl,tsa.h). 47 + For instance "fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;". 48 + 49 + patternProperties: 50 + '^tdm@[0-1]$': 51 + description: 52 + The TDM managed by this controller 53 + type: object 54 + 55 + additionalProperties: false 56 + 57 + properties: 58 + reg: 59 + minimum: 0 60 + maximum: 1 61 + description: 62 + The TDM number for this TDM, 0 for TDMa and 1 for TDMb 63 + 64 + fsl,common-rxtx-pins: 65 + $ref: /schemas/types.yaml#/definitions/flag 66 + description: 67 + The hardware can use four dedicated pins for Tx clock, Tx sync, Rx 68 + clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync. 69 + Without the 'fsl,common-rxtx-pins' property, the four pins are used. 70 + With the 'fsl,common-rxtx-pins' property, two pins are used. 71 + 72 + clocks: 73 + minItems: 2 74 + items: 75 + - description: External clock connected to L1RSYNC pin 76 + - description: External clock connected to L1RCLK pin 77 + - description: External clock connected to L1TSYNC pin 78 + - description: External clock connected to L1TCLK pin 79 + 80 + clock-names: 81 + minItems: 2 82 + items: 83 + - const: l1rsync 84 + - const: l1rclk 85 + - const: l1tsync 86 + - const: l1tclk 87 + 88 + fsl,rx-frame-sync-delay-bits: 89 + enum: [0, 1, 2, 3] 90 + default: 0 91 + description: | 92 + Receive frame sync delay in number of bits. 93 + Indicates the delay between the Rx sync and the first bit of the Rx 94 + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. 95 + 96 + fsl,tx-frame-sync-delay-bits: 97 + enum: [0, 1, 2, 3] 98 + default: 0 99 + description: | 100 + Transmit frame sync delay in number of bits. 101 + Indicates the delay between the Tx sync and the first bit of the Tx 102 + frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay. 103 + 104 + fsl,clock-falling-edge: 105 + $ref: /schemas/types.yaml#/definitions/flag 106 + description: 107 + Data is sent on falling edge of the clock (and received on the rising 108 + edge). If 'clock-falling-edge' is not present, data is sent on the 109 + rising edge (and received on the falling edge). 110 + 111 + fsl,fsync-rising-edge: 112 + $ref: /schemas/types.yaml#/definitions/flag 113 + description: 114 + Frame sync pulses are sampled with the rising edge of the channel 115 + clock. If 'fsync-rising-edge' is not present, pulses are sampled with 116 + the falling edge. 117 + 118 + fsl,double-speed-clock: 119 + $ref: /schemas/types.yaml#/definitions/flag 120 + description: 121 + The channel clock is twice the data rate. 122 + 123 + patternProperties: 124 + '^fsl,[rt]x-ts-routes$': 125 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 126 + description: | 127 + A list of tuple that indicates the Tx or Rx time-slots routes. 128 + items: 129 + items: 130 + - description: 131 + The number of time-slots 132 + minimum: 1 133 + maximum: 64 134 + - description: | 135 + The source (Tx) or destination (Rx) serial interface 136 + (dt-bindings/soc/cpm1-fsl,tsa.h defines these values) 137 + - 0: No destination 138 + - 1: SCC2 139 + - 2: SCC3 140 + - 3: SCC4 141 + - 4: SMC1 142 + - 5: SMC2 143 + enum: [0, 1, 2, 3, 4, 5] 144 + minItems: 1 145 + maxItems: 64 146 + 147 + allOf: 148 + # If fsl,common-rxtx-pins is present, only 2 clocks are needed. 149 + # Else, the 4 clocks must be present. 150 + - if: 151 + required: 152 + - fsl,common-rxtx-pins 153 + then: 154 + properties: 155 + clocks: 156 + maxItems: 2 157 + clock-names: 158 + maxItems: 2 159 + else: 160 + properties: 161 + clocks: 162 + minItems: 4 163 + clock-names: 164 + minItems: 4 165 + 166 + required: 167 + - reg 168 + - clocks 169 + - clock-names 170 + 171 + required: 172 + - compatible 173 + - reg 174 + - reg-names 175 + - '#address-cells' 176 + - '#size-cells' 177 + - '#fsl,serial-cells' 178 + 179 + additionalProperties: false 180 + 181 + examples: 182 + - | 183 + #include <dt-bindings/soc/cpm1-fsl,tsa.h> 184 + 185 + tsa@ae0 { 186 + compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa"; 187 + reg = <0xae0 0x10>, 188 + <0xc00 0x200>; 189 + reg-names = "si_regs", "si_ram"; 190 + 191 + #address-cells = <1>; 192 + #size-cells = <0>; 193 + #fsl,serial-cells = <1>; 194 + 195 + tdm@0 { 196 + /* TDMa */ 197 + reg = <0>; 198 + 199 + clocks = <&clk_l1rsynca>, <&clk_l1rclka>; 200 + clock-names = "l1rsync", "l1rclk"; 201 + 202 + fsl,common-rxtx-pins; 203 + fsl,fsync-rising-edge; 204 + 205 + fsl,tx-ts-routes = <2 0>, /* TS 0..1 */ 206 + <24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */ 207 + <1 0>, /* TS 26 */ 208 + <5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */ 209 + 210 + fsl,rx-ts-routes = <2 0>, /* TS 0..1 */ 211 + <24 FSL_CPM_TSA_SCC4>, /* 2..25 */ 212 + <1 0>, /* TS 26 */ 213 + <5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */ 214 + }; 215 + };
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include/dt-bindings/soc/cpm1-fsl,tsa.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 2 + 3 + #ifndef __DT_BINDINGS_SOC_FSL_TSA_H 4 + #define __DT_BINDINGS_SOC_FSL_TSA_H 5 + 6 + #define FSL_CPM_TSA_NU 0 /* Pseuso Cell Id for not used item */ 7 + #define FSL_CPM_TSA_SCC2 1 8 + #define FSL_CPM_TSA_SCC3 2 9 + #define FSL_CPM_TSA_SCC4 3 10 + #define FSL_CPM_TSA_SMC1 4 11 + #define FSL_CPM_TSA_SMC2 5 12 + 13 + #endif