tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
PCI: remove printks about disabled bridge windows
PCI: fold pci_calc_resource_flags() into decode_bar()
PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR
PCI: correct pcie_set_readrq write size
PCI: pciehp: change wait time for valid configuration access
x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems
PCI: ARI is a PCIe v2 feature
x86/PCI: quirks: Use pci_dev->revision
PCI: Make the struct pci_dev * argument of pci_fixup_irqs const.
PCI hotplug: cpqphp: use pci_dev->vendor
PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device}
x86/PCI: config space accessor functions should not ignore the segment argument
PCI: Assign values to 'pci_obff_signal_type' enumeration constants
x86/PCI: reduce severity of host bridge window conflict warnings
PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI
PCI: PCIe AER: add aer_recover_queue
x86/PCI: select direct access mode for mmconfig option
PCI hotplug: Rename is_ejectable which also exists in dock.c
+294
-215
+1
-1
arch/alpha/kernel/sys_alcor.c
+1
-1
arch/alpha/kernel/sys_alcor.c
+3
-3
arch/alpha/kernel/sys_cabriolet.c
+3
-3
arch/alpha/kernel/sys_cabriolet.c
···
175
175
*/
176
176
177
177
static inline int __init
178
-
eb66p_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
178
+
eb66p_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
179
179
{
180
180
static char irq_tab[5][5] __initdata = {
181
181
/*INT INTA INTB INTC INTD */
···
205
205
*/
206
206
207
207
static inline int __init
208
-
cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
208
+
cabriolet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
209
209
{
210
210
static char irq_tab[5][5] __initdata = {
211
211
/*INT INTA INTB INTC INTD */
···
289
289
*/
290
290
291
291
static inline int __init
292
-
alphapc164_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
292
+
alphapc164_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
293
293
{
294
294
static char irq_tab[7][5] __initdata = {
295
295
/*INT INTA INTB INTC INTD */
+4
-4
arch/alpha/kernel/sys_dp264.c
+4
-4
arch/alpha/kernel/sys_dp264.c
···
382
382
}
383
383
384
384
static int __init
385
-
dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
385
+
dp264_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
386
386
{
387
387
static char irq_tab[6][5] __initdata = {
388
388
/*INT INTA INTB INTC INTD */
···
404
404
}
405
405
406
406
static int __init
407
-
monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
407
+
monet_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
408
408
{
409
409
static char irq_tab[13][5] __initdata = {
410
410
/*INT INTA INTB INTC INTD */
···
466
466
}
467
467
468
468
static int __init
469
-
webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
469
+
webbrick_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
470
470
{
471
471
static char irq_tab[13][5] __initdata = {
472
472
/*INT INTA INTB INTC INTD */
···
488
488
}
489
489
490
490
static int __init
491
-
clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
491
+
clipper_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
492
492
{
493
493
static char irq_tab[7][5] __initdata = {
494
494
/*INT INTA INTB INTC INTD */
+1
-1
arch/alpha/kernel/sys_eb64p.c
+1
-1
arch/alpha/kernel/sys_eb64p.c
+1
-1
arch/alpha/kernel/sys_eiger.c
+1
-1
arch/alpha/kernel/sys_eiger.c
+1
-1
arch/alpha/kernel/sys_marvel.c
+1
-1
arch/alpha/kernel/sys_marvel.c
+1
-1
arch/alpha/kernel/sys_miata.c
+1
-1
arch/alpha/kernel/sys_miata.c
+1
-1
arch/alpha/kernel/sys_mikasa.c
+1
-1
arch/alpha/kernel/sys_mikasa.c
+1
-1
arch/alpha/kernel/sys_nautilus.c
+1
-1
arch/alpha/kernel/sys_nautilus.c
+1
-1
arch/alpha/kernel/sys_noritake.c
+1
-1
arch/alpha/kernel/sys_noritake.c
+1
-1
arch/alpha/kernel/sys_rawhide.c
+1
-1
arch/alpha/kernel/sys_rawhide.c
+1
-1
arch/alpha/kernel/sys_ruffian.c
+1
-1
arch/alpha/kernel/sys_ruffian.c
+1
-1
arch/alpha/kernel/sys_rx164.c
+1
-1
arch/alpha/kernel/sys_rx164.c
+2
-2
arch/alpha/kernel/sys_sable.c
+2
-2
arch/alpha/kernel/sys_sable.c
···
194
194
*/
195
195
196
196
static int __init
197
-
sable_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
197
+
sable_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
198
198
{
199
199
static char irq_tab[9][5] __initdata = {
200
200
/*INT INTA INTB INTC INTD */
···
376
376
*/
377
377
378
378
static int __init
379
-
lynx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
379
+
lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
380
380
{
381
381
static char irq_tab[19][5] __initdata = {
382
382
/*INT INTA INTB INTC INTD */
+2
-2
arch/alpha/kernel/sys_sio.c
+2
-2
arch/alpha/kernel/sys_sio.c
···
146
146
}
147
147
148
148
static inline int __init
149
-
noname_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
149
+
noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
150
150
{
151
151
/*
152
152
* The Noname board has 5 PCI slots with each of the 4
···
185
185
}
186
186
187
187
static inline int __init
188
-
p2k_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
188
+
p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
189
189
{
190
190
static char irq_tab[][5] __initdata = {
191
191
/*INT A B C D */
+1
-1
arch/alpha/kernel/sys_sx164.c
+1
-1
arch/alpha/kernel/sys_sx164.c
+2
-2
arch/alpha/kernel/sys_takara.c
+2
-2
arch/alpha/kernel/sys_takara.c
···
157
157
*/
158
158
159
159
static int __init
160
-
takara_map_irq_srm(struct pci_dev *dev, u8 slot, u8 pin)
160
+
takara_map_irq_srm(const struct pci_dev *dev, u8 slot, u8 pin)
161
161
{
162
162
static char irq_tab[15][5] __initdata = {
163
163
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
···
188
188
}
189
189
190
190
static int __init
191
-
takara_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
191
+
takara_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
192
192
{
193
193
static char irq_tab[15][5] __initdata = {
194
194
{ 16+3, 16+3, 16+3, 16+3, 16+3}, /* slot 6 == device 3 */
+1
-1
arch/alpha/kernel/sys_titan.c
+1
-1
arch/alpha/kernel/sys_titan.c
+1
-1
arch/alpha/kernel/sys_wildfire.c
+1
-1
arch/alpha/kernel/sys_wildfire.c
+1
-1
arch/arm/common/it8152.c
+1
-1
arch/arm/common/it8152.c
···
144
144
}
145
145
146
146
/* mapping for on-chip devices */
147
-
int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
147
+
int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
148
148
{
149
149
if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
150
150
(dev->device == PCI_DEVICE_ID_ITE_8152)) {
+1
-1
arch/arm/include/asm/hardware/it8152.h
+1
-1
arch/arm/include/asm/hardware/it8152.h
···
105
105
106
106
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
107
107
extern void it8152_init_irq(void);
108
-
extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
108
+
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
109
109
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
110
110
extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
111
111
+2
-2
arch/arm/include/asm/mach/pci.h
+2
-2
arch/arm/include/asm/mach/pci.h
···
25
25
void (*preinit)(void);
26
26
void (*postinit)(void);
27
27
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
28
-
int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
28
+
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
29
29
};
30
30
31
31
/*
···
44
44
/* Bridge swizzling */
45
45
u8 (*swizzle)(struct pci_dev *, u8 *);
46
46
/* IRQ mapping */
47
-
int (*map_irq)(struct pci_dev *, u8, u8);
47
+
int (*map_irq)(const struct pci_dev *, u8, u8);
48
48
struct hw_pci *hw;
49
49
void *private_data; /* platform controller private data */
50
50
};
+1
-1
arch/arm/kernel/bios32.c
+1
-1
arch/arm/kernel/bios32.c
+1
-1
arch/arm/mach-cns3xxx/pcie.c
+1
-1
arch/arm/mach-cns3xxx/pcie.c
···
172
172
return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
173
173
}
174
174
175
-
static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
175
+
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
176
176
{
177
177
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
178
178
int irq = cnspci->irqs[slot];
+1
-1
arch/arm/mach-dove/pcie.c
+1
-1
arch/arm/mach-dove/pcie.c
+1
-1
arch/arm/mach-footbridge/cats-pci.c
+1
-1
arch/arm/mach-footbridge/cats-pci.c
···
16
16
/* cats host-specific stuff */
17
17
static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
18
18
19
-
static int __init cats_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
19
+
static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
20
20
{
21
21
if (dev->irq >= 255)
22
22
return -1; /* not a valid interrupt. */
+1
-1
arch/arm/mach-footbridge/ebsa285-pci.c
+1
-1
arch/arm/mach-footbridge/ebsa285-pci.c
···
15
15
16
16
static int irqmap_ebsa285[] __initdata = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI };
17
17
18
-
static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
18
+
static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
19
19
{
20
20
if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
21
21
dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
+1
-1
arch/arm/mach-footbridge/netwinder-pci.c
+1
-1
arch/arm/mach-footbridge/netwinder-pci.c
···
17
17
* We now use the slot ID instead of the device identifiers to select
18
18
* which interrupt is routed where.
19
19
*/
20
-
static int __init netwinder_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
20
+
static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
21
21
{
22
22
switch (slot) {
23
23
case 0: /* host bridge */
+2
-1
arch/arm/mach-footbridge/personal-pci.c
+2
-1
arch/arm/mach-footbridge/personal-pci.c
+1
-1
arch/arm/mach-integrator/pci.c
+1
-1
arch/arm/mach-integrator/pci.c
···
95
95
* map the specified device/slot/pin to an IRQ. This works out such
96
96
* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
97
97
*/
98
-
static int __init integrator_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
98
+
static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
99
99
{
100
100
int intnr = ((slot - 9) + (pin - 1)) & 3;
101
101
+1
-1
arch/arm/mach-iop13xx/iq81340mc.c
+1
-1
arch/arm/mach-iop13xx/iq81340mc.c
···
30
30
extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */
31
31
32
32
static int __init
33
-
iq81340mc_pcix_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
33
+
iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
34
34
{
35
35
switch (idsel) {
36
36
case 1:
+1
-1
arch/arm/mach-iop13xx/pci.c
+1
-1
arch/arm/mach-iop13xx/pci.c
+1
-1
arch/arm/mach-iop32x/em7210.c
+1
-1
arch/arm/mach-iop32x/em7210.c
+1
-1
arch/arm/mach-iop32x/glantank.c
+1
-1
arch/arm/mach-iop32x/glantank.c
+2
-2
arch/arm/mach-iop32x/iq31244.c
+2
-2
arch/arm/mach-iop32x/iq31244.c
···
103
103
* EP80219/IQ31244 PCI.
104
104
*/
105
105
static int __init
106
-
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
106
+
ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
107
107
{
108
108
int irq;
109
109
···
139
139
};
140
140
141
141
static int __init
142
-
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
142
+
iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
143
143
{
144
144
int irq;
145
145
+1
-1
arch/arm/mach-iop32x/iq80321.c
+1
-1
arch/arm/mach-iop32x/iq80321.c
+1
-1
arch/arm/mach-iop32x/n2100.c
+1
-1
arch/arm/mach-iop32x/n2100.c
+1
-1
arch/arm/mach-iop33x/iq80331.c
+1
-1
arch/arm/mach-iop33x/iq80331.c
+1
-1
arch/arm/mach-iop33x/iq80332.c
+1
-1
arch/arm/mach-iop33x/iq80332.c
+2
-1
arch/arm/mach-ixp2000/enp2611.c
+2
-1
arch/arm/mach-ixp2000/enp2611.c
+2
-1
arch/arm/mach-ixp2000/ixdp2400.c
+2
-1
arch/arm/mach-ixp2000/ixdp2400.c
+2
-1
arch/arm/mach-ixp2000/ixdp2800.c
+2
-1
arch/arm/mach-ixp2000/ixdp2800.c
+2
-1
arch/arm/mach-ixp2000/ixdp2x01.c
+2
-1
arch/arm/mach-ixp2000/ixdp2x01.c
···
252
252
253
253
#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
254
254
255
-
static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
255
+
static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
256
+
u8 pin)
256
257
{
257
258
u8 bus = dev->bus->number;
258
259
u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
+1
-1
arch/arm/mach-ixp23xx/ixdp2351.c
+1
-1
arch/arm/mach-ixp23xx/ixdp2351.c
···
168
168
*/
169
169
#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
170
170
171
-
static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
171
+
static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
172
172
{
173
173
u8 bus = dev->bus->number;
174
174
u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
+2
-1
arch/arm/mach-ixp23xx/roadrunner.c
+2
-1
arch/arm/mach-ixp23xx/roadrunner.c
···
56
56
#define INTC_PIN IXP23XX_GPIO_PIN_11
57
57
#define INTD_PIN IXP23XX_GPIO_PIN_12
58
58
59
-
static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
59
+
static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel,
60
+
u8 pin)
60
61
{
61
62
static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
62
63
static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
+1
-1
arch/arm/mach-ixp4xx/avila-pci.c
+1
-1
arch/arm/mach-ixp4xx/avila-pci.c
+1
-1
arch/arm/mach-ixp4xx/coyote-pci.c
+1
-1
arch/arm/mach-ixp4xx/coyote-pci.c
+1
-1
arch/arm/mach-ixp4xx/dsmg600-pci.c
+1
-1
arch/arm/mach-ixp4xx/dsmg600-pci.c
···
44
44
ixp4xx_pci_preinit();
45
45
}
46
46
47
-
static int __init dsmg600_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
47
+
static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
48
48
{
49
49
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
50
50
{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
+1
-1
arch/arm/mach-ixp4xx/fsg-pci.c
+1
-1
arch/arm/mach-ixp4xx/fsg-pci.c
+2
-1
arch/arm/mach-ixp4xx/gateway7001-pci.c
+2
-1
arch/arm/mach-ixp4xx/gateway7001-pci.c
+1
-1
arch/arm/mach-ixp4xx/goramo_mlr.c
+1
-1
arch/arm/mach-ixp4xx/goramo_mlr.c
+1
-1
arch/arm/mach-ixp4xx/gtwx5715-pci.c
+1
-1
arch/arm/mach-ixp4xx/gtwx5715-pci.c
+1
-1
arch/arm/mach-ixp4xx/ixdp425-pci.c
+1
-1
arch/arm/mach-ixp4xx/ixdp425-pci.c
+1
-1
arch/arm/mach-ixp4xx/ixdpg425-pci.c
+1
-1
arch/arm/mach-ixp4xx/ixdpg425-pci.c
+1
-1
arch/arm/mach-ixp4xx/nas100d-pci.c
+1
-1
arch/arm/mach-ixp4xx/nas100d-pci.c
···
41
41
ixp4xx_pci_preinit();
42
42
}
43
43
44
-
static int __init nas100d_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
44
+
static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
45
45
{
46
46
static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
47
47
{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
+1
-1
arch/arm/mach-ixp4xx/nslu2-pci.c
+1
-1
arch/arm/mach-ixp4xx/nslu2-pci.c
+1
-1
arch/arm/mach-ixp4xx/vulcan-pci.c
+1
-1
arch/arm/mach-ixp4xx/vulcan-pci.c
+1
-1
arch/arm/mach-ixp4xx/wg302v2-pci.c
+1
-1
arch/arm/mach-ixp4xx/wg302v2-pci.c
+2
-1
arch/arm/mach-kirkwood/pcie.c
+2
-1
arch/arm/mach-kirkwood/pcie.c
+1
-1
arch/arm/mach-ks8695/board-dsm320.c
+1
-1
arch/arm/mach-ks8695/board-dsm320.c
+1
-1
arch/arm/mach-ks8695/board-micrel.c
+1
-1
arch/arm/mach-ks8695/board-micrel.c
+1
-1
arch/arm/mach-ks8695/include/mach/devices.h
+1
-1
arch/arm/mach-ks8695/include/mach/devices.h
+2
-1
arch/arm/mach-mv78xx0/pcie.c
+2
-1
arch/arm/mach-mv78xx0/pcie.c
+1
-1
arch/arm/mach-orion5x/common.h
+1
-1
arch/arm/mach-orion5x/common.h
···
51
51
void orion5x_pci_set_cardbus_mode(void);
52
52
int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
53
53
struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
54
-
int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
54
+
int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
55
55
56
56
struct machine_desc;
57
57
struct meminfo;
+2
-1
arch/arm/mach-orion5x/db88f5281-setup.c
+2
-1
arch/arm/mach-orion5x/db88f5281-setup.c
+2
-2
arch/arm/mach-orion5x/dns323-setup.c
+2
-2
arch/arm/mach-orion5x/dns323-setup.c
···
70
70
* PCI setup
71
71
*/
72
72
73
-
static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
73
+
static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
74
74
{
75
75
int irq;
76
76
77
77
/*
78
78
* Check for devices with hard-wired IRQs.
79
79
*/
80
-
irq = orion5x_pci_map_irq(dev, slot, pin);
80
+
irq = orion5x_pci_map_irq(const dev, slot, pin);
81
81
if (irq != -1)
82
82
return irq;
83
83
+2
-1
arch/arm/mach-orion5x/kurobox_pro-setup.c
+2
-1
arch/arm/mach-orion5x/kurobox_pro-setup.c
···
119
119
* PCI
120
120
****************************************************************************/
121
121
122
-
static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
122
+
static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
123
+
u8 pin)
123
124
{
124
125
int irq;
125
126
+1
-1
arch/arm/mach-orion5x/mss2-setup.c
+1
-1
arch/arm/mach-orion5x/mss2-setup.c
···
73
73
/****************************************************************************
74
74
* PCI setup
75
75
****************************************************************************/
76
-
static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
76
+
static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
77
77
{
78
78
int irq;
79
79
+1
-1
arch/arm/mach-orion5x/pci.c
+1
-1
arch/arm/mach-orion5x/pci.c
+1
-1
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+1
-1
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+1
-1
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+1
-1
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+2
-1
arch/arm/mach-orion5x/rd88f5182-setup.c
+2
-1
arch/arm/mach-orion5x/rd88f5182-setup.c
+1
-1
arch/arm/mach-orion5x/terastation_pro2-setup.c
+1
-1
arch/arm/mach-orion5x/terastation_pro2-setup.c
+2
-1
arch/arm/mach-orion5x/ts209-setup.c
+2
-1
arch/arm/mach-orion5x/ts209-setup.c
+2
-1
arch/arm/mach-orion5x/ts409-setup.c
+2
-1
arch/arm/mach-orion5x/ts409-setup.c
···
121
121
* PCI
122
122
****************************************************************************/
123
123
124
-
static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
124
+
static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
125
+
u8 pin)
125
126
{
126
127
int irq;
127
128
+2
-1
arch/arm/mach-orion5x/wnr854t-setup.c
+2
-1
arch/arm/mach-orion5x/wnr854t-setup.c
+2
-1
arch/arm/mach-orion5x/wrt350n-v2-setup.c
+2
-1
arch/arm/mach-orion5x/wrt350n-v2-setup.c
+1
-1
arch/arm/mach-pxa/cm-x2xx-pci.c
+1
-1
arch/arm/mach-pxa/cm-x2xx-pci.c
+2
-1
arch/arm/mach-sa1100/pci-nanoengine.c
+2
-1
arch/arm/mach-sa1100/pci-nanoengine.c
···
122
122
.write = nanoengine_write_config,
123
123
};
124
124
125
-
static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
125
+
static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
126
+
u8 pin)
126
127
{
127
128
return NANOENGINE_IRQ_GPIO_PCI;
128
129
}
+1
-1
arch/arm/mach-shark/pci.c
+1
-1
arch/arm/mach-shark/pci.c
+1
-1
arch/arm/mach-tegra/pcie.c
+1
-1
arch/arm/mach-tegra/pcie.c
+1
-1
arch/arm/mach-versatile/pci.c
+1
-1
arch/arm/mach-versatile/pci.c
···
328
328
/*
329
329
* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
330
330
*/
331
-
static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
331
+
static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
332
332
{
333
333
int irq;
334
334
int devslot = PCI_SLOT(dev->devfn);
+1
-1
arch/sh/drivers/pci/fixups-cayman.c
+1
-1
arch/sh/drivers/pci/fixups-cayman.c
+1
-1
arch/sh/drivers/pci/fixups-dreamcast.c
+1
-1
arch/sh/drivers/pci/fixups-dreamcast.c
···
64
64
}
65
65
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, gapspci_fixup_resources);
66
66
67
-
int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
67
+
int __init pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin)
68
68
{
69
69
/*
70
70
* The interrupt routing semantics here are quite trivial.
+1
-1
arch/sh/drivers/pci/fixups-landisk.c
+1
-1
arch/sh/drivers/pci/fixups-landisk.c
+1
-1
arch/sh/drivers/pci/fixups-r7780rp.c
+1
-1
arch/sh/drivers/pci/fixups-r7780rp.c
+1
-1
arch/sh/drivers/pci/fixups-rts7751r2d.c
+1
-1
arch/sh/drivers/pci/fixups-rts7751r2d.c
···
31
31
IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
32
32
};
33
33
34
-
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
34
+
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
35
35
{
36
36
if (mach_is_lboxre2())
37
37
return lboxre2_irq_tab[slot];
+1
-1
arch/sh/drivers/pci/fixups-sdk7780.c
+1
-1
arch/sh/drivers/pci/fixups-sdk7780.c
···
27
27
{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28
28
};
29
29
30
-
int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
30
+
int __init pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
31
31
{
32
32
return sdk7780_irq_tab[pin-1][slot];
33
33
}
+1
-1
arch/sh/drivers/pci/fixups-se7751.c
+1
-1
arch/sh/drivers/pci/fixups-se7751.c
+1
-1
arch/sh/drivers/pci/fixups-sh03.c
+1
-1
arch/sh/drivers/pci/fixups-sh03.c
+1
-1
arch/sh/drivers/pci/fixups-snapgear.c
+1
-1
arch/sh/drivers/pci/fixups-snapgear.c
+1
-1
arch/sh/drivers/pci/fixups-titan.c
+1
-1
arch/sh/drivers/pci/fixups-titan.c
+1
-1
arch/sh/drivers/pci/pcie-sh7786.c
+1
-1
arch/sh/drivers/pci/pcie-sh7786.c
+1
-1
arch/sh/include/asm/pci.h
+1
-1
arch/sh/include/asm/pci.h
···
112
112
#endif
113
113
114
114
/* Board-specific fixup routines. */
115
-
int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
115
+
int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
116
116
117
117
extern void pcibios_resource_to_bus(struct pci_dev *dev,
118
118
struct pci_bus_region *region, struct resource *res);
+1
-1
arch/sparc/include/asm/leon_pci.h
+1
-1
arch/sparc/include/asm/leon_pci.h
+1
-1
arch/sparc/kernel/leon_pci_grpci2.c
+1
-1
arch/sparc/kernel/leon_pci_grpci2.c
···
215
215
DEFINE_SPINLOCK(grpci2_dev_lock);
216
216
struct grpci2_priv *grpci2priv;
217
217
218
-
int grpci2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
218
+
int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
219
219
{
220
220
struct grpci2_priv *priv = dev->bus->sysdata;
221
221
int irq_group;
+1
-1
arch/tile/kernel/pci.c
+1
-1
arch/tile/kernel/pci.c
···
228
228
* (pin - 1) converts from the PCI standard's [1:4] convention to
229
229
* a normal [0:3] range.
230
230
*/
231
-
static int tile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
231
+
static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
232
232
{
233
233
struct pci_controller *controller =
234
234
(struct pci_controller *)dev->sysdata;
+1
-1
arch/unicore32/kernel/pci.c
+1
-1
arch/unicore32/kernel/pci.c
···
102
102
writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD);
103
103
}
104
104
105
-
static int __init pci_puv3_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
105
+
static int __init pci_puv3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
106
106
{
107
107
if (dev->bus->number == 0) {
108
108
#ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
+1
-1
arch/x86/Kconfig
+1
-1
arch/x86/Kconfig
···
1905
1905
# x86-64 doesn't support PCI BIOS access from long mode so always go direct.
1906
1906
config PCI_DIRECT
1907
1907
def_bool y
1908
-
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC))
1908
+
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC || PCI_GOMMCONFIG))
1909
1909
1910
1910
config PCI_MMCONFIG
1911
1911
def_bool y
+3
-4
arch/x86/pci/acpi.c
+3
-4
arch/x86/pci/acpi.c
···
246
246
247
247
conflict = insert_resource_conflict(root, res);
248
248
if (conflict)
249
-
dev_err(&info->bridge->dev,
250
-
"address space collision: host bridge window %pR "
251
-
"conflicts with %s %pR\n",
252
-
res, conflict->name, conflict);
249
+
dev_info(&info->bridge->dev,
250
+
"ignoring host bridge window %pR (conflicts with %s %pR)\n",
251
+
res, conflict->name, conflict);
253
252
else
254
253
pci_bus_add_resource(info->bus, res, 0);
255
254
}
+2
arch/x86/pci/ce4100.c
+2
arch/x86/pci/ce4100.c
···
257
257
{
258
258
int i;
259
259
260
+
WARN_ON(seg);
260
261
if (bus == 1) {
261
262
for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
262
263
if (bus1_fixups[i].dev_func == devfn &&
···
283
282
{
284
283
int i;
285
284
285
+
WARN_ON(seg);
286
286
if (bus == 1) {
287
287
for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
288
288
if (bus1_fixups[i].dev_func == devfn &&
+7
-7
arch/x86/pci/common.c
+7
-7
arch/x86/pci/common.c
···
247
247
},
248
248
#endif /* __i386__ */
249
249
{
250
-
.callback = find_sort_method,
251
-
.ident = "Dell System",
252
-
.matches = {
253
-
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
254
-
},
255
-
},
256
-
{
257
250
.callback = set_bf_sort,
258
251
.ident = "Dell PowerEdge 1950",
259
252
.matches = {
···
284
291
.matches = {
285
292
DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
286
293
DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
294
+
},
295
+
},
296
+
{
297
+
.callback = find_sort_method,
298
+
.ident = "Dell System",
299
+
.matches = {
300
+
DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
287
301
},
288
302
},
289
303
{
+4
-2
arch/x86/pci/direct.c
+4
-2
arch/x86/pci/direct.c
···
22
22
{
23
23
unsigned long flags;
24
24
25
-
if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
25
+
if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
26
26
*value = -1;
27
27
return -EINVAL;
28
28
}
···
53
53
{
54
54
unsigned long flags;
55
55
56
-
if ((bus > 255) || (devfn > 255) || (reg > 4095))
56
+
if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
57
57
return -EINVAL;
58
58
59
59
raw_spin_lock_irqsave(&pci_config_lock, flags);
···
97
97
unsigned long flags;
98
98
int dev, fn;
99
99
100
+
WARN_ON(seg);
100
101
if ((bus > 255) || (devfn > 255) || (reg > 255)) {
101
102
*value = -1;
102
103
return -EINVAL;
···
139
138
unsigned long flags;
140
139
int dev, fn;
141
140
141
+
WARN_ON(seg);
142
142
if ((bus > 255) || (devfn > 255) || (reg > 255))
143
143
return -EINVAL;
144
144
+2
arch/x86/pci/numaq_32.c
+2
arch/x86/pci/numaq_32.c
···
34
34
unsigned long flags;
35
35
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
36
36
37
+
WARN_ON(seg);
37
38
if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
38
39
return -EINVAL;
39
40
···
74
73
unsigned long flags;
75
74
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
76
75
76
+
WARN_ON(seg);
77
77
if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
78
78
return -EINVAL;
79
79
+4
arch/x86/pci/olpc.c
+4
arch/x86/pci/olpc.c
···
206
206
{
207
207
uint32_t *addr;
208
208
209
+
WARN_ON(seg);
210
+
209
211
/* Use the hardware mechanism for non-simulated devices */
210
212
if (!is_simulated(bus, devfn))
211
213
return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
···
266
264
static int pci_olpc_write(unsigned int seg, unsigned int bus,
267
265
unsigned int devfn, int reg, int len, uint32_t value)
268
266
{
267
+
WARN_ON(seg);
268
+
269
269
/* Use the hardware mechanism for non-simulated devices */
270
270
if (!is_simulated(bus, devfn))
271
271
return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
+2
arch/x86/pci/pcbios.c
+2
arch/x86/pci/pcbios.c
···
181
181
unsigned long flags;
182
182
unsigned long bx = (bus << 8) | devfn;
183
183
184
+
WARN_ON(seg);
184
185
if (!value || (bus > 255) || (devfn > 255) || (reg > 255))
185
186
return -EINVAL;
186
187
···
248
247
unsigned long flags;
249
248
unsigned long bx = (bus << 8) | devfn;
250
249
250
+
WARN_ON(seg);
251
251
if ((bus > 255) || (devfn > 255) || (reg > 255))
252
252
return -EINVAL;
253
253
+1
-1
arch/x86/pci/visws.c
+1
-1
arch/x86/pci/visws.c
+3
-3
drivers/pci/hotplug/acpi_pcihp.c
+3
-3
drivers/pci/hotplug/acpi_pcihp.c
···
408
408
}
409
409
EXPORT_SYMBOL(acpi_get_hp_hw_control_from_firmware);
410
410
411
-
static int is_ejectable(acpi_handle handle)
411
+
static int pcihp_is_ejectable(acpi_handle handle)
412
412
{
413
413
acpi_status status;
414
414
acpi_handle tmp;
···
442
442
return 0;
443
443
if (bridge_handle != parent_handle)
444
444
return 0;
445
-
return is_ejectable(handle);
445
+
return pcihp_is_ejectable(handle);
446
446
}
447
447
EXPORT_SYMBOL_GPL(acpi_pci_check_ejectable);
448
448
···
450
450
check_hotplug(acpi_handle handle, u32 lvl, void *context, void **rv)
451
451
{
452
452
int *found = (int *)context;
453
-
if (is_ejectable(handle)) {
453
+
if (pcihp_is_ejectable(handle)) {
454
454
*found = 1;
455
455
return AE_CTRL_TERMINATE;
456
456
}
+5
-12
drivers/pci/hotplug/cpqphp_core.c
+5
-12
drivers/pci/hotplug/cpqphp_core.c
···
840
840
/* Need to read VID early b/c it's used to differentiate CPQ and INTC
841
841
* discovery
842
842
*/
843
-
rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
844
-
if (rc || ((vendor_id != PCI_VENDOR_ID_COMPAQ) && (vendor_id != PCI_VENDOR_ID_INTEL))) {
843
+
vendor_id = pdev->vendor;
844
+
if ((vendor_id != PCI_VENDOR_ID_COMPAQ) &&
845
+
(vendor_id != PCI_VENDOR_ID_INTEL)) {
845
846
err(msg_HPC_non_compaq_or_intel);
846
847
rc = -ENODEV;
847
848
goto err_disable_device;
···
869
868
/* TODO: This code can be made to support non-Compaq or Intel
870
869
* subsystem IDs
871
870
*/
872
-
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &subsystem_vid);
873
-
if (rc) {
874
-
err("%s : pci_read_config_word failed\n", __func__);
875
-
goto err_disable_device;
876
-
}
871
+
subsystem_vid = pdev->subsystem_vendor;
877
872
dbg("Subsystem Vendor ID: %x\n", subsystem_vid);
878
873
if ((subsystem_vid != PCI_VENDOR_ID_COMPAQ) && (subsystem_vid != PCI_VENDOR_ID_INTEL)) {
879
874
err(msg_HPC_non_compaq_or_intel);
···
884
887
goto err_disable_device;
885
888
}
886
889
887
-
rc = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsystem_deviceid);
888
-
if (rc) {
889
-
err("%s : pci_read_config_word failed\n", __func__);
890
-
goto err_free_ctrl;
891
-
}
890
+
subsystem_deviceid = pdev->subsystem_device;
892
891
893
892
info("Hot Plug Subsystem Device ID: %x\n", subsystem_deviceid);
894
893
+3
drivers/pci/hotplug/pciehp_ctrl.c
+3
drivers/pci/hotplug/pciehp_ctrl.c
···
213
213
goto err_exit;
214
214
}
215
215
216
+
/* Wait for 1 second after checking link training status */
217
+
msleep(1000);
218
+
216
219
/* Check for a power fault */
217
220
if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
218
221
ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
+2
-9
drivers/pci/hotplug/pciehp_hpc.c
+2
-9
drivers/pci/hotplug/pciehp_hpc.c
···
275
275
* hot-plug capable downstream port. But old controller might
276
276
* not implement it. In this case, we wait for 1000 ms.
277
277
*/
278
-
if (ctrl->link_active_reporting){
279
-
/* Wait for Data Link Layer Link Active bit to be set */
278
+
if (ctrl->link_active_reporting)
280
279
pcie_wait_link_active(ctrl);
281
-
/*
282
-
* We must wait for 100 ms after the Data Link Layer
283
-
* Link Active bit reads 1b before initiating a
284
-
* configuration access to the hot added device.
285
-
*/
286
-
msleep(100);
287
-
} else
280
+
else
288
281
msleep(1000);
289
282
290
283
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
+8
-3
drivers/pci/pci.c
+8
-3
drivers/pci/pci.c
···
1905
1905
{
1906
1906
int pos;
1907
1907
u32 cap;
1908
-
u16 ctrl;
1908
+
u16 flags, ctrl;
1909
1909
struct pci_dev *bridge;
1910
1910
1911
1911
if (!pci_is_pcie(dev) || dev->devfn)
···
1921
1921
1922
1922
pos = pci_pcie_cap(bridge);
1923
1923
if (!pos)
1924
+
return;
1925
+
1926
+
/* ARI is a PCIe v2 feature */
1927
+
pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1928
+
if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1924
1929
return;
1925
1930
1926
1931
pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
···
3191
3186
* @rq: maximum memory read count in bytes
3192
3187
* valid values are 128, 256, 512, 1024, 2048, 4096
3193
3188
*
3194
-
* If possible sets maximum read byte count
3189
+
* If possible sets maximum memory read request in bytes
3195
3190
*/
3196
3191
int pcie_set_readrq(struct pci_dev *dev, int rq)
3197
3192
{
···
3214
3209
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3215
3210
ctl &= ~PCI_EXP_DEVCTL_READRQ;
3216
3211
ctl |= v;
3217
-
err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
3212
+
err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3218
3213
}
3219
3214
3220
3215
out:
+69
-7
drivers/pci/pcie/aer/aerdrv_core.c
+69
-7
drivers/pci/pcie/aer/aerdrv_core.c
···
24
24
#include <linux/suspend.h>
25
25
#include <linux/delay.h>
26
26
#include <linux/slab.h>
27
+
#include <linux/kfifo.h>
27
28
#include "aerdrv.h"
28
29
29
30
static int forceload;
···
446
445
return drv;
447
446
}
448
447
449
-
static pci_ers_result_t reset_link(struct pcie_device *aerdev,
450
-
struct pci_dev *dev)
448
+
static pci_ers_result_t reset_link(struct pci_dev *dev)
451
449
{
452
450
struct pci_dev *udev;
453
451
pci_ers_result_t status;
···
486
486
487
487
/**
488
488
* do_recovery - handle nonfatal/fatal error recovery process
489
-
* @aerdev: pointer to a pcie_device data structure of root port
490
489
* @dev: pointer to a pci_dev data structure of agent detecting an error
491
490
* @severity: error severity type
492
491
*
···
493
494
* error detected message to all downstream drivers within a hierarchy in
494
495
* question and return the returned code.
495
496
*/
496
-
static void do_recovery(struct pcie_device *aerdev, struct pci_dev *dev,
497
-
int severity)
497
+
static void do_recovery(struct pci_dev *dev, int severity)
498
498
{
499
499
pci_ers_result_t status, result = PCI_ERS_RESULT_RECOVERED;
500
500
enum pci_channel_state state;
···
509
511
report_error_detected);
510
512
511
513
if (severity == AER_FATAL) {
512
-
result = reset_link(aerdev, dev);
514
+
result = reset_link(dev);
513
515
if (result != PCI_ERS_RESULT_RECOVERED)
514
516
goto failed;
515
517
}
···
574
576
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
575
577
info->status);
576
578
} else
577
-
do_recovery(aerdev, dev, info->severity);
579
+
do_recovery(dev, info->severity);
578
580
}
581
+
582
+
#ifdef CONFIG_ACPI_APEI_PCIEAER
583
+
static void aer_recover_work_func(struct work_struct *work);
584
+
585
+
#define AER_RECOVER_RING_ORDER 4
586
+
#define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
587
+
588
+
struct aer_recover_entry
589
+
{
590
+
u8 bus;
591
+
u8 devfn;
592
+
u16 domain;
593
+
int severity;
594
+
};
595
+
596
+
static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
597
+
AER_RECOVER_RING_SIZE);
598
+
/*
599
+
* Mutual exclusion for writers of aer_recover_ring, reader side don't
600
+
* need lock, because there is only one reader and lock is not needed
601
+
* between reader and writer.
602
+
*/
603
+
static DEFINE_SPINLOCK(aer_recover_ring_lock);
604
+
static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
605
+
606
+
void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
607
+
int severity)
608
+
{
609
+
unsigned long flags;
610
+
struct aer_recover_entry entry = {
611
+
.bus = bus,
612
+
.devfn = devfn,
613
+
.domain = domain,
614
+
.severity = severity,
615
+
};
616
+
617
+
spin_lock_irqsave(&aer_recover_ring_lock, flags);
618
+
if (kfifo_put(&aer_recover_ring, &entry))
619
+
schedule_work(&aer_recover_work);
620
+
else
621
+
pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
622
+
domain, bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
623
+
spin_unlock_irqrestore(&aer_recover_ring_lock, flags);
624
+
}
625
+
EXPORT_SYMBOL_GPL(aer_recover_queue);
626
+
627
+
static void aer_recover_work_func(struct work_struct *work)
628
+
{
629
+
struct aer_recover_entry entry;
630
+
struct pci_dev *pdev;
631
+
632
+
while (kfifo_get(&aer_recover_ring, &entry)) {
633
+
pdev = pci_get_domain_bus_and_slot(entry.domain, entry.bus,
634
+
entry.devfn);
635
+
if (!pdev) {
636
+
pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
637
+
entry.domain, entry.bus,
638
+
PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
639
+
continue;
640
+
}
641
+
do_recovery(pdev, entry.severity);
642
+
}
643
+
}
644
+
#endif
579
645
580
646
/**
581
647
* get_device_error_info - read error status from dev and store it to info
+2
-1
drivers/pci/pcie/aer/aerdrv_errprint.c
+2
-1
drivers/pci/pcie/aer/aerdrv_errprint.c
···
204
204
}
205
205
206
206
#ifdef CONFIG_ACPI_APEI_PCIEAER
207
-
static int cper_severity_to_aer(int cper_severity)
207
+
int cper_severity_to_aer(int cper_severity)
208
208
{
209
209
switch (cper_severity) {
210
210
case CPER_SEV_RECOVERABLE:
···
215
215
return AER_CORRECTABLE;
216
216
}
217
217
}
218
+
EXPORT_SYMBOL_GPL(cper_severity_to_aer);
218
219
219
220
void cper_print_aer(const char *prefix, int cper_severity,
220
221
struct aer_capability_regs *aer)
+41
-46
drivers/pci/probe.c
+41
-46
drivers/pci/probe.c
···
68
68
}
69
69
postcore_initcall(pcibus_class_init);
70
70
71
-
/*
72
-
* Translate the low bits of the PCI base
73
-
* to the resource type
74
-
*/
75
-
static inline unsigned int pci_calc_resource_flags(unsigned int flags)
76
-
{
77
-
if (flags & PCI_BASE_ADDRESS_SPACE_IO)
78
-
return IORESOURCE_IO;
79
-
80
-
if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
81
-
return IORESOURCE_MEM | IORESOURCE_PREFETCH;
82
-
83
-
return IORESOURCE_MEM;
84
-
}
85
-
86
71
static u64 pci_size(u64 base, u64 maxbase, u64 mask)
87
72
{
88
73
u64 size = mask & maxbase; /* Find the significant bits */
···
86
101
return size;
87
102
}
88
103
89
-
static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
104
+
static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
90
105
{
106
+
u32 mem_type;
107
+
unsigned long flags;
108
+
91
109
if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
92
-
res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
93
-
return pci_bar_io;
110
+
flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
111
+
flags |= IORESOURCE_IO;
112
+
return flags;
94
113
}
95
114
96
-
res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
115
+
flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
116
+
flags |= IORESOURCE_MEM;
117
+
if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
118
+
flags |= IORESOURCE_PREFETCH;
97
119
98
-
if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
99
-
return pci_bar_mem64;
100
-
return pci_bar_mem32;
120
+
mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
121
+
switch (mem_type) {
122
+
case PCI_BASE_ADDRESS_MEM_TYPE_32:
123
+
break;
124
+
case PCI_BASE_ADDRESS_MEM_TYPE_1M:
125
+
dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
126
+
break;
127
+
case PCI_BASE_ADDRESS_MEM_TYPE_64:
128
+
flags |= IORESOURCE_MEM_64;
129
+
break;
130
+
default:
131
+
dev_warn(&dev->dev,
132
+
"mem unknown type %x treated as 32-bit BAR\n",
133
+
mem_type);
134
+
break;
135
+
}
136
+
return flags;
101
137
}
102
138
103
139
/**
···
171
165
l = 0;
172
166
173
167
if (type == pci_bar_unknown) {
174
-
type = decode_bar(res, l);
175
-
res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
176
-
if (type == pci_bar_io) {
168
+
res->flags = decode_bar(dev, l);
169
+
res->flags |= IORESOURCE_SIZEALIGN;
170
+
if (res->flags & IORESOURCE_IO) {
177
171
l &= PCI_BASE_ADDRESS_IO_MASK;
178
172
mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
179
173
} else {
···
186
180
mask = (u32)PCI_ROM_ADDRESS_MASK;
187
181
}
188
182
189
-
if (type == pci_bar_mem64) {
183
+
if (res->flags & IORESOURCE_MEM_64) {
190
184
u64 l64 = l;
191
185
u64 sz64 = sz;
192
186
u64 mask64 = mask | (u64)~0 << 32;
···
210
204
goto fail;
211
205
}
212
206
213
-
res->flags |= IORESOURCE_MEM_64;
214
207
if ((sizeof(resource_size_t) < 8) && l) {
215
208
/* Address above 32-bit boundary; disable the BAR */
216
209
pci_write_config_dword(dev, pos, 0);
···
235
230
}
236
231
237
232
out:
238
-
return (type == pci_bar_mem64) ? 1 : 0;
233
+
return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
239
234
fail:
240
235
res->flags = 0;
241
236
goto out;
···
289
284
if (!res->end)
290
285
res->end = limit + 0xfff;
291
286
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
292
-
} else {
293
-
dev_printk(KERN_DEBUG, &dev->dev,
294
-
" bridge window [io %#06lx-%#06lx] (disabled)\n",
295
-
base, limit);
296
287
}
297
288
}
298
289
···
309
308
res->start = base;
310
309
res->end = limit + 0xfffff;
311
310
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
312
-
} else {
313
-
dev_printk(KERN_DEBUG, &dev->dev,
314
-
" bridge window [mem %#010lx-%#010lx] (disabled)\n",
315
-
base, limit + 0xfffff);
316
311
}
317
312
}
318
313
···
356
359
res->start = base;
357
360
res->end = limit + 0xfffff;
358
361
dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
359
-
} else {
360
-
dev_printk(KERN_DEBUG, &dev->dev,
361
-
" bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
362
-
base, limit + 0xfffff);
363
362
}
364
363
}
365
364
···
718
725
pci_write_config_word(dev, PCI_STATUS, 0xffff);
719
726
720
727
/* Prevent assigning a bus number that already exists.
721
-
* This can happen when a bridge is hot-plugged */
722
-
if (pci_find_bus(pci_domain_nr(bus), max+1))
723
-
goto out;
724
-
child = pci_add_new_bus(bus, dev, ++max);
725
-
if (!child)
726
-
goto out;
728
+
* This can happen when a bridge is hot-plugged, so in
729
+
* this case we only re-scan this bus. */
730
+
child = pci_find_bus(pci_domain_nr(bus), max+1);
731
+
if (!child) {
732
+
child = pci_add_new_bus(bus, dev, ++max);
733
+
if (!child)
734
+
goto out;
735
+
}
727
736
buses = (buses & 0xff000000)
728
737
| ((unsigned int)(child->primary) << 0)
729
738
| ((unsigned int)(child->secondary) << 8)
-3
drivers/pci/setup-bus.c
-3
drivers/pci/setup-bus.c
···
336
336
/* Clear upper 16 bits of I/O base/limit. */
337
337
io_upper16 = 0;
338
338
l = 0x00f0;
339
-
dev_info(&bridge->dev, " bridge window [io disabled]\n");
340
339
}
341
340
/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
342
341
pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
···
361
362
dev_info(&bridge->dev, " bridge window %pR\n", res);
362
363
} else {
363
364
l = 0x0000fff0;
364
-
dev_info(&bridge->dev, " bridge window [mem disabled]\n");
365
365
}
366
366
pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
367
367
}
···
391
393
dev_info(&bridge->dev, " bridge window %pR\n", res);
392
394
} else {
393
395
l = 0x0000fff0;
394
-
dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
395
396
}
396
397
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
397
398
+2
-2
drivers/pci/setup-irq.c
+2
-2
drivers/pci/setup-irq.c
···
21
21
static void __init
22
22
pdev_fixup_irq(struct pci_dev *dev,
23
23
u8 (*swizzle)(struct pci_dev *, u8 *),
24
-
int (*map_irq)(struct pci_dev *, u8, u8))
24
+
int (*map_irq)(const struct pci_dev *, u8, u8))
25
25
{
26
26
u8 pin, slot;
27
27
int irq = 0;
···
56
56
57
57
void __init
58
58
pci_fixup_irqs(u8 (*swizzle)(struct pci_dev *, u8 *),
59
-
int (*map_irq)(struct pci_dev *, u8, u8))
59
+
int (*map_irq)(const struct pci_dev *, u8, u8))
60
60
{
61
61
struct pci_dev *dev = NULL;
62
62
for_each_pci_dev(dev)
+1
-2
drivers/pci/setup-res.c
+1
-2
drivers/pci/setup-res.c
···
74
74
resno, new, check);
75
75
}
76
76
77
-
if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
78
-
(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
77
+
if (res->flags & IORESOURCE_MEM_64) {
79
78
new = region.start >> 16 >> 16;
80
79
pci_write_config_dword(dev, reg + 4, new);
81
80
pci_read_config_dword(dev, reg + 4, &check);
+3
include/linux/aer.h
+3
include/linux/aer.h
···
51
51
52
52
extern void cper_print_aer(const char *prefix, int cper_severity,
53
53
struct aer_capability_regs *aer);
54
+
extern int cper_severity_to_aer(int cper_severity);
55
+
extern void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
56
+
int severity);
54
57
#endif //_AER_H_
55
58
+3
-3
include/linux/pci.h
+3
-3
include/linux/pci.h
···
843
843
void pci_disable_ido(struct pci_dev *dev, unsigned long type);
844
844
845
845
enum pci_obff_signal_type {
846
-
PCI_EXP_OBFF_SIGNAL_L0,
847
-
PCI_EXP_OBFF_SIGNAL_ALWAYS,
846
+
PCI_EXP_OBFF_SIGNAL_L0 = 0,
847
+
PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
848
848
};
849
849
int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
850
850
void pci_disable_obff(struct pci_dev *dev);
···
879
879
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
880
880
int pci_enable_resources(struct pci_dev *, int mask);
881
881
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
882
-
int (*)(struct pci_dev *, u8, u8));
882
+
int (*)(const struct pci_dev *, u8, u8));
883
883
#define HAVE_PCI_REQ_REGIONS 2
884
884
int __must_check pci_request_regions(struct pci_dev *, const char *);
885
885
int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);