[SCSI] qla2xxx: Use PCI-X/PCI-Express read control interfaces.

Original from Peter Oruba <peter.oruba@amd.com>. Additional
cleanups included.

Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>

authored by Andrew Vasquez and committed by James Bottomley f85ec187 fd34f556

+4 -21
+4 -21
drivers/scsi/qla2xxx/qla_init.c
··· 255 255 uint32_t d; 256 256 unsigned long flags = 0; 257 257 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 258 - int pcix_cmd_reg, pcie_dctl_reg; 259 258 260 259 pci_set_master(ha->pdev); 261 260 ret = pci_set_mwi(ha->pdev); ··· 267 268 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 268 269 269 270 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 270 - pcix_cmd_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX); 271 - if (pcix_cmd_reg) { 272 - uint16_t pcix_cmd; 273 - 274 - pcix_cmd_reg += PCI_X_CMD; 275 - pci_read_config_word(ha->pdev, pcix_cmd_reg, &pcix_cmd); 276 - pcix_cmd &= ~PCI_X_CMD_MAX_READ; 277 - pcix_cmd |= 0x0008; 278 - pci_write_config_word(ha->pdev, pcix_cmd_reg, pcix_cmd); 279 - } 271 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 272 + pcix_set_mmrbc(ha->pdev, 2048); 280 273 281 274 /* PCIe -- adjust Maximum Read Request Size (2048). */ 282 - pcie_dctl_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 283 - if (pcie_dctl_reg) { 284 - uint16_t pcie_dctl; 285 - 286 - pcie_dctl_reg += PCI_EXP_DEVCTL; 287 - pci_read_config_word(ha->pdev, pcie_dctl_reg, &pcie_dctl); 288 - pcie_dctl &= ~PCI_EXP_DEVCTL_READRQ; 289 - pcie_dctl |= 0x4000; 290 - pci_write_config_word(ha->pdev, pcie_dctl_reg, pcie_dctl); 291 - } 275 + if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP)) 276 + pcie_set_readrq(ha->pdev, 2048); 292 277 293 278 /* Reset expansion ROM address decode enable */ 294 279 pci_read_config_dword(ha->pdev, PCI_ROM_ADDRESS, &d);