Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

bfin: reorg clock init steps for bf609

So that user can set the clocks through menuconfig.

Signed-off-by: Bob Liu <lliubbo@gmail.com>

Bob Liu f82f16d2 e70f4660

+224 -133
+5
arch/blackfin/Kconfig
··· 352 352 depends on (BFIN526_EZBRD) 353 353 default y 354 354 355 + config MEM_MT47H64M16 356 + bool 357 + depends on (BFIN609_EZKIT) 358 + default y 359 + 355 360 source "arch/blackfin/mach-bf518/Kconfig" 356 361 source "arch/blackfin/mach-bf527/Kconfig" 357 362 source "arch/blackfin/mach-bf533/Kconfig"
+212
arch/blackfin/include/asm/mem_init.h
··· 6 6 * Licensed under the GPL-2 or later. 7 7 */ 8 8 9 + #ifndef __MEM_INIT_H__ 10 + #define __MEM_INIT_H__ 11 + 9 12 #if defined(EBIU_SDGCTL) 10 13 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \ 11 14 defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \ ··· 280 277 #else 281 278 #define PLL_BYPASS 0 282 279 #endif 280 + 281 + #ifdef CONFIG_BF60x 282 + 283 + /* DMC status bits */ 284 + #define IDLE 0x1 285 + #define MEMINITDONE 0x4 286 + #define SRACK 0x8 287 + #define PDACK 0x10 288 + #define DPDACK 0x20 289 + #define DLLCALDONE 0x2000 290 + #define PENDREF 0xF0000 291 + #define PHYRDPHASE 0xF00000 292 + #define PHYRDPHASE_OFFSET 20 293 + 294 + /* DMC control bits */ 295 + #define LPDDR 0x2 296 + #define INIT 0x4 297 + #define SRREQ 0x8 298 + #define PDREQ 0x10 299 + #define DPDREQ 0x20 300 + #define PREC 0x40 301 + #define ADDRMODE 0x100 302 + #define RDTOWR 0xE00 303 + #define PPREF 0x1000 304 + #define DLLCAL 0x2000 305 + 306 + /* DMC DLL control bits */ 307 + #define DLLCALRDCNT 0xFF 308 + #define DATACYC 0xF00 309 + #define DATACYC_OFFSET 8 310 + 311 + /* CGU Divisor bits */ 312 + #define CSEL_OFFSET 0 313 + #define S0SEL_OFFSET 5 314 + #define SYSSEL_OFFSET 8 315 + #define S1SEL_OFFSET 13 316 + #define DSEL_OFFSET 16 317 + #define OSEL_OFFSET 22 318 + #define ALGN 0x20000000 319 + #define UPDT 0x40000000 320 + #define LOCK 0x80000000 321 + 322 + /* CGU Status bits */ 323 + #define PLLEN 0x1 324 + #define PLLBP 0x2 325 + #define PLOCK 0x4 326 + #define CLKSALGN 0x8 327 + 328 + /* CGU Control bits */ 329 + #define MSEL_MASK 0x7F00 330 + #define DF_MASK 0x1 331 + 332 + struct ddr_config { 333 + u32 ddr_clk; 334 + u32 dmc_ddrctl; 335 + u32 dmc_ddrcfg; 336 + u32 dmc_ddrtr0; 337 + u32 dmc_ddrtr1; 338 + u32 dmc_ddrtr2; 339 + u32 dmc_ddrmr; 340 + u32 dmc_ddrmr1; 341 + }; 342 + 343 + #if defined(CONFIG_MEM_MT47H64M16) 344 + static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { 345 + [0] = { 346 + .ddr_clk = 125, 347 + .dmc_ddrctl = 0x00000904, 348 + .dmc_ddrcfg = 0x00000422, 349 + .dmc_ddrtr0 = 0x20705212, 350 + .dmc_ddrtr1 = 0x201003CF, 351 + .dmc_ddrtr2 = 0x00320107, 352 + .dmc_ddrmr = 0x00000422, 353 + .dmc_ddrmr1 = 0x4, 354 + }, 355 + [1] = { 356 + .ddr_clk = 133, 357 + .dmc_ddrctl = 0x00000904, 358 + .dmc_ddrcfg = 0x00000422, 359 + .dmc_ddrtr0 = 0x20806313, 360 + .dmc_ddrtr1 = 0x2013040D, 361 + .dmc_ddrtr2 = 0x00320108, 362 + .dmc_ddrmr = 0x00000632, 363 + .dmc_ddrmr1 = 0x4, 364 + }, 365 + [2] = { 366 + .ddr_clk = 150, 367 + .dmc_ddrctl = 0x00000904, 368 + .dmc_ddrcfg = 0x00000422, 369 + .dmc_ddrtr0 = 0x20A07323, 370 + .dmc_ddrtr1 = 0x20160492, 371 + .dmc_ddrtr2 = 0x00320209, 372 + .dmc_ddrmr = 0x00000632, 373 + .dmc_ddrmr1 = 0x4, 374 + }, 375 + [3] = { 376 + .ddr_clk = 166, 377 + .dmc_ddrctl = 0x00000904, 378 + .dmc_ddrcfg = 0x00000422, 379 + .dmc_ddrtr0 = 0x20A07323, 380 + .dmc_ddrtr1 = 0x2016050E, 381 + .dmc_ddrtr2 = 0x00320209, 382 + .dmc_ddrmr = 0x00000632, 383 + .dmc_ddrmr1 = 0x4, 384 + }, 385 + [4] = { 386 + .ddr_clk = 200, 387 + .dmc_ddrctl = 0x00000904, 388 + .dmc_ddrcfg = 0x00000422, 389 + .dmc_ddrtr0 = 0x20a07323, 390 + .dmc_ddrtr1 = 0x2016050f, 391 + .dmc_ddrtr2 = 0x00320509, 392 + .dmc_ddrmr = 0x00000632, 393 + .dmc_ddrmr1 = 0x4, 394 + }, 395 + [5] = { 396 + .ddr_clk = 225, 397 + .dmc_ddrctl = 0x00000904, 398 + .dmc_ddrcfg = 0x00000422, 399 + .dmc_ddrtr0 = 0x20E0A424, 400 + .dmc_ddrtr1 = 0x302006DB, 401 + .dmc_ddrtr2 = 0x0032020D, 402 + .dmc_ddrmr = 0x00000842, 403 + .dmc_ddrmr1 = 0x4, 404 + }, 405 + [6] = { 406 + .ddr_clk = 250, 407 + .dmc_ddrctl = 0x00000904, 408 + .dmc_ddrcfg = 0x00000422, 409 + .dmc_ddrtr0 = 0x20E0A424, 410 + .dmc_ddrtr1 = 0x3020079E, 411 + .dmc_ddrtr2 = 0x0032020D, 412 + .dmc_ddrmr = 0x00000842, 413 + .dmc_ddrmr1 = 0x4, 414 + }, 415 + }; 416 + #endif 417 + 418 + static inline void dmc_enter_self_refresh(void) 419 + { 420 + if (bfin_read_DMC0_STAT() & MEMINITDONE) { 421 + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ); 422 + while (!(bfin_read_DMC0_STAT() & SRACK)) 423 + continue; 424 + } 425 + } 426 + 427 + static inline void dmc_exit_self_refresh(void) 428 + { 429 + if (bfin_read_DMC0_STAT() & MEMINITDONE) { 430 + bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ); 431 + while (bfin_read_DMC0_STAT() & SRACK) 432 + continue; 433 + } 434 + } 435 + 436 + static inline void init_cgu(u32 cgu_div, u32 cgu_ctl) 437 + { 438 + dmc_enter_self_refresh(); 439 + 440 + /* Don't set the same value of MSEL and DF to CGU_CTL */ 441 + if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK)) 442 + != cgu_ctl) { 443 + bfin_write32(CGU0_DIV, cgu_div); 444 + bfin_write32(CGU0_CTL, cgu_ctl); 445 + while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) || 446 + !(bfin_read32(CGU0_STAT) & PLOCK)) 447 + continue; 448 + } 449 + 450 + bfin_write32(CGU0_DIV, cgu_div | UPDT); 451 + while (bfin_read32(CGU0_STAT) & CLKSALGN) 452 + continue; 453 + 454 + dmc_exit_self_refresh(); 455 + } 456 + 457 + static inline void init_dmc(u32 dmc_clk) 458 + { 459 + int i, dlldatacycle, dll_ctl; 460 + 461 + for (i = 0; i < 7; i++) { 462 + if (ddr_config_table[i].ddr_clk == dmc_clk) { 463 + bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg); 464 + bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0); 465 + bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1); 466 + bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); 467 + bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); 468 + bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); 469 + bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); 470 + break; 471 + } 472 + } 473 + 474 + while (!(bfin_read_DMC0_STAT() & MEMINITDONE)) 475 + continue; 476 + 477 + dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET; 478 + dll_ctl = bfin_read_DMC0_DLLCTL(); 479 + dll_ctl &= ~DATACYC; 480 + bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET)); 481 + 482 + while (!(bfin_read_DMC0_STAT() & DLLCALDONE)) 483 + continue; 484 + } 485 + #endif 486 + 487 + #endif /*__MEM_INIT_H__*/ 488 +
-1
arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
··· 2665 2665 #define DEVSZ_1G 0x400 /* DMC External Bank Size = 1Gbit */ 2666 2666 #define DEVSZ_2G 0x500 /* DMC External Bank Size = 2Gbit */ 2667 2667 2668 - 2669 2668 /* ========================= 2670 2669 L2CTL Registers 2671 2670 ========================= */
+7 -132
arch/blackfin/mach-common/clocks-init.c
··· 16 16 #include <asm/dpmc.h> 17 17 18 18 #ifdef CONFIG_BF60x 19 - #define CSEL_P 0 20 - #define S0SEL_P 5 21 - #define SYSSEL_P 8 22 - #define S1SEL_P 13 23 - #define DSEL_P 16 24 - #define OSEL_P 22 25 - #define ALGN_P 29 26 - #define UPDT_P 30 27 - #define LOCK_P 31 28 19 29 20 #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF) 30 21 #define CGU_DIV_VAL \ 31 - ((CONFIG_CCLK_DIV << CSEL_P) | \ 32 - (CONFIG_SCLK_DIV << SYSSEL_P) | \ 33 - (CONFIG_SCLK0_DIV << S0SEL_P) | \ 34 - (CONFIG_SCLK1_DIV << S1SEL_P) | \ 35 - (CONFIG_DCLK_DIV << DSEL_P)) 22 + ((CONFIG_CCLK_DIV << CSEL_OFFSET) | \ 23 + (CONFIG_SCLK_DIV << SYSSEL_OFFSET) | \ 24 + (CONFIG_SCLK0_DIV << S0SEL_OFFSET) | \ 25 + (CONFIG_SCLK1_DIV << S1SEL_OFFSET) | \ 26 + (CONFIG_DCLK_DIV << DSEL_OFFSET)) 36 27 37 28 #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000) 38 29 #if ((CONFIG_BFIN_DCLK != 125) && \ ··· 32 41 (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250)) 33 42 #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz" 34 43 #endif 35 - struct ddr_config { 36 - u32 ddr_clk; 37 - u32 dmc_ddrctl; 38 - u32 dmc_ddrcfg; 39 - u32 dmc_ddrtr0; 40 - u32 dmc_ddrtr1; 41 - u32 dmc_ddrtr2; 42 - u32 dmc_ddrmr; 43 - u32 dmc_ddrmr1; 44 - }; 45 44 46 - struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = { 47 - [0] = { 48 - .ddr_clk = 125, 49 - .dmc_ddrctl = 0x00000904, 50 - .dmc_ddrcfg = 0x00000422, 51 - .dmc_ddrtr0 = 0x20705212, 52 - .dmc_ddrtr1 = 0x201003CF, 53 - .dmc_ddrtr2 = 0x00320107, 54 - .dmc_ddrmr = 0x00000422, 55 - .dmc_ddrmr1 = 0x4, 56 - }, 57 - [1] = { 58 - .ddr_clk = 133, 59 - .dmc_ddrctl = 0x00000904, 60 - .dmc_ddrcfg = 0x00000422, 61 - .dmc_ddrtr0 = 0x20806313, 62 - .dmc_ddrtr1 = 0x2013040D, 63 - .dmc_ddrtr2 = 0x00320108, 64 - .dmc_ddrmr = 0x00000632, 65 - .dmc_ddrmr1 = 0x4, 66 - }, 67 - [2] = { 68 - .ddr_clk = 150, 69 - .dmc_ddrctl = 0x00000904, 70 - .dmc_ddrcfg = 0x00000422, 71 - .dmc_ddrtr0 = 0x20A07323, 72 - .dmc_ddrtr1 = 0x20160492, 73 - .dmc_ddrtr2 = 0x00320209, 74 - .dmc_ddrmr = 0x00000632, 75 - .dmc_ddrmr1 = 0x4, 76 - }, 77 - [3] = { 78 - .ddr_clk = 166, 79 - .dmc_ddrctl = 0x00000904, 80 - .dmc_ddrcfg = 0x00000422, 81 - .dmc_ddrtr0 = 0x20A07323, 82 - .dmc_ddrtr1 = 0x2016050E, 83 - .dmc_ddrtr2 = 0x00320209, 84 - .dmc_ddrmr = 0x00000632, 85 - .dmc_ddrmr1 = 0x4, 86 - }, 87 - [4] = { 88 - .ddr_clk = 200, 89 - .dmc_ddrctl = 0x00000904, 90 - .dmc_ddrcfg = 0x00000422, 91 - .dmc_ddrtr0 = 0x20a07323, 92 - .dmc_ddrtr1 = 0x2016050f, 93 - .dmc_ddrtr2 = 0x00320509, 94 - .dmc_ddrmr = 0x00000632, 95 - .dmc_ddrmr1 = 0x4, 96 - }, 97 - [5] = { 98 - .ddr_clk = 225, 99 - .dmc_ddrctl = 0x00000904, 100 - .dmc_ddrcfg = 0x00000422, 101 - .dmc_ddrtr0 = 0x20E0A424, 102 - .dmc_ddrtr1 = 0x302006DB, 103 - .dmc_ddrtr2 = 0x0032020D, 104 - .dmc_ddrmr = 0x00000842, 105 - .dmc_ddrmr1 = 0x4, 106 - }, 107 - [6] = { 108 - .ddr_clk = 250, 109 - .dmc_ddrctl = 0x00000904, 110 - .dmc_ddrcfg = 0x00000422, 111 - .dmc_ddrtr0 = 0x20E0A424, 112 - .dmc_ddrtr1 = 0x3020079E, 113 - .dmc_ddrtr2 = 0x0032020D, 114 - .dmc_ddrmr = 0x00000842, 115 - .dmc_ddrmr1 = 0x4, 116 - }, 117 - }; 118 45 #else 119 46 #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 120 47 #define PLL_CTL_VAL \ ··· 53 144 * in the middle of reprogramming things, and that'll screw us up. 54 145 * For example, any automatic DMAs left by U-Boot for splash screens. 55 146 */ 56 - 57 147 #ifdef CONFIG_BF60x 58 - int i, dlldatacycle, dll_ctl; 59 - bfin_write32(CGU0_DIV, CGU_DIV_VAL); 60 - bfin_write32(CGU0_CTL, CGU_CTL_VAL); 61 - while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4)) 62 - continue; 63 - 64 - bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P)); 65 - while (bfin_read32(CGU0_STAT) & (1 << 3)) 66 - continue; 67 - 68 - for (i = 0; i < 7; i++) { 69 - if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) { 70 - bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg); 71 - bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0); 72 - bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1); 73 - bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2); 74 - bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr); 75 - bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1); 76 - bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl); 77 - break; 78 - } 79 - } 80 - 81 - do_sync(); 82 - while (!(bfin_read_DDR0_STAT() & 0x4)) 83 - continue; 84 - 85 - dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20; 86 - dll_ctl = bfin_read_DDR0_DLLCTL(); 87 - dll_ctl &= 0x0ff; 88 - bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8)); 89 - 90 - do_sync(); 91 - while (!(bfin_read_DDR0_STAT() & 0x2000)) 92 - continue; 148 + init_cgu(CGU_DIV_VAL, CGU_CTL_VAL); 149 + init_dmc(CONFIG_BFIN_DCLK); 93 150 #else 94 151 size_t i; 95 152 for (i = 0; i < MAX_DMA_CHANNELS; ++i) {