Merge branch 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

+5

arch/arm/mach-exynos/clock.c

··· 472 472 .enable = exynos4_clk_ip_cam_ctrl, 473 473 .ctrlbit = (1 << 5), 474 474 }, { 475 + .name = "jpeg", 476 + .id = 0, 477 + .enable = exynos4_clk_ip_cam_ctrl, 478 + .ctrlbit = (1 << 6), 479 + }, { 475 480 .name = "fimc", 476 481 .devname = "exynos4-fimc.0", 477 482 .enable = exynos4_clk_ip_cam_ctrl,

+47 -13

arch/arm/mach-exynos/common.c

··· 26 26 #include <asm/hardware/gic.h> 27 27 #include <asm/mach/map.h> 28 28 #include <asm/mach/irq.h> 29 + #include <asm/cacheflush.h> 29 30 30 31 #include <mach/regs-irq.h> 31 32 #include <mach/regs-pmu.h> 32 33 #include <mach/regs-gpio.h> 34 + #include <mach/pmu.h> 33 35 34 36 #include <plat/cpu.h> 35 37 #include <plat/clock.h> ··· 47 45 #include <plat/regs-serial.h> 48 46 49 47 #include "common.h" 48 + #define L2_AUX_VAL 0x7C470001 49 + #define L2_AUX_MASK 0xC200ffff 50 50 51 51 static const char name_exynos4210[] = "EXYNOS4210"; 52 52 static const char name_exynos4212[] = "EXYNOS4212"; ··· 177 173 }, { 178 174 .virtual = (unsigned long)S5P_VA_DMC0, 179 175 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), 180 - .length = SZ_4K, 176 + .length = SZ_64K, 177 + .type = MT_DEVICE, 178 + }, { 179 + .virtual = (unsigned long)S5P_VA_DMC1, 180 + .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1), 181 + .length = SZ_64K, 181 182 .type = MT_DEVICE, 182 183 }, { 183 184 .virtual = (unsigned long)S3C_VA_USB_HSPHY, ··· 442 433 #ifdef CONFIG_CACHE_L2X0 443 434 static int __init exynos4_l2x0_cache_init(void) 444 435 { 445 - /* TAG, Data Latency Control: 2cycle */ 446 - __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 436 + int ret; 437 + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); 438 + if (!ret) { 439 + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); 440 + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); 441 + return 0; 442 + } 447 443 448 - if (soc_is_exynos4210()) 449 - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 450 - else if (soc_is_exynos4212() || soc_is_exynos4412()) 451 - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 444 + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) { 445 + l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC; 446 + /* TAG, Data Latency Control: 2 cycles */ 447 + l2x0_saved_regs.tag_latency = 0x110; 452 448 453 - /* L2X0 Prefetch Control */ 454 - __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); 449 + if (soc_is_exynos4212() || soc_is_exynos4412()) 450 + l2x0_saved_regs.data_latency = 0x120; 451 + else 452 + l2x0_saved_regs.data_latency = 0x110; 455 453 456 - /* L2X0 Power Control */ 457 - __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, 458 - S5P_VA_L2CC + L2X0_POWER_CTRL); 454 + l2x0_saved_regs.prefetch_ctrl = 0x30000007; 455 + l2x0_saved_regs.pwr_ctrl = 456 + (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN); 459 457 460 - l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff); 458 + l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); 461 459 460 + __raw_writel(l2x0_saved_regs.tag_latency, 461 + S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 462 + __raw_writel(l2x0_saved_regs.data_latency, 463 + S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); 464 + 465 + /* L2X0 Prefetch Control */ 466 + __raw_writel(l2x0_saved_regs.prefetch_ctrl, 467 + S5P_VA_L2CC + L2X0_PREFETCH_CTRL); 468 + 469 + /* L2X0 Power Control */ 470 + __raw_writel(l2x0_saved_regs.pwr_ctrl, 471 + S5P_VA_L2CC + L2X0_POWER_CTRL); 472 + 473 + clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long)); 474 + clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs)); 475 + } 476 + 477 + l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK); 462 478 return 0; 463 479 } 464 480

+147 -4

arch/arm/mach-exynos/cpuidle.c

··· 11 11 #include <linux/kernel.h> 12 12 #include <linux/init.h> 13 13 #include <linux/cpuidle.h> 14 + #include <linux/cpu_pm.h> 14 15 #include <linux/io.h> 15 16 #include <linux/export.h> 16 17 #include <linux/time.h> 17 18 18 19 #include <asm/proc-fns.h> 20 + #include <asm/smp_scu.h> 21 + #include <asm/suspend.h> 22 + #include <asm/unified.h> 23 + #include <mach/regs-pmu.h> 24 + #include <mach/pmu.h> 25 + 26 + #include <plat/cpu.h> 27 + 28 + #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 29 + S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 30 + (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) 31 + #define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ 32 + S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ 33 + (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) 34 + 35 + #define S5P_CHECK_AFTR 0xFCBA0D10 19 36 20 37 static int exynos4_enter_idle(struct cpuidle_device *dev, 21 38 struct cpuidle_driver *drv, 22 39 int index); 40 + static int exynos4_enter_lowpower(struct cpuidle_device *dev, 41 + struct cpuidle_driver *drv, 42 + int index); 23 43 24 - static struct cpuidle_state exynos4_cpuidle_set[] = { 44 + static struct cpuidle_state exynos4_cpuidle_set[] __initdata = { 25 45 [0] = { 26 46 .enter = exynos4_enter_idle, 27 47 .exit_latency = 1, 28 48 .target_residency = 100000, 29 49 .flags = CPUIDLE_FLAG_TIME_VALID, 30 - .name = "IDLE", 50 + .name = "C0", 31 51 .desc = "ARM clock gating(WFI)", 52 + }, 53 + [1] = { 54 + .enter = exynos4_enter_lowpower, 55 + .exit_latency = 300, 56 + .target_residency = 100000, 57 + .flags = CPUIDLE_FLAG_TIME_VALID, 58 + .name = "C1", 59 + .desc = "ARM power down", 32 60 }, 33 61 }; 34 62 ··· 67 39 .owner = THIS_MODULE, 68 40 }; 69 41 42 + /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ 43 + static void exynos4_set_wakeupmask(void) 44 + { 45 + __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK); 46 + } 47 + 48 + static unsigned int g_pwr_ctrl, g_diag_reg; 49 + 50 + static void save_cpu_arch_register(void) 51 + { 52 + /*read power control register*/ 53 + asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc"); 54 + /*read diagnostic register*/ 55 + asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc"); 56 + return; 57 + } 58 + 59 + static void restore_cpu_arch_register(void) 60 + { 61 + /*write power control register*/ 62 + asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc"); 63 + /*write diagnostic register*/ 64 + asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc"); 65 + return; 66 + } 67 + 68 + static int idle_finisher(unsigned long flags) 69 + { 70 + cpu_do_idle(); 71 + return 1; 72 + } 73 + 74 + static int exynos4_enter_core0_aftr(struct cpuidle_device *dev, 75 + struct cpuidle_driver *drv, 76 + int index) 77 + { 78 + struct timeval before, after; 79 + int idle_time; 80 + unsigned long tmp; 81 + 82 + local_irq_disable(); 83 + do_gettimeofday(&before); 84 + 85 + exynos4_set_wakeupmask(); 86 + 87 + /* Set value of power down register for aftr mode */ 88 + exynos4_sys_powerdown_conf(SYS_AFTR); 89 + 90 + __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR); 91 + __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG); 92 + 93 + save_cpu_arch_register(); 94 + 95 + /* Setting Central Sequence Register for power down mode */ 96 + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 97 + tmp &= ~S5P_CENTRAL_LOWPWR_CFG; 98 + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 99 + 100 + cpu_pm_enter(); 101 + cpu_suspend(0, idle_finisher); 102 + 103 + #ifdef CONFIG_SMP 104 + scu_enable(S5P_VA_SCU); 105 + #endif 106 + cpu_pm_exit(); 107 + 108 + restore_cpu_arch_register(); 109 + 110 + /* 111 + * If PMU failed while entering sleep mode, WFI will be 112 + * ignored by PMU and then exiting cpu_do_idle(). 113 + * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically 114 + * in this situation. 115 + */ 116 + tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION); 117 + if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) { 118 + tmp |= S5P_CENTRAL_LOWPWR_CFG; 119 + __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); 120 + } 121 + 122 + /* Clear wakeup state register */ 123 + __raw_writel(0x0, S5P_WAKEUP_STAT); 124 + 125 + do_gettimeofday(&after); 126 + 127 + local_irq_enable(); 128 + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + 129 + (after.tv_usec - before.tv_usec); 130 + 131 + dev->last_residency = idle_time; 132 + return index; 133 + } 134 + 70 135 static int exynos4_enter_idle(struct cpuidle_device *dev, 71 136 struct cpuidle_driver *drv, 72 - int index) 137 + int index) 73 138 { 74 139 struct timeval before, after; 75 140 int idle_time; ··· 181 60 return index; 182 61 } 183 62 63 + static int exynos4_enter_lowpower(struct cpuidle_device *dev, 64 + struct cpuidle_driver *drv, 65 + int index) 66 + { 67 + int new_index = index; 68 + 69 + /* This mode only can be entered when other core's are offline */ 70 + if (num_online_cpus() > 1) 71 + new_index = drv->safe_state_index; 72 + 73 + if (new_index == 0) 74 + return exynos4_enter_idle(dev, drv, new_index); 75 + else 76 + return exynos4_enter_core0_aftr(dev, drv, new_index); 77 + } 78 + 184 79 static int __init exynos4_init_cpuidle(void) 185 80 { 186 81 int i, max_cpuidle_state, cpu_id; ··· 211 74 memcpy(&drv->states[i], &exynos4_cpuidle_set[i], 212 75 sizeof(struct cpuidle_state)); 213 76 } 77 + drv->safe_state_index = 0; 214 78 cpuidle_register_driver(&exynos4_idle_driver); 215 79 216 80 for_each_cpu(cpu_id, cpu_online_mask) { 217 81 device = &per_cpu(exynos4_cpuidle_device, cpu_id); 218 82 device->cpu = cpu_id; 219 83 220 - device->state_count = drv->state_count; 84 + if (cpu_id == 0) 85 + device->state_count = (sizeof(exynos4_cpuidle_set) / 86 + sizeof(struct cpuidle_state)); 87 + else 88 + device->state_count = 1; /* Support IDLE only */ 221 89 222 90 if (cpuidle_register_device(device)) { 223 91 printk(KERN_ERR "CPUidle register device failed\n,"); 224 92 return -EIO; 225 93 } 226 94 } 95 + 227 96 return 0; 228 97 } 229 98 device_initcall(exynos4_init_cpuidle);

+7

arch/arm/mach-exynos/include/mach/map.h

··· 31 31 #define EXYNOS4_PA_FIMC2 0x11820000 32 32 #define EXYNOS4_PA_FIMC3 0x11830000 33 33 34 + #define EXYNOS4_PA_JPEG 0x11840000 35 + 36 + #define EXYNOS4_PA_G2D 0x12800000 37 + 34 38 #define EXYNOS4_PA_I2S0 0x03830000 35 39 #define EXYNOS4_PA_I2S1 0xE3100000 36 40 #define EXYNOS4_PA_I2S2 0xE2A00000 ··· 61 57 #define EXYNOS4_PA_KEYPAD 0x100A0000 62 58 63 59 #define EXYNOS4_PA_DMC0 0x10400000 60 + #define EXYNOS4_PA_DMC1 0x10410000 64 61 65 62 #define EXYNOS4_PA_COMBINER 0x10440000 66 63 ··· 167 162 #define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1 168 163 #define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2 169 164 #define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 165 + #define S5P_PA_JPEG EXYNOS4_PA_JPEG 166 + #define S5P_PA_G2D EXYNOS4_PA_G2D 170 167 #define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0 171 168 #define S5P_PA_HDMI EXYNOS4_PA_HDMI 172 169 #define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY

+2

arch/arm/mach-exynos/include/mach/pmu.h

··· 22 22 NUM_SYS_POWERDOWN, 23 23 }; 24 24 25 + extern unsigned long l2x0_regs_phys; 25 26 struct exynos4_pmu_conf { 26 27 void __iomem *reg; 27 28 unsigned int val[NUM_SYS_POWERDOWN]; 28 29 }; 29 30 30 31 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); 32 + extern void s3c_cpu_resume(void); 31 33 32 34 #endif /* __ASM_ARCH_PMU_H */

+13 -8

arch/arm/mach-exynos/mct.c

··· 29 29 #include <mach/regs-mct.h> 30 30 #include <asm/mach/time.h> 31 31 32 + #define TICK_BASE_CNT 1 33 + 32 34 enum { 33 35 MCT_INT_SPI, 34 36 MCT_INT_PPI 35 37 }; 36 38 37 - static unsigned long clk_cnt_per_tick; 38 39 static unsigned long clk_rate; 39 40 static unsigned int mct_int_type; 40 41 ··· 206 205 static void exynos4_comp_set_mode(enum clock_event_mode mode, 207 206 struct clock_event_device *evt) 208 207 { 208 + unsigned long cycles_per_jiffy; 209 209 exynos4_mct_comp0_stop(); 210 210 211 211 switch (mode) { 212 212 case CLOCK_EVT_MODE_PERIODIC: 213 - exynos4_mct_comp0_start(mode, clk_cnt_per_tick); 213 + cycles_per_jiffy = 214 + (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); 215 + exynos4_mct_comp0_start(mode, cycles_per_jiffy); 214 216 break; 215 217 216 218 case CLOCK_EVT_MODE_ONESHOT: ··· 252 248 253 249 static void exynos4_clockevent_init(void) 254 250 { 255 - clk_cnt_per_tick = clk_rate / 2 / HZ; 256 - 257 - clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5); 251 + clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5); 258 252 mct_comp_device.max_delta_ns = 259 253 clockevent_delta2ns(0xffffffff, &mct_comp_device); 260 254 mct_comp_device.min_delta_ns = ··· 316 314 struct clock_event_device *evt) 317 315 { 318 316 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); 317 + unsigned long cycles_per_jiffy; 319 318 320 319 exynos4_mct_tick_stop(mevt); 321 320 322 321 switch (mode) { 323 322 case CLOCK_EVT_MODE_PERIODIC: 324 - exynos4_mct_tick_start(clk_cnt_per_tick, mevt); 323 + cycles_per_jiffy = 324 + (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); 325 + exynos4_mct_tick_start(cycles_per_jiffy, mevt); 325 326 break; 326 327 327 328 case CLOCK_EVT_MODE_ONESHOT: ··· 398 393 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 399 394 evt->rating = 450; 400 395 401 - clockevents_calc_mult_shift(evt, clk_rate / 2, 5); 396 + clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5); 402 397 evt->max_delta_ns = 403 398 clockevent_delta2ns(0x7fffffff, evt); 404 399 evt->min_delta_ns = ··· 406 401 407 402 clockevents_register_device(evt); 408 403 409 - exynos4_mct_write(0x1, mevt->base + MCT_L_TCNTB_OFFSET); 404 + exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 410 405 411 406 if (mct_int_type == MCT_INT_SPI) { 412 407 if (cpu == 0) {

-15

arch/arm/mach-exynos/pm.c

··· 155 155 SAVE_ITEM(S5P_SROM_BC3), 156 156 }; 157 157 158 - static struct sleep_save exynos4_l2cc_save[] = { 159 - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), 160 - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), 161 - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), 162 - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), 163 - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), 164 - }; 165 158 166 159 /* For Cortex-A9 Diagnostic and Power control register */ 167 160 static unsigned int save_arm_register[2]; ··· 175 182 u32 tmp; 176 183 177 184 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); 178 - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 179 185 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); 180 186 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); 181 187 ··· 378 386 379 387 #ifdef CONFIG_SMP 380 388 scu_enable(S5P_VA_SCU); 381 - #endif 382 - 383 - #ifdef CONFIG_CACHE_L2X0 384 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); 385 - outer_inv_all(); 386 - /* enable L2X0*/ 387 - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); 388 389 #endif 389 390 390 391 early_wakeup:

+8

arch/arm/mach-s3c64xx/Kconfig

··· 83 83 help 84 84 Common setup code for SPI GPIO configurations 85 85 86 + config S3C64XX_SETUP_USB_PHY 87 + bool 88 + help 89 + Common setup code for USB PHY controller 90 + 86 91 # S36400 Macchine support 87 92 88 93 config MACH_SMDK6400 ··· 162 157 select S3C64XX_SETUP_IDE 163 158 select S3C64XX_SETUP_FB_24BPP 164 159 select S3C64XX_SETUP_KEYPAD 160 + select S3C64XX_SETUP_USB_PHY 165 161 help 166 162 Machine support for the Samsung SMDK6410 167 163 ··· 262 256 select S3C_DEV_USB_HOST 263 257 select S3C64XX_SETUP_SDHCI 264 258 select S3C64XX_SETUP_FB_24BPP 259 + select S3C64XX_SETUP_USB_PHY 265 260 select SAMSUNG_DEV_ADC 266 261 select SAMSUNG_DEV_PWM 267 262 select SAMSUNG_DEV_TS ··· 290 283 select S3C64XX_SETUP_FB_24BPP 291 284 select S3C64XX_SETUP_KEYPAD 292 285 select S3C64XX_SETUP_SPI 286 + select S3C64XX_SETUP_USB_PHY 293 287 select SAMSUNG_DEV_ADC 294 288 select SAMSUNG_DEV_KEYPAD 295 289 select S3C_DEV_USB_HOST

+2

arch/arm/mach-s3c64xx/Makefile

··· 22 22 # PM 23 23 24 24 obj-$(CONFIG_PM) += pm.o irq-pm.o sleep.o 25 + obj-$(CONFIG_CPU_IDLE) += cpuidle.o 25 26 26 27 # DMA support 27 28 ··· 43 42 obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o 44 43 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 45 44 obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o 45 + obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o 46 46 47 47 # Machine support 48 48

+111 -10

arch/arm/mach-s3c64xx/clock.c

··· 207 207 .enable = s3c64xx_sclk_ctrl, 208 208 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, 209 209 }, { 210 + .name = "ac97", 211 + .parent = &clk_p, 212 + .ctrlbit = S3C_CLKCON_PCLK_AC97, 213 + }, { 214 + .name = "cfcon", 215 + .parent = &clk_h, 216 + .enable = s3c64xx_hclk_ctrl, 217 + .ctrlbit = S3C_CLKCON_HCLK_IHOST, 218 + }, { 210 219 .name = "dma0", 211 220 .parent = &clk_h, 212 221 .enable = s3c64xx_hclk_ctrl, ··· 225 216 .parent = &clk_h, 226 217 .enable = s3c64xx_hclk_ctrl, 227 218 .ctrlbit = S3C_CLKCON_HCLK_DMA1, 219 + }, { 220 + .name = "3dse", 221 + .parent = &clk_h, 222 + .enable = s3c64xx_hclk_ctrl, 223 + .ctrlbit = S3C_CLKCON_HCLK_3DSE, 224 + }, { 225 + .name = "hclk_secur", 226 + .parent = &clk_h, 227 + .enable = s3c64xx_hclk_ctrl, 228 + .ctrlbit = S3C_CLKCON_HCLK_SECUR, 229 + }, { 230 + .name = "sdma1", 231 + .parent = &clk_h, 232 + .enable = s3c64xx_hclk_ctrl, 233 + .ctrlbit = S3C_CLKCON_HCLK_SDMA1, 234 + }, { 235 + .name = "sdma0", 236 + .parent = &clk_h, 237 + .enable = s3c64xx_hclk_ctrl, 238 + .ctrlbit = S3C_CLKCON_HCLK_SDMA0, 239 + }, { 240 + .name = "hclk_jpeg", 241 + .parent = &clk_h, 242 + .enable = s3c64xx_hclk_ctrl, 243 + .ctrlbit = S3C_CLKCON_HCLK_JPEG, 244 + }, { 245 + .name = "camif", 246 + .parent = &clk_h, 247 + .enable = s3c64xx_hclk_ctrl, 248 + .ctrlbit = S3C_CLKCON_HCLK_CAMIF, 249 + }, { 250 + .name = "hclk_scaler", 251 + .parent = &clk_h, 252 + .enable = s3c64xx_hclk_ctrl, 253 + .ctrlbit = S3C_CLKCON_HCLK_SCALER, 254 + }, { 255 + .name = "2d", 256 + .parent = &clk_h, 257 + .enable = s3c64xx_hclk_ctrl, 258 + .ctrlbit = S3C_CLKCON_HCLK_2D, 259 + }, { 260 + .name = "tv", 261 + .parent = &clk_h, 262 + .enable = s3c64xx_hclk_ctrl, 263 + .ctrlbit = S3C_CLKCON_HCLK_TV, 264 + }, { 265 + .name = "post0", 266 + .parent = &clk_h, 267 + .enable = s3c64xx_hclk_ctrl, 268 + .ctrlbit = S3C_CLKCON_HCLK_POST0, 269 + }, { 270 + .name = "rot", 271 + .parent = &clk_h, 272 + .enable = s3c64xx_hclk_ctrl, 273 + .ctrlbit = S3C_CLKCON_HCLK_ROT, 274 + }, { 275 + .name = "hclk_mfc", 276 + .parent = &clk_h, 277 + .enable = s3c64xx_hclk_ctrl, 278 + .ctrlbit = S3C_CLKCON_HCLK_MFC, 279 + }, { 280 + .name = "pclk_mfc", 281 + .parent = &clk_p, 282 + .enable = s3c64xx_pclk_ctrl, 283 + .ctrlbit = S3C_CLKCON_PCLK_MFC, 284 + }, { 285 + .name = "dac27", 286 + .enable = s3c64xx_sclk_ctrl, 287 + .ctrlbit = S3C_CLKCON_SCLK_DAC27, 288 + }, { 289 + .name = "tv27", 290 + .enable = s3c64xx_sclk_ctrl, 291 + .ctrlbit = S3C_CLKCON_SCLK_TV27, 292 + }, { 293 + .name = "scaler27", 294 + .enable = s3c64xx_sclk_ctrl, 295 + .ctrlbit = S3C_CLKCON_SCLK_SCALER27, 296 + }, { 297 + .name = "sclk_scaler", 298 + .enable = s3c64xx_sclk_ctrl, 299 + .ctrlbit = S3C_CLKCON_SCLK_SCALER, 300 + }, { 301 + .name = "post0_27", 302 + .enable = s3c64xx_sclk_ctrl, 303 + .ctrlbit = S3C_CLKCON_SCLK_POST0_27, 304 + }, { 305 + .name = "secur", 306 + .enable = s3c64xx_sclk_ctrl, 307 + .ctrlbit = S3C_CLKCON_SCLK_SECUR, 308 + }, { 309 + .name = "sclk_mfc", 310 + .enable = s3c64xx_sclk_ctrl, 311 + .ctrlbit = S3C_CLKCON_SCLK_MFC, 312 + }, { 313 + .name = "cam", 314 + .enable = s3c64xx_sclk_ctrl, 315 + .ctrlbit = S3C_CLKCON_SCLK_CAM, 316 + }, { 317 + .name = "sclk_jpeg", 318 + .enable = s3c64xx_sclk_ctrl, 319 + .ctrlbit = S3C_CLKCON_SCLK_JPEG, 228 320 }, 229 321 }; 230 322 ··· 399 289 .name = "watchdog", 400 290 .parent = &clk_p, 401 291 .ctrlbit = S3C_CLKCON_PCLK_WDT, 402 - }, { 403 - .name = "ac97", 404 - .parent = &clk_p, 405 - .ctrlbit = S3C_CLKCON_PCLK_AC97, 406 - }, { 407 - .name = "cfcon", 408 - .parent = &clk_h, 409 - .enable = s3c64xx_hclk_ctrl, 410 - .ctrlbit = S3C_CLKCON_HCLK_IHOST, 411 - } 292 + }, 412 293 }; 413 294 414 295 static struct clk clk_hsmmc0 = {

+91

arch/arm/mach-s3c64xx/cpuidle.c

··· 1 + /* linux/arch/arm/mach-s3c64xx/cpuidle.c 2 + * 3 + * Copyright (c) 2011 Wolfson Microelectronics, plc 4 + * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 + * http://www.samsung.com 6 + * 7 + * This program is free software; you can redistribute it and/or modify 8 + * it under the terms of the GNU General Public License version 2 as 9 + * published by the Free Software Foundation. 10 + */ 11 + 12 + #include <linux/kernel.h> 13 + #include <linux/init.h> 14 + #include <linux/cpuidle.h> 15 + #include <linux/io.h> 16 + #include <linux/export.h> 17 + #include <linux/time.h> 18 + 19 + #include <asm/proc-fns.h> 20 + 21 + #include <mach/map.h> 22 + 23 + #include <mach/regs-sys.h> 24 + #include <mach/regs-syscon-power.h> 25 + 26 + static int s3c64xx_enter_idle(struct cpuidle_device *dev, 27 + struct cpuidle_driver *drv, 28 + int index) 29 + { 30 + struct timeval before, after; 31 + unsigned long tmp; 32 + int idle_time; 33 + 34 + local_irq_disable(); 35 + do_gettimeofday(&before); 36 + 37 + /* Setup PWRCFG to enter idle mode */ 38 + tmp = __raw_readl(S3C64XX_PWR_CFG); 39 + tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK; 40 + tmp |= S3C64XX_PWRCFG_CFG_WFI_IDLE; 41 + __raw_writel(tmp, S3C64XX_PWR_CFG); 42 + 43 + cpu_do_idle(); 44 + 45 + do_gettimeofday(&after); 46 + local_irq_enable(); 47 + idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC + 48 + (after.tv_usec - before.tv_usec); 49 + 50 + dev->last_residency = idle_time; 51 + return index; 52 + } 53 + 54 + static struct cpuidle_state s3c64xx_cpuidle_set[] = { 55 + [0] = { 56 + .enter = s3c64xx_enter_idle, 57 + .exit_latency = 1, 58 + .target_residency = 1, 59 + .flags = CPUIDLE_FLAG_TIME_VALID, 60 + .name = "IDLE", 61 + .desc = "System active, ARM gated", 62 + }, 63 + }; 64 + 65 + static struct cpuidle_driver s3c64xx_cpuidle_driver = { 66 + .name = "s3c64xx_cpuidle", 67 + .owner = THIS_MODULE, 68 + .state_count = ARRAY_SIZE(s3c64xx_cpuidle_set), 69 + }; 70 + 71 + static struct cpuidle_device s3c64xx_cpuidle_device = { 72 + .state_count = ARRAY_SIZE(s3c64xx_cpuidle_set), 73 + }; 74 + 75 + static int __init s3c64xx_init_cpuidle(void) 76 + { 77 + int ret; 78 + 79 + memcpy(s3c64xx_cpuidle_driver.states, s3c64xx_cpuidle_set, 80 + sizeof(s3c64xx_cpuidle_set)); 81 + cpuidle_register_driver(&s3c64xx_cpuidle_driver); 82 + 83 + ret = cpuidle_register_device(&s3c64xx_cpuidle_device); 84 + if (ret) { 85 + pr_err("Failed to register cpuidle device: %d\n", ret); 86 + return ret; 87 + } 88 + 89 + return 0; 90 + } 91 + device_initcall(s3c64xx_init_cpuidle);

+4

arch/arm/mach-s3c64xx/mach-crag6410.c

··· 59 59 #include <plat/sdhci.h> 60 60 #include <plat/gpio-cfg.h> 61 61 #include <plat/s3c64xx-spi.h> 62 + #include <plat/udc-hs.h> 62 63 63 64 #include <plat/keypad.h> 64 65 #include <plat/clock.h> ··· 699 698 .cfg_gpio = crag6410_cfg_sdhci0, 700 699 }; 701 700 701 + static struct s3c_hsotg_plat crag6410_hsotg_pdata; 702 + 702 703 static void __init crag6410_machine_init(void) 703 704 { 704 705 /* Open drain IRQs need pullups */ ··· 725 722 s3c_i2c0_set_platdata(&i2c0_pdata); 726 723 s3c_i2c1_set_platdata(&i2c1_pdata); 727 724 s3c_fb_set_platdata(&crag6410_lcd_pdata); 725 + s3c_hsotg_set_platdata(&crag6410_hsotg_pdata); 728 726 729 727 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); 730 728 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));

+3

arch/arm/mach-s3c64xx/mach-smartq.c

··· 187 187 }, 188 188 }; 189 189 190 + static struct s3c_hsotg_plat smartq_hsotg_pdata; 191 + 190 192 static int __init smartq_lcd_setup_gpio(void) 191 193 { 192 194 int ret; ··· 385 383 void __init smartq_machine_init(void) 386 384 { 387 385 s3c_i2c0_set_platdata(NULL); 386 + s3c_hsotg_set_platdata(&smartq_hsotg_pdata); 388 387 s3c_hwmon_set_platdata(&smartq_hwmon_pdata); 389 388 s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata); 390 389 s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata);

+4

arch/arm/mach-s3c64xx/mach-smdk6410.c

··· 72 72 #include <plat/keypad.h> 73 73 #include <plat/backlight.h> 74 74 #include <plat/regs-fb-v4.h> 75 + #include <plat/udc-hs.h> 75 76 76 77 #include "common.h" 77 78 ··· 632 631 .pwm_id = 1, 633 632 }; 634 633 634 + static struct s3c_hsotg_plat smdk6410_hsotg_pdata; 635 + 635 636 static void __init smdk6410_map_io(void) 636 637 { 637 638 u32 tmp; ··· 662 659 s3c_i2c0_set_platdata(NULL); 663 660 s3c_i2c1_set_platdata(NULL); 664 661 s3c_fb_set_platdata(&smdk6410_lcd_pdata); 662 + s3c_hsotg_set_platdata(&smdk6410_hsotg_pdata); 665 663 666 664 samsung_keypad_set_platdata(&smdk6410_keypad_data); 667 665

+90

arch/arm/mach-s3c64xx/setup-usb-phy.c

··· 1 + /* 2 + * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 + * Author: Joonyoung Shim <jy0922.shim@samsung.com> 4 + * 5 + * This program is free software; you can redistribute it and/or modify it 6 + * under the terms of the GNU General Public License as published by the 7 + * Free Software Foundation; either version 2 of the License, or (at your 8 + * option) any later version. 9 + * 10 + */ 11 + 12 + #include <linux/clk.h> 13 + #include <linux/delay.h> 14 + #include <linux/err.h> 15 + #include <linux/io.h> 16 + #include <linux/platform_device.h> 17 + #include <mach/map.h> 18 + #include <mach/regs-sys.h> 19 + #include <plat/cpu.h> 20 + #include <plat/regs-usb-hsotg-phy.h> 21 + #include <plat/usb-phy.h> 22 + 23 + static int s3c_usb_otgphy_init(struct platform_device *pdev) 24 + { 25 + struct clk *xusbxti; 26 + u32 phyclk; 27 + 28 + writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); 29 + 30 + /* set clock frequency for PLL */ 31 + phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; 32 + 33 + xusbxti = clk_get(&pdev->dev, "xusbxti"); 34 + if (xusbxti && !IS_ERR(xusbxti)) { 35 + switch (clk_get_rate(xusbxti)) { 36 + case 12 * MHZ: 37 + phyclk |= S3C_PHYCLK_CLKSEL_12M; 38 + break; 39 + case 24 * MHZ: 40 + phyclk |= S3C_PHYCLK_CLKSEL_24M; 41 + break; 42 + default: 43 + case 48 * MHZ: 44 + /* default reference clock */ 45 + break; 46 + } 47 + clk_put(xusbxti); 48 + } 49 + 50 + /* TODO: select external clock/oscillator */ 51 + writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); 52 + 53 + /* set to normal OTG PHY */ 54 + writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); 55 + mdelay(1); 56 + 57 + /* reset OTG PHY and Link */ 58 + writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, 59 + S3C_RSTCON); 60 + udelay(20); /* at-least 10uS */ 61 + writel(0, S3C_RSTCON); 62 + 63 + return 0; 64 + } 65 + 66 + static int s3c_usb_otgphy_exit(struct platform_device *pdev) 67 + { 68 + writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | 69 + S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR); 70 + 71 + writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); 72 + 73 + return 0; 74 + } 75 + 76 + int s5p_usb_phy_init(struct platform_device *pdev, int type) 77 + { 78 + if (type == S5P_USB_PHY_DEVICE) 79 + return s3c_usb_otgphy_init(pdev); 80 + 81 + return -EINVAL; 82 + } 83 + 84 + int s5p_usb_phy_exit(struct platform_device *pdev, int type) 85 + { 86 + if (type == S5P_USB_PHY_DEVICE) 87 + return s3c_usb_otgphy_exit(pdev); 88 + 89 + return -EINVAL; 90 + }

+6

arch/arm/mach-s5pv210/Kconfig

··· 65 65 help 66 66 Common setup code for SPI GPIO configurations. 67 67 68 + config S5PV210_SETUP_USB_PHY 69 + bool 70 + help 71 + Common setup code for USB PHY controller 72 + 68 73 menu "S5PC110 Machines" 69 74 70 75 config MACH_AQUILA ··· 112 107 select S5PV210_SETUP_KEYPAD 113 108 select S5PV210_SETUP_SDHCI 114 109 select S5PV210_SETUP_FIMC 110 + select S5PV210_SETUP_USB_PHY 115 111 help 116 112 Machine support for Samsung GONI board 117 113 S5PC110(MCP) is one of package option of S5PV210

+1

arch/arm/mach-s5pv210/Makefile

··· 39 39 obj-$(CONFIG_S5PV210_SETUP_KEYPAD) += setup-keypad.o 40 40 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o 41 41 obj-$(CONFIG_S5PV210_SETUP_SPI) += setup-spi.o 42 + obj-$(CONFIG_S5PV210_SETUP_USB_PHY) += setup-usb-phy.o

-4

arch/arm/mach-s5pv210/include/mach/regs-sys.h

··· 13 13 #define S5PV210_USB_PHY_CON (S3C_VA_SYS + 0xE80C) 14 14 #define S5PV210_USB_PHY0_EN (1 << 0) 15 15 #define S5PV210_USB_PHY1_EN (1 << 1) 16 - 17 - /* compatibility defines for s3c-hsotg driver */ 18 - #define S3C64XX_OTHERS S5PV210_USB_PHY_CON 19 - #define S3C64XX_OTHERS_USBMASK S5PV210_USB_PHY0_EN

+90

arch/arm/mach-s5pv210/setup-usb-phy.c

··· 1 + /* 2 + * Copyright (C) 2012 Samsung Electronics Co.Ltd 3 + * Author: Joonyoung Shim <jy0922.shim@samsung.com> 4 + * 5 + * This program is free software; you can redistribute it and/or modify 6 + * it under the terms of the GNU General Public License version 2 as 7 + * published by the Free Software Foundationr 8 + */ 9 + 10 + #include <linux/clk.h> 11 + #include <linux/delay.h> 12 + #include <linux/err.h> 13 + #include <linux/io.h> 14 + #include <linux/platform_device.h> 15 + #include <mach/map.h> 16 + #include <mach/regs-sys.h> 17 + #include <plat/cpu.h> 18 + #include <plat/regs-usb-hsotg-phy.h> 19 + #include <plat/usb-phy.h> 20 + 21 + static int s5pv210_usb_otgphy_init(struct platform_device *pdev) 22 + { 23 + struct clk *xusbxti; 24 + u32 phyclk; 25 + 26 + writel(readl(S5PV210_USB_PHY_CON) | S5PV210_USB_PHY0_EN, 27 + S5PV210_USB_PHY_CON); 28 + 29 + /* set clock frequency for PLL */ 30 + phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; 31 + 32 + xusbxti = clk_get(&pdev->dev, "xusbxti"); 33 + if (xusbxti && !IS_ERR(xusbxti)) { 34 + switch (clk_get_rate(xusbxti)) { 35 + case 12 * MHZ: 36 + phyclk |= S3C_PHYCLK_CLKSEL_12M; 37 + break; 38 + case 24 * MHZ: 39 + phyclk |= S3C_PHYCLK_CLKSEL_24M; 40 + break; 41 + default: 42 + case 48 * MHZ: 43 + /* default reference clock */ 44 + break; 45 + } 46 + clk_put(xusbxti); 47 + } 48 + 49 + /* TODO: select external clock/oscillator */ 50 + writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); 51 + 52 + /* set to normal OTG PHY */ 53 + writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); 54 + mdelay(1); 55 + 56 + /* reset OTG PHY and Link */ 57 + writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, 58 + S3C_RSTCON); 59 + udelay(20); /* at-least 10uS */ 60 + writel(0, S3C_RSTCON); 61 + 62 + return 0; 63 + } 64 + 65 + static int s5pv210_usb_otgphy_exit(struct platform_device *pdev) 66 + { 67 + writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | 68 + S3C_PHYPWR_OTG_DISABLE), S3C_PHYPWR); 69 + 70 + writel(readl(S5PV210_USB_PHY_CON) & ~S5PV210_USB_PHY0_EN, 71 + S5PV210_USB_PHY_CON); 72 + 73 + return 0; 74 + } 75 + 76 + int s5p_usb_phy_init(struct platform_device *pdev, int type) 77 + { 78 + if (type == S5P_USB_PHY_DEVICE) 79 + return s5pv210_usb_otgphy_init(pdev); 80 + 81 + return -EINVAL; 82 + } 83 + 84 + int s5p_usb_phy_exit(struct platform_device *pdev, int type) 85 + { 86 + if (type == S5P_USB_PHY_DEVICE) 87 + return s5pv210_usb_otgphy_exit(pdev); 88 + 89 + return -EINVAL; 90 + }

+10

arch/arm/plat-s5p/Kconfig

··· 80 80 help 81 81 Compile in platform device definitions for FIMC controller 3 82 82 83 + config S5P_DEV_JPEG 84 + bool 85 + help 86 + Compile in platform device definitions for JPEG codec 87 + 88 + config S5P_DEV_G2D 89 + bool 90 + help 91 + Compile in platform device definitions for G2D device 92 + 83 93 config S5P_DEV_FIMD0 84 94 bool 85 95 help

+38 -6

arch/arm/plat-s5p/sleep.S

··· 23 23 */ 24 24 25 25 #include <linux/linkage.h> 26 - #include <asm/assembler.h> 26 + #include <asm/asm-offsets.h> 27 + #include <asm/hardware/cache-l2x0.h> 27 28 28 - .text 29 + /* 30 + * The following code is located into the .data section. This is to 31 + * allow l2x0_regs_phys to be accessed with a relative load while we 32 + * can't rely on any MMU translation. We could have put l2x0_regs_phys 33 + * in the .text section as well, but some setups might insist on it to 34 + * be truly read-only. (Reference from: arch/arm/kernel/sleep.S) 35 + */ 36 + .data 37 + .align 29 38 30 39 /* 31 40 * sleep magic, to allow the bootloader to check for an valid ··· 48 39 * s3c_cpu_resume 49 40 * 50 41 * resume code entry for bootloader to call 51 - * 52 - * we must put this code here in the data segment as we have no 53 - * other way of restoring the stack pointer after sleep, and we 54 - * must not write to the code segment (code is read-only) 55 42 */ 56 43 57 44 ENTRY(s3c_cpu_resume) 45 + #ifdef CONFIG_CACHE_L2X0 46 + adr r0, l2x0_regs_phys 47 + ldr r0, [r0] 48 + ldr r1, [r0, #L2X0_R_PHY_BASE] 49 + ldr r2, [r1, #L2X0_CTRL] 50 + tst r2, #0x1 51 + bne resume_l2on 52 + ldr r2, [r0, #L2X0_R_AUX_CTRL] 53 + str r2, [r1, #L2X0_AUX_CTRL] 54 + ldr r2, [r0, #L2X0_R_TAG_LATENCY] 55 + str r2, [r1, #L2X0_TAG_LATENCY_CTRL] 56 + ldr r2, [r0, #L2X0_R_DATA_LATENCY] 57 + str r2, [r1, #L2X0_DATA_LATENCY_CTRL] 58 + ldr r2, [r0, #L2X0_R_PREFETCH_CTRL] 59 + str r2, [r1, #L2X0_PREFETCH_CTRL] 60 + ldr r2, [r0, #L2X0_R_PWR_CTRL] 61 + str r2, [r1, #L2X0_POWER_CTRL] 62 + mov r2, #1 63 + str r2, [r1, #L2X0_CTRL] 64 + resume_l2on: 65 + #endif 58 66 b cpu_resume 67 + ENDPROC(s3c_cpu_resume) 68 + #ifdef CONFIG_CACHE_L2X0 69 + .globl l2x0_regs_phys 70 + l2x0_regs_phys: 71 + .long 0 72 + #endif

+8 -4

arch/arm/plat-samsung/clock.c

··· 84 84 85 85 int clk_enable(struct clk *clk) 86 86 { 87 + unsigned long flags; 88 + 87 89 if (IS_ERR(clk) || clk == NULL) 88 90 return -EINVAL; 89 91 90 92 clk_enable(clk->parent); 91 93 92 - spin_lock(&clocks_lock); 94 + spin_lock_irqsave(&clocks_lock, flags); 93 95 94 96 if ((clk->usage++) == 0) 95 97 (clk->enable)(clk, 1); 96 98 97 - spin_unlock(&clocks_lock); 99 + spin_unlock_irqrestore(&clocks_lock, flags); 98 100 return 0; 99 101 } 100 102 101 103 void clk_disable(struct clk *clk) 102 104 { 105 + unsigned long flags; 106 + 103 107 if (IS_ERR(clk) || clk == NULL) 104 108 return; 105 109 106 - spin_lock(&clocks_lock); 110 + spin_lock_irqsave(&clocks_lock, flags); 107 111 108 112 if ((--clk->usage) == 0) 109 113 (clk->enable)(clk, 0); 110 114 111 - spin_unlock(&clocks_lock); 115 + spin_unlock_irqrestore(&clocks_lock, flags); 112 116 clk_disable(clk->parent); 113 117 } 114 118

+3 -1

arch/arm/plat-samsung/dev-backlight.c

··· 77 77 * @gpio_info: structure containing GPIO info for PWM timer 78 78 * @bl_data: structure containing Backlight control data 79 79 */ 80 - void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, 80 + void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, 81 81 struct platform_pwm_backlight_data *bl_data) 82 82 { 83 83 int ret = 0; ··· 115 115 samsung_bl_data->init = bl_data->init; 116 116 if (bl_data->notify) 117 117 samsung_bl_data->notify = bl_data->notify; 118 + if (bl_data->notify_after) 119 + samsung_bl_data->notify_after = bl_data->notify_after; 118 120 if (bl_data->exit) 119 121 samsung_bl_data->exit = bl_data->exit; 120 122 if (bl_data->check_fb)

+64 -4

arch/arm/plat-samsung/devs.c

··· 57 57 #include <plat/sdhci.h> 58 58 #include <plat/ts.h> 59 59 #include <plat/udc.h> 60 + #include <plat/udc-hs.h> 60 61 #include <plat/usb-control.h> 61 62 #include <plat/usb-phy.h> 62 63 #include <plat/regs-iic.h> ··· 267 266 }, 268 267 }; 269 268 #endif /* CONFIG_S5P_DEV_FIMC3 */ 269 + 270 + /* G2D */ 271 + 272 + #ifdef CONFIG_S5P_DEV_G2D 273 + static struct resource s5p_g2d_resource[] = { 274 + [0] = { 275 + .start = S5P_PA_G2D, 276 + .end = S5P_PA_G2D + SZ_4K - 1, 277 + .flags = IORESOURCE_MEM, 278 + }, 279 + [1] = { 280 + .start = IRQ_2D, 281 + .end = IRQ_2D, 282 + .flags = IORESOURCE_IRQ, 283 + }, 284 + }; 285 + 286 + struct platform_device s5p_device_g2d = { 287 + .name = "s5p-g2d", 288 + .id = 0, 289 + .num_resources = ARRAY_SIZE(s5p_g2d_resource), 290 + .resource = s5p_g2d_resource, 291 + .dev = { 292 + .dma_mask = &samsung_device_dma_mask, 293 + .coherent_dma_mask = DMA_BIT_MASK(32), 294 + }, 295 + }; 296 + #endif /* CONFIG_S5P_DEV_G2D */ 297 + 298 + #ifdef CONFIG_S5P_DEV_JPEG 299 + static struct resource s5p_jpeg_resource[] = { 300 + [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K), 301 + [1] = DEFINE_RES_IRQ(IRQ_JPEG), 302 + }; 303 + 304 + struct platform_device s5p_device_jpeg = { 305 + .name = "s5p-jpeg", 306 + .id = 0, 307 + .num_resources = ARRAY_SIZE(s5p_jpeg_resource), 308 + .resource = s5p_jpeg_resource, 309 + .dev = { 310 + .dma_mask = &samsung_device_dma_mask, 311 + .coherent_dma_mask = DMA_BIT_MASK(32), 312 + }, 313 + }; 314 + #endif /* CONFIG_S5P_DEV_JPEG */ 270 315 271 316 /* FIMD0 */ 272 317 ··· 816 769 .resource = s3c_cfcon_resource, 817 770 }; 818 771 819 - void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) 772 + void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) 820 773 { 821 774 s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata), 822 775 &s3c_device_cfcon); ··· 934 887 935 888 #ifdef CONFIG_S5P_DEV_CSIS0 936 889 static struct resource s5p_mipi_csis0_resource[] = { 937 - [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K), 890 + [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K), 938 891 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0), 939 892 }; 940 893 ··· 948 901 949 902 #ifdef CONFIG_S5P_DEV_CSIS1 950 903 static struct resource s5p_mipi_csis1_resource[] = { 951 - [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K), 904 + [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K), 952 905 [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1), 953 906 }; 954 907 ··· 1096 1049 .resource = s3c64xx_onenand1_resources, 1097 1050 }; 1098 1051 1099 - void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) 1052 + void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) 1100 1053 { 1101 1054 s3c_set_platdata(pdata, sizeof(struct onenand_platform_data), 1102 1055 &s3c64xx_device_onenand1); ··· 1470 1423 .coherent_dma_mask = DMA_BIT_MASK(32), 1471 1424 }, 1472 1425 }; 1426 + 1427 + void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd) 1428 + { 1429 + struct s3c_hsotg_plat *npd; 1430 + 1431 + npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat), 1432 + &s3c_device_usb_hsotg); 1433 + 1434 + if (!npd->phy_init) 1435 + npd->phy_init = s5p_usb_phy_init; 1436 + if (!npd->phy_exit) 1437 + npd->phy_exit = s5p_usb_phy_exit; 1438 + } 1473 1439 #endif /* CONFIG_S3C_DEV_USB_HSOTG */ 1474 1440 1475 1441 /* USB High Spped 2.0 Device (Gadget) */

+2

arch/arm/plat-samsung/include/plat/devs.h

··· 79 79 extern struct platform_device s5p_device_fimc2; 80 80 extern struct platform_device s5p_device_fimc3; 81 81 extern struct platform_device s5p_device_fimc_md; 82 + extern struct platform_device s5p_device_jpeg; 83 + extern struct platform_device s5p_device_g2d; 82 84 extern struct platform_device s5p_device_fimd0; 83 85 extern struct platform_device s5p_device_hdmi; 84 86 extern struct platform_device s5p_device_i2c_hdmiphy;

+4 -3

arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h

··· 25 25 #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 26 26 27 27 #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 28 - #define SRC_PHYPWR_OTG_DISABLE (1 << 4) 29 - #define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3) 28 + #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 29 + #define S3C_PHYPWR_OTG_DISABLE (1 << 4) 30 + #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 30 31 #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 31 32 32 33 #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) ··· 43 42 44 43 #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 45 44 #define S3C_RSTCON_PHYCLK (1 << 2) 46 - #define S3C_RSTCON_HCLK (1 << 2) 45 + #define S3C_RSTCON_HCLK (1 << 1) 47 46 #define S3C_RSTCON_PHY (1 << 0) 48 47 49 48 #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)

+5

arch/arm/plat-samsung/include/plat/udc-hs.h

··· 26 26 struct s3c_hsotg_plat { 27 27 enum s3c_hsotg_dmamode dma; 28 28 unsigned int is_osc : 1; 29 + 30 + int (*phy_init)(struct platform_device *pdev, int type); 31 + int (*phy_exit)(struct platform_device *pdev, int type); 29 32 }; 33 + 34 + extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);