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drm/panel: st7701: Add Anbernic RG28XX panel support

The Anbernic RG28XX is a handheld gaming device with a 2.8 inch 480x640
display. Add support for the display panel.

This panel is driven by a variant of ST7701 driver IC internally,
confirmed by dumping and analyzing its BSP initialization sequence
by using a logic analyzer. It is very similar to the existing
densitron,dmt028vghmcmi-1a panel, but differs in some unknown
register values. Besides, it is connected via SPI, so add a new entry
for the panel.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240804061503.881283-6-kikuchan98@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240804061503.881283-6-kikuchan98@gmail.com

authored by

Hironori KIKUCHI and committed by
Neil Armstrong f7c4a152 6a60273a

+151
+151
drivers/gpu/drm/panel/panel-sitronix-st7701.c
··· 471 471 msleep(120); 472 472 } 473 473 474 + static void rg28xx_gip_sequence(struct st7701 *st7701) 475 + { 476 + st7701_switch_cmd_bkx(st7701, true, 3); 477 + ST7701_WRITE(st7701, 0xEF, 0x08); 478 + 479 + st7701_switch_cmd_bkx(st7701, true, 0); 480 + ST7701_WRITE(st7701, 0xC3, 0x02, 0x10, 0x02); 481 + ST7701_WRITE(st7701, 0xC7, 0x04); 482 + ST7701_WRITE(st7701, 0xCC, 0x10); 483 + 484 + st7701_switch_cmd_bkx(st7701, true, 1); 485 + ST7701_WRITE(st7701, 0xEE, 0x42); 486 + ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02); 487 + 488 + ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0, 489 + 0x00, 0x44, 0x44); 490 + ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 491 + 0x00, 0x00, 0x00, 0x00); 492 + ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22); 493 + ST7701_WRITE(st7701, 0xE4, 0x44, 0x44); 494 + ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0, 495 + 0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0); 496 + ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22); 497 + ST7701_WRITE(st7701, 0xE7, 0x44, 0x44); 498 + ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0, 499 + 0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0); 500 + ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x40); 501 + ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xBA, 0xFF, 502 + 0xFF, 0xAB, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF); 503 + ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54); 504 + 505 + st7701_switch_cmd_bkx(st7701, false, 0); 506 + 507 + st7701_switch_cmd_bkx(st7701, true, 3); 508 + ST7701_WRITE(st7701, 0xE6, 0x16); 509 + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E); 510 + 511 + st7701_switch_cmd_bkx(st7701, false, 0); 512 + ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10); 513 + ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE); 514 + msleep(120); 515 + 516 + st7701_switch_cmd_bkx(st7701, true, 3); 517 + ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C); 518 + msleep(10); 519 + ST7701_WRITE(st7701, 0xE8, 0x00, 0x00); 520 + st7701_switch_cmd_bkx(st7701, false, 0); 521 + } 522 + 474 523 static int st7701_prepare(struct drm_panel *panel) 475 524 { 476 525 struct st7701 *st7701 = panel_to_st7701(panel); ··· 1035 986 .gip_sequence = rg_arc_gip_sequence, 1036 987 }; 1037 988 989 + static const struct drm_display_mode rg28xx_mode = { 990 + .clock = 22325, 991 + 992 + .hdisplay = 480, 993 + .hsync_start = 480 + 40, 994 + .hsync_end = 480 + 40 + 4, 995 + .htotal = 480 + 40 + 4 + 20, 996 + 997 + .vdisplay = 640, 998 + .vsync_start = 640 + 2, 999 + .vsync_end = 640 + 2 + 40, 1000 + .vtotal = 640 + 2 + 40 + 16, 1001 + 1002 + .width_mm = 44, 1003 + .height_mm = 58, 1004 + 1005 + .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1006 + 1007 + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 1008 + }; 1009 + 1010 + static const struct st7701_panel_desc rg28xx_desc = { 1011 + .mode = &rg28xx_mode, 1012 + 1013 + .panel_sleep_delay = 80, 1014 + 1015 + .pv_gamma = { 1016 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1017 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 1018 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1019 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10), 1020 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1021 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17), 1022 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd), 1023 + 1024 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1025 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 1026 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 1027 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5), 1028 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 1029 + 1030 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7), 1031 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f), 1032 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4), 1033 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1034 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11), 1035 + 1036 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe), 1037 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1038 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29), 1039 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1040 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 1041 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1042 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 1043 + }, 1044 + .nv_gamma = { 1045 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1046 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0), 1047 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1048 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd), 1049 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1050 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14), 1051 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe), 1052 + 1053 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1054 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11), 1055 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6), 1056 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4), 1057 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8), 1058 + 1059 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8), 1060 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20), 1061 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5), 1062 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1063 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13), 1064 + 1065 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13), 1066 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1067 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26), 1068 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1069 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30), 1070 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) | 1071 + CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f) 1072 + }, 1073 + .nlinv = 7, 1074 + .vop_uv = 4800000, 1075 + .vcom_uv = 1512500, 1076 + .vgh_mv = 15000, 1077 + .vgl_mv = -11730, 1078 + .avdd_mv = 6600, 1079 + .avcl_mv = -4400, 1080 + .gamma_op_bias = OP_BIAS_MIDDLE, 1081 + .input_op_bias = OP_BIAS_MIN, 1082 + .output_op_bias = OP_BIAS_MIN, 1083 + .t2d_ns = 1600, 1084 + .t3d_ns = 10400, 1085 + .eot_en = true, 1086 + .gip_sequence = rg28xx_gip_sequence, 1087 + }; 1088 + 1038 1089 static void st7701_cleanup(void *data) 1039 1090 { 1040 1091 struct st7701 *st7701 = (struct st7701 *)data; ··· 1269 1120 MODULE_DEVICE_TABLE(of, st7701_dsi_of_match); 1270 1121 1271 1122 static const struct of_device_id st7701_spi_of_match[] = { 1123 + { .compatible = "anbernic,rg28xx-panel", .data = &rg28xx_desc }, 1272 1124 { /* sentinel */ } 1273 1125 }; 1274 1126 MODULE_DEVICE_TABLE(of, st7701_spi_of_match); 1275 1127 1276 1128 static const struct spi_device_id st7701_spi_ids[] = { 1129 + { "rg28xx-panel" }, 1277 1130 { /* sentinel */ } 1278 1131 }; 1279 1132 MODULE_DEVICE_TABLE(spi, st7701_spi_ids);