Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Move populate phaton function to dml

The function dcn32_helper_populate_phantom_dlg_params uses FPU
operations. For this reason, this commit moves this function to the
dcn32_fpu file, and we ensure that we only invoke it under the
kernel_fpu protection.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rodrigo Siqueira and committed by
Alex Deucher
f7bacd97 465576ca

+55 -44
+7
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
··· 88 88 #include "dml/dcn30/display_mode_vba_30.h" 89 89 #include "vm_helper.h" 90 90 #include "dcn20/dcn20_vmid.h" 91 + #include "dml/dcn32/dcn32_fpu.h" 91 92 92 93 #define DCN_BASE__INST0_SEG1 0x000000C0 93 94 #define DCN_BASE__INST0_SEG2 0x000034C0 ··· 313 312 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 314 313 regBIF_BX0_ ## reg_name 315 314 315 + #undef CTX 316 316 #define CTX ctx 317 317 #define REG(reg_name) \ 318 318 (DCN_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) ··· 2667 2665 memset(split, 0, MAX_PIPES * sizeof(int)); 2668 2666 memset(merge, 0, MAX_PIPES * sizeof(bool)); 2669 2667 *vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, *vlevel, split, merge); 2668 + 2669 + // Most populate phantom DLG params before programming hardware / timing for phantom pipe 2670 + DC_FP_START(); 2671 + dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt); 2672 + DC_FP_END(); 2670 2673 2671 2674 // Note: We can't apply the phantom pipes to hardware at this time. We have to wait 2672 2675 // until driver has acquired the DMCUB lock to do it safely.
-44
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
··· 30 30 31 31 /** 32 32 * ******************************************************************************************** 33 - * dcn32_helper_populate_phantom_dlg_params: Get DLG params for phantom pipes and populate pipe_ctx 34 - * with those params. 35 - * 36 - * This function must be called AFTER the phantom pipes are added to context and run through DML 37 - * (so that the DLG params for the phantom pipes can be populated), and BEFORE we program the 38 - * timing for the phantom pipes. 39 - * 40 - * @param [in] dc: current dc state 41 - * @param [in] context: new dc state 42 - * @param [in] pipes: DML pipe params array 43 - * @param [in] pipe_cnt: DML pipe count 44 - * 45 - * @return: void 46 - * 47 - * ******************************************************************************************** 48 - */ 49 - void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 50 - struct dc_state *context, 51 - display_e2e_pipe_params_st *pipes, 52 - int pipe_cnt) 53 - { 54 - uint32_t i, pipe_idx; 55 - for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 56 - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 57 - if (!pipe->stream) 58 - continue; 59 - 60 - if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 61 - pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, 62 - pipe_idx); 63 - pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 64 - pipe_idx); 65 - pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, 66 - pipe_idx); 67 - pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, 68 - pipe_idx); 69 - pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 70 - } 71 - pipe_idx++; 72 - } 73 - } 74 - 75 - /** 76 - * ******************************************************************************************** 77 33 * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed for SubVP 78 34 * 79 35 * This function first checks the bytes required per pixel on the SubVP pipe, then calculates
+43
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
··· 111 111 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; 112 112 } 113 113 114 + /** 115 + * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes 116 + * and populate pipe_ctx with those params. 117 + * 118 + * This function must be called AFTER the phantom pipes are added to context 119 + * and run through DML (so that the DLG params for the phantom pipes can be 120 + * populated), and BEFORE we program the timing for the phantom pipes. 121 + * 122 + * @dc: [in] current dc state 123 + * @context: [in] new dc state 124 + * @pipes: [in] DML pipe params array 125 + * @pipe_cnt: [in] DML pipe count 126 + */ 127 + void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 128 + struct dc_state *context, 129 + display_e2e_pipe_params_st *pipes, 130 + int pipe_cnt) 131 + { 132 + uint32_t i, pipe_idx; 133 + 134 + dc_assert_fp_enabled(); 135 + 136 + for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 137 + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 138 + 139 + if (!pipe->stream) 140 + continue; 141 + 142 + if (pipe->plane_state && pipe->stream->mall_stream_config.type == SUBVP_PHANTOM) { 143 + pipes[pipe_idx].pipe.dest.vstartup_start = 144 + get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 145 + pipes[pipe_idx].pipe.dest.vupdate_offset = 146 + get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 147 + pipes[pipe_idx].pipe.dest.vupdate_width = 148 + get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 149 + pipes[pipe_idx].pipe.dest.vready_offset = 150 + get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); 151 + pipe->pipe_dlg_param = pipes[pipe_idx].pipe.dest; 152 + } 153 + pipe_idx++; 154 + } 155 + } 156 +
+5
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h
··· 31 31 32 32 void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr); 33 33 34 + void dcn32_helper_populate_phantom_dlg_params(struct dc *dc, 35 + struct dc_state *context, 36 + display_e2e_pipe_params_st *pipes, 37 + int pipe_cnt); 38 + 34 39 #endif