tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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mlx4_core: Add ethernet fields to CQE struct

Add ethernet-related fields to struct mlx4_cqe so that the mlx4_en
ethernet NIC driver can share the same definition.

Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>

authored by Yevgeny Petrilin and committed by Roland Dreier f780a9f1 6e86841d

+40 -29
unified split
+16 -17
drivers/infiniband/hw/mlx4/cq.c
··· 515 515 wc->vendor_err = cqe->vendor_err_syndrome; 516 516 } 517 517 518 - static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum) 518 + static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) 519 519 { 520 - return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | 521 - MLX4_CQE_IPOIB_STATUS_IPV4F | 522 - MLX4_CQE_IPOIB_STATUS_IPV4OPT | 523 - MLX4_CQE_IPOIB_STATUS_IPV6 | 524 - MLX4_CQE_IPOIB_STATUS_IPOK)) == 525 - cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | 526 - MLX4_CQE_IPOIB_STATUS_IPOK)) && 527 - (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP | 528 - MLX4_CQE_IPOIB_STATUS_TCP)) && 520 + return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 521 + MLX4_CQE_STATUS_IPV4F | 522 + MLX4_CQE_STATUS_IPV4OPT | 523 + MLX4_CQE_STATUS_IPV6 | 524 + MLX4_CQE_STATUS_IPOK)) == 525 + cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 526 + MLX4_CQE_STATUS_IPOK)) && 527 + (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | 528 + MLX4_CQE_STATUS_TCP)) && 529 529 checksum == cpu_to_be16(0xffff); 530 530 } 531 531 ··· 582 582 } 583 583 584 584 if (!*cur_qp || 585 - (be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) { 585 + (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { 586 586 /* 587 587 * We do not have to take the QP table lock here, 588 588 * because CQs will be locked while QPs are removed 589 589 * from the table. 590 590 */ 591 591 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, 592 - be32_to_cpu(cqe->my_qpn)); 592 + be32_to_cpu(cqe->vlan_my_qpn)); 593 593 if (unlikely(!mqp)) { 594 594 printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n", 595 - cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff); 595 + cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK); 596 596 return -EINVAL; 597 597 } 598 598 ··· 692 692 } 693 693 694 694 wc->slid = be16_to_cpu(cqe->rlid); 695 - wc->sl = cqe->sl >> 4; 695 + wc->sl = be16_to_cpu(cqe->sl_vid >> 12); 696 696 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); 697 697 wc->src_qp = g_mlpath_rqpn & 0xffffff; 698 698 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 699 699 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 700 700 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 701 - wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status, 702 - cqe->checksum); 701 + wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum); 703 702 } 704 703 705 704 return 0; ··· 766 767 */ 767 768 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { 768 769 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); 769 - if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) { 770 + if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { 770 771 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) 771 772 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); 772 773 ++nfreed;
+24 -12
include/linux/mlx4/cq.h
··· 39 39 #include <linux/mlx4/doorbell.h> 40 40 41 41 struct mlx4_cqe { 42 - __be32 my_qpn; 42 + __be32 vlan_my_qpn; 43 43 __be32 immed_rss_invalid; 44 44 __be32 g_mlpath_rqpn; 45 - u8 sl; 46 - u8 reserved1; 45 + __be16 sl_vid; 47 46 __be16 rlid; 48 - __be32 ipoib_status; 47 + __be16 status; 48 + u8 ipv6_ext_mask; 49 + u8 badfcs_enc; 49 50 __be32 byte_cnt; 50 51 __be16 wqe_index; 51 52 __be16 checksum; 52 - u8 reserved2[3]; 53 + u8 reserved[3]; 53 54 u8 owner_sr_opcode; 54 55 }; 55 56 ··· 62 61 u8 syndrome; 63 62 u8 reserved2[3]; 64 63 u8 owner_sr_opcode; 64 + }; 65 + 66 + enum { 67 + MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, 68 + MLX4_CQE_QPN_MASK = 0xffffff, 65 69 }; 66 70 67 71 enum { ··· 92 86 }; 93 87 94 88 enum { 95 - MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, 96 - MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, 97 - MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, 98 - MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, 99 - MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, 100 - MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, 101 - MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, 89 + MLX4_CQE_STATUS_IPV4 = 1 << 6, 90 + MLX4_CQE_STATUS_IPV4F = 1 << 7, 91 + MLX4_CQE_STATUS_IPV6 = 1 << 8, 92 + MLX4_CQE_STATUS_IPV4OPT = 1 << 9, 93 + MLX4_CQE_STATUS_TCP = 1 << 10, 94 + MLX4_CQE_STATUS_UDP = 1 << 11, 95 + MLX4_CQE_STATUS_IPOK = 1 << 12, 96 + }; 97 + 98 + enum { 99 + MLX4_CQE_LLC = 1, 100 + MLX4_CQE_SNAP = 1 << 1, 101 + MLX4_CQE_BAD_FCS = 1 << 4, 102 102 }; 103 103 104 104 static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,