staging: vt6656: mac.h clean up macros · tjh.dev/kernel@f752c2e

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

staging: vt6656: mac.h clean up macros

White space and comment clean up

Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Malcolm Priestley and committed by

Greg Kroah-Hartman 11 years ago f752c2e3 d7f2d8f6

+284 -323

1 changed file

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drivers

staging

vt6656

mac.h

+284 -323

drivers/staging/vt6656/mac.h

··· 36 36 37 37 #include "device.h" 38 38 39 - #define REV_ID_VT3253_A0 0x00 40 - #define REV_ID_VT3253_A1 0x01 41 - #define REV_ID_VT3253_B0 0x08 42 - #define REV_ID_VT3253_B1 0x09 39 + #define REV_ID_VT3253_A0 0x00 40 + #define REV_ID_VT3253_A1 0x01 41 + #define REV_ID_VT3253_B0 0x08 42 + #define REV_ID_VT3253_B1 0x09 43 43 44 - // 45 - // Registers in the MAC 46 - // 47 - #define MAC_REG_BISTCMD 0x04 48 - #define MAC_REG_BISTSR0 0x05 49 - #define MAC_REG_BISTSR1 0x06 50 - #define MAC_REG_BISTSR2 0x07 51 - #define MAC_REG_I2MCSR 0x08 52 - #define MAC_REG_I2MTGID 0x09 53 - #define MAC_REG_I2MTGAD 0x0A 54 - #define MAC_REG_I2MCFG 0x0B 55 - #define MAC_REG_I2MDIPT 0x0C 56 - #define MAC_REG_I2MDOPT 0x0E 57 - #define MAC_REG_USBSUS 0x0F 44 + /* Registers in the MAC */ 45 + #define MAC_REG_BISTCMD 0x04 46 + #define MAC_REG_BISTSR0 0x05 47 + #define MAC_REG_BISTSR1 0x06 48 + #define MAC_REG_BISTSR2 0x07 49 + #define MAC_REG_I2MCSR 0x08 50 + #define MAC_REG_I2MTGID 0x09 51 + #define MAC_REG_I2MTGAD 0x0a 52 + #define MAC_REG_I2MCFG 0x0b 53 + #define MAC_REG_I2MDIPT 0x0c 54 + #define MAC_REG_I2MDOPT 0x0e 55 + #define MAC_REG_USBSUS 0x0f 58 56 59 - #define MAC_REG_LOCALID 0x14 60 - #define MAC_REG_TESTCFG 0x15 61 - #define MAC_REG_JUMPER0 0x16 62 - #define MAC_REG_JUMPER1 0x17 63 - #define MAC_REG_TMCTL 0x18 64 - #define MAC_REG_TMDATA0 0x1C 65 - #define MAC_REG_TMDATA1 0x1D 66 - #define MAC_REG_TMDATA2 0x1E 67 - #define MAC_REG_TMDATA3 0x1F 57 + #define MAC_REG_LOCALID 0x14 58 + #define MAC_REG_TESTCFG 0x15 59 + #define MAC_REG_JUMPER0 0x16 60 + #define MAC_REG_JUMPER1 0x17 61 + #define MAC_REG_TMCTL 0x18 62 + #define MAC_REG_TMDATA0 0x1c 63 + #define MAC_REG_TMDATA1 0x1d 64 + #define MAC_REG_TMDATA2 0x1e 65 + #define MAC_REG_TMDATA3 0x1f 68 66 69 - // MAC Parameter related 70 - #define MAC_REG_LRT 0x20 // 71 - #define MAC_REG_SRT 0x21 // 72 - #define MAC_REG_SIFS 0x22 // 73 - #define MAC_REG_DIFS 0x23 // 74 - #define MAC_REG_EIFS 0x24 // 75 - #define MAC_REG_SLOT 0x25 // 76 - #define MAC_REG_BI 0x26 // 77 - #define MAC_REG_CWMAXMIN0 0x28 // 78 - #define MAC_REG_LINKOFFTOTM 0x2A 79 - #define MAC_REG_SWTMOT 0x2B 80 - #define MAC_REG_RTSOKCNT 0x2C 81 - #define MAC_REG_RTSFAILCNT 0x2D 82 - #define MAC_REG_ACKFAILCNT 0x2E 83 - #define MAC_REG_FCSERRCNT 0x2F 84 - // TSF Related 85 - #define MAC_REG_TSFCNTR 0x30 // 86 - #define MAC_REG_NEXTTBTT 0x38 // 87 - #define MAC_REG_TSFOFST 0x40 // 88 - #define MAC_REG_TFTCTL 0x48 // 89 - // WMAC Control/Status Related 90 - #define MAC_REG_ENCFG0 0x4C // 91 - #define MAC_REG_ENCFG1 0x4D // 92 - #define MAC_REG_ENCFG2 0x4E // 67 + /* MAC Parameter related */ 68 + #define MAC_REG_LRT 0x20 69 + #define MAC_REG_SRT 0x21 70 + #define MAC_REG_SIFS 0x22 71 + #define MAC_REG_DIFS 0x23 72 + #define MAC_REG_EIFS 0x24 73 + #define MAC_REG_SLOT 0x25 74 + #define MAC_REG_BI 0x26 75 + #define MAC_REG_CWMAXMIN0 0x28 76 + #define MAC_REG_LINKOFFTOTM 0x2a 77 + #define MAC_REG_SWTMOT 0x2b 78 + #define MAC_REG_RTSOKCNT 0x2c 79 + #define MAC_REG_RTSFAILCNT 0x2d 80 + #define MAC_REG_ACKFAILCNT 0x2e 81 + #define MAC_REG_FCSERRCNT 0x2f 93 82 94 - #define MAC_REG_CFG 0x50 // 95 - #define MAC_REG_TEST 0x52 // 96 - #define MAC_REG_HOSTCR 0x54 // 97 - #define MAC_REG_MACCR 0x55 // 98 - #define MAC_REG_RCR 0x56 // 99 - #define MAC_REG_TCR 0x57 // 100 - #define MAC_REG_IMR 0x58 // 101 - #define MAC_REG_ISR 0x5C 102 - #define MAC_REG_ISR1 0x5D 103 - // Power Saving Related 104 - #define MAC_REG_PSCFG 0x60 // 105 - #define MAC_REG_PSCTL 0x61 // 106 - #define MAC_REG_PSPWRSIG 0x62 // 107 - #define MAC_REG_BBCR13 0x63 108 - #define MAC_REG_AIDATIM 0x64 109 - #define MAC_REG_PWBT 0x66 110 - #define MAC_REG_WAKEOKTMR 0x68 111 - #define MAC_REG_CALTMR 0x69 112 - #define MAC_REG_SYNSPACCNT 0x6A 113 - #define MAC_REG_WAKSYNOPT 0x6B 114 - // Baseband/IF Control Group 115 - #define MAC_REG_BBREGCTL 0x6C // 116 - #define MAC_REG_CHANNEL 0x6D 117 - #define MAC_REG_BBREGADR 0x6E 118 - #define MAC_REG_BBREGDATA 0x6F 119 - #define MAC_REG_IFREGCTL 0x70 // 120 - #define MAC_REG_IFDATA 0x71 // 121 - #define MAC_REG_ITRTMSET 0x74 // 122 - #define MAC_REG_PAPEDELAY 0x77 123 - #define MAC_REG_SOFTPWRCTL 0x78 // 124 - #define MAC_REG_SOFTPWRCTL2 0x79 // 125 - #define MAC_REG_GPIOCTL0 0x7A // 126 - #define MAC_REG_GPIOCTL1 0x7B // 83 + /* TSF Related */ 84 + #define MAC_REG_TSFCNTR 0x30 85 + #define MAC_REG_NEXTTBTT 0x38 86 + #define MAC_REG_TSFOFST 0x40 87 + #define MAC_REG_TFTCTL 0x48 127 88 128 - // MiscFF PIO related 129 - #define MAC_REG_MISCFFNDEX 0xBC 130 - #define MAC_REG_MISCFFCTL 0xBE 131 - #define MAC_REG_MISCFFDATA 0xC0 89 + /* WMAC Control/Status Related */ 90 + #define MAC_REG_ENCFG0 0x4c 91 + #define MAC_REG_ENCFG1 0x4d 92 + #define MAC_REG_ENCFG2 0x4e 132 93 133 - // MAC Configuration Group 134 - #define MAC_REG_PAR0 0xC4 135 - #define MAC_REG_PAR4 0xC8 136 - #define MAC_REG_BSSID0 0xCC 137 - #define MAC_REG_BSSID4 0xD0 138 - #define MAC_REG_MAR0 0xD4 139 - #define MAC_REG_MAR4 0xD8 140 - // MAC RSPPKT INFO Group 141 - #define MAC_REG_RSPINF_B_1 0xDC 142 - #define MAC_REG_RSPINF_B_2 0xE0 143 - #define MAC_REG_RSPINF_B_5 0xE4 144 - #define MAC_REG_RSPINF_B_11 0xE8 145 - #define MAC_REG_RSPINF_A_6 0xEC 146 - #define MAC_REG_RSPINF_A_9 0xEE 147 - #define MAC_REG_RSPINF_A_12 0xF0 148 - #define MAC_REG_RSPINF_A_18 0xF2 149 - #define MAC_REG_RSPINF_A_24 0xF4 150 - #define MAC_REG_RSPINF_A_36 0xF6 151 - #define MAC_REG_RSPINF_A_48 0xF8 152 - #define MAC_REG_RSPINF_A_54 0xFA 153 - #define MAC_REG_RSPINF_A_72 0xFC 94 + #define MAC_REG_CFG 0x50 95 + #define MAC_REG_TEST 0x52 96 + #define MAC_REG_HOSTCR 0x54 97 + #define MAC_REG_MACCR 0x55 98 + #define MAC_REG_RCR 0x56 99 + #define MAC_REG_TCR 0x57 100 + #define MAC_REG_IMR 0x58 101 + #define MAC_REG_ISR 0x5c 102 + #define MAC_REG_ISR1 0x5d 154 103 155 - // 156 - // Bits in the I2MCFG EEPROM register 157 - // 158 - #define I2MCFG_BOUNDCTL 0x80 159 - #define I2MCFG_WAITCTL 0x20 160 - #define I2MCFG_SCLOECTL 0x10 161 - #define I2MCFG_WBUSYCTL 0x08 162 - #define I2MCFG_NORETRY 0x04 163 - #define I2MCFG_I2MLDSEQ 0x02 164 - #define I2MCFG_I2CMFAST 0x01 104 + /* Power Saving Related */ 105 + #define MAC_REG_PSCFG 0x60 106 + #define MAC_REG_PSCTL 0x61 107 + #define MAC_REG_PSPWRSIG 0x62 108 + #define MAC_REG_BBCR13 0x63 109 + #define MAC_REG_AIDATIM 0x64 110 + #define MAC_REG_PWBT 0x66 111 + #define MAC_REG_WAKEOKTMR 0x68 112 + #define MAC_REG_CALTMR 0x69 113 + #define MAC_REG_SYNSPACCNT 0x6a 114 + #define MAC_REG_WAKSYNOPT 0x6b 165 115 166 - // 167 - // Bits in the I2MCSR EEPROM register 168 - // 169 - #define I2MCSR_EEMW 0x80 170 - #define I2MCSR_EEMR 0x40 171 - #define I2MCSR_AUTOLD 0x08 172 - #define I2MCSR_NACK 0x02 173 - #define I2MCSR_DONE 0x01 116 + /* Baseband/IF Control Group */ 117 + #define MAC_REG_BBREGCTL 0x6c 118 + #define MAC_REG_CHANNEL 0x6d 119 + #define MAC_REG_BBREGADR 0x6e 120 + #define MAC_REG_BBREGDATA 0x6f 121 + #define MAC_REG_IFREGCTL 0x70 122 + #define MAC_REG_IFDATA 0x71 123 + #define MAC_REG_ITRTMSET 0x74 124 + #define MAC_REG_PAPEDELAY 0x77 125 + #define MAC_REG_SOFTPWRCTL 0x78 126 + #define MAC_REG_SOFTPWRCTL2 0x79 127 + #define MAC_REG_GPIOCTL0 0x7a 128 + #define MAC_REG_GPIOCTL1 0x7b 174 129 175 - // 176 - // Bits in the TMCTL register 177 - // 178 - #define TMCTL_TSUSP 0x04 179 - #define TMCTL_TMD 0x02 180 - #define TMCTL_TE 0x01 130 + /* MiscFF PIO related */ 131 + #define MAC_REG_MISCFFNDEX 0xbc 132 + #define MAC_REG_MISCFFCTL 0xbe 133 + #define MAC_REG_MISCFFDATA 0xc0 181 134 182 - // 183 - // Bits in the TFTCTL register 184 - // 185 - #define TFTCTL_HWUTSF 0x80 // 186 - #define TFTCTL_TBTTSYNC 0x40 187 - #define TFTCTL_HWUTSFEN 0x20 188 - #define TFTCTL_TSFCNTRRD 0x10 // 189 - #define TFTCTL_TBTTSYNCEN 0x08 // 190 - #define TFTCTL_TSFSYNCEN 0x04 // 191 - #define TFTCTL_TSFCNTRST 0x02 // 192 - #define TFTCTL_TSFCNTREN 0x01 // 135 + /* MAC Configuration Group */ 136 + #define MAC_REG_PAR0 0xc4 137 + #define MAC_REG_PAR4 0xc8 138 + #define MAC_REG_BSSID0 0xcc 139 + #define MAC_REG_BSSID4 0xd0 140 + #define MAC_REG_MAR0 0xd4 141 + #define MAC_REG_MAR4 0xd8 193 142 194 - // 195 - // Bits in the EnhanceCFG_0 register 196 - // 197 - #define EnCFG_BBType_a 0x00 198 - #define EnCFG_BBType_b 0x01 199 - #define EnCFG_BBType_g 0x02 200 - #define EnCFG_BBType_MASK 0x03 201 - #define EnCFG_ProtectMd 0x20 143 + /* MAC RSPPKT INFO Group */ 144 + #define MAC_REG_RSPINF_B_1 0xdC 145 + #define MAC_REG_RSPINF_B_2 0xe0 146 + #define MAC_REG_RSPINF_B_5 0xe4 147 + #define MAC_REG_RSPINF_B_11 0xe8 148 + #define MAC_REG_RSPINF_A_6 0xec 149 + #define MAC_REG_RSPINF_A_9 0xee 150 + #define MAC_REG_RSPINF_A_12 0xf0 151 + #define MAC_REG_RSPINF_A_18 0xf2 152 + #define MAC_REG_RSPINF_A_24 0xf4 153 + #define MAC_REG_RSPINF_A_36 0xf6 154 + #define MAC_REG_RSPINF_A_48 0xf8 155 + #define MAC_REG_RSPINF_A_54 0xfa 156 + #define MAC_REG_RSPINF_A_72 0xfc 202 157 203 - // 204 - // Bits in the EnhanceCFG_1 register 205 - // 206 - #define EnCFG_BcnSusInd 0x01 207 - #define EnCFG_BcnSusClr 0x02 158 + /* Bits in the I2MCFG EEPROM register */ 159 + #define I2MCFG_BOUNDCTL 0x80 160 + #define I2MCFG_WAITCTL 0x20 161 + #define I2MCFG_SCLOECTL 0x10 162 + #define I2MCFG_WBUSYCTL 0x08 163 + #define I2MCFG_NORETRY 0x04 164 + #define I2MCFG_I2MLDSEQ 0x02 165 + #define I2MCFG_I2CMFAST 0x01 208 166 209 - // 210 - // Bits in the EnhanceCFG_2 register 211 - // 212 - #define EnCFG_NXTBTTCFPSTR 0x01 213 - #define EnCFG_BarkerPream 0x02 214 - #define EnCFG_PktBurstMode 0x04 167 + /* Bits in the I2MCSR EEPROM register */ 168 + #define I2MCSR_EEMW 0x80 169 + #define I2MCSR_EEMR 0x40 170 + #define I2MCSR_AUTOLD 0x08 171 + #define I2MCSR_NACK 0x02 172 + #define I2MCSR_DONE 0x01 215 173 216 - // 217 - // Bits in the CFG register 218 - // 219 - #define CFG_TKIPOPT 0x80 220 - #define CFG_RXDMAOPT 0x40 221 - #define CFG_TMOT_SW 0x20 222 - #define CFG_TMOT_HWLONG 0x10 223 - #define CFG_TMOT_HW 0x00 224 - #define CFG_CFPENDOPT 0x08 225 - #define CFG_BCNSUSEN 0x04 226 - #define CFG_NOTXTIMEOUT 0x02 227 - #define CFG_NOBUFOPT 0x01 174 + /* Bits in the TMCTL register */ 175 + #define TMCTL_TSUSP 0x04 176 + #define TMCTL_TMD 0x02 177 + #define TMCTL_TE 0x01 228 178 229 - // 230 - // Bits in the TEST register 231 - // 232 - #define TEST_LBEXT 0x80 // 233 - #define TEST_LBINT 0x40 // 234 - #define TEST_LBNONE 0x00 // 235 - #define TEST_SOFTINT 0x20 // 236 - #define TEST_CONTTX 0x10 // 237 - #define TEST_TXPE 0x08 // 238 - #define TEST_NAVDIS 0x04 // 239 - #define TEST_NOCTS 0x02 // 240 - #define TEST_NOACK 0x01 // 179 + /* Bits in the TFTCTL register */ 180 + #define TFTCTL_HWUTSF 0x80 181 + #define TFTCTL_TBTTSYNC 0x40 182 + #define TFTCTL_HWUTSFEN 0x20 183 + #define TFTCTL_TSFCNTRRD 0x10 184 + #define TFTCTL_TBTTSYNCEN 0x08 185 + #define TFTCTL_TSFSYNCEN 0x04 186 + #define TFTCTL_TSFCNTRST 0x02 187 + #define TFTCTL_TSFCNTREN 0x01 241 188 242 - // 243 - // Bits in the HOSTCR register 244 - // 245 - #define HOSTCR_TXONST 0x80 // 246 - #define HOSTCR_RXONST 0x40 // 247 - #define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc 248 - #define HOSTCR_AP 0x10 // Port Type 1 = AP 249 - #define HOSTCR_TXON 0x08 //0000 1000 250 - #define HOSTCR_RXON 0x04 //0000 0100 251 - #define HOSTCR_MACEN 0x02 //0000 0010 252 - #define HOSTCR_SOFTRST 0x01 //0000 0001 189 + /* Bits in the EnhanceCFG_0 register */ 190 + #define EnCFG_BBType_a 0x00 191 + #define EnCFG_BBType_b 0x01 192 + #define EnCFG_BBType_g 0x02 193 + #define EnCFG_BBType_MASK 0x03 194 + #define EnCFG_ProtectMd 0x20 253 195 254 - // 255 - // Bits in the MACCR register 256 - // 257 - #define MACCR_SYNCFLUSHOK 0x04 // 258 - #define MACCR_SYNCFLUSH 0x02 // 259 - #define MACCR_CLRNAV 0x01 // 196 + /* Bits in the EnhanceCFG_1 register */ 197 + #define EnCFG_BcnSusInd 0x01 198 + #define EnCFG_BcnSusClr 0x02 260 199 261 - // 262 - // Bits in the RCR register 263 - // 264 - #define RCR_SSID 0x80 265 - #define RCR_RXALLTYPE 0x40 // 266 - #define RCR_UNICAST 0x20 // 267 - #define RCR_BROADCAST 0x10 // 268 - #define RCR_MULTICAST 0x08 // 269 - #define RCR_WPAERR 0x04 // 270 - #define RCR_ERRCRC 0x02 // 271 - #define RCR_BSSID 0x01 // 200 + /* Bits in the EnhanceCFG_2 register */ 201 + #define EnCFG_NXTBTTCFPSTR 0x01 202 + #define EnCFG_BarkerPream 0x02 203 + #define EnCFG_PktBurstMode 0x04 272 204 273 - // 274 - // Bits in the TCR register 275 - // 276 - #define TCR_SYNCDCFOPT 0x02 // 277 - #define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable 205 + /* Bits in the CFG register */ 206 + #define CFG_TKIPOPT 0x80 207 + #define CFG_RXDMAOPT 0x40 208 + #define CFG_TMOT_SW 0x20 209 + #define CFG_TMOT_HWLONG 0x10 210 + #define CFG_TMOT_HW 0x00 211 + #define CFG_CFPENDOPT 0x08 212 + #define CFG_BCNSUSEN 0x04 213 + #define CFG_NOTXTIMEOUT 0x02 214 + #define CFG_NOBUFOPT 0x01 278 215 279 - //ISR1 280 - #define ISR_GPIO3 0x40 281 - #define ISR_RXNOBUF 0x08 282 - #define ISR_MIBNEARFULL 0x04 283 - #define ISR_SOFTINT 0x02 284 - #define ISR_FETALERR 0x01 216 + /* Bits in the TEST register */ 217 + #define TEST_LBEXT 0x80 218 + #define TEST_LBINT 0x40 219 + #define TEST_LBNONE 0x00 220 + #define TEST_SOFTINT 0x20 221 + #define TEST_CONTTX 0x10 222 + #define TEST_TXPE 0x08 223 + #define TEST_NAVDIS 0x04 224 + #define TEST_NOCTS 0x02 225 + #define TEST_NOACK 0x01 285 226 286 - #define LEDSTS_STS 0x06 287 - #define LEDSTS_TMLEN 0x78 288 - #define LEDSTS_OFF 0x00 289 - #define LEDSTS_ON 0x02 290 - #define LEDSTS_SLOW 0x04 291 - #define LEDSTS_INTER 0x06 227 + /* Bits in the HOSTCR register */ 228 + #define HOSTCR_TXONST 0x80 229 + #define HOSTCR_RXONST 0x40 230 + #define HOSTCR_ADHOC 0x20 231 + #define HOSTCR_AP 0x10 232 + #define HOSTCR_TXON 0x08 233 + #define HOSTCR_RXON 0x04 234 + #define HOSTCR_MACEN 0x02 235 + #define HOSTCR_SOFTRST 0x01 292 236 293 - //ISR0 294 - #define ISR_WATCHDOG 0x80 295 - #define ISR_SOFTTIMER 0x40 296 - #define ISR_GPIO0 0x20 297 - #define ISR_TBTT 0x10 298 - #define ISR_RXDMA0 0x08 299 - #define ISR_BNTX 0x04 300 - #define ISR_ACTX 0x01 237 + /* Bits in the MACCR register */ 238 + #define MACCR_SYNCFLUSHOK 0x04 239 + #define MACCR_SYNCFLUSH 0x02 240 + #define MACCR_CLRNAV 0x01 301 241 302 - // 303 - // Bits in the PSCFG register 304 - // 305 - #define PSCFG_PHILIPMD 0x40 // 306 - #define PSCFG_WAKECALEN 0x20 // 307 - #define PSCFG_WAKETMREN 0x10 // 308 - #define PSCFG_BBPSPROG 0x08 // 309 - #define PSCFG_WAKESYN 0x04 // 310 - #define PSCFG_SLEEPSYN 0x02 // 311 - #define PSCFG_AUTOSLEEP 0x01 // 242 + /* Bits in the RCR register */ 243 + #define RCR_SSID 0x80 244 + #define RCR_RXALLTYPE 0x40 245 + #define RCR_UNICAST 0x20 246 + #define RCR_BROADCAST 0x10 247 + #define RCR_MULTICAST 0x08 248 + #define RCR_WPAERR 0x04 249 + #define RCR_ERRCRC 0x02 250 + #define RCR_BSSID 0x01 312 251 313 - // 314 - // Bits in the PSCTL register 315 - // 316 - #define PSCTL_WAKEDONE 0x20 // 317 - #define PSCTL_PS 0x10 // 318 - #define PSCTL_GO2DOZE 0x08 // 319 - #define PSCTL_LNBCN 0x04 // 320 - #define PSCTL_ALBCN 0x02 // 321 - #define PSCTL_PSEN 0x01 // 252 + /* Bits in the TCR register */ 253 + #define TCR_SYNCDCFOPT 0x02 254 + #define TCR_AUTOBCNTX 0x01 322 255 323 - // 324 - // Bits in the PSPWSIG register 325 - // 326 - #define PSSIG_WPE3 0x80 // 327 - #define PSSIG_WPE2 0x40 // 328 - #define PSSIG_WPE1 0x20 // 329 - #define PSSIG_WRADIOPE 0x10 // 330 - #define PSSIG_SPE3 0x08 // 331 - #define PSSIG_SPE2 0x04 // 332 - #define PSSIG_SPE1 0x02 // 333 - #define PSSIG_SRADIOPE 0x01 // 256 + /* ISR1 */ 257 + #define ISR_GPIO3 0x40 258 + #define ISR_RXNOBUF 0x08 259 + #define ISR_MIBNEARFULL 0x04 260 + #define ISR_SOFTINT 0x02 261 + #define ISR_FETALERR 0x01 334 262 335 - // 336 - // Bits in the BBREGCTL register 337 - // 338 - #define BBREGCTL_DONE 0x04 // 339 - #define BBREGCTL_REGR 0x02 // 340 - #define BBREGCTL_REGW 0x01 // 263 + #define LEDSTS_STS 0x06 264 + #define LEDSTS_TMLEN 0x78 265 + #define LEDSTS_OFF 0x00 266 + #define LEDSTS_ON 0x02 267 + #define LEDSTS_SLOW 0x04 268 + #define LEDSTS_INTER 0x06 341 269 342 - // 343 - // Bits in the IFREGCTL register 344 - // 345 - #define IFREGCTL_DONE 0x04 // 346 - #define IFREGCTL_IFRF 0x02 // 347 - #define IFREGCTL_REGW 0x01 // 270 + /* ISR0 */ 271 + #define ISR_WATCHDOG 0x80 272 + #define ISR_SOFTTIMER 0x40 273 + #define ISR_GPIO0 0x20 274 + #define ISR_TBTT 0x10 275 + #define ISR_RXDMA0 0x08 276 + #define ISR_BNTX 0x04 277 + #define ISR_ACTX 0x01 348 278 349 - // 350 - // Bits in the SOFTPWRCTL register 351 - // 352 - #define SOFTPWRCTL_RFLEOPT 0x08 // 353 - #define SOFTPWRCTL_TXPEINV 0x02 // 354 - #define SOFTPWRCTL_SWPECTI 0x01 // 355 - #define SOFTPWRCTL_SWPAPE 0x20 // 356 - #define SOFTPWRCTL_SWCALEN 0x10 // 357 - #define SOFTPWRCTL_SWRADIO_PE 0x08 // 358 - #define SOFTPWRCTL_SWPE2 0x04 // 359 - #define SOFTPWRCTL_SWPE1 0x02 // 360 - #define SOFTPWRCTL_SWPE3 0x01 // 279 + /* Bits in the PSCFG register */ 280 + #define PSCFG_PHILIPMD 0x40 281 + #define PSCFG_WAKECALEN 0x20 282 + #define PSCFG_WAKETMREN 0x10 283 + #define PSCFG_BBPSPROG 0x08 284 + #define PSCFG_WAKESYN 0x04 285 + #define PSCFG_SLEEPSYN 0x02 286 + #define PSCFG_AUTOSLEEP 0x01 361 287 362 - // 363 - // Bits in the GPIOCTL1 register 364 - // 365 - #define GPIO3_MD 0x20 // 366 - #define GPIO3_DATA 0x40 // 367 - #define GPIO3_INTMD 0x80 // 288 + /* Bits in the PSCTL register */ 289 + #define PSCTL_WAKEDONE 0x20 290 + #define PSCTL_PS 0x10 291 + #define PSCTL_GO2DOZE 0x08 292 + #define PSCTL_LNBCN 0x04 293 + #define PSCTL_ALBCN 0x02 294 + #define PSCTL_PSEN 0x01 368 295 369 - // 370 - // Bits in the MISCFFCTL register 371 - // 372 - #define MISCFFCTL_WRITE 0x0001 // 296 + /* Bits in the PSPWSIG register */ 297 + #define PSSIG_WPE3 0x80 298 + #define PSSIG_WPE2 0x40 299 + #define PSSIG_WPE1 0x20 300 + #define PSSIG_WRADIOPE 0x10 301 + #define PSSIG_SPE3 0x08 302 + #define PSSIG_SPE2 0x04 303 + #define PSSIG_SPE1 0x02 304 + #define PSSIG_SRADIOPE 0x01 373 305 374 - // Loopback mode 375 - #define MAC_LB_EXT 0x02 // 376 - #define MAC_LB_INTERNAL 0x01 // 377 - #define MAC_LB_NONE 0x00 // 306 + /* Bits in the BBREGCTL register */ 307 + #define BBREGCTL_DONE 0x04 308 + #define BBREGCTL_REGR 0x02 309 + #define BBREGCTL_REGW 0x01 378 310 379 - // Ethernet address filter type 380 - #define PKT_TYPE_NONE 0x00 // turn off receiver 381 - #define PKT_TYPE_ALL_MULTICAST 0x80 382 - #define PKT_TYPE_PROMISCUOUS 0x40 383 - #define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted 384 - #define PKT_TYPE_BROADCAST 0x10 385 - #define PKT_TYPE_MULTICAST 0x08 386 - #define PKT_TYPE_ERROR_WPA 0x04 387 - #define PKT_TYPE_ERROR_CRC 0x02 388 - #define PKT_TYPE_BSSID 0x01 311 + /* Bits in the IFREGCTL register */ 312 + #define IFREGCTL_DONE 0x04 313 + #define IFREGCTL_IFRF 0x02 314 + #define IFREGCTL_REGW 0x01 315 + 316 + /* Bits in the SOFTPWRCTL register */ 317 + #define SOFTPWRCTL_RFLEOPT 0x08 318 + #define SOFTPWRCTL_TXPEINV 0x02 319 + #define SOFTPWRCTL_SWPECTI 0x01 320 + #define SOFTPWRCTL_SWPAPE 0x20 321 + #define SOFTPWRCTL_SWCALEN 0x10 322 + #define SOFTPWRCTL_SWRADIO_PE 0x08 323 + #define SOFTPWRCTL_SWPE2 0x04 324 + #define SOFTPWRCTL_SWPE1 0x02 325 + #define SOFTPWRCTL_SWPE3 0x01 326 + 327 + /* Bits in the GPIOCTL1 register */ 328 + #define GPIO3_MD 0x20 329 + #define GPIO3_DATA 0x40 330 + #define GPIO3_INTMD 0x80 331 + 332 + /* Bits in the MISCFFCTL register */ 333 + #define MISCFFCTL_WRITE 0x0001 334 + 335 + /* Loopback mode */ 336 + #define MAC_LB_EXT 0x02 337 + #define MAC_LB_INTERNAL 0x01 338 + #define MAC_LB_NONE 0x00 339 + 340 + /* Ethernet address filter type */ 341 + #define PKT_TYPE_NONE 0x00 /* turn off receiver */ 342 + #define PKT_TYPE_ALL_MULTICAST 0x80 343 + #define PKT_TYPE_PROMISCUOUS 0x40 344 + #define PKT_TYPE_DIRECTED 0x20 /* obselete */ 345 + #define PKT_TYPE_BROADCAST 0x10 346 + #define PKT_TYPE_MULTICAST 0x08 347 + #define PKT_TYPE_ERROR_WPA 0x04 348 + #define PKT_TYPE_ERROR_CRC 0x02 349 + #define PKT_TYPE_BSSID 0x01 389 350 390 351 #define Default_BI 0x200 391 352 392 - // MiscFIFO Offset 393 - #define MISCFIFO_KEYETRY0 32 394 - #define MISCFIFO_KEYENTRYSIZE 22 353 + /* MiscFIFO Offset */ 354 + #define MISCFIFO_KEYETRY0 32 355 + #define MISCFIFO_KEYENTRYSIZE 22 395 356 396 357 // max time out delay time 397 358 #define W_MAX_TIMEOUT 0xFFF0U // ··· 360 399 // wait time within loop 361 400 #define CB_DELAY_LOOP_WAIT 10 // 10ms 362 401 363 - #define MAC_REVISION_A0 0x00 364 - #define MAC_REVISION_A1 0x01 402 + #define MAC_REVISION_A0 0x00 403 + #define MAC_REVISION_A1 0x01 365 404 366 405 struct vnt_mac_set_key { 367 406 union {