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kernel
os
linux
sh: fix watchdog timer for sh7780/sh7785
Signed-off-by: Valentin Sitdikov <valentin.sitdikov@siemens.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
authored by
Valentin R Sitsikov
and committed by
Paul Mundt
f72f7876
376abbb4
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arch/sh/include/asm/watchdog.h
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arch/sh/include/asm/watchdog.h
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* include/asm-sh/watchdog.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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* Copyright (C) 2009 Siemens AG
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* Copyright (C) 2009 Valentin Sitdikov
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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#define WTCSR_CKS_2048 0x06
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#define WTCSR_CKS_4096 0x07
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#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
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/**
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* sh_wdt_read_cnt - Read from Counter
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* Reads back the WTCNT value.
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*/
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static inline __u32 sh_wdt_read_cnt(void)
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{
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return ctrl_inl(WTCNT_R);
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}
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/**
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* sh_wdt_write_cnt - Write to Counter
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* @val: Value to write
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*
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* Writes the given value @val to the lower byte of the timer counter.
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* The upper byte is set manually on each write.
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*/
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static inline void sh_wdt_write_cnt(__u32 val)
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{
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ctrl_outl((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
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}
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/**
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* sh_wdt_write_bst - Write to Counter
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* @val: Value to write
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*
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* Writes the given value @val to the lower byte of the timer counter.
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* The upper byte is set manually on each write.
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*/
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static inline void sh_wdt_write_bst(__u32 val)
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{
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ctrl_outl((WTBST_HIGH << 24) | (__u32)val, WTBST);
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}
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/**
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* sh_wdt_read_csr - Read from Control/Status Register
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*
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* Reads back the WTCSR value.
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*/
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static inline __u32 sh_wdt_read_csr(void)
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{
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return ctrl_inl(WTCSR_R);
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}
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/**
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* sh_wdt_write_csr - Write to Control/Status Register
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* @val: Value to write
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*
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* Writes the given value @val to the lower byte of the control/status
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* register. The upper byte is set manually on each write.
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*/
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static inline void sh_wdt_write_csr(__u32 val)
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{
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ctrl_outl((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
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}
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#else
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/**
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* sh_wdt_read_cnt - Read from Counter
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* Reads back the WTCNT value.
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{
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ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
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}
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#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_WATCHDOG_H */
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arch/sh/include/cpu-sh4/cpu/watchdog.h
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arch/sh/include/cpu-sh4/cpu/watchdog.h
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* include/asm-sh/cpu-sh4/watchdog.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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* Copyright (C) 2009 Siemens AG
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* Copyright (C) 2009 Sitdikov Valentin
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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#ifndef __ASM_CPU_SH4_WATCHDOG_H
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#define __ASM_CPU_SH4_WATCHDOG_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
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/* Prefix definition */
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#define WTBST_HIGH 0x55
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/* Register definitions */
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#define WTCNT_R 0xffcc0010 /*WDTCNT*/
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#define WTCSR 0xffcc0004 /*WDTCSR*/
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#define WTCNT 0xffcc0000 /*WDTST*/
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#define WTST WTCNT
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#define WTBST 0xffcc0008 /*WDTBST*/
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#else
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/* Register definitions */
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#define WTCNT 0xffc00008
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#define WTCSR 0xffc0000c
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#endif
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/* Bit definitions */
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#define WTCSR_TME 0x80