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ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices

The drive/sample clocks can be phase shifted. The drive clock
could be used in a future patch to adjust hold times. The sample
clock is used for tuning.

Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

authored by

Alexandru M Stan and committed by
Ulf Hansson f71ddc58 cbb79e43

+12 -8
+12 -8
arch/arm/boot/dts/rk3288.dtsi
··· 222 222 sdmmc: dwmmc@ff0c0000 { 223 223 compatible = "rockchip,rk3288-dw-mshc"; 224 224 clock-freq-min-max = <400000 150000000>; 225 - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 226 - clock-names = "biu", "ciu"; 225 + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 226 + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 227 + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 227 228 fifo-depth = <0x100>; 228 229 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 229 230 reg = <0xff0c0000 0x4000>; ··· 234 233 sdio0: dwmmc@ff0d0000 { 235 234 compatible = "rockchip,rk3288-dw-mshc"; 236 235 clock-freq-min-max = <400000 150000000>; 237 - clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; 238 - clock-names = "biu", "ciu"; 236 + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 237 + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 238 + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 239 239 fifo-depth = <0x100>; 240 240 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 241 241 reg = <0xff0d0000 0x4000>; ··· 246 244 sdio1: dwmmc@ff0e0000 { 247 245 compatible = "rockchip,rk3288-dw-mshc"; 248 246 clock-freq-min-max = <400000 150000000>; 249 - clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; 250 - clock-names = "biu", "ciu"; 247 + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 248 + <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 249 + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 251 250 fifo-depth = <0x100>; 252 251 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 253 252 reg = <0xff0e0000 0x4000>; ··· 258 255 emmc: dwmmc@ff0f0000 { 259 256 compatible = "rockchip,rk3288-dw-mshc"; 260 257 clock-freq-min-max = <400000 150000000>; 261 - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 262 - clock-names = "biu", "ciu"; 258 + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 259 + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 260 + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 263 261 fifo-depth = <0x100>; 264 262 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 265 263 reg = <0xff0f0000 0x4000>;