Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog

* git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog:
[WATCHDOG] hpwdt: Fix kdump when using hpwdt
[WATCHDOG] hpwdt: set the mapped BIOS address space as executable
[WATCHDOG] iTCO_wdt: add PCI ID's for ICH9 & ICH10 chipsets
[WATCHDOG] iTCO_wdt : correct status clearing
[WATCHDOG] iTCO_wdt : problem with rebooting on new ICH9 based motherboards
[WATCHDOG] fix mtx1_wdt compilation failure

+116 -88
+4 -1
drivers/watchdog/hpwdt.c
··· 40 40 #include <linux/bootmem.h> 41 41 #include <linux/slab.h> 42 42 #include <asm/desc.h> 43 + #include <asm/cacheflush.h> 43 44 44 45 #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ 45 46 #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 ··· 395 394 smbios_cru64_ptr->double_offset; 396 395 cru_rom_addr = ioremap(cru_physical_address, 397 396 smbios_cru64_ptr->double_length); 397 + set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK, 398 + smbios_cru64_ptr->double_length >> PAGE_SHIFT); 398 399 } 399 400 } 400 401 } ··· 485 482 "Management Log for details.\n"); 486 483 } 487 484 488 - return NOTIFY_STOP; 485 + return NOTIFY_OK; 489 486 } 490 487 491 488 /*
+4 -27
drivers/watchdog/iTCO_vendor_support.c
··· 1 1 /* 2 2 * intel TCO vendor specific watchdog driver support 3 3 * 4 - * (c) Copyright 2006 Wim Van Sebroeck <wim@iguana.be>. 4 + * (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>. 5 5 * 6 6 * This program is free software; you can redistribute it and/or 7 7 * modify it under the terms of the GNU General Public License ··· 19 19 20 20 /* Module and version information */ 21 21 #define DRV_NAME "iTCO_vendor_support" 22 - #define DRV_VERSION "1.01" 23 - #define DRV_RELDATE "11-Nov-2006" 22 + #define DRV_VERSION "1.02" 24 23 #define PFX DRV_NAME ": " 25 24 26 25 /* Includes */ ··· 76 77 * time is about 40 seconds, and the minimum hang time is about 77 78 * 20.6 seconds. 78 79 */ 79 - 80 - static void supermicro_old_pre_start(unsigned long acpibase) 81 - { 82 - unsigned long val32; 83 - 84 - val32 = inl(SMI_EN); 85 - val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 86 - outl(val32, SMI_EN); /* Needed to activate watchdog */ 87 - } 88 - 89 - static void supermicro_old_pre_stop(unsigned long acpibase) 90 - { 91 - unsigned long val32; 92 - 93 - val32 = inl(SMI_EN); 94 - val32 &= 0x00002000; /* Turn on SMI clearing watchdog */ 95 - outl(val32, SMI_EN); /* Needed to deactivate watchdog */ 96 - } 97 80 98 81 static void supermicro_old_pre_keepalive(unsigned long acpibase) 99 82 { ··· 228 247 void iTCO_vendor_pre_start(unsigned long acpibase, 229 248 unsigned int heartbeat) 230 249 { 231 - if (vendorsupport == SUPERMICRO_OLD_BOARD) 232 - supermicro_old_pre_start(acpibase); 233 - else if (vendorsupport == SUPERMICRO_NEW_BOARD) 250 + if (vendorsupport == SUPERMICRO_NEW_BOARD) 234 251 supermicro_new_pre_start(heartbeat); 235 252 } 236 253 EXPORT_SYMBOL(iTCO_vendor_pre_start); 237 254 238 255 void iTCO_vendor_pre_stop(unsigned long acpibase) 239 256 { 240 - if (vendorsupport == SUPERMICRO_OLD_BOARD) 241 - supermicro_old_pre_stop(acpibase); 242 - else if (vendorsupport == SUPERMICRO_NEW_BOARD) 257 + if (vendorsupport == SUPERMICRO_NEW_BOARD) 243 258 supermicro_new_pre_stop(); 244 259 } 245 260 EXPORT_SYMBOL(iTCO_vendor_pre_stop);
+104 -60
drivers/watchdog/iTCO_wdt.c
··· 1 1 /* 2 2 * intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets) 3 3 * 4 - * (c) Copyright 2006-2007 Wim Van Sebroeck <wim@iguana.be>. 4 + * (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>. 5 5 * 6 6 * This program is free software; you can redistribute it and/or 7 7 * modify it under the terms of the GNU General Public License ··· 20 20 * 82801BAM (ICH2-M) : document number 290687-002, 298242-027, 21 21 * 82801CA (ICH3-S) : document number 290733-003, 290739-013, 22 22 * 82801CAM (ICH3-M) : document number 290716-001, 290718-007, 23 - * 82801DB (ICH4) : document number 290744-001, 290745-020, 24 - * 82801DBM (ICH4-M) : document number 252337-001, 252663-005, 23 + * 82801DB (ICH4) : document number 290744-001, 290745-025, 24 + * 82801DBM (ICH4-M) : document number 252337-001, 252663-008, 25 25 * 82801E (C-ICH) : document number 273599-001, 273645-002, 26 - * 82801EB (ICH5) : document number 252516-001, 252517-003, 27 - * 82801ER (ICH5R) : document number 252516-001, 252517-003, 28 - * 82801FB (ICH6) : document number 301473-002, 301474-007, 29 - * 82801FR (ICH6R) : document number 301473-002, 301474-007, 30 - * 82801FBM (ICH6-M) : document number 301473-002, 301474-007, 31 - * 82801FW (ICH6W) : document number 301473-001, 301474-007, 32 - * 82801FRW (ICH6RW) : document number 301473-001, 301474-007, 33 - * 82801GB (ICH7) : document number 307013-002, 307014-009, 34 - * 82801GR (ICH7R) : document number 307013-002, 307014-009, 35 - * 82801GDH (ICH7DH) : document number 307013-002, 307014-009, 36 - * 82801GBM (ICH7-M) : document number 307013-002, 307014-009, 37 - * 82801GHM (ICH7-M DH) : document number 307013-002, 307014-009, 38 - * 82801HB (ICH8) : document number 313056-003, 313057-009, 39 - * 82801HR (ICH8R) : document number 313056-003, 313057-009, 40 - * 82801HBM (ICH8M) : document number 313056-003, 313057-009, 41 - * 82801HH (ICH8DH) : document number 313056-003, 313057-009, 42 - * 82801HO (ICH8DO) : document number 313056-003, 313057-009, 43 - * 82801HEM (ICH8M-E) : document number 313056-003, 313057-009, 44 - * 82801IB (ICH9) : document number 316972-001, 316973-006, 45 - * 82801IR (ICH9R) : document number 316972-001, 316973-006, 46 - * 82801IH (ICH9DH) : document number 316972-001, 316973-006, 47 - * 82801IO (ICH9DO) : document number 316972-001, 316973-006, 48 - * 6300ESB (6300ESB) : document number 300641-003, 300884-010, 49 - * 631xESB (631xESB) : document number 313082-001, 313075-005, 50 - * 632xESB (632xESB) : document number 313082-001, 313075-005 26 + * 82801EB (ICH5) : document number 252516-001, 252517-028, 27 + * 82801ER (ICH5R) : document number 252516-001, 252517-028, 28 + * 6300ESB (6300ESB) : document number 300641-004, 300884-013, 29 + * 82801FB (ICH6) : document number 301473-002, 301474-026, 30 + * 82801FR (ICH6R) : document number 301473-002, 301474-026, 31 + * 82801FBM (ICH6-M) : document number 301473-002, 301474-026, 32 + * 82801FW (ICH6W) : document number 301473-001, 301474-026, 33 + * 82801FRW (ICH6RW) : document number 301473-001, 301474-026, 34 + * 631xESB (631xESB) : document number 313082-001, 313075-006, 35 + * 632xESB (632xESB) : document number 313082-001, 313075-006, 36 + * 82801GB (ICH7) : document number 307013-003, 307014-024, 37 + * 82801GR (ICH7R) : document number 307013-003, 307014-024, 38 + * 82801GDH (ICH7DH) : document number 307013-003, 307014-024, 39 + * 82801GBM (ICH7-M) : document number 307013-003, 307014-024, 40 + * 82801GHM (ICH7-M DH) : document number 307013-003, 307014-024, 41 + * 82801GU (ICH7-U) : document number 307013-003, 307014-024, 42 + * 82801HB (ICH8) : document number 313056-003, 313057-017, 43 + * 82801HR (ICH8R) : document number 313056-003, 313057-017, 44 + * 82801HBM (ICH8M) : document number 313056-003, 313057-017, 45 + * 82801HH (ICH8DH) : document number 313056-003, 313057-017, 46 + * 82801HO (ICH8DO) : document number 313056-003, 313057-017, 47 + * 82801HEM (ICH8M-E) : document number 313056-003, 313057-017, 48 + * 82801IB (ICH9) : document number 316972-004, 316973-012, 49 + * 82801IR (ICH9R) : document number 316972-004, 316973-012, 50 + * 82801IH (ICH9DH) : document number 316972-004, 316973-012, 51 + * 82801IO (ICH9DO) : document number 316972-004, 316973-012, 52 + * 82801IBM (ICH9M) : document number 316972-004, 316973-012, 53 + * 82801IEM (ICH9M-E) : document number 316972-004, 316973-012, 54 + * 82801JIB (ICH10) : document number 319973-002, 319974-002, 55 + * 82801JIR (ICH10R) : document number 319973-002, 319974-002, 56 + * 82801JD (ICH10D) : document number 319973-002, 319974-002, 57 + * 82801JDO (ICH10DO) : document number 319973-002, 319974-002 51 58 */ 52 59 53 60 /* ··· 63 56 64 57 /* Module and version information */ 65 58 #define DRV_NAME "iTCO_wdt" 66 - #define DRV_VERSION "1.03" 67 - #define DRV_RELDATE "30-Apr-2008" 59 + #define DRV_VERSION "1.04" 68 60 #define PFX DRV_NAME ": " 69 61 70 62 /* Includes */ ··· 102 96 TCO_ICH6, /* ICH6 & ICH6R */ 103 97 TCO_ICH6M, /* ICH6-M */ 104 98 TCO_ICH6W, /* ICH6W & ICH6RW */ 99 + TCO_631XESB, /* 631xESB/632xESB */ 105 100 TCO_ICH7, /* ICH7 & ICH7R */ 106 - TCO_ICH7M, /* ICH7-M */ 101 + TCO_ICH7DH, /* ICH7DH */ 102 + TCO_ICH7M, /* ICH7-M & ICH7-U */ 107 103 TCO_ICH7MDH, /* ICH7-M DH */ 108 104 TCO_ICH8, /* ICH8 & ICH8R */ 109 - TCO_ICH8ME, /* ICH8M-E */ 110 105 TCO_ICH8DH, /* ICH8DH */ 111 106 TCO_ICH8DO, /* ICH8DO */ 112 107 TCO_ICH8M, /* ICH8M */ 108 + TCO_ICH8ME, /* ICH8M-E */ 113 109 TCO_ICH9, /* ICH9 */ 114 110 TCO_ICH9R, /* ICH9R */ 115 111 TCO_ICH9DH, /* ICH9DH */ 116 112 TCO_ICH9DO, /* ICH9DO */ 117 - TCO_631XESB, /* 631xESB/632xESB */ 113 + TCO_ICH9M, /* ICH9M */ 114 + TCO_ICH9ME, /* ICH9M-E */ 115 + TCO_ICH10, /* ICH10 */ 116 + TCO_ICH10R, /* ICH10R */ 117 + TCO_ICH10D, /* ICH10D */ 118 + TCO_ICH10DO, /* ICH10DO */ 118 119 }; 119 120 120 121 static struct { ··· 142 129 {"ICH6 or ICH6R", 2}, 143 130 {"ICH6-M", 2}, 144 131 {"ICH6W or ICH6RW", 2}, 132 + {"631xESB/632xESB", 2}, 145 133 {"ICH7 or ICH7R", 2}, 146 - {"ICH7-M", 2}, 134 + {"ICH7DH", 2}, 135 + {"ICH7-M or ICH7-U", 2}, 147 136 {"ICH7-M DH", 2}, 148 137 {"ICH8 or ICH8R", 2}, 149 - {"ICH8M-E", 2}, 150 138 {"ICH8DH", 2}, 151 139 {"ICH8DO", 2}, 152 140 {"ICH8M", 2}, 141 + {"ICH8M-E", 2}, 153 142 {"ICH9", 2}, 154 143 {"ICH9R", 2}, 155 144 {"ICH9DH", 2}, 156 145 {"ICH9DO", 2}, 157 - {"631xESB/632xESB", 2}, 146 + {"ICH9M", 2}, 147 + {"ICH9M-E", 2}, 148 + {"ICH10", 2}, 149 + {"ICH10R", 2}, 150 + {"ICH10D", 2}, 151 + {"ICH10DO", 2}, 158 152 {NULL, 0} 159 153 }; 160 154 ··· 195 175 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)}, 196 176 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)}, 197 177 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)}, 198 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, 199 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, 200 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, 201 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, 202 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, 203 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, 204 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, 205 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, 206 - { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, 207 - { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, 208 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, 209 - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, 210 178 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, 211 179 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, 212 180 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, ··· 211 203 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)}, 212 204 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)}, 213 205 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, 206 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, 207 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)}, 208 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, 209 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, 210 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, 211 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, 212 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, 213 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, 214 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, 215 + { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, 216 + { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, 217 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, 218 + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, 219 + { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)}, 220 + { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)}, 221 + { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)}, 222 + { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)}, 223 + { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)}, 224 + { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)}, 214 225 { 0, }, /* End of list */ 215 226 }; 216 227 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); ··· 338 311 static int iTCO_wdt_start(void) 339 312 { 340 313 unsigned int val; 314 + unsigned long val32; 341 315 342 316 spin_lock(&iTCO_wdt_private.io_lock); 343 317 ··· 350 322 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n"); 351 323 return -EIO; 352 324 } 325 + 326 + /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */ 327 + val32 = inl(SMI_EN); 328 + val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 329 + outl(val32, SMI_EN); 330 + 331 + /* Force the timer to its reload value by writing to the TCO_RLD 332 + register */ 333 + if (iTCO_wdt_private.iTCO_version == 2) 334 + outw(0x01, TCO_RLD); 335 + else if (iTCO_wdt_private.iTCO_version == 1) 336 + outb(0x01, TCO_RLD); 353 337 354 338 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */ 355 339 val = inw(TCO1_CNT); ··· 378 338 static int iTCO_wdt_stop(void) 379 339 { 380 340 unsigned int val; 341 + unsigned long val32; 381 342 382 343 spin_lock(&iTCO_wdt_private.io_lock); 383 344 ··· 389 348 val |= 0x0800; 390 349 outw(val, TCO1_CNT); 391 350 val = inw(TCO1_CNT); 351 + 352 + /* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */ 353 + val32 = inl(SMI_EN); 354 + val32 &= 0x00002000; 355 + outl(val32, SMI_EN); 392 356 393 357 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 394 358 iTCO_wdt_set_NO_REBOOT_bit(); ··· 505 459 /* 506 460 * Reload and activate timer 507 461 */ 508 - iTCO_wdt_keepalive(); 509 462 iTCO_wdt_start(); 510 463 return nonseekable_open(inode, file); 511 464 } ··· 649 604 int ret; 650 605 u32 base_address; 651 606 unsigned long RCBA; 652 - unsigned long val32; 653 607 654 608 /* 655 609 * Find the ACPI/PM base I/O address which is the base ··· 688 644 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ 689 645 iTCO_wdt_set_NO_REBOOT_bit(); 690 646 691 - /* Set the TCO_EN bit in SMI_EN register */ 647 + /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ 692 648 if (!request_region(SMI_EN, 4, "iTCO_wdt")) { 693 649 printk(KERN_ERR PFX 694 650 "I/O address 0x%04lx already in use\n", SMI_EN); 695 651 ret = -EIO; 696 652 goto out; 697 653 } 698 - val32 = inl(SMI_EN); 699 - val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */ 700 - outl(val32, SMI_EN); 701 - release_region(SMI_EN, 4); 702 654 703 655 /* The TCO I/O registers reside in a 32-byte range pointed to 704 656 by the TCOBASE value */ ··· 702 662 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", 703 663 TCOBASE); 704 664 ret = -EIO; 705 - goto out; 665 + goto unreg_smi_en; 706 666 } 707 667 708 668 printk(KERN_INFO PFX ··· 712 672 TCOBASE); 713 673 714 674 /* Clear out the (probably old) status */ 715 - outb(0, TCO1_STS); 716 - outb(3, TCO2_STS); 675 + outb(8, TCO1_STS); /* Clear the Time Out Status bit */ 676 + outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */ 677 + outb(4, TCO2_STS); /* Clear BOOT_STS bit */ 717 678 718 679 /* Make sure the watchdog is not running */ 719 680 iTCO_wdt_stop(); ··· 742 701 743 702 unreg_region: 744 703 release_region(TCOBASE, 0x20); 704 + unreg_smi_en: 705 + release_region(SMI_EN, 4); 745 706 out: 746 707 if (iTCO_wdt_private.iTCO_version == 2) 747 708 iounmap(iTCO_wdt_private.gcs); ··· 761 718 /* Deregister */ 762 719 misc_deregister(&iTCO_wdt_miscdev); 763 720 release_region(TCOBASE, 0x20); 721 + release_region(SMI_EN, 4); 764 722 if (iTCO_wdt_private.iTCO_version == 2) 765 723 iounmap(iTCO_wdt_private.gcs); 766 724 pci_dev_put(iTCO_wdt_private.pdev); ··· 826 782 { 827 783 int err; 828 784 829 - printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s (%s)\n", 830 - DRV_VERSION, DRV_RELDATE); 785 + printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n", 786 + DRV_VERSION); 831 787 832 788 err = platform_driver_register(&iTCO_wdt_driver); 833 789 if (err)
+4
drivers/watchdog/mtx-1_wdt.c
··· 98 98 99 99 static void mtx1_wdt_start(void) 100 100 { 101 + unsigned long flags; 102 + 101 103 spin_lock_irqsave(&mtx1_wdt_device.lock, flags); 102 104 if (!mtx1_wdt_device.queue) { 103 105 mtx1_wdt_device.queue = 1; ··· 112 110 113 111 static int mtx1_wdt_stop(void) 114 112 { 113 + unsigned long flags; 114 + 115 115 spin_lock_irqsave(&mtx1_wdt_device.lock, flags); 116 116 if (mtx1_wdt_device.queue) { 117 117 mtx1_wdt_device.queue = 0;