tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
"This is mostly some DT updates, but also a handful of cleanups and
some fixes. The most user-visible of those are:
- A device tree for the Sundance Polarberry, along with a handful of
fixes and clenups to the PolarFire SOC device trees and bindings.
- The memfd_secret syscall number is now visible to userspace,
- Some improvements to the vm layout dump, which really should have
followed shortly after the sv48 patches but I missed"
* tag 'riscv-for-linus-5.19-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Move alternative length validation into subsection
riscv: mm: init: make pt_ops_set_[early|late|fixmap] static
riscv: move errata/ and kvm/ builds to arch/riscv/Kbuild
RISC-V: Mark IORESOURCE_EXCLUSIVE for reserved mem instead of IORESOURCE_BUSY
riscv: Wire up memfd_secret in UAPI header
riscv: Fix irq_work when SMP is disabled
riscv: Improve virtual kernel memory layout dump
riscv: Initialize thread pointer before calling C functions
Documentation: riscv: Add sv48 description to VM layout
RISC-V: Only default to spinwait on SBI-0.1 and M-mode
riscv: dts: icicle: sort nodes alphabetically
riscv: microchip: icicle: readability fixes
riscv: dts: microchip: add the sundance polarberry
dt-bindings: riscv: microchip: add polarberry compatible string
dt-bindings: vendor-prefixes: add Sundance DSP
riscv: dts: microchip: make the fabric dtsi board specific
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: remove soc vendor from filenames
riscv: dts: microchip: move sysctrlr out of soc bus
riscv: dts: microchip: remove icicle memory clocks
+304
-104
+2
Documentation/devicetree/bindings/riscv/microchip.yaml
+2
Documentation/devicetree/bindings/riscv/microchip.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
Documentation/devicetree/bindings/vendor-prefixes.yaml
+36
Documentation/riscv/vm-layout.rst
+36
Documentation/riscv/vm-layout.rst
···
61
61
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
62
62
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
63
63
__________________|____________|__________________|_________|____________________________________________________________
64
+
65
+
66
+
RISC-V Linux Kernel SV48
67
+
------------------------
68
+
69
+
::
70
+
71
+
========================================================================================================================
72
+
Start addr | Offset | End addr | Size | VM area description
73
+
========================================================================================================================
74
+
| | | |
75
+
0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different per mm
76
+
__________________|____________|__________________|_________|___________________________________________________________
77
+
| | | |
78
+
0000800000000000 | +128 TB | ffff7fffffffffff | ~16M TB | ... huge, almost 64 bits wide hole of non-canonical
79
+
| | | | virtual memory addresses up to the -128 TB
80
+
| | | | starting offset of kernel mappings.
81
+
__________________|____________|__________________|_________|___________________________________________________________
82
+
|
83
+
| Kernel-space virtual memory, shared between all processes:
84
+
____________________________________________________________|___________________________________________________________
85
+
| | | |
86
+
ffff8d7ffee00000 | -114.5 TB | ffff8d7ffeffffff | 2 MB | fixmap
87
+
ffff8d7fff000000 | -114.5 TB | ffff8d7fffffffff | 16 MB | PCI io
88
+
ffff8d8000000000 | -114.5 TB | ffff8f7fffffffff | 2 TB | vmemmap
89
+
ffff8f8000000000 | -112.5 TB | ffffaf7fffffffff | 32 TB | vmalloc/ioremap space
90
+
ffffaf8000000000 | -80.5 TB | ffffef7fffffffff | 64 TB | direct mapping of all physical memory
91
+
ffffef8000000000 | -16.5 TB | fffffffeffffffff | 16.5 TB | kasan
92
+
__________________|____________|__________________|_________|____________________________________________________________
93
+
|
94
+
| Identical layout to the 39-bit one from here on:
95
+
____________________________________________________________|____________________________________________________________
96
+
| | | |
97
+
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
98
+
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
99
+
__________________|____________|__________________|_________|____________________________________________________________
+2
arch/riscv/Kbuild
+2
arch/riscv/Kbuild
+7
-1
arch/riscv/Kconfig
+7
-1
arch/riscv/Kconfig
···
396
396
config RISCV_BOOT_SPINWAIT
397
397
bool "Spinwait booting method"
398
398
depends on SMP
399
-
default y
399
+
default y if RISCV_SBI_V01 || RISCV_M_MODE
400
400
help
401
401
This enables support for booting Linux via spinwait method. In the
402
402
spinwait method, all cores randomly jump to Linux. One of the cores
···
406
406
on older firmware without SBI HSM extension. All other platforms should
407
407
rely on ordered booting via SBI HSM extension which gets chosen
408
408
dynamically at runtime if the firmware supports it.
409
+
410
+
Since spinwait is incompatible with sparse hart IDs, it requires
411
+
NR_CPUS be large enough to contain the physical hart ID of the first
412
+
hart to enter Linux.
413
+
414
+
If unsure what to do here, say N.
409
415
410
416
config KEXEC
411
417
bool "Kexec system call"
-3
arch/riscv/Makefile
-3
arch/riscv/Makefile
+2
-1
arch/riscv/boot/dts/microchip/Makefile
+2
-1
arch/riscv/boot/dts/microchip/Makefile
···
1
1
# SPDX-License-Identifier: GPL-2.0
2
-
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
2
+
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
3
+
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
3
4
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
+2
arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+2
arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+70
-69
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+70
-69
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
···
3
3
4
4
/dts-v1/;
5
5
6
-
#include "microchip-mpfs.dtsi"
6
+
#include "mpfs.dtsi"
7
+
#include "mpfs-icicle-kit-fabric.dtsi"
7
8
8
9
/* Clock frequency (in Hz) of the rtcclk */
9
10
#define RTCCLK_FREQ 1000000
···
33
32
ddrc_cache_lo: memory@80000000 {
34
33
device_type = "memory";
35
34
reg = <0x0 0x80000000 0x0 0x2e000000>;
36
-
clocks = <&clkcfg CLK_DDRC>;
37
35
status = "okay";
38
36
};
39
37
40
38
ddrc_cache_hi: memory@1000000000 {
41
39
device_type = "memory";
42
40
reg = <0x10 0x0 0x0 0x40000000>;
43
-
clocks = <&clkcfg CLK_DDRC>;
44
41
status = "okay";
45
42
};
46
43
};
47
44
48
-
&refclk {
49
-
clock-frequency = <125000000>;
50
-
};
51
-
52
-
&mmuart1 {
45
+
&core_pwm0 {
53
46
status = "okay";
54
47
};
55
48
56
-
&mmuart2 {
57
-
status = "okay";
58
-
};
59
-
60
-
&mmuart3 {
61
-
status = "okay";
62
-
};
63
-
64
-
&mmuart4 {
65
-
status = "okay";
66
-
};
67
-
68
-
&mmc {
69
-
status = "okay";
70
-
71
-
bus-width = <4>;
72
-
disable-wp;
73
-
cap-sd-highspeed;
74
-
cap-mmc-highspeed;
75
-
card-detect-delay = <200>;
76
-
mmc-ddr-1_8v;
77
-
mmc-hs200-1_8v;
78
-
sd-uhs-sdr12;
79
-
sd-uhs-sdr25;
80
-
sd-uhs-sdr50;
81
-
sd-uhs-sdr104;
82
-
};
83
-
84
-
&spi0 {
85
-
status = "okay";
86
-
};
87
-
88
-
&spi1 {
89
-
status = "okay";
90
-
};
91
-
92
-
&qspi {
49
+
&gpio2 {
50
+
interrupts = <53>, <53>, <53>, <53>,
51
+
<53>, <53>, <53>, <53>,
52
+
<53>, <53>, <53>, <53>,
53
+
<53>, <53>, <53>, <53>,
54
+
<53>, <53>, <53>, <53>,
55
+
<53>, <53>, <53>, <53>,
56
+
<53>, <53>, <53>, <53>,
57
+
<53>, <53>, <53>, <53>;
93
58
status = "okay";
94
59
};
95
60
···
74
107
&mac0 {
75
108
phy-mode = "sgmii";
76
109
phy-handle = <&phy0>;
110
+
status = "okay";
77
111
};
78
112
79
113
&mac1 {
80
-
status = "okay";
81
114
phy-mode = "sgmii";
82
115
phy-handle = <&phy1>;
116
+
status = "okay";
117
+
83
118
phy1: ethernet-phy@9 {
84
119
reg = <9>;
85
120
ti,fifo-depth = <0x1>;
86
121
};
122
+
87
123
phy0: ethernet-phy@8 {
88
124
reg = <8>;
89
125
ti,fifo-depth = <0x1>;
90
126
};
91
127
};
92
128
93
-
&gpio2 {
94
-
interrupts = <53>, <53>, <53>, <53>,
95
-
<53>, <53>, <53>, <53>,
96
-
<53>, <53>, <53>, <53>,
97
-
<53>, <53>, <53>, <53>,
98
-
<53>, <53>, <53>, <53>,
99
-
<53>, <53>, <53>, <53>,
100
-
<53>, <53>, <53>, <53>,
101
-
<53>, <53>, <53>, <53>;
102
-
status = "okay";
103
-
};
104
-
105
-
&rtc {
106
-
status = "okay";
107
-
};
108
-
109
-
&usb {
110
-
status = "okay";
111
-
dr_mode = "host";
112
-
};
113
-
114
129
&mbox {
115
130
status = "okay";
116
131
};
117
132
118
-
&syscontroller {
133
+
&mmc {
134
+
bus-width = <4>;
135
+
disable-wp;
136
+
cap-sd-highspeed;
137
+
cap-mmc-highspeed;
138
+
card-detect-delay = <200>;
139
+
mmc-ddr-1_8v;
140
+
mmc-hs200-1_8v;
141
+
sd-uhs-sdr12;
142
+
sd-uhs-sdr25;
143
+
sd-uhs-sdr50;
144
+
sd-uhs-sdr104;
145
+
status = "okay";
146
+
};
147
+
148
+
&mmuart1 {
149
+
status = "okay";
150
+
};
151
+
152
+
&mmuart2 {
153
+
status = "okay";
154
+
};
155
+
156
+
&mmuart3 {
157
+
status = "okay";
158
+
};
159
+
160
+
&mmuart4 {
119
161
status = "okay";
120
162
};
121
163
···
132
156
status = "okay";
133
157
};
134
158
135
-
&core_pwm0 {
159
+
&qspi {
136
160
status = "okay";
161
+
};
162
+
163
+
&refclk {
164
+
clock-frequency = <125000000>;
165
+
};
166
+
167
+
&rtc {
168
+
status = "okay";
169
+
};
170
+
171
+
&spi0 {
172
+
status = "okay";
173
+
};
174
+
175
+
&spi1 {
176
+
status = "okay";
177
+
};
178
+
179
+
&syscontroller {
180
+
status = "okay";
181
+
};
182
+
183
+
&usb {
184
+
status = "okay";
185
+
dr_mode = "host";
137
186
};
+5
-6
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
arch/riscv/boot/dts/microchip/mpfs.dtsi
+5
-6
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
arch/riscv/boot/dts/microchip/mpfs.dtsi
···
3
3
4
4
/dts-v1/;
5
5
#include "dt-bindings/clock/microchip,mpfs-clock.h"
6
-
#include "microchip-mpfs-fabric.dtsi"
7
6
8
7
/ {
9
8
#address-cells = <2>;
···
143
144
refclk: mssrefclk {
144
145
compatible = "fixed-clock";
145
146
#clock-cells = <0>;
147
+
};
148
+
149
+
syscontroller: syscontroller {
150
+
compatible = "microchip,mpfs-sys-controller";
151
+
mboxes = <&mbox 0>;
146
152
};
147
153
148
154
soc {
···
449
445
interrupts = <96>;
450
446
#mbox-cells = <1>;
451
447
status = "disabled";
452
-
};
453
-
454
-
syscontroller: syscontroller {
455
-
compatible = "microchip,mpfs-sys-controller";
456
-
mboxes = <&mbox 0>;
457
448
};
458
449
};
459
450
};
+16
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+16
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/* Copyright (c) 2020-2022 Microchip Technology Inc */
3
+
4
+
/ {
5
+
fabric_clk3: fabric-clk3 {
6
+
compatible = "fixed-clock";
7
+
#clock-cells = <0>;
8
+
clock-frequency = <62500000>;
9
+
};
10
+
11
+
fabric_clk1: fabric-clk1 {
12
+
compatible = "fixed-clock";
13
+
#clock-cells = <0>;
14
+
clock-frequency = <125000000>;
15
+
};
16
+
};
+99
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
+99
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
+
/* Copyright (c) 2020-2022 Microchip Technology Inc */
3
+
4
+
/dts-v1/;
5
+
6
+
#include "mpfs.dtsi"
7
+
#include "mpfs-polarberry-fabric.dtsi"
8
+
9
+
/* Clock frequency (in Hz) of the rtcclk */
10
+
#define MTIMER_FREQ 1000000
11
+
12
+
/ {
13
+
model = "Sundance PolarBerry";
14
+
compatible = "sundance,polarberry", "microchip,mpfs";
15
+
16
+
aliases {
17
+
ethernet0 = &mac1;
18
+
serial0 = &mmuart0;
19
+
};
20
+
21
+
chosen {
22
+
stdout-path = "serial0:115200n8";
23
+
};
24
+
25
+
cpus {
26
+
timebase-frequency = <MTIMER_FREQ>;
27
+
};
28
+
29
+
ddrc_cache_lo: memory@80000000 {
30
+
device_type = "memory";
31
+
reg = <0x0 0x80000000 0x0 0x2e000000>;
32
+
};
33
+
34
+
ddrc_cache_hi: memory@1000000000 {
35
+
device_type = "memory";
36
+
reg = <0x10 0x00000000 0x0 0xC0000000>;
37
+
};
38
+
};
39
+
40
+
/*
41
+
* phy0 is connected to mac0, but the port itself is on the (optional) carrier
42
+
* board.
43
+
*/
44
+
&mac0 {
45
+
phy-mode = "sgmii";
46
+
phy-handle = <&phy0>;
47
+
status = "disabled";
48
+
};
49
+
50
+
&mac1 {
51
+
phy-mode = "sgmii";
52
+
phy-handle = <&phy1>;
53
+
status = "okay";
54
+
55
+
phy1: ethernet-phy@5 {
56
+
reg = <5>;
57
+
ti,fifo-depth = <0x01>;
58
+
};
59
+
60
+
phy0: ethernet-phy@4 {
61
+
reg = <4>;
62
+
ti,fifo-depth = <0x01>;
63
+
};
64
+
};
65
+
66
+
&mbox {
67
+
status = "okay";
68
+
};
69
+
70
+
&mmc {
71
+
bus-width = <4>;
72
+
disable-wp;
73
+
cap-sd-highspeed;
74
+
cap-mmc-highspeed;
75
+
card-detect-delay = <200>;
76
+
mmc-ddr-1_8v;
77
+
mmc-hs200-1_8v;
78
+
sd-uhs-sdr12;
79
+
sd-uhs-sdr25;
80
+
sd-uhs-sdr50;
81
+
sd-uhs-sdr104;
82
+
status = "okay";
83
+
};
84
+
85
+
&mmuart0 {
86
+
status = "okay";
87
+
};
88
+
89
+
&refclk {
90
+
clock-frequency = <125000000>;
91
+
};
92
+
93
+
&rtc {
94
+
status = "okay";
95
+
};
96
+
97
+
&syscontroller {
98
+
status = "okay";
99
+
};
+2
-2
arch/riscv/include/asm/alternative-macros.h
+2
-2
arch/riscv/include/asm/alternative-macros.h
···
27
27
\new_c
28
28
.option pop
29
29
889 :
30
-
.previous
31
30
.org . - (889b - 888b) + (887b - 886b)
32
31
.org . - (887b - 886b) + (889b - 888b)
32
+
.previous
33
33
.endif
34
34
.endm
35
35
···
94
94
new_c "\n" \
95
95
".option pop\n" \
96
96
"889 :\n" \
97
-
".previous\n" \
98
97
".org . - (887b - 886b) + (889b - 888b)\n" \
99
98
".org . - (889b - 888b) + (887b - 886b)\n" \
99
+
".previous\n" \
100
100
".endif\n"
101
101
102
102
#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
+1
-1
arch/riscv/include/asm/irq_work.h
+1
-1
arch/riscv/include/asm/irq_work.h
-1
arch/riscv/include/asm/unistd.h
-1
arch/riscv/include/asm/unistd.h
+1
arch/riscv/include/uapi/asm/unistd.h
+1
arch/riscv/include/uapi/asm/unistd.h
+1
arch/riscv/kernel/head.S
+1
arch/riscv/kernel/head.S
+2
-2
arch/riscv/kernel/setup.c
+2
-2
arch/riscv/kernel/setup.c
···
190
190
res = &mem_res[res_idx--];
191
191
192
192
res->name = "Reserved";
193
-
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
193
+
res->flags = IORESOURCE_MEM | IORESOURCE_EXCLUSIVE;
194
194
res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));
195
195
res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;
196
196
···
215
215
216
216
if (unlikely(memblock_is_nomap(region))) {
217
217
res->name = "Reserved";
218
-
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
218
+
res->flags = IORESOURCE_MEM | IORESOURCE_EXCLUSIVE;
219
219
} else {
220
220
res->name = "System RAM";
221
221
res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
+54
-18
arch/riscv/mm/init.c
+54
-18
arch/riscv/mm/init.c
···
76
76
}
77
77
78
78
#if defined(CONFIG_MMU) && defined(CONFIG_DEBUG_VM)
79
+
80
+
#define LOG2_SZ_1K ilog2(SZ_1K)
81
+
#define LOG2_SZ_1M ilog2(SZ_1M)
82
+
#define LOG2_SZ_1G ilog2(SZ_1G)
83
+
#define LOG2_SZ_1T ilog2(SZ_1T)
84
+
79
85
static inline void print_mlk(char *name, unsigned long b, unsigned long t)
80
86
{
81
87
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld kB)\n", name, b, t,
82
-
(((t) - (b)) >> 10));
88
+
(((t) - (b)) >> LOG2_SZ_1K));
83
89
}
84
90
85
91
static inline void print_mlm(char *name, unsigned long b, unsigned long t)
86
92
{
87
93
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld MB)\n", name, b, t,
88
-
(((t) - (b)) >> 20));
94
+
(((t) - (b)) >> LOG2_SZ_1M));
95
+
}
96
+
97
+
static inline void print_mlg(char *name, unsigned long b, unsigned long t)
98
+
{
99
+
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld GB)\n", name, b, t,
100
+
(((t) - (b)) >> LOG2_SZ_1G));
101
+
}
102
+
103
+
#ifdef CONFIG_64BIT
104
+
static inline void print_mlt(char *name, unsigned long b, unsigned long t)
105
+
{
106
+
pr_notice("%12s : 0x%08lx - 0x%08lx (%4ld TB)\n", name, b, t,
107
+
(((t) - (b)) >> LOG2_SZ_1T));
108
+
}
109
+
#else
110
+
#define print_mlt(n, b, t) do {} while (0)
111
+
#endif
112
+
113
+
static inline void print_ml(char *name, unsigned long b, unsigned long t)
114
+
{
115
+
unsigned long diff = t - b;
116
+
117
+
if (IS_ENABLED(CONFIG_64BIT) && (diff >> LOG2_SZ_1T) >= 10)
118
+
print_mlt(name, b, t);
119
+
else if ((diff >> LOG2_SZ_1G) >= 10)
120
+
print_mlg(name, b, t);
121
+
else if ((diff >> LOG2_SZ_1M) >= 10)
122
+
print_mlm(name, b, t);
123
+
else
124
+
print_mlk(name, b, t);
89
125
}
90
126
91
127
static void __init print_vm_layout(void)
92
128
{
93
129
pr_notice("Virtual kernel memory layout:\n");
94
-
print_mlk("fixmap", (unsigned long)FIXADDR_START,
95
-
(unsigned long)FIXADDR_TOP);
96
-
print_mlm("pci io", (unsigned long)PCI_IO_START,
97
-
(unsigned long)PCI_IO_END);
98
-
print_mlm("vmemmap", (unsigned long)VMEMMAP_START,
99
-
(unsigned long)VMEMMAP_END);
100
-
print_mlm("vmalloc", (unsigned long)VMALLOC_START,
101
-
(unsigned long)VMALLOC_END);
102
-
print_mlm("lowmem", (unsigned long)PAGE_OFFSET,
103
-
(unsigned long)high_memory);
130
+
print_ml("fixmap", (unsigned long)FIXADDR_START,
131
+
(unsigned long)FIXADDR_TOP);
132
+
print_ml("pci io", (unsigned long)PCI_IO_START,
133
+
(unsigned long)PCI_IO_END);
134
+
print_ml("vmemmap", (unsigned long)VMEMMAP_START,
135
+
(unsigned long)VMEMMAP_END);
136
+
print_ml("vmalloc", (unsigned long)VMALLOC_START,
137
+
(unsigned long)VMALLOC_END);
138
+
print_ml("lowmem", (unsigned long)PAGE_OFFSET,
139
+
(unsigned long)high_memory);
104
140
if (IS_ENABLED(CONFIG_64BIT)) {
105
141
#ifdef CONFIG_KASAN
106
-
print_mlm("kasan", KASAN_SHADOW_START, KASAN_SHADOW_END);
142
+
print_ml("kasan", KASAN_SHADOW_START, KASAN_SHADOW_END);
107
143
#endif
108
144
109
-
print_mlm("kernel", (unsigned long)KERNEL_LINK_ADDR,
110
-
(unsigned long)ADDRESS_SPACE_END);
145
+
print_ml("kernel", (unsigned long)KERNEL_LINK_ADDR,
146
+
(unsigned long)ADDRESS_SPACE_END);
111
147
}
112
148
}
113
149
#else
···
879
843
* MMU is not enabled, the page tables are allocated directly using
880
844
* early_pmd/pud/p4d and the address returned is the physical one.
881
845
*/
882
-
void __init pt_ops_set_early(void)
846
+
static void __init pt_ops_set_early(void)
883
847
{
884
848
pt_ops.alloc_pte = alloc_pte_early;
885
849
pt_ops.get_pte_virt = get_pte_virt_early;
···
901
865
* Note that this is called with MMU disabled, hence kernel_mapping_pa_to_va,
902
866
* but it will be used as described above.
903
867
*/
904
-
void __init pt_ops_set_fixmap(void)
868
+
static void __init pt_ops_set_fixmap(void)
905
869
{
906
870
pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap);
907
871
pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap);
···
919
883
* MMU is enabled and page table setup is complete, so from now, we can use
920
884
* generic page allocation functions to setup page table.
921
885
*/
922
-
void __init pt_ops_set_late(void)
886
+
static void __init pt_ops_set_late(void)
923
887
{
924
888
pt_ops.alloc_pte = alloc_pte_late;
925
889
pt_ops.get_pte_virt = get_pte_virt_late;