EDAC/{skx_comm,imh}: Detect 2-level memory configuration

Detect 2-level memory configurations and notify the 'skx_common' library
to enable ADXL 2-level memory error decoding.

Tested-by: Yi Lai <[e-mail]>
Signed-off-by: Qiuxu Zhuo <[e-mail]>
Signed-off-by: Tony Luck <[e-mail]>
Link: https://patch.msgid.link/[e-mail]

drivers/edac/imh_base.c

···
 #define TOLM(reg)			(((u64)GET_BITFIELD(reg, 16, 31)) << 16)
 #define TOHM(reg)			(((u64)GET_BITFIELD(reg, 16, 51)) << 16)
 
+/* Home Agent (HA) */
+#define NMCACHING(reg)			GET_BITFIELD(reg, 8, 8)
+
 /**
  * struct local_reg - A register as described in the local package view.
  *
···
 	return 0;
 }
 
+static bool check_2lm_enabled(struct res_config *cfg, struct skx_dev *d, int ha_idx)
+{
+	DEFINE_LOCAL_REG(reg, cfg, d->pkg, true, ha, ha_idx, mode);
+
+	if (!read_local_reg(&reg))
+		return false;
+
+	if (!NMCACHING(reg.val))
+		return false;
+
+	edac_dbg(2, "2-level memory configuration (reg 0x%llx, ha idx %d)\n", reg.val, ha_idx);
+	return true;
+}
+
+/* Check whether the system has a 2-level memory configuration. */
+static bool imh_2lm_enabled(struct res_config *cfg, struct list_head *head)
+{
+	struct skx_dev *d;
+	int i;
+
+	list_for_each_entry(d, head, list) {
+		for (i = 0; i < cfg->ddr_imc_num; i++)
+			if (check_2lm_enabled(cfg, d, i))
+				return true;
+	}
+
+	return false;
+}
+
 /* Helpers to read memory controller registers */
 static u64 read_imc_reg(struct skx_imc *imc, int chan, u32 offset, u8 width)
 {
···
 	.sca_reg_tolm_width		= 8,
 	.sca_reg_tohm_offset		= 0x2108,
 	.sca_reg_tohm_width		= 8,
+	.ha_base			= 0x3eb000,
+	.ha_size			= 0x1000,
+	.ha_reg_mode_offset		= 0x4a0,
+	.ha_reg_mode_width		= 4,
 };
 
 static const struct x86_cpu_id imh_cpuids[] = {
···
 	rc = imh_get_munits(cfg, edac_list);
 	if (rc)
 		goto fail;
+
+	skx_set_mem_cfg(imh_2lm_enabled(cfg, edac_list));
 
 	rc = imh_register_mci(cfg, edac_list);
 	if (rc)

drivers/edac/skx_common.h

···
 			u8  sca_reg_tolm_width;
 			u32 sca_reg_tohm_offset;
 			u8  sca_reg_tohm_width;
+			u64 ha_base;
+			u32 ha_size;
+			u32 ha_reg_mode_offset;
+			u8  ha_reg_mode_width;
 		};
 	};
 };