Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: watermark latencies is not enough on DCN31

[Why]
The original latencies were causing underflow in some modes.
Resolution: 2880x1620@60p when HDR enable

[How]
1. Replace with the up-to-date watermark values based on new measurments
2. Correct the ddr_wm_table name to DDR5 on DCN31

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

authored by

Paul Hsieh and committed by
Alex Deucher
f5fa54f4 2d8ae25d

+10 -10
+10 -10
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
··· 329 329 330 330 }; 331 331 332 - static struct wm_table ddr4_wm_table = { 332 + static struct wm_table ddr5_wm_table = { 333 333 .entries = { 334 334 { 335 335 .wm_inst = WM_A, 336 336 .wm_type = WM_TYPE_PSTATE_CHG, 337 337 .pstate_latency_us = 11.72, 338 - .sr_exit_time_us = 6.09, 339 - .sr_enter_plus_exit_time_us = 7.14, 338 + .sr_exit_time_us = 9, 339 + .sr_enter_plus_exit_time_us = 11, 340 340 .valid = true, 341 341 }, 342 342 { 343 343 .wm_inst = WM_B, 344 344 .wm_type = WM_TYPE_PSTATE_CHG, 345 345 .pstate_latency_us = 11.72, 346 - .sr_exit_time_us = 10.12, 347 - .sr_enter_plus_exit_time_us = 11.48, 346 + .sr_exit_time_us = 9, 347 + .sr_enter_plus_exit_time_us = 11, 348 348 .valid = true, 349 349 }, 350 350 { 351 351 .wm_inst = WM_C, 352 352 .wm_type = WM_TYPE_PSTATE_CHG, 353 353 .pstate_latency_us = 11.72, 354 - .sr_exit_time_us = 10.12, 355 - .sr_enter_plus_exit_time_us = 11.48, 354 + .sr_exit_time_us = 9, 355 + .sr_enter_plus_exit_time_us = 11, 356 356 .valid = true, 357 357 }, 358 358 { 359 359 .wm_inst = WM_D, 360 360 .wm_type = WM_TYPE_PSTATE_CHG, 361 361 .pstate_latency_us = 11.72, 362 - .sr_exit_time_us = 10.12, 363 - .sr_enter_plus_exit_time_us = 11.48, 362 + .sr_exit_time_us = 9, 363 + .sr_enter_plus_exit_time_us = 11, 364 364 .valid = true, 365 365 }, 366 366 } ··· 687 687 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { 688 688 dcn31_bw_params.wm_table = lpddr5_wm_table; 689 689 } else { 690 - dcn31_bw_params.wm_table = ddr4_wm_table; 690 + dcn31_bw_params.wm_table = ddr5_wm_table; 691 691 } 692 692 /* Saved clocks configured at boot for debug purposes */ 693 693 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);