tjh.dev
+7
-1
arch/arm/Kconfig
+7
-1
arch/arm/Kconfig
···
1293
1293
1294
1294
config NR_CPUS
1295
1295
int "Maximum number of CPUs (2-32)"
1296
-
range 2 32
1296
+
range 2 16 if DEBUG_KMAP_LOCAL
1297
+
range 2 32 if !DEBUG_KMAP_LOCAL
1297
1298
depends on SMP
1298
1299
default "4"
1300
+
help
1301
+
The maximum number of CPUs that the kernel can support.
1302
+
Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1303
+
debugging is enabled, which uses half of the per-CPU fixmap
1304
+
slots as guard regions.
1299
1305
1300
1306
config HOTPLUG_CPU
1301
1307
bool "Support for hot-pluggable CPUs"
+2
-2
arch/arm/mach-footbridge/cats-pci.c
+2
-2
arch/arm/mach-footbridge/cats-pci.c
···
15
15
#include <asm/mach-types.h>
16
16
17
17
/* cats host-specific stuff */
18
-
static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
18
+
static int irqmap_cats[] = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
19
19
20
20
static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin)
21
21
{
22
22
return 0;
23
23
}
24
24
25
-
static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25
+
static int cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
26
26
{
27
27
if (dev->irq >= 255)
28
28
return -1; /* not a valid interrupt. */
+2
-2
arch/arm/mach-footbridge/ebsa285-pci.c
+2
-2
arch/arm/mach-footbridge/ebsa285-pci.c
···
14
14
#include <asm/mach/pci.h>
15
15
#include <asm/mach-types.h>
16
16
17
-
static int irqmap_ebsa285[] __initdata = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI };
17
+
static int irqmap_ebsa285[] = { IRQ_IN3, IRQ_IN1, IRQ_IN0, IRQ_PCI };
18
18
19
-
static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
19
+
static int ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
20
20
{
21
21
if (dev->vendor == PCI_VENDOR_ID_CONTAQ &&
22
22
dev->device == PCI_DEVICE_ID_CONTAQ_82C693)
+1
-1
arch/arm/mach-footbridge/netwinder-pci.c
+1
-1
arch/arm/mach-footbridge/netwinder-pci.c
···
18
18
* We now use the slot ID instead of the device identifiers to select
19
19
* which interrupt is routed where.
20
20
*/
21
-
static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
21
+
static int netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
22
22
{
23
23
switch (slot) {
24
24
case 0: /* host bridge */
+2
-3
arch/arm/mach-footbridge/personal-pci.c
+2
-3
arch/arm/mach-footbridge/personal-pci.c
···
14
14
#include <asm/mach/pci.h>
15
15
#include <asm/mach-types.h>
16
16
17
-
static int irqmap_personal_server[] __initdata = {
17
+
static int irqmap_personal_server[] = {
18
18
IRQ_IN0, IRQ_IN1, IRQ_IN2, IRQ_IN3, 0, 0, 0,
19
19
IRQ_DOORBELLHOST, IRQ_DMA1, IRQ_DMA2, IRQ_PCI
20
20
};
21
21
22
-
static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot,
23
-
u8 pin)
22
+
static int personal_server_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
24
23
{
25
24
unsigned char line;
26
25
+1
-2
arch/arm/mm/mmu.c
+1
-2
arch/arm/mm/mmu.c
···
387
387
pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
388
388
389
389
/* Make sure fixmap region does not exceed available allocation. */
390
-
BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
391
-
FIXADDR_END);
390
+
BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START);
392
391
BUG_ON(idx >= __end_of_fixed_addresses);
393
392
394
393
/* we only support device mappings until pgprot_kernel has been set */
+3
-1
arch/arm/mm/pmsa-v7.c
+3
-1
arch/arm/mm/pmsa-v7.c
···
235
235
phys_addr_t mem_end;
236
236
phys_addr_t reg_start, reg_end;
237
237
unsigned int mem_max_regions;
238
+
bool first = true;
238
239
int num;
239
240
u64 i;
240
241
···
264
263
#endif
265
264
266
265
for_each_mem_range(i, ®_start, ®_end) {
267
-
if (i == 0) {
266
+
if (first) {
268
267
phys_addr_t phys_offset = PHYS_OFFSET;
269
268
270
269
/*
···
276
275
mem_start = reg_start;
277
276
mem_end = reg_end;
278
277
specified_mem_size = mem_end - mem_start;
278
+
first = false;
279
279
} else {
280
280
/*
281
281
* memblock auto merges contiguous blocks, remove
+3
-1
arch/arm/mm/pmsa-v8.c
+3
-1
arch/arm/mm/pmsa-v8.c
···
95
95
{
96
96
phys_addr_t mem_end;
97
97
phys_addr_t reg_start, reg_end;
98
+
bool first = true;
98
99
u64 i;
99
100
100
101
for_each_mem_range(i, ®_start, ®_end) {
101
-
if (i == 0) {
102
+
if (first) {
102
103
phys_addr_t phys_offset = PHYS_OFFSET;
103
104
104
105
/*
···
108
107
if (reg_start != phys_offset)
109
108
panic("First memory bank must be contiguous from PHYS_OFFSET");
110
109
mem_end = reg_end;
110
+
first = false;
111
111
} else {
112
112
/*
113
113
* memblock auto merges contiguous blocks, remove
+2
-2
arch/arm/probes/uprobes/core.c
+2
-2
arch/arm/probes/uprobes/core.c
···
204
204
static struct undef_hook uprobes_arm_break_hook = {
205
205
.instr_mask = 0x0fffffff,
206
206
.instr_val = (UPROBE_SWBP_ARM_INSN & 0x0fffffff),
207
-
.cpsr_mask = MODE_MASK,
207
+
.cpsr_mask = (PSR_T_BIT | MODE_MASK),
208
208
.cpsr_val = USR_MODE,
209
209
.fn = uprobe_trap_handler,
210
210
};
···
212
212
static struct undef_hook uprobes_arm_ss_hook = {
213
213
.instr_mask = 0x0fffffff,
214
214
.instr_val = (UPROBE_SS_ARM_INSN & 0x0fffffff),
215
-
.cpsr_mask = MODE_MASK,
215
+
.cpsr_mask = (PSR_T_BIT | MODE_MASK),
216
216
.cpsr_val = USR_MODE,
217
217
.fn = uprobe_trap_handler,
218
218
};