dt-bindings: firmware: imx: sync with SCFW kit v1.13.0

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Sync defines with the latest available SCFW kit version 1.13.0,
may be found at the address below:

https://www.nxp.com/webapp/Download?colCode=L5.15.32_2.0.0_SCFWKIT-1.13.0&appType=license

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

authored by

Viorel Suman and committed by

Shawn Guo 3 years ago f5798ced 9abf2313

+206 -96

1 changed file

expand all

include

dt-bindings

firmware

imx

rsrc.h

+206 -96

include/dt-bindings/firmware/imx/rsrc.h

··· 13 13 * never be changed or removed (only added to at the end of the list). 14 14 */ 15 15 16 - #define IMX_SC_R_A53 0 17 - #define IMX_SC_R_A53_0 1 18 - #define IMX_SC_R_A53_1 2 19 - #define IMX_SC_R_A53_2 3 20 - #define IMX_SC_R_A53_3 4 21 - #define IMX_SC_R_A72 5 22 - #define IMX_SC_R_A72_0 6 23 - #define IMX_SC_R_A72_1 7 24 - #define IMX_SC_R_A72_2 8 25 - #define IMX_SC_R_A72_3 9 16 + #define IMX_SC_R_AP_0 0 17 + #define IMX_SC_R_AP_0_0 1 18 + #define IMX_SC_R_AP_0_1 2 19 + #define IMX_SC_R_AP_0_2 3 20 + #define IMX_SC_R_AP_0_3 4 21 + #define IMX_SC_R_AP_1 5 22 + #define IMX_SC_R_AP_1_0 6 23 + #define IMX_SC_R_AP_1_1 7 24 + #define IMX_SC_R_AP_1_2 8 25 + #define IMX_SC_R_AP_1_3 9 26 26 #define IMX_SC_R_CCI 10 27 27 #define IMX_SC_R_DB 11 28 28 #define IMX_SC_R_DRC_0 12 29 29 #define IMX_SC_R_DRC_1 13 30 30 #define IMX_SC_R_GIC_SMMU 14 31 - #define IMX_SC_R_IRQSTR_M4_0 15 32 - #define IMX_SC_R_IRQSTR_M4_1 16 33 - #define IMX_SC_R_SMMU 17 34 - #define IMX_SC_R_GIC 18 31 + #define IMX_SC_R_IRQSTR_MCU_0 15 32 + #define IMX_SC_R_IRQSTR_MCU_1 16 33 + #define IMX_SC_R_SMMU_0 17 34 + #define IMX_SC_R_GIC_0 18 35 35 #define IMX_SC_R_DC_0_BLIT0 19 36 36 #define IMX_SC_R_DC_0_BLIT1 20 37 37 #define IMX_SC_R_DC_0_BLIT2 21 38 38 #define IMX_SC_R_DC_0_BLIT_OUT 22 39 - #define IMX_SC_R_PERF 23 39 + #define IMX_SC_R_PERF_0 23 40 40 #define IMX_SC_R_USB_1_PHY 24 41 41 #define IMX_SC_R_DC_0_WARP 25 42 42 #define IMX_SC_R_V2X_MU_0 26 ··· 56 56 #define IMX_SC_R_V2X_MU_3 40 57 57 #define IMX_SC_R_V2X_MU_4 41 58 58 #define IMX_SC_R_DC_1_WARP 42 59 + #define IMX_SC_R_STM 43 59 60 #define IMX_SC_R_SECVIO 44 60 61 #define IMX_SC_R_DC_1_VIDEO0 45 61 62 #define IMX_SC_R_DC_1_VIDEO1 46 62 63 #define IMX_SC_R_DC_1_FRAC0 47 64 + #define IMX_SC_R_V2X 48 63 65 #define IMX_SC_R_DC_1 49 66 + #define IMX_SC_R_UNUSED14 50 64 67 #define IMX_SC_R_DC_1_PLL_0 51 65 68 #define IMX_SC_R_DC_1_PLL_1 52 66 69 #define IMX_SC_R_SPI_0 53 ··· 154 151 #define IMX_SC_R_DMA_1_CH29 137 155 152 #define IMX_SC_R_DMA_1_CH30 138 156 153 #define IMX_SC_R_DMA_1_CH31 139 157 - #define IMX_SC_R_UNUSED1 140 158 - #define IMX_SC_R_UNUSED2 141 159 - #define IMX_SC_R_UNUSED3 142 160 - #define IMX_SC_R_UNUSED4 143 154 + #define IMX_SC_R_V2X_PID0 140 155 + #define IMX_SC_R_V2X_PID1 141 156 + #define IMX_SC_R_V2X_PID2 142 157 + #define IMX_SC_R_V2X_PID3 143 161 158 #define IMX_SC_R_GPU_0_PID0 144 162 159 #define IMX_SC_R_GPU_0_PID1 145 163 160 #define IMX_SC_R_GPU_0_PID2 146 ··· 186 183 #define IMX_SC_R_PCIE_B 169 187 184 #define IMX_SC_R_SATA_0 170 188 185 #define IMX_SC_R_SERDES_1 171 189 - #define IMX_SC_R_HSIO_GPIO 172 186 + #define IMX_SC_R_HSIO_GPIO_0 172 190 187 #define IMX_SC_R_MATCH_15 173 191 188 #define IMX_SC_R_MATCH_16 174 192 189 #define IMX_SC_R_MATCH_17 175 ··· 253 250 #define IMX_SC_R_ROM_0 236 254 251 #define IMX_SC_R_FSPI_0 237 255 252 #define IMX_SC_R_FSPI_1 238 256 - #define IMX_SC_R_IEE 239 257 - #define IMX_SC_R_IEE_R0 240 258 - #define IMX_SC_R_IEE_R1 241 259 - #define IMX_SC_R_IEE_R2 242 260 - #define IMX_SC_R_IEE_R3 243 261 - #define IMX_SC_R_IEE_R4 244 262 - #define IMX_SC_R_IEE_R5 245 263 - #define IMX_SC_R_IEE_R6 246 264 - #define IMX_SC_R_IEE_R7 247 253 + #define IMX_SC_R_IEE_0 239 254 + #define IMX_SC_R_IEE_0_R0 240 255 + #define IMX_SC_R_IEE_0_R1 241 256 + #define IMX_SC_R_IEE_0_R2 242 257 + #define IMX_SC_R_IEE_0_R3 243 258 + #define IMX_SC_R_IEE_0_R4 244 259 + #define IMX_SC_R_IEE_0_R5 245 260 + #define IMX_SC_R_IEE_0_R6 246 261 + #define IMX_SC_R_IEE_0_R7 247 265 262 #define IMX_SC_R_SDHC_0 248 266 263 #define IMX_SC_R_SDHC_1 249 267 264 #define IMX_SC_R_SDHC_2 250 ··· 292 289 #define IMX_SC_R_LVDS_2_PWM_0 275 293 290 #define IMX_SC_R_LVDS_2_I2C_0 276 294 291 #define IMX_SC_R_LVDS_2_I2C_1 277 295 - #define IMX_SC_R_M4_0_PID0 278 296 - #define IMX_SC_R_M4_0_PID1 279 297 - #define IMX_SC_R_M4_0_PID2 280 298 - #define IMX_SC_R_M4_0_PID3 281 299 - #define IMX_SC_R_M4_0_PID4 282 300 - #define IMX_SC_R_M4_0_RGPIO 283 301 - #define IMX_SC_R_M4_0_SEMA42 284 302 - #define IMX_SC_R_M4_0_TPM 285 303 - #define IMX_SC_R_M4_0_PIT 286 304 - #define IMX_SC_R_M4_0_UART 287 305 - #define IMX_SC_R_M4_0_I2C 288 306 - #define IMX_SC_R_M4_0_INTMUX 289 307 - #define IMX_SC_R_M4_0_MU_0B 292 308 - #define IMX_SC_R_M4_0_MU_0A0 293 309 - #define IMX_SC_R_M4_0_MU_0A1 294 310 - #define IMX_SC_R_M4_0_MU_0A2 295 311 - #define IMX_SC_R_M4_0_MU_0A3 296 312 - #define IMX_SC_R_M4_0_MU_1A 297 313 - #define IMX_SC_R_M4_1_PID0 298 314 - #define IMX_SC_R_M4_1_PID1 299 315 - #define IMX_SC_R_M4_1_PID2 300 316 - #define IMX_SC_R_M4_1_PID3 301 317 - #define IMX_SC_R_M4_1_PID4 302 318 - #define IMX_SC_R_M4_1_RGPIO 303 319 - #define IMX_SC_R_M4_1_SEMA42 304 320 - #define IMX_SC_R_M4_1_TPM 305 321 - #define IMX_SC_R_M4_1_PIT 306 322 - #define IMX_SC_R_M4_1_UART 307 323 - #define IMX_SC_R_M4_1_I2C 308 324 - #define IMX_SC_R_M4_1_INTMUX 309 325 - #define IMX_SC_R_M4_1_MU_0B 312 326 - #define IMX_SC_R_M4_1_MU_0A0 313 327 - #define IMX_SC_R_M4_1_MU_0A1 314 328 - #define IMX_SC_R_M4_1_MU_0A2 315 329 - #define IMX_SC_R_M4_1_MU_0A3 316 330 - #define IMX_SC_R_M4_1_MU_1A 317 292 + #define IMX_SC_R_MCU_0_PID0 278 293 + #define IMX_SC_R_MCU_0_PID1 279 294 + #define IMX_SC_R_MCU_0_PID2 280 295 + #define IMX_SC_R_MCU_0_PID3 281 296 + #define IMX_SC_R_MCU_0_PID4 282 297 + #define IMX_SC_R_MCU_0_RGPIO 283 298 + #define IMX_SC_R_MCU_0_SEMA42 284 299 + #define IMX_SC_R_MCU_0_TPM 285 300 + #define IMX_SC_R_MCU_0_PIT 286 301 + #define IMX_SC_R_MCU_0_UART 287 302 + #define IMX_SC_R_MCU_0_I2C 288 303 + #define IMX_SC_R_MCU_0_INTMUX 289 304 + #define IMX_SC_R_ENET_0_A0 290 305 + #define IMX_SC_R_ENET_0_A1 291 306 + #define IMX_SC_R_MCU_0_MU_0B 292 307 + #define IMX_SC_R_MCU_0_MU_0A0 293 308 + #define IMX_SC_R_MCU_0_MU_0A1 294 309 + #define IMX_SC_R_MCU_0_MU_0A2 295 310 + #define IMX_SC_R_MCU_0_MU_0A3 296 311 + #define IMX_SC_R_MCU_0_MU_1A 297 312 + #define IMX_SC_R_MCU_1_PID0 298 313 + #define IMX_SC_R_MCU_1_PID1 299 314 + #define IMX_SC_R_MCU_1_PID2 300 315 + #define IMX_SC_R_MCU_1_PID3 301 316 + #define IMX_SC_R_MCU_1_PID4 302 317 + #define IMX_SC_R_MCU_1_RGPIO 303 318 + #define IMX_SC_R_MCU_1_SEMA42 304 319 + #define IMX_SC_R_MCU_1_TPM 305 320 + #define IMX_SC_R_MCU_1_PIT 306 321 + #define IMX_SC_R_MCU_1_UART 307 322 + #define IMX_SC_R_MCU_1_I2C 308 323 + #define IMX_SC_R_MCU_1_INTMUX 309 324 + #define IMX_SC_R_UNUSED17 310 325 + #define IMX_SC_R_UNUSED18 311 326 + #define IMX_SC_R_MCU_1_MU_0B 312 327 + #define IMX_SC_R_MCU_1_MU_0A0 313 328 + #define IMX_SC_R_MCU_1_MU_0A1 314 329 + #define IMX_SC_R_MCU_1_MU_0A2 315 330 + #define IMX_SC_R_MCU_1_MU_0A3 316 331 + #define IMX_SC_R_MCU_1_MU_1A 317 331 332 #define IMX_SC_R_SAI_0 318 332 333 #define IMX_SC_R_SAI_1 319 333 334 #define IMX_SC_R_SAI_2 320 334 - #define IMX_SC_R_IRQSTR_SCU2 321 335 + #define IMX_SC_R_IRQSTR_AP_0 321 335 336 #define IMX_SC_R_IRQSTR_DSP 322 336 337 #define IMX_SC_R_ELCDIF_PLL 323 337 338 #define IMX_SC_R_OCRAM 324 ··· 380 373 #define IMX_SC_R_VPU_PID5 363 381 374 #define IMX_SC_R_VPU_PID6 364 382 375 #define IMX_SC_R_VPU_PID7 365 383 - #define IMX_SC_R_VPU_UART 366 384 - #define IMX_SC_R_VPUCORE 367 385 - #define IMX_SC_R_VPUCORE_0 368 386 - #define IMX_SC_R_VPUCORE_1 369 387 - #define IMX_SC_R_VPUCORE_2 370 388 - #define IMX_SC_R_VPUCORE_3 371 376 + #define IMX_SC_R_ENET_0_A2 366 377 + #define IMX_SC_R_ENET_1_A0 367 378 + #define IMX_SC_R_ENET_1_A1 368 379 + #define IMX_SC_R_ENET_1_A2 369 380 + #define IMX_SC_R_ENET_1_A3 370 381 + #define IMX_SC_R_ENET_1_A4 371 389 382 #define IMX_SC_R_DMA_4_CH0 372 390 383 #define IMX_SC_R_DMA_4_CH1 373 391 384 #define IMX_SC_R_DMA_4_CH2 374 392 385 #define IMX_SC_R_DMA_4_CH3 375 393 386 #define IMX_SC_R_DMA_4_CH4 376 394 - #define IMX_SC_R_ISI_CH0 377 395 - #define IMX_SC_R_ISI_CH1 378 396 - #define IMX_SC_R_ISI_CH2 379 397 - #define IMX_SC_R_ISI_CH3 380 398 - #define IMX_SC_R_ISI_CH4 381 399 - #define IMX_SC_R_ISI_CH5 382 400 - #define IMX_SC_R_ISI_CH6 383 401 - #define IMX_SC_R_ISI_CH7 384 402 - #define IMX_SC_R_MJPEG_DEC_S0 385 403 - #define IMX_SC_R_MJPEG_DEC_S1 386 404 - #define IMX_SC_R_MJPEG_DEC_S2 387 405 - #define IMX_SC_R_MJPEG_DEC_S3 388 406 - #define IMX_SC_R_MJPEG_ENC_S0 389 407 - #define IMX_SC_R_MJPEG_ENC_S1 390 408 - #define IMX_SC_R_MJPEG_ENC_S2 391 409 - #define IMX_SC_R_MJPEG_ENC_S3 392 387 + #define IMX_SC_R_ISI_0_CH0 377 388 + #define IMX_SC_R_ISI_0_CH1 378 389 + #define IMX_SC_R_ISI_0_CH2 379 390 + #define IMX_SC_R_ISI_0_CH3 380 391 + #define IMX_SC_R_ISI_0_CH4 381 392 + #define IMX_SC_R_ISI_0_CH5 382 393 + #define IMX_SC_R_ISI_0_CH6 383 394 + #define IMX_SC_R_ISI_0_CH7 384 395 + #define IMX_SC_R_MJPEG_0_DEC_S0 385 396 + #define IMX_SC_R_MJPEG_0_DEC_S1 386 397 + #define IMX_SC_R_MJPEG_0_DEC_S2 387 398 + #define IMX_SC_R_MJPEG_0_DEC_S3 388 399 + #define IMX_SC_R_MJPEG_0_ENC_S0 389 400 + #define IMX_SC_R_MJPEG_0_ENC_S1 390 401 + #define IMX_SC_R_MJPEG_0_ENC_S2 391 402 + #define IMX_SC_R_MJPEG_0_ENC_S3 392 410 403 #define IMX_SC_R_MIPI_0 393 411 404 #define IMX_SC_R_MIPI_0_PWM_0 394 412 405 #define IMX_SC_R_MIPI_0_I2C_0 395 ··· 521 514 #define IMX_SC_R_SECO_MU_3 504 522 515 #define IMX_SC_R_SECO_MU_4 505 523 516 #define IMX_SC_R_HDMI_RX_PWM_0 506 524 - #define IMX_SC_R_A35 507 525 - #define IMX_SC_R_A35_0 508 526 - #define IMX_SC_R_A35_1 509 527 - #define IMX_SC_R_A35_2 510 528 - #define IMX_SC_R_A35_3 511 517 + #define IMX_SC_R_AP_2 507 518 + #define IMX_SC_R_AP_2_0 508 519 + #define IMX_SC_R_AP_2_1 509 520 + #define IMX_SC_R_AP_2_2 510 521 + #define IMX_SC_R_AP_2_3 511 529 522 #define IMX_SC_R_DSP 512 530 523 #define IMX_SC_R_DSP_RAM 513 531 524 #define IMX_SC_R_CAAM_JR1_OUT 514 ··· 546 539 #define IMX_SC_R_BOARD_R5 529 547 540 #define IMX_SC_R_BOARD_R6 530 548 541 #define IMX_SC_R_BOARD_R7 531 549 - #define IMX_SC_R_MJPEG_DEC_MP 532 550 - #define IMX_SC_R_MJPEG_ENC_MP 533 542 + #define IMX_SC_R_MJPEG_0_DEC_MP 532 543 + #define IMX_SC_R_MJPEG_0_ENC_MP 533 551 544 #define IMX_SC_R_VPU_TS_0 534 552 545 #define IMX_SC_R_VPU_MU_0 535 553 546 #define IMX_SC_R_VPU_MU_1 536 ··· 578 571 #define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ 579 572 #define IMX_SC_PM_CLK_PLL 4 /* PLL */ 580 573 #define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ 574 + 575 + /* 576 + * Compatibility defines for sc_rsrc_t 577 + */ 578 + #define IMX_SC_R_A35 IMX_SC_R_AP_2 579 + #define IMX_SC_R_A35_0 IMX_SC_R_AP_2_0 580 + #define IMX_SC_R_A35_1 IMX_SC_R_AP_2_1 581 + #define IMX_SC_R_A35_2 IMX_SC_R_AP_2_2 582 + #define IMX_SC_R_A35_3 IMX_SC_R_AP_2_3 583 + #define IMX_SC_R_A53 IMX_SC_R_AP_0 584 + #define IMX_SC_R_A53_0 IMX_SC_R_AP_0_0 585 + #define IMX_SC_R_A53_1 IMX_SC_R_AP_0_1 586 + #define IMX_SC_R_A53_2 IMX_SC_R_AP_0_2 587 + #define IMX_SC_R_A53_3 IMX_SC_R_AP_0_3 588 + #define IMX_SC_R_A72 IMX_SC_R_AP_1 589 + #define IMX_SC_R_A72_0 IMX_SC_R_AP_1_0 590 + #define IMX_SC_R_A72_1 IMX_SC_R_AP_1_1 591 + #define IMX_SC_R_A72_2 IMX_SC_R_AP_1_2 592 + #define IMX_SC_R_A72_3 IMX_SC_R_AP_1_3 593 + #define IMX_SC_R_GIC IMX_SC_R_GIC_0 594 + #define IMX_SC_R_HSIO_GPIO IMX_SC_R_HSIO_GPIO_0 595 + #define IMX_SC_R_IEE IMX_SC_R_IEE_0 596 + #define IMX_SC_R_IEE_R0 IMX_SC_R_IEE_0_R0 597 + #define IMX_SC_R_IEE_R1 IMX_SC_R_IEE_0_R1 598 + #define IMX_SC_R_IEE_R2 IMX_SC_R_IEE_0_R2 599 + #define IMX_SC_R_IEE_R3 IMX_SC_R_IEE_0_R3 600 + #define IMX_SC_R_IEE_R4 IMX_SC_R_IEE_0_R4 601 + #define IMX_SC_R_IEE_R5 IMX_SC_R_IEE_0_R5 602 + #define IMX_SC_R_IEE_R6 IMX_SC_R_IEE_0_R6 603 + #define IMX_SC_R_IEE_R7 IMX_SC_R_IEE_0_R7 604 + #define IMX_SC_R_IRQSTR_M4_0 IMX_SC_R_IRQSTR_MCU_0 605 + #define IMX_SC_R_IRQSTR_M4_1 IMX_SC_R_IRQSTR_MCU_1 606 + #define IMX_SC_R_IRQSTR_SCU2 IMX_SC_R_IRQSTR_AP_0 607 + #define IMX_SC_R_ISI_CH0 IMX_SC_R_ISI_0_CH0 608 + #define IMX_SC_R_ISI_CH1 IMX_SC_R_ISI_0_CH1 609 + #define IMX_SC_R_ISI_CH2 IMX_SC_R_ISI_0_CH2 610 + #define IMX_SC_R_ISI_CH3 IMX_SC_R_ISI_0_CH3 611 + #define IMX_SC_R_ISI_CH4 IMX_SC_R_ISI_0_CH4 612 + #define IMX_SC_R_ISI_CH5 IMX_SC_R_ISI_0_CH5 613 + #define IMX_SC_R_ISI_CH6 IMX_SC_R_ISI_0_CH6 614 + #define IMX_SC_R_ISI_CH7 IMX_SC_R_ISI_0_CH7 615 + #define IMX_SC_R_M4_0_I2C IMX_SC_R_MCU_0_I2C 616 + #define IMX_SC_R_M4_0_INTMUX IMX_SC_R_MCU_0_INTMUX 617 + #define IMX_SC_R_M4_0_MU_0A0 IMX_SC_R_MCU_0_MU_0A0 618 + #define IMX_SC_R_M4_0_MU_0A1 IMX_SC_R_MCU_0_MU_0A1 619 + #define IMX_SC_R_M4_0_MU_0A2 IMX_SC_R_MCU_0_MU_0A2 620 + #define IMX_SC_R_M4_0_MU_0A3 IMX_SC_R_MCU_0_MU_0A3 621 + #define IMX_SC_R_M4_0_MU_0B IMX_SC_R_MCU_0_MU_0B 622 + #define IMX_SC_R_M4_0_MU_1A IMX_SC_R_MCU_0_MU_1A 623 + #define IMX_SC_R_M4_0_PID0 IMX_SC_R_MCU_0_PID0 624 + #define IMX_SC_R_M4_0_PID1 IMX_SC_R_MCU_0_PID1 625 + #define IMX_SC_R_M4_0_PID2 IMX_SC_R_MCU_0_PID2 626 + #define IMX_SC_R_M4_0_PID3 IMX_SC_R_MCU_0_PID3 627 + #define IMX_SC_R_M4_0_PID4 IMX_SC_R_MCU_0_PID4 628 + #define IMX_SC_R_M4_0_PIT IMX_SC_R_MCU_0_PIT 629 + #define IMX_SC_R_M4_0_RGPIO IMX_SC_R_MCU_0_RGPIO 630 + #define IMX_SC_R_M4_0_SEMA42 IMX_SC_R_MCU_0_SEMA42 631 + #define IMX_SC_R_M4_0_TPM IMX_SC_R_MCU_0_TPM 632 + #define IMX_SC_R_M4_0_UART IMX_SC_R_MCU_0_UART 633 + #define IMX_SC_R_M4_1_I2C IMX_SC_R_MCU_1_I2C 634 + #define IMX_SC_R_M4_1_INTMUX IMX_SC_R_MCU_1_INTMUX 635 + #define IMX_SC_R_M4_1_MU_0A0 IMX_SC_R_MCU_1_MU_0A0 636 + #define IMX_SC_R_M4_1_MU_0A1 IMX_SC_R_MCU_1_MU_0A1 637 + #define IMX_SC_R_M4_1_MU_0A2 IMX_SC_R_MCU_1_MU_0A2 638 + #define IMX_SC_R_M4_1_MU_0A3 IMX_SC_R_MCU_1_MU_0A3 639 + #define IMX_SC_R_M4_1_MU_0B IMX_SC_R_MCU_1_MU_0B 640 + #define IMX_SC_R_M4_1_MU_1A IMX_SC_R_MCU_1_MU_1A 641 + #define IMX_SC_R_M4_1_PID0 IMX_SC_R_MCU_1_PID0 642 + #define IMX_SC_R_M4_1_PID1 IMX_SC_R_MCU_1_PID1 643 + #define IMX_SC_R_M4_1_PID2 IMX_SC_R_MCU_1_PID2 644 + #define IMX_SC_R_M4_1_PID3 IMX_SC_R_MCU_1_PID3 645 + #define IMX_SC_R_M4_1_PID4 IMX_SC_R_MCU_1_PID4 646 + #define IMX_SC_R_M4_1_PIT IMX_SC_R_MCU_1_PIT 647 + #define IMX_SC_R_M4_1_RGPIO IMX_SC_R_MCU_1_RGPIO 648 + #define IMX_SC_R_M4_1_SEMA42 IMX_SC_R_MCU_1_SEMA42 649 + #define IMX_SC_R_M4_1_TPM IMX_SC_R_MCU_1_TPM 650 + #define IMX_SC_R_M4_1_UART IMX_SC_R_MCU_1_UART 651 + #define IMX_SC_R_MJPEG_DEC_MP IMX_SC_R_MJPEG_0_DEC_MP 652 + #define IMX_SC_R_MJPEG_DEC_S0 IMX_SC_R_MJPEG_0_DEC_S0 653 + #define IMX_SC_R_MJPEG_DEC_S1 IMX_SC_R_MJPEG_0_DEC_S1 654 + #define IMX_SC_R_MJPEG_DEC_S2 IMX_SC_R_MJPEG_0_DEC_S2 655 + #define IMX_SC_R_MJPEG_DEC_S3 IMX_SC_R_MJPEG_0_DEC_S3 656 + #define IMX_SC_R_MJPEG_ENC_MP IMX_SC_R_MJPEG_0_ENC_MP 657 + #define IMX_SC_R_MJPEG_ENC_S0 IMX_SC_R_MJPEG_0_ENC_S0 658 + #define IMX_SC_R_MJPEG_ENC_S1 IMX_SC_R_MJPEG_0_ENC_S1 659 + #define IMX_SC_R_MJPEG_ENC_S2 IMX_SC_R_MJPEG_0_ENC_S2 660 + #define IMX_SC_R_MJPEG_ENC_S3 IMX_SC_R_MJPEG_0_ENC_S3 661 + #define IMX_SC_R_PERF IMX_SC_R_PERF_0 662 + #define IMX_SC_R_SMMU IMX_SC_R_SMMU_0 663 + #define IMX_SC_R_VPU_UART IMX_SC_R_ENET_0_A2 664 + #define IMX_SC_R_VPUCORE IMX_SC_R_ENET_1_A0 665 + #define IMX_SC_R_VPUCORE_0 IMX_SC_R_ENET_1_A1 666 + #define IMX_SC_R_VPUCORE_1 IMX_SC_R_ENET_1_A2 667 + #define IMX_SC_R_VPUCORE_2 IMX_SC_R_ENET_1_A3 668 + #define IMX_SC_R_VPUCORE_3 IMX_SC_R_ENET_1_A4 669 + #define IMX_SC_R_UNUSED1 IMX_SC_R_V2X_PID0 670 + #define IMX_SC_R_UNUSED2 IMX_SC_R_V2X_PID1 671 + #define IMX_SC_R_UNUSED3 IMX_SC_R_V2X_PID2 672 + #define IMX_SC_R_UNUSED4 IMX_SC_R_V2X_PID3 581 673 582 674 /* 583 675 * Defines for SC CONTROL ··· 743 637 #define IMX_SC_C_INTF_SEL 59 744 638 #define IMX_SC_C_RXC_DLY 60 745 639 #define IMX_SC_C_TIMER_SEL 61 746 - #define IMX_SC_C_LAST 62 640 + #define IMX_SC_C_MISC0 62 641 + #define IMX_SC_C_MISC1 63 642 + #define IMX_SC_C_MISC2 64 643 + #define IMX_SC_C_MISC3 65 644 + #define IMX_SC_C_LAST 66 747 645 748 646 #endif /* __DT_BINDINGS_RSCRC_IMX_H */