tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
MIPS: ralink: cleanup the soc specific pinmux data
Before we had a pinctrl driver we used a custom OF api. This patch converts the
soc specific pinmux data to a new set of structs. We also add some new pinmux
setings.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/8009/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
authored by
John Crispin
and committed by
Ralf Baechle
f576fb6a
4248f7f1
+294
-420
+30
-11
arch/mips/include/asm/mach-ralink/mt7620.h
+30
-11
arch/mips/include/asm/mach-ralink/mt7620.h
···
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#define MT7620_DDR2_SIZE_MIN 32
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#define MT7620_DDR2_SIZE_MAX 256
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-
#define MT7620_GPIO_MODE_I2C BIT(0)
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#define MT7620_GPIO_MODE_UART0_SHIFT 2
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#define MT7620_GPIO_MODE_UART0_MASK 0x7
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#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
···
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#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
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#define MT7620_GPIO_MODE_GPIO_I2S 0x6
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#define MT7620_GPIO_MODE_GPIO 0x7
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-
#define MT7620_GPIO_MODE_UART1 BIT(5)
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#define MT7620_GPIO_MODE_MDIO BIT(8)
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#define MT7620_GPIO_MODE_RGMII1 BIT(9)
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#define MT7620_GPIO_MODE_RGMII2 BIT(10)
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#define MT7620_GPIO_MODE_SPI BIT(11)
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#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
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#define MT7620_GPIO_MODE_WLED BIT(13)
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#define MT7620_GPIO_MODE_JTAG BIT(15)
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#define MT7620_GPIO_MODE_EPHY BIT(15)
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#define MT7620_GPIO_MODE_WDT BIT(22)
97
+
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#define MT7620_GPIO_MODE_NAND 0
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#define MT7620_GPIO_MODE_SD 1
100
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#define MT7620_GPIO_MODE_ND_SD_GPIO 2
101
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#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
102
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#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
103
+
104
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#define MT7620_GPIO_MODE_PCIE_RST 0
105
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#define MT7620_GPIO_MODE_PCIE_REF 1
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#define MT7620_GPIO_MODE_PCIE_GPIO 2
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#define MT7620_GPIO_MODE_PCIE_MASK 0x3
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#define MT7620_GPIO_MODE_PCIE_SHIFT 16
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+
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#define MT7620_GPIO_MODE_WDT_RST 0
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#define MT7620_GPIO_MODE_WDT_REF 1
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#define MT7620_GPIO_MODE_WDT_GPIO 2
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#define MT7620_GPIO_MODE_WDT_MASK 0x3
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#define MT7620_GPIO_MODE_WDT_SHIFT 21
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+
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#define MT7620_GPIO_MODE_I2C 0
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#define MT7620_GPIO_MODE_UART1 5
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#define MT7620_GPIO_MODE_MDIO 8
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#define MT7620_GPIO_MODE_RGMII1 9
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#define MT7620_GPIO_MODE_RGMII2 10
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#define MT7620_GPIO_MODE_SPI 11
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#define MT7620_GPIO_MODE_SPI_REF_CLK 12
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#define MT7620_GPIO_MODE_WLED 13
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#define MT7620_GPIO_MODE_JTAG 15
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#define MT7620_GPIO_MODE_EPHY 15
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#define MT7620_GPIO_MODE_PA 20
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static inline int mt7620_get_eco(void)
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129
{
+55
arch/mips/include/asm/mach-ralink/pinmux.h
+55
arch/mips/include/asm/mach-ralink/pinmux.h
···
1
+
/*
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+
* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*
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* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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*/
8
+
9
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#ifndef _RT288X_PINMUX_H__
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#define _RT288X_PINMUX_H__
11
+
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#define FUNC(name, value, pin_first, pin_count) \
13
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{ name, value, pin_first, pin_count }
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+
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#define GRP(_name, _func, _mask, _shift) \
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{ .name = _name, .mask = _mask, .shift = _shift, \
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.func = _func, .gpio = _mask, \
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.func_count = ARRAY_SIZE(_func) }
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+
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#define GRP_G(_name, _func, _mask, _gpio, _shift) \
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{ .name = _name, .mask = _mask, .shift = _shift, \
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.func = _func, .gpio = _gpio, \
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.func_count = ARRAY_SIZE(_func) }
24
+
25
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struct rt2880_pmx_group;
26
+
27
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struct rt2880_pmx_func {
28
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const char *name;
29
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const char value;
30
+
31
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int pin_first;
32
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int pin_count;
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int *pins;
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+
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int *groups;
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int group_count;
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+
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int enabled;
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};
40
+
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struct rt2880_pmx_group {
42
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const char *name;
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int enabled;
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+
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const u32 shift;
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const char mask;
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const char gpio;
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+
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struct rt2880_pmx_func *func;
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int func_count;
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};
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+
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extern struct rt2880_pmx_group *rt2880_pinmux_data;
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+
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#endif
+20
-15
arch/mips/include/asm/mach-ralink/rt305x.h
+20
-15
arch/mips/include/asm/mach-ralink/rt305x.h
···
125
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#define RT305X_GPIO_GE0_TXD0 40
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#define RT305X_GPIO_GE0_RXCLK 51
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-
#define RT305X_GPIO_MODE_I2C BIT(0)
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#define RT305X_GPIO_MODE_SPI BIT(1)
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128
#define RT305X_GPIO_MODE_UART0_SHIFT 2
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#define RT305X_GPIO_MODE_UART0_MASK 0x7
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#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
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#define RT305X_GPIO_MODE_UARTF 0x0
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#define RT305X_GPIO_MODE_PCM_UARTF 0x1
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#define RT305X_GPIO_MODE_PCM_I2S 0x2
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#define RT305X_GPIO_MODE_I2S_UARTF 0x3
137
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#define RT305X_GPIO_MODE_PCM_GPIO 0x4
138
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#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
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#define RT305X_GPIO_MODE_GPIO_I2S 0x6
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#define RT305X_GPIO_MODE_GPIO 0x7
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-
#define RT305X_GPIO_MODE_UART1 BIT(5)
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#define RT305X_GPIO_MODE_JTAG BIT(6)
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#define RT305X_GPIO_MODE_MDIO BIT(7)
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-
#define RT305X_GPIO_MODE_SDRAM BIT(8)
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-
#define RT305X_GPIO_MODE_RGMII BIT(9)
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#define RT305X_GPIO_MODE_UARTF 0
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#define RT305X_GPIO_MODE_PCM_UARTF 1
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#define RT305X_GPIO_MODE_PCM_I2S 2
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#define RT305X_GPIO_MODE_I2S_UARTF 3
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#define RT305X_GPIO_MODE_PCM_GPIO 4
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#define RT305X_GPIO_MODE_GPIO_UARTF 5
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#define RT305X_GPIO_MODE_GPIO_I2S 6
138
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#define RT305X_GPIO_MODE_GPIO 7
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+
140
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#define RT305X_GPIO_MODE_I2C 0
141
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#define RT305X_GPIO_MODE_SPI 1
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#define RT305X_GPIO_MODE_UART1 5
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#define RT305X_GPIO_MODE_JTAG 6
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#define RT305X_GPIO_MODE_MDIO 7
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#define RT305X_GPIO_MODE_SDRAM 8
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#define RT305X_GPIO_MODE_RGMII 9
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#define RT5350_GPIO_MODE_PHY_LED 14
148
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#define RT5350_GPIO_MODE_SPI_CS1 21
149
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#define RT3352_GPIO_MODE_LNA 18
150
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#define RT3352_GPIO_MODE_PA 20
146
151
147
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#define RT3352_SYSC_REG_SYSCFG0 0x010
148
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#define RT3352_SYSC_REG_SYSCFG1 0x014
+9
-7
arch/mips/include/asm/mach-ralink/rt3883.h
+9
-7
arch/mips/include/asm/mach-ralink/rt3883.h
···
112
112
#define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
113
113
#define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
114
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115
-
#define RT3883_GPIO_MODE_I2C BIT(0)
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#define RT3883_GPIO_MODE_SPI BIT(1)
117
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#define RT3883_GPIO_MODE_UART0_SHIFT 2
118
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#define RT3883_GPIO_MODE_UART0_MASK 0x7
119
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#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
···
123
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#define RT3883_GPIO_MODE_GPIO_UARTF 0x5
124
126
#define RT3883_GPIO_MODE_GPIO_I2S 0x6
125
127
#define RT3883_GPIO_MODE_GPIO 0x7
126
-
#define RT3883_GPIO_MODE_UART1 BIT(5)
127
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#define RT3883_GPIO_MODE_JTAG BIT(6)
128
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#define RT3883_GPIO_MODE_MDIO BIT(7)
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#define RT3883_GPIO_MODE_GE1 BIT(9)
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#define RT3883_GPIO_MODE_GE2 BIT(10)
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+
129
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#define RT3883_GPIO_MODE_I2C 0
130
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#define RT3883_GPIO_MODE_SPI 1
131
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#define RT3883_GPIO_MODE_UART1 5
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#define RT3883_GPIO_MODE_JTAG 6
133
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#define RT3883_GPIO_MODE_MDIO 7
134
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#define RT3883_GPIO_MODE_GE1 9
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#define RT3883_GPIO_MODE_GE2 10
136
+
131
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#define RT3883_GPIO_MODE_PCI_SHIFT 11
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#define RT3883_GPIO_MODE_PCI_MASK 0x7
133
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#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
-19
arch/mips/ralink/common.h
-19
arch/mips/ralink/common.h
···
11
11
12
12
#define RAMIPS_SYS_TYPE_LEN 32
13
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-
struct ralink_pinmux_grp {
15
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const char *name;
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u32 mask;
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int gpio_first;
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int gpio_last;
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};
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21
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struct ralink_pinmux {
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struct ralink_pinmux_grp *mode;
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struct ralink_pinmux_grp *uart;
24
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int uart_shift;
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u32 uart_mask;
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void (*wdt_reset)(void);
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struct ralink_pinmux_grp *pci;
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int pci_shift;
29
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u32 pci_mask;
30
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};
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extern struct ralink_pinmux rt_gpio_pinmux;
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-
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14
struct ralink_soc_info {
34
15
unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
35
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unsigned char *compatible;
+51
-110
arch/mips/ralink/mt7620.c
+51
-110
arch/mips/ralink/mt7620.c
···
17
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#include <asm/mipsregs.h>
18
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7620.h>
20
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#include <asm/mach-ralink/pinmux.h>
20
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#include "common.h"
22
23
···
40
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/* does the board have sdram or ddram */
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static int dram_type;
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static struct ralink_pinmux_grp mode_mux[] = {
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{
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.name = "i2c",
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.mask = MT7620_GPIO_MODE_I2C,
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.gpio_first = 1,
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.gpio_last = 2,
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}, {
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.name = "spi",
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.mask = MT7620_GPIO_MODE_SPI,
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.gpio_first = 3,
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.gpio_last = 6,
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}, {
55
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.name = "uartlite",
56
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.mask = MT7620_GPIO_MODE_UART1,
57
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.gpio_first = 15,
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.gpio_last = 16,
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}, {
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.name = "wdt",
61
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.mask = MT7620_GPIO_MODE_WDT,
62
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.gpio_first = 17,
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.gpio_last = 17,
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}, {
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.name = "mdio",
66
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.mask = MT7620_GPIO_MODE_MDIO,
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.gpio_first = 22,
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.gpio_last = 23,
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}, {
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.name = "rgmii1",
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.mask = MT7620_GPIO_MODE_RGMII1,
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.gpio_first = 24,
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.gpio_last = 35,
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}, {
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.name = "spi refclk",
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.mask = MT7620_GPIO_MODE_SPI_REF_CLK,
77
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.gpio_first = 37,
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.gpio_last = 39,
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}, {
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.name = "jtag",
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.mask = MT7620_GPIO_MODE_JTAG,
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.gpio_first = 40,
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.gpio_last = 44,
84
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}, {
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/* shared lines with jtag */
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.name = "ephy",
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.mask = MT7620_GPIO_MODE_EPHY,
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.gpio_first = 40,
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.gpio_last = 44,
90
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}, {
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.name = "nand",
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.mask = MT7620_GPIO_MODE_JTAG,
93
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.gpio_first = 45,
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.gpio_last = 59,
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}, {
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.name = "rgmii2",
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.mask = MT7620_GPIO_MODE_RGMII2,
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.gpio_first = 60,
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.gpio_last = 71,
100
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}, {
101
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.name = "wled",
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.mask = MT7620_GPIO_MODE_WLED,
103
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.gpio_first = 72,
104
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.gpio_last = 72,
105
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}, {0}
42
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static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
43
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static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
44
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static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
45
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static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
46
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static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
47
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static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
48
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static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
49
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static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
50
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static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
51
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static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
52
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static struct rt2880_pmx_func uartf_grp[] = {
53
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FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
54
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FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
55
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FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
56
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FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
57
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FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
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FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
59
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FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
60
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};
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static struct rt2880_pmx_func wdt_grp[] = {
62
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FUNC("wdt rst", 0, 17, 1),
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FUNC("wdt refclk", 0, 17, 1),
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};
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static struct rt2880_pmx_func pcie_rst_grp[] = {
66
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FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
67
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FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
68
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};
69
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static struct rt2880_pmx_func nd_sd_grp[] = {
70
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FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
71
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FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
106
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};
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static struct ralink_pinmux_grp uart_mux[] = {
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{
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.name = "uartf",
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.mask = MT7620_GPIO_MODE_UARTF,
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.gpio_first = 7,
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.gpio_last = 14,
114
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}, {
115
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.name = "pcm uartf",
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.mask = MT7620_GPIO_MODE_PCM_UARTF,
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.gpio_first = 7,
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.gpio_last = 14,
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}, {
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.name = "pcm i2s",
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.mask = MT7620_GPIO_MODE_PCM_I2S,
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.gpio_first = 7,
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.gpio_last = 14,
124
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}, {
125
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.name = "i2s uartf",
126
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.mask = MT7620_GPIO_MODE_I2S_UARTF,
127
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.gpio_first = 7,
128
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.gpio_last = 14,
129
-
}, {
130
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.name = "pcm gpio",
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.mask = MT7620_GPIO_MODE_PCM_GPIO,
132
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.gpio_first = 11,
133
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.gpio_last = 14,
134
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}, {
135
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.name = "gpio uartf",
136
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.mask = MT7620_GPIO_MODE_GPIO_UARTF,
137
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.gpio_first = 7,
138
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.gpio_last = 10,
139
-
}, {
140
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.name = "gpio i2s",
141
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.mask = MT7620_GPIO_MODE_GPIO_I2S,
142
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.gpio_first = 7,
143
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.gpio_last = 10,
144
-
}, {
145
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.name = "gpio",
146
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.mask = MT7620_GPIO_MODE_GPIO,
147
-
}, {0}
148
-
};
149
-
150
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struct ralink_pinmux rt_gpio_pinmux = {
151
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.mode = mode_mux,
152
-
.uart = uart_mux,
153
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.uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
154
-
.uart_mask = MT7620_GPIO_MODE_UART0_MASK,
74
+
static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
75
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GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
76
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GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
77
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MT7620_GPIO_MODE_UART0_SHIFT),
78
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GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
79
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GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
80
+
GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
81
+
MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
82
+
GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
83
+
GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
84
+
GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
85
+
GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
86
+
MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
87
+
GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
88
+
MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
89
+
GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
90
+
GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
91
+
GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
92
+
GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
93
+
{ 0 }
155
94
};
156
95
157
96
static __init u32
+1
arch/mips/ralink/prom.c
+1
arch/mips/ralink/prom.c
+20
-42
arch/mips/ralink/rt288x.c
+20
-42
arch/mips/ralink/rt288x.c
···
17
17
#include <asm/mipsregs.h>
18
18
#include <asm/mach-ralink/ralink_regs.h>
19
19
#include <asm/mach-ralink/rt288x.h>
20
+
#include <asm/mach-ralink/pinmux.h>
20
21
21
22
#include "common.h"
22
23
23
-
static struct ralink_pinmux_grp mode_mux[] = {
24
-
{
25
-
.name = "i2c",
26
-
.mask = RT2880_GPIO_MODE_I2C,
27
-
.gpio_first = 1,
28
-
.gpio_last = 2,
29
-
}, {
30
-
.name = "spi",
31
-
.mask = RT2880_GPIO_MODE_SPI,
32
-
.gpio_first = 3,
33
-
.gpio_last = 6,
34
-
}, {
35
-
.name = "uartlite",
36
-
.mask = RT2880_GPIO_MODE_UART0,
37
-
.gpio_first = 7,
38
-
.gpio_last = 14,
39
-
}, {
40
-
.name = "jtag",
41
-
.mask = RT2880_GPIO_MODE_JTAG,
42
-
.gpio_first = 17,
43
-
.gpio_last = 21,
44
-
}, {
45
-
.name = "mdio",
46
-
.mask = RT2880_GPIO_MODE_MDIO,
47
-
.gpio_first = 22,
48
-
.gpio_last = 23,
49
-
}, {
50
-
.name = "sdram",
51
-
.mask = RT2880_GPIO_MODE_SDRAM,
52
-
.gpio_first = 24,
53
-
.gpio_last = 39,
54
-
}, {
55
-
.name = "pci",
56
-
.mask = RT2880_GPIO_MODE_PCI,
57
-
.gpio_first = 40,
58
-
.gpio_last = 71,
59
-
}, {0}
24
+
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
25
+
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
26
+
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
27
+
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
28
+
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
29
+
static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
30
+
static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
31
+
32
+
static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
33
+
GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
34
+
GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
35
+
GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
36
+
GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
37
+
GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
38
+
GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
39
+
GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
40
+
{ 0 }
60
41
};
61
42
62
43
static void rt288x_wdt_reset(void)
···
49
68
t |= CLKCFG_SRAM_CS_N_WDT;
50
69
rt_sysc_w32(t, SYSC_REG_CLKCFG);
51
70
}
52
-
53
-
struct ralink_pinmux rt_gpio_pinmux = {
54
-
.mode = mode_mux,
55
-
.wdt_reset = rt288x_wdt_reset,
56
-
};
57
71
58
72
void __init ralink_clk_init(void)
59
73
{
···
117
141
soc_info->mem_base = RT2880_SDRAM_BASE;
118
142
soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
119
143
soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
144
+
145
+
rt2880_pinmux_data = rt2880_pinmux_data_act;
120
146
}
+68
-85
arch/mips/ralink/rt305x.c
+68
-85
arch/mips/ralink/rt305x.c
···
17
17
#include <asm/mipsregs.h>
18
18
#include <asm/mach-ralink/ralink_regs.h>
19
19
#include <asm/mach-ralink/rt305x.h>
20
+
#include <asm/mach-ralink/pinmux.h>
20
21
21
22
#include "common.h"
22
23
23
24
enum rt305x_soc_type rt305x_soc;
24
25
25
-
static struct ralink_pinmux_grp mode_mux[] = {
26
-
{
27
-
.name = "i2c",
28
-
.mask = RT305X_GPIO_MODE_I2C,
29
-
.gpio_first = RT305X_GPIO_I2C_SD,
30
-
.gpio_last = RT305X_GPIO_I2C_SCLK,
31
-
}, {
32
-
.name = "spi",
33
-
.mask = RT305X_GPIO_MODE_SPI,
34
-
.gpio_first = RT305X_GPIO_SPI_EN,
35
-
.gpio_last = RT305X_GPIO_SPI_CLK,
36
-
}, {
37
-
.name = "uartlite",
38
-
.mask = RT305X_GPIO_MODE_UART1,
39
-
.gpio_first = RT305X_GPIO_UART1_TXD,
40
-
.gpio_last = RT305X_GPIO_UART1_RXD,
41
-
}, {
42
-
.name = "jtag",
43
-
.mask = RT305X_GPIO_MODE_JTAG,
44
-
.gpio_first = RT305X_GPIO_JTAG_TDO,
45
-
.gpio_last = RT305X_GPIO_JTAG_TDI,
46
-
}, {
47
-
.name = "mdio",
48
-
.mask = RT305X_GPIO_MODE_MDIO,
49
-
.gpio_first = RT305X_GPIO_MDIO_MDC,
50
-
.gpio_last = RT305X_GPIO_MDIO_MDIO,
51
-
}, {
52
-
.name = "sdram",
53
-
.mask = RT305X_GPIO_MODE_SDRAM,
54
-
.gpio_first = RT305X_GPIO_SDRAM_MD16,
55
-
.gpio_last = RT305X_GPIO_SDRAM_MD31,
56
-
}, {
57
-
.name = "rgmii",
58
-
.mask = RT305X_GPIO_MODE_RGMII,
59
-
.gpio_first = RT305X_GPIO_GE0_TXD0,
60
-
.gpio_last = RT305X_GPIO_GE0_RXCLK,
61
-
}, {0}
26
+
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
27
+
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
28
+
static struct rt2880_pmx_func uartf_func[] = {
29
+
FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
30
+
FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
31
+
FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
32
+
FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
33
+
FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
34
+
FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
35
+
FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
36
+
};
37
+
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
38
+
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
39
+
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
40
+
static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
41
+
static struct rt2880_pmx_func rt5350_cs1_func[] = {
42
+
FUNC("spi_cs1", 0, 27, 1),
43
+
FUNC("wdg_cs1", 1, 27, 1),
44
+
};
45
+
static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
46
+
static struct rt2880_pmx_func rt3352_rgmii_func[] = {
47
+
FUNC("rgmii", 0, 24, 12)
48
+
};
49
+
static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
50
+
static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
51
+
static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
52
+
static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
53
+
54
+
static struct rt2880_pmx_group rt3050_pinmux_data[] = {
55
+
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
56
+
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
57
+
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
58
+
RT305X_GPIO_MODE_UART0_SHIFT),
59
+
GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
60
+
GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
61
+
GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
62
+
GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
63
+
GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
64
+
{ 0 }
62
65
};
63
66
64
-
static struct ralink_pinmux_grp uart_mux[] = {
65
-
{
66
-
.name = "uartf",
67
-
.mask = RT305X_GPIO_MODE_UARTF,
68
-
.gpio_first = RT305X_GPIO_7,
69
-
.gpio_last = RT305X_GPIO_14,
70
-
}, {
71
-
.name = "pcm uartf",
72
-
.mask = RT305X_GPIO_MODE_PCM_UARTF,
73
-
.gpio_first = RT305X_GPIO_7,
74
-
.gpio_last = RT305X_GPIO_14,
75
-
}, {
76
-
.name = "pcm i2s",
77
-
.mask = RT305X_GPIO_MODE_PCM_I2S,
78
-
.gpio_first = RT305X_GPIO_7,
79
-
.gpio_last = RT305X_GPIO_14,
80
-
}, {
81
-
.name = "i2s uartf",
82
-
.mask = RT305X_GPIO_MODE_I2S_UARTF,
83
-
.gpio_first = RT305X_GPIO_7,
84
-
.gpio_last = RT305X_GPIO_14,
85
-
}, {
86
-
.name = "pcm gpio",
87
-
.mask = RT305X_GPIO_MODE_PCM_GPIO,
88
-
.gpio_first = RT305X_GPIO_10,
89
-
.gpio_last = RT305X_GPIO_14,
90
-
}, {
91
-
.name = "gpio uartf",
92
-
.mask = RT305X_GPIO_MODE_GPIO_UARTF,
93
-
.gpio_first = RT305X_GPIO_7,
94
-
.gpio_last = RT305X_GPIO_10,
95
-
}, {
96
-
.name = "gpio i2s",
97
-
.mask = RT305X_GPIO_MODE_GPIO_I2S,
98
-
.gpio_first = RT305X_GPIO_7,
99
-
.gpio_last = RT305X_GPIO_10,
100
-
}, {
101
-
.name = "gpio",
102
-
.mask = RT305X_GPIO_MODE_GPIO,
103
-
}, {0}
67
+
static struct rt2880_pmx_group rt3352_pinmux_data[] = {
68
+
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
69
+
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
70
+
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
71
+
RT305X_GPIO_MODE_UART0_SHIFT),
72
+
GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
73
+
GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
74
+
GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
75
+
GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
76
+
GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
77
+
GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
78
+
GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
79
+
{ 0 }
80
+
};
81
+
82
+
static struct rt2880_pmx_group rt5350_pinmux_data[] = {
83
+
GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
84
+
GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
85
+
GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
86
+
RT305X_GPIO_MODE_UART0_SHIFT),
87
+
GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
88
+
GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
89
+
GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
90
+
GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
91
+
{ 0 }
104
92
};
105
93
106
94
static void rt305x_wdt_reset(void)
···
101
113
RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
102
114
rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
103
115
}
104
-
105
-
struct ralink_pinmux rt_gpio_pinmux = {
106
-
.mode = mode_mux,
107
-
.uart = uart_mux,
108
-
.uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
109
-
.uart_mask = RT305X_GPIO_MODE_UART0_MASK,
110
-
.wdt_reset = rt305x_wdt_reset,
111
-
};
112
116
113
117
static unsigned long rt5350_get_mem_size(void)
114
118
{
···
270
290
soc_info->mem_base = RT305X_SDRAM_BASE;
271
291
if (soc_is_rt5350()) {
272
292
soc_info->mem_size = rt5350_get_mem_size();
293
+
rt2880_pinmux_data = rt5350_pinmux_data;
273
294
} else if (soc_is_rt305x() || soc_is_rt3350()) {
274
295
soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
275
296
soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
297
+
rt2880_pinmux_data = rt3050_pinmux_data;
276
298
} else if (soc_is_rt3352()) {
277
299
soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
278
300
soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
301
+
rt2880_pinmux_data = rt3352_pinmux_data;
279
302
}
280
303
}
+40
-131
arch/mips/ralink/rt3883.c
+40
-131
arch/mips/ralink/rt3883.c
···
17
17
#include <asm/mipsregs.h>
18
18
#include <asm/mach-ralink/ralink_regs.h>
19
19
#include <asm/mach-ralink/rt3883.h>
20
+
#include <asm/mach-ralink/pinmux.h>
20
21
21
22
#include "common.h"
22
23
23
-
static struct ralink_pinmux_grp mode_mux[] = {
24
-
{
25
-
.name = "i2c",
26
-
.mask = RT3883_GPIO_MODE_I2C,
27
-
.gpio_first = RT3883_GPIO_I2C_SD,
28
-
.gpio_last = RT3883_GPIO_I2C_SCLK,
29
-
}, {
30
-
.name = "spi",
31
-
.mask = RT3883_GPIO_MODE_SPI,
32
-
.gpio_first = RT3883_GPIO_SPI_CS0,
33
-
.gpio_last = RT3883_GPIO_SPI_MISO,
34
-
}, {
35
-
.name = "uartlite",
36
-
.mask = RT3883_GPIO_MODE_UART1,
37
-
.gpio_first = RT3883_GPIO_UART1_TXD,
38
-
.gpio_last = RT3883_GPIO_UART1_RXD,
39
-
}, {
40
-
.name = "jtag",
41
-
.mask = RT3883_GPIO_MODE_JTAG,
42
-
.gpio_first = RT3883_GPIO_JTAG_TDO,
43
-
.gpio_last = RT3883_GPIO_JTAG_TCLK,
44
-
}, {
45
-
.name = "mdio",
46
-
.mask = RT3883_GPIO_MODE_MDIO,
47
-
.gpio_first = RT3883_GPIO_MDIO_MDC,
48
-
.gpio_last = RT3883_GPIO_MDIO_MDIO,
49
-
}, {
50
-
.name = "ge1",
51
-
.mask = RT3883_GPIO_MODE_GE1,
52
-
.gpio_first = RT3883_GPIO_GE1_TXD0,
53
-
.gpio_last = RT3883_GPIO_GE1_RXCLK,
54
-
}, {
55
-
.name = "ge2",
56
-
.mask = RT3883_GPIO_MODE_GE2,
57
-
.gpio_first = RT3883_GPIO_GE2_TXD0,
58
-
.gpio_last = RT3883_GPIO_GE2_RXCLK,
59
-
}, {
60
-
.name = "pci",
61
-
.mask = RT3883_GPIO_MODE_PCI,
62
-
.gpio_first = RT3883_GPIO_PCI_AD0,
63
-
.gpio_last = RT3883_GPIO_PCI_AD31,
64
-
}, {
65
-
.name = "lna a",
66
-
.mask = RT3883_GPIO_MODE_LNA_A,
67
-
.gpio_first = RT3883_GPIO_LNA_PE_A0,
68
-
.gpio_last = RT3883_GPIO_LNA_PE_A2,
69
-
}, {
70
-
.name = "lna g",
71
-
.mask = RT3883_GPIO_MODE_LNA_G,
72
-
.gpio_first = RT3883_GPIO_LNA_PE_G0,
73
-
.gpio_last = RT3883_GPIO_LNA_PE_G2,
74
-
}, {0}
24
+
static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
25
+
static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
26
+
static struct rt2880_pmx_func uartf_func[] = {
27
+
FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
28
+
FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
29
+
FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
30
+
FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
31
+
FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
32
+
FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
33
+
FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
75
34
};
76
-
77
-
static struct ralink_pinmux_grp uart_mux[] = {
78
-
{
79
-
.name = "uartf",
80
-
.mask = RT3883_GPIO_MODE_UARTF,
81
-
.gpio_first = RT3883_GPIO_7,
82
-
.gpio_last = RT3883_GPIO_14,
83
-
}, {
84
-
.name = "pcm uartf",
85
-
.mask = RT3883_GPIO_MODE_PCM_UARTF,
86
-
.gpio_first = RT3883_GPIO_7,
87
-
.gpio_last = RT3883_GPIO_14,
88
-
}, {
89
-
.name = "pcm i2s",
90
-
.mask = RT3883_GPIO_MODE_PCM_I2S,
91
-
.gpio_first = RT3883_GPIO_7,
92
-
.gpio_last = RT3883_GPIO_14,
93
-
}, {
94
-
.name = "i2s uartf",
95
-
.mask = RT3883_GPIO_MODE_I2S_UARTF,
96
-
.gpio_first = RT3883_GPIO_7,
97
-
.gpio_last = RT3883_GPIO_14,
98
-
}, {
99
-
.name = "pcm gpio",
100
-
.mask = RT3883_GPIO_MODE_PCM_GPIO,
101
-
.gpio_first = RT3883_GPIO_11,
102
-
.gpio_last = RT3883_GPIO_14,
103
-
}, {
104
-
.name = "gpio uartf",
105
-
.mask = RT3883_GPIO_MODE_GPIO_UARTF,
106
-
.gpio_first = RT3883_GPIO_7,
107
-
.gpio_last = RT3883_GPIO_10,
108
-
}, {
109
-
.name = "gpio i2s",
110
-
.mask = RT3883_GPIO_MODE_GPIO_I2S,
111
-
.gpio_first = RT3883_GPIO_7,
112
-
.gpio_last = RT3883_GPIO_10,
113
-
}, {
114
-
.name = "gpio",
115
-
.mask = RT3883_GPIO_MODE_GPIO,
116
-
}, {0}
35
+
static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
36
+
static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
37
+
static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
38
+
static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
39
+
static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
40
+
static struct rt2880_pmx_func pci_func[] = {
41
+
FUNC("pci-dev", 0, 40, 32),
42
+
FUNC("pci-host2", 1, 40, 32),
43
+
FUNC("pci-host1", 2, 40, 32),
44
+
FUNC("pci-fnc", 3, 40, 32)
117
45
};
46
+
static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
47
+
static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
118
48
119
-
static struct ralink_pinmux_grp pci_mux[] = {
120
-
{
121
-
.name = "pci-dev",
122
-
.mask = 0,
123
-
.gpio_first = RT3883_GPIO_PCI_AD0,
124
-
.gpio_last = RT3883_GPIO_PCI_AD31,
125
-
}, {
126
-
.name = "pci-host2",
127
-
.mask = 1,
128
-
.gpio_first = RT3883_GPIO_PCI_AD0,
129
-
.gpio_last = RT3883_GPIO_PCI_AD31,
130
-
}, {
131
-
.name = "pci-host1",
132
-
.mask = 2,
133
-
.gpio_first = RT3883_GPIO_PCI_AD0,
134
-
.gpio_last = RT3883_GPIO_PCI_AD31,
135
-
}, {
136
-
.name = "pci-fnc",
137
-
.mask = 3,
138
-
.gpio_first = RT3883_GPIO_PCI_AD0,
139
-
.gpio_last = RT3883_GPIO_PCI_AD31,
140
-
}, {
141
-
.name = "pci-gpio",
142
-
.mask = 7,
143
-
.gpio_first = RT3883_GPIO_PCI_AD0,
144
-
.gpio_last = RT3883_GPIO_PCI_AD31,
145
-
}, {0}
49
+
static struct rt2880_pmx_group rt3883_pinmux_data[] = {
50
+
GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
51
+
GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
52
+
GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
53
+
RT3883_GPIO_MODE_UART0_SHIFT),
54
+
GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
55
+
GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
56
+
GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
57
+
GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
58
+
GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
59
+
GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
60
+
RT3883_GPIO_MODE_PCI_SHIFT),
61
+
GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
62
+
GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
63
+
{ 0 }
146
64
};
147
65
148
66
static void rt3883_wdt_reset(void)
···
72
154
t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
73
155
rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
74
156
}
75
-
76
-
struct ralink_pinmux rt_gpio_pinmux = {
77
-
.mode = mode_mux,
78
-
.uart = uart_mux,
79
-
.uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
80
-
.uart_mask = RT3883_GPIO_MODE_UART0_MASK,
81
-
.wdt_reset = rt3883_wdt_reset,
82
-
.pci = pci_mux,
83
-
.pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
84
-
.pci_mask = RT3883_GPIO_MODE_PCI_MASK,
85
-
};
86
157
87
158
void __init ralink_clk_init(void)
88
159
{
···
151
244
soc_info->mem_base = RT3883_SDRAM_BASE;
152
245
soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
153
246
soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
247
+
248
+
rt2880_pinmux_data = rt3883_pinmux_data;
154
249
}