Merge tag 'omap-for-v3.11/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

From Tony Lindgren:
Omap GPMC (General Purpose Memory Controller) changes.

* tag 'omap-for-v3.11/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: gpmc: Converts GPMC driver to pm_runtime capable
ARM: OMAP2+: gpmc: get number of useable GPMC chip-selects via DT
ARM: dts: OMAP2+: Simplify NAND support
ARM: OMAP2+: Allow NAND transfer mode to be specified in DT
ARM: OMAP2+: nand: reorganize gpmc timing values

Signed-off-by: Olof Johansson <olof@lixom.net>

Olof Johansson 13 years ago f54ffe0f ff299f1b

+63 -55

6 changed files

expand all

Documentation

devicetree

bindings

bus

ti-gpmc.txt

mtd

gpmc-nand.txt

arch

arm

boot

dts

omap3430-sdp.dts

mach-omap2

board-flash.c

gpmc-nand.c

gpmc.c

-1

Documentation/devicetree/bindings/bus/ti-gpmc.txt

··· 95 95 - gpmc,burst-wrap Enables wrap bursting 96 96 - gpmc,burst-read Enables read page/burst mode 97 97 - gpmc,burst-write Enables write page/burst mode 98 - - gpmc,device-nand Device is NAND 99 98 - gpmc,device-width Total width of device(s) connected to a GPMC 100 99 chip-select in bytes. The GPMC supports 8-bit 101 100 and 16-bit devices and so this property must be

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

··· 29 29 "bch4" 4-bit BCH ecc code 30 30 "bch8" 8-bit BCH ecc code 31 31 32 + - ti,nand-xfer-type: A string setting the data transfer type. One of: 33 + 34 + "prefetch-polled" Prefetch polled mode (default) 35 + "polled" Polled mode, without prefetch 36 + "prefetch-dma" Prefetch enabled sDMA mode 37 + "prefetch-irq" Prefetch enabled irq mode 38 + 32 39 - elm_id: Specifies elm device node. This is required to support BCH 33 40 error correction using ELM module. 34 41 ··· 62 55 reg = <0 0 0>; /* CS0, offset 0 */ 63 56 nand-bus-width = <16>; 64 57 ti,nand-ecc-opt = "bch8"; 58 + ti,nand-xfer-type = "polled"; 65 59 66 60 gpmc,sync-clk-ps = <0>; 67 61 gpmc,cs-on-ns = <0>;

-1

arch/arm/boot/dts/omap3430-sdp.dts

··· 105 105 nand-bus-width = <8>; 106 106 107 107 ti,nand-ecc-opt = "sw"; 108 - gpmc,device-nand; 109 108 gpmc,cs-on-ns = <0>; 110 109 gpmc,cs-rd-off-ns = <36>; 111 110 gpmc,cs-wr-off-ns = <36>;

arch/arm/mach-omap2/board-flash.c

··· 112 112 .cs_rd_off = 36, 113 113 .cs_wr_off = 36, 114 114 115 + .we_on = 6, 116 + .oe_on = 6, 117 + 115 118 .adv_on = 6, 116 119 .adv_rd_off = 24, 117 120 .adv_wr_off = 36,

+3 -41

arch/arm/mach-omap2/gpmc-nand.c

··· 43 43 .resource = gpmc_nand_resource, 44 44 }; 45 45 46 - static int omap2_nand_gpmc_retime( 47 - struct omap_nand_platform_data *gpmc_nand_data, 48 - struct gpmc_timings *gpmc_t) 49 - { 50 - struct gpmc_timings t; 51 - int err; 52 - 53 - memset(&t, 0, sizeof(t)); 54 - t.sync_clk = gpmc_t->sync_clk; 55 - t.cs_on = gpmc_t->cs_on; 56 - t.adv_on = gpmc_t->adv_on; 57 - 58 - /* Read */ 59 - t.adv_rd_off = gpmc_t->adv_rd_off; 60 - t.oe_on = t.adv_on; 61 - t.access = gpmc_t->access; 62 - t.oe_off = gpmc_t->oe_off; 63 - t.cs_rd_off = gpmc_t->cs_rd_off; 64 - t.rd_cycle = gpmc_t->rd_cycle; 65 - 66 - /* Write */ 67 - t.adv_wr_off = gpmc_t->adv_wr_off; 68 - t.we_on = t.oe_on; 69 - if (cpu_is_omap34xx()) { 70 - t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus; 71 - t.wr_access = gpmc_t->wr_access; 72 - } 73 - t.we_off = gpmc_t->we_off; 74 - t.cs_wr_off = gpmc_t->cs_wr_off; 75 - t.wr_cycle = gpmc_t->wr_cycle; 76 - 77 - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); 78 - if (err) 79 - return err; 80 - 81 - return 0; 82 - } 83 - 84 46 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 85 47 { 86 48 /* support only OMAP3 class */ ··· 93 131 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); 94 132 95 133 if (gpmc_t) { 96 - err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t); 134 + err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); 97 135 if (err < 0) { 98 136 dev_err(dev, "Unable to set gpmc timings: %d\n", err); 99 137 return err; ··· 102 140 if (gpmc_nand_data->of_node) { 103 141 gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); 104 142 } else { 105 - s.device_nand = true; 106 - 107 143 /* Enable RD PIN Monitoring Reg */ 108 144 if (gpmc_nand_data->dev_ready) { 109 145 s.wait_on_read = true; 110 146 s.wait_on_write = true; 111 147 } 112 148 } 149 + 150 + s.device_nand = true; 113 151 114 152 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) 115 153 s.device_width = GPMC_DEVWIDTH_16BIT;

+49 -12

arch/arm/mach-omap2/gpmc.c

··· 30 30 #include <linux/of_mtd.h> 31 31 #include <linux/of_device.h> 32 32 #include <linux/mtd/nand.h> 33 + #include <linux/pm_runtime.h> 33 34 34 35 #include <linux/platform_data/mtd-nand-omap2.h> 35 36 ··· 156 155 static DEFINE_SPINLOCK(gpmc_mem_lock); 157 156 /* Define chip-selects as reserved by default until probe completes */ 158 157 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); 158 + static unsigned int gpmc_cs_num = GPMC_CS_NUM; 159 159 static unsigned int gpmc_nr_waitpins; 160 160 static struct device *gpmc_dev; 161 161 static int gpmc_irq; ··· 523 521 int ret; 524 522 u32 old_base, size; 525 523 526 - if (cs > GPMC_CS_NUM) 524 + if (cs > gpmc_cs_num) { 525 + pr_err("%s: requested chip-select is disabled\n", __func__); 527 526 return -ENODEV; 527 + } 528 528 gpmc_cs_get_memconf(cs, &old_base, &size); 529 529 if (base == old_base) 530 530 return 0; ··· 549 545 struct resource *res = &gpmc_cs_mem[cs]; 550 546 int r = -1; 551 547 552 - if (cs > GPMC_CS_NUM) 548 + if (cs > gpmc_cs_num) { 549 + pr_err("%s: requested chip-select is disabled\n", __func__); 553 550 return -ENODEV; 554 - 551 + } 555 552 size = gpmc_mem_align(size); 556 553 if (size > (1 << GPMC_SECTION_SHIFT)) 557 554 return -ENOMEM; ··· 587 582 void gpmc_cs_free(int cs) 588 583 { 589 584 spin_lock(&gpmc_mem_lock); 590 - if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { 585 + if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 591 586 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 592 587 BUG(); 593 588 spin_unlock(&gpmc_mem_lock); ··· 782 777 { 783 778 int cs; 784 779 785 - for (cs = 0; cs < GPMC_CS_NUM; cs++) { 780 + for (cs = 0; cs < gpmc_cs_num; cs++) { 786 781 if (!gpmc_cs_mem_enabled(cs)) 787 782 continue; 788 783 gpmc_cs_delete_mem(cs); ··· 803 798 gpmc_mem_root.end = GPMC_MEM_END; 804 799 805 800 /* Reserve all regions that has been set up by bootloader */ 806 - for (cs = 0; cs < GPMC_CS_NUM; cs++) { 801 + for (cs = 0; cs < gpmc_cs_num; cs++) { 807 802 u32 base, size; 808 803 809 804 if (!gpmc_cs_mem_enabled(cs)) ··· 1250 1245 1251 1246 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1252 1247 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1253 - p->device_nand = of_property_read_bool(np, "gpmc,device-nand"); 1254 1248 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1255 1249 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1256 1250 ··· 1349 1345 [OMAP_ECC_BCH8_CODE_HW] = "bch8", 1350 1346 }; 1351 1347 1348 + static const char * const nand_xfer_types[] = { 1349 + [NAND_OMAP_PREFETCH_POLLED] = "prefetch-polled", 1350 + [NAND_OMAP_POLLED] = "polled", 1351 + [NAND_OMAP_PREFETCH_DMA] = "prefetch-dma", 1352 + [NAND_OMAP_PREFETCH_IRQ] = "prefetch-irq", 1353 + }; 1354 + 1352 1355 static int gpmc_probe_nand_child(struct platform_device *pdev, 1353 1356 struct device_node *child) 1354 1357 { ··· 1382 1371 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++) 1383 1372 if (!strcasecmp(s, nand_ecc_opts[val])) { 1384 1373 gpmc_nand_data->ecc_opt = val; 1374 + break; 1375 + } 1376 + 1377 + if (!of_property_read_string(child, "ti,nand-xfer-type", &s)) 1378 + for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++) 1379 + if (!strcasecmp(s, nand_xfer_types[val])) { 1380 + gpmc_nand_data->xfer_type = val; 1385 1381 break; 1386 1382 } 1387 1383 ··· 1531 1513 if (!of_id) 1532 1514 return 0; 1533 1515 1516 + ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 1517 + &gpmc_cs_num); 1518 + if (ret < 0) { 1519 + pr_err("%s: number of chip-selects not defined\n", __func__); 1520 + return ret; 1521 + } else if (gpmc_cs_num < 1) { 1522 + pr_err("%s: all chip-selects are disabled\n", __func__); 1523 + return -EINVAL; 1524 + } else if (gpmc_cs_num > GPMC_CS_NUM) { 1525 + pr_err("%s: number of supported chip-selects cannot be > %d\n", 1526 + __func__, GPMC_CS_NUM); 1527 + return -EINVAL; 1528 + } 1529 + 1534 1530 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 1535 1531 &gpmc_nr_waitpins); 1536 1532 if (ret < 0) { ··· 1609 1577 return PTR_ERR(gpmc_l3_clk); 1610 1578 } 1611 1579 1612 - clk_prepare_enable(gpmc_l3_clk); 1580 + pm_runtime_enable(&pdev->dev); 1581 + pm_runtime_get_sync(&pdev->dev); 1613 1582 1614 1583 gpmc_dev = &pdev->dev; 1615 1584 ··· 1643 1610 /* Now the GPMC is initialised, unreserve the chip-selects */ 1644 1611 gpmc_cs_map = 0; 1645 1612 1646 - if (!pdev->dev.of_node) 1613 + if (!pdev->dev.of_node) { 1614 + gpmc_cs_num = GPMC_CS_NUM; 1647 1615 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 1616 + } 1648 1617 1649 1618 rc = gpmc_probe_dt(pdev); 1650 1619 if (rc < 0) { 1651 - clk_disable_unprepare(gpmc_l3_clk); 1620 + pm_runtime_put_sync(&pdev->dev); 1652 1621 clk_put(gpmc_l3_clk); 1653 1622 dev_err(gpmc_dev, "failed to probe DT parameters\n"); 1654 1623 return rc; ··· 1663 1628 { 1664 1629 gpmc_free_irq(); 1665 1630 gpmc_mem_exit(); 1631 + pm_runtime_put_sync(&pdev->dev); 1632 + pm_runtime_disable(&pdev->dev); 1666 1633 gpmc_dev = NULL; 1667 1634 return 0; 1668 1635 } ··· 1752 1715 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 1753 1716 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 1754 1717 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 1755 - for (i = 0; i < GPMC_CS_NUM; i++) { 1718 + for (i = 0; i < gpmc_cs_num; i++) { 1756 1719 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 1757 1720 if (gpmc_context.cs_context[i].is_valid) { 1758 1721 gpmc_context.cs_context[i].config1 = ··· 1784 1747 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 1785 1748 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 1786 1749 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 1787 - for (i = 0; i < GPMC_CS_NUM; i++) { 1750 + for (i = 0; i < gpmc_cs_num; i++) { 1788 1751 if (gpmc_context.cs_context[i].is_valid) { 1789 1752 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 1790 1753 gpmc_context.cs_context[i].config1);