tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add MMHUB 2.0 register headers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher f519f0be be4008b8

+10293
+927
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_default.h
··· 1 + /* 2 + * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _mmhub_2_0_0_DEFAULT_HEADER 22 + #define _mmhub_2_0_0_DEFAULT_HEADER 23 + 24 + 25 + // addressBlock: mmhub_dagbdec 26 + #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 27 + #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 28 + #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 29 + #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 30 + #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 31 + #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 32 + #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 33 + #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 34 + #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 35 + #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 36 + #define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 37 + #define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 38 + #define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 39 + #define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 40 + #define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 41 + #define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 42 + #define mmDAGB0_RDCLI16_DEFAULT 0xfe5fe0f9 43 + #define mmDAGB0_RDCLI17_DEFAULT 0xfe5fe0f9 44 + #define mmDAGB0_RDCLI18_DEFAULT 0xfe5fe0f9 45 + #define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 46 + #define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x00003046 47 + #define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 48 + #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 49 + #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 50 + #define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 51 + #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 52 + #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 53 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 54 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 55 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 56 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 57 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 58 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 59 + #define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 60 + #define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 61 + #define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 62 + #define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 63 + #define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 64 + #define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 65 + #define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 66 + #define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 67 + #define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a0e408 68 + #define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 69 + #define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 70 + #define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 71 + #define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 72 + #define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 73 + #define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 74 + #define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 75 + #define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 76 + #define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 77 + #define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 78 + #define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 79 + #define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 80 + #define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 81 + #define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 82 + #define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 83 + #define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 84 + #define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 85 + #define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 86 + #define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 87 + #define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 88 + #define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 89 + #define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 90 + #define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 91 + #define mmDAGB0_WRCLI16_DEFAULT 0xfe5fe0f9 92 + #define mmDAGB0_WRCLI17_DEFAULT 0xfe5fe0f9 93 + #define mmDAGB0_WRCLI18_DEFAULT 0xfe5fe0f9 94 + #define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 95 + #define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x00003046 96 + #define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 97 + #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 98 + #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 99 + #define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 100 + #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 101 + #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 102 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 103 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 104 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 105 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 106 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_DEFAULT 0x88888888 107 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_DEFAULT 0x11111111 108 + #define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 109 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 110 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 111 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 112 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 113 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_DEFAULT 0x11111111 114 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_DEFAULT 0x00000000 115 + #define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 116 + #define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 117 + #define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 118 + #define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 119 + #define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 120 + #define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 121 + #define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 122 + #define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 123 + #define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a0e408 124 + #define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 125 + #define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x60606070 126 + #define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 127 + #define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 128 + #define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 129 + #define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 130 + #define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 131 + #define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 132 + #define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 133 + #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 134 + #define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 135 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_DEFAULT 0x00000000 136 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_DEFAULT 0x00000000 137 + #define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 138 + #define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa 139 + #define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 140 + #define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff 141 + #define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 142 + #define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff 143 + #define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff 144 + #define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 145 + #define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 146 + #define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 147 + #define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 148 + #define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 149 + #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 150 + #define mmDAGB0_RESERVE0_DEFAULT 0xffffffff 151 + #define mmDAGB0_RESERVE1_DEFAULT 0xffffffff 152 + #define mmDAGB0_RESERVE2_DEFAULT 0xffffffff 153 + #define mmDAGB0_RESERVE3_DEFAULT 0xffffffff 154 + #define mmDAGB0_RESERVE4_DEFAULT 0xffffffff 155 + #define mmDAGB0_RESERVE5_DEFAULT 0xffffffff 156 + #define mmDAGB0_RESERVE6_DEFAULT 0xffffffff 157 + #define mmDAGB0_RESERVE7_DEFAULT 0xffffffff 158 + #define mmDAGB0_RESERVE8_DEFAULT 0xffffffff 159 + #define mmDAGB0_RESERVE9_DEFAULT 0xffffffff 160 + #define mmDAGB0_RESERVE10_DEFAULT 0xffffffff 161 + #define mmDAGB0_RESERVE11_DEFAULT 0xffffffff 162 + #define mmDAGB0_RESERVE12_DEFAULT 0xffffffff 163 + #define mmDAGB0_RESERVE13_DEFAULT 0xffffffff 164 + #define mmDAGB0_RESERVE14_DEFAULT 0xffffffff 165 + #define mmDAGB0_RESERVE15_DEFAULT 0xffffffff 166 + #define mmDAGB0_RESERVE16_DEFAULT 0xffffffff 167 + #define mmDAGB0_RESERVE17_DEFAULT 0xffffffff 168 + #define mmDAGB0_RESERVE18_DEFAULT 0xffffffff 169 + #define mmDAGB0_RESERVE19_DEFAULT 0xffffffff 170 + #define mmDAGB0_RESERVE20_DEFAULT 0xffffffff 171 + #define mmDAGB0_RESERVE21_DEFAULT 0xffffffff 172 + #define mmDAGB0_RESERVE22_DEFAULT 0xffffffff 173 + #define mmDAGB0_RESERVE23_DEFAULT 0xffffffff 174 + #define mmDAGB0_RESERVE24_DEFAULT 0xffffffff 175 + #define mmDAGB0_RESERVE25_DEFAULT 0xffffffff 176 + #define mmDAGB0_RESERVE26_DEFAULT 0xffffffff 177 + #define mmDAGB0_RESERVE27_DEFAULT 0xffffffff 178 + #define mmDAGB0_RESERVE28_DEFAULT 0xffffffff 179 + #define mmDAGB0_RESERVE29_DEFAULT 0xffffffff 180 + #define mmDAGB0_RESERVE30_DEFAULT 0xffffffff 181 + #define mmDAGB0_RESERVE31_DEFAULT 0xffffffff 182 + #define mmDAGB0_RESERVE32_DEFAULT 0xffffffff 183 + #define mmDAGB0_RESERVE33_DEFAULT 0xffffffff 184 + #define mmDAGB0_RESERVE34_DEFAULT 0xffffffff 185 + #define mmDAGB0_RESERVE35_DEFAULT 0xffffffff 186 + #define mmDAGB0_RESERVE36_DEFAULT 0xffffffff 187 + #define mmDAGB0_RESERVE37_DEFAULT 0xffffffff 188 + #define mmDAGB0_RESERVE38_DEFAULT 0xffffffff 189 + #define mmDAGB0_RESERVE39_DEFAULT 0xffffffff 190 + #define mmDAGB0_RESERVE40_DEFAULT 0xffffffff 191 + #define mmDAGB0_RESERVE41_DEFAULT 0xffffffff 192 + #define mmDAGB0_RESERVE42_DEFAULT 0xffffffff 193 + #define mmDAGB0_RESERVE43_DEFAULT 0xffffffff 194 + #define mmDAGB0_RESERVE44_DEFAULT 0xffffffff 195 + #define mmDAGB0_RESERVE45_DEFAULT 0xffffffff 196 + #define mmDAGB0_RESERVE46_DEFAULT 0xffffffff 197 + #define mmDAGB0_RESERVE47_DEFAULT 0xffffffff 198 + #define mmDAGB0_RESERVE48_DEFAULT 0xffffffff 199 + #define mmDAGB0_RESERVE49_DEFAULT 0xffffffff 200 + #define mmDAGB0_RESERVE50_DEFAULT 0xffffffff 201 + #define mmDAGB0_RESERVE51_DEFAULT 0xffffffff 202 + #define mmDAGB0_RESERVE52_DEFAULT 0xffffffff 203 + #define mmDAGB0_RESERVE53_DEFAULT 0xffffffff 204 + #define mmDAGB0_RESERVE54_DEFAULT 0xffffffff 205 + #define mmDAGB0_RESERVE55_DEFAULT 0xffffffff 206 + #define mmDAGB0_RESERVE56_DEFAULT 0xffffffff 207 + #define mmDAGB0_RESERVE57_DEFAULT 0xffffffff 208 + #define mmDAGB0_RESERVE58_DEFAULT 0xffffffff 209 + #define mmDAGB0_RESERVE59_DEFAULT 0xffffffff 210 + #define mmDAGB0_RESERVE60_DEFAULT 0xffffffff 211 + #define mmDAGB0_RESERVE61_DEFAULT 0xffffffff 212 + #define mmDAGB0_RESERVE62_DEFAULT 0xffffffff 213 + #define mmDAGB0_RESERVE63_DEFAULT 0xffffffff 214 + #define mmDAGB0_RESERVE64_DEFAULT 0xffffffff 215 + #define mmDAGB0_RESERVE65_DEFAULT 0xffffffff 216 + #define mmDAGB0_RESERVE66_DEFAULT 0xffffffff 217 + #define mmDAGB0_RESERVE67_DEFAULT 0xffffffff 218 + #define mmDAGB0_RESERVE68_DEFAULT 0xffffffff 219 + #define mmDAGB0_RESERVE69_DEFAULT 0xffffffff 220 + #define mmDAGB0_RESERVE70_DEFAULT 0xffffffff 221 + #define mmDAGB0_RESERVE71_DEFAULT 0xffffffff 222 + #define mmDAGB0_RESERVE72_DEFAULT 0xffffffff 223 + #define mmDAGB0_RESERVE73_DEFAULT 0xffffffff 224 + #define mmDAGB0_RESERVE74_DEFAULT 0xffffffff 225 + #define mmDAGB0_RESERVE75_DEFAULT 0xffffffff 226 + #define mmDAGB0_RESERVE76_DEFAULT 0xffffffff 227 + #define mmDAGB0_RESERVE77_DEFAULT 0xffffffff 228 + #define mmDAGB0_RESERVE78_DEFAULT 0xffffffff 229 + #define mmDAGB0_RESERVE79_DEFAULT 0xffffffff 230 + #define mmDAGB0_RESERVE80_DEFAULT 0xffffffff 231 + #define mmDAGB0_RESERVE81_DEFAULT 0xffffffff 232 + #define mmDAGB0_RESERVE82_DEFAULT 0xffffffff 233 + #define mmDAGB0_RESERVE83_DEFAULT 0xffffffff 234 + #define mmDAGB0_RESERVE84_DEFAULT 0xffffffff 235 + #define mmDAGB0_RESERVE85_DEFAULT 0xffffffff 236 + #define mmDAGB0_RESERVE86_DEFAULT 0xffffffff 237 + #define mmDAGB0_RESERVE87_DEFAULT 0xffffffff 238 + #define mmDAGB0_RESERVE88_DEFAULT 0xffffffff 239 + #define mmDAGB0_RESERVE89_DEFAULT 0xffffffff 240 + #define mmDAGB0_RESERVE90_DEFAULT 0xffffffff 241 + #define mmDAGB0_RESERVE91_DEFAULT 0xffffffff 242 + #define mmDAGB0_RESERVE92_DEFAULT 0xffffffff 243 + #define mmDAGB0_RESERVE93_DEFAULT 0xffffffff 244 + #define mmDAGB0_RESERVE94_DEFAULT 0xffffffff 245 + #define mmDAGB0_RESERVE95_DEFAULT 0xffffffff 246 + #define mmDAGB0_RESERVE96_DEFAULT 0xffffffff 247 + #define mmDAGB0_RESERVE97_DEFAULT 0xffffffff 248 + #define mmDAGB0_RESERVE98_DEFAULT 0xffffffff 249 + #define mmDAGB0_RESERVE99_DEFAULT 0xffffffff 250 + #define mmDAGB0_RESERVE100_DEFAULT 0xffffffff 251 + #define mmDAGB0_RESERVE101_DEFAULT 0xffffffff 252 + #define mmDAGB0_RESERVE102_DEFAULT 0xffffffff 253 + #define mmDAGB0_RESERVE103_DEFAULT 0xffffffff 254 + #define mmDAGB0_RESERVE104_DEFAULT 0xffffffff 255 + #define mmDAGB0_RESERVE105_DEFAULT 0xffffffff 256 + #define mmDAGB0_RESERVE106_DEFAULT 0xffffffff 257 + #define mmDAGB0_RESERVE107_DEFAULT 0xffffffff 258 + #define mmDAGB0_RESERVE108_DEFAULT 0xffffffff 259 + #define mmDAGB0_RESERVE109_DEFAULT 0xffffffff 260 + #define mmDAGB0_RESERVE110_DEFAULT 0xffffffff 261 + #define mmDAGB0_RESERVE111_DEFAULT 0xffffffff 262 + #define mmDAGB0_RESERVE112_DEFAULT 0xffffffff 263 + #define mmDAGB0_RESERVE113_DEFAULT 0xffffffff 264 + #define mmDAGB0_RESERVE114_DEFAULT 0xffffffff 265 + #define mmDAGB0_RESERVE115_DEFAULT 0xffffffff 266 + #define mmDAGB0_RESERVE116_DEFAULT 0xffffffff 267 + #define mmDAGB0_RESERVE117_DEFAULT 0xffffffff 268 + #define mmDAGB0_RESERVE118_DEFAULT 0xffffffff 269 + #define mmDAGB0_RESERVE119_DEFAULT 0xffffffff 270 + #define mmDAGB0_RESERVE120_DEFAULT 0xffffffff 271 + #define mmDAGB0_RESERVE121_DEFAULT 0xffffffff 272 + #define mmDAGB0_RESERVE122_DEFAULT 0xffffffff 273 + #define mmDAGB0_RESERVE123_DEFAULT 0xffffffff 274 + #define mmDAGB0_RESERVE124_DEFAULT 0xffffffff 275 + #define mmDAGB0_RESERVE125_DEFAULT 0xffffffff 276 + #define mmDAGB0_RESERVE126_DEFAULT 0xffffffff 277 + #define mmDAGB0_RESERVE127_DEFAULT 0xffffffff 278 + #define mmDAGB0_RESERVE128_DEFAULT 0xffffffff 279 + #define mmDAGB0_RESERVE129_DEFAULT 0xffffffff 280 + #define mmDAGB0_RESERVE130_DEFAULT 0xffffffff 281 + #define mmDAGB0_RESERVE131_DEFAULT 0xffffffff 282 + 283 + 284 + // addressBlock: mmhub_mmea_mmeadec 285 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 286 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 287 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 288 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 289 + #define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 290 + #define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 291 + #define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x78000924 292 + #define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x78000924 293 + #define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x16db4444 294 + #define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x16db4444 295 + #define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 296 + #define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 297 + #define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 298 + #define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 299 + #define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 300 + #define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 301 + #define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 302 + #define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 303 + #define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 304 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 305 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 306 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 307 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 308 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 309 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 310 + #define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 311 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 312 + #define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 313 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 314 + #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 315 + #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_DEFAULT 0x00000000 316 + #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_DEFAULT 0x00000000 317 + #define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef 318 + #define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0xfffff000 319 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 320 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 321 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 322 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 323 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 324 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 325 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 326 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 327 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 328 + #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 329 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_DEFAULT 0x00000000 330 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_DEFAULT 0x00000000 331 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_DEFAULT 0x00000000 332 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_DEFAULT 0x00000000 333 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 334 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 335 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 336 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 337 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 338 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 339 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 340 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 341 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe 342 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe 343 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 344 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 345 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 346 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 347 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 348 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 349 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 350 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 351 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 352 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 353 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 354 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 355 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 356 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 357 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 358 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 359 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 360 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 361 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 362 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 363 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 364 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 365 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe 366 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe 367 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe 368 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe 369 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 370 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 371 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 372 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 373 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 374 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 375 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 376 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 377 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 378 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 379 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 380 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 381 + #define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 382 + #define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 383 + #define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 384 + #define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 385 + #define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 386 + #define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 387 + #define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 388 + #define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 389 + #define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 390 + #define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 391 + #define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 392 + #define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 393 + #define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 394 + #define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 395 + #define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 396 + #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 397 + #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_DEFAULT 0xffffffff 398 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 399 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 400 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff 401 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f 402 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f 403 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff 404 + #define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00101e40 405 + #define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff 406 + #define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 407 + #define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 408 + #define mmMMEA0_SDP_CREDITS_DEFAULT 0x000101bf 409 + #define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 410 + #define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 411 + #define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 412 + #define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 413 + #define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 414 + #define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 415 + #define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f 416 + #define mmMMEA0_MISC_DEFAULT 0x0c00a070 417 + #define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 418 + #define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 419 + #define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 420 + #define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 421 + #define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 422 + #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 423 + #define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 424 + #define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 425 + #define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 426 + #define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 427 + #define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 428 + #define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 429 + #define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 430 + #define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 431 + #define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 432 + #define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 433 + #define mmMMEA0_ERR_STATUS_DEFAULT 0x00000300 434 + #define mmMMEA0_MISC2_DEFAULT 0x00000000 435 + #define mmMMEA0_ADDRDEC_SELECT_DEFAULT 0x00000000 436 + 437 + 438 + // addressBlock: mmhub_pctldec 439 + #define mmPCTL_MISC_DEFAULT 0x00000889 440 + #define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 441 + #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 442 + #define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 443 + #define mmPCTL_PG_DAGB_DEFAULT 0x00000000 444 + #define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 445 + #define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 446 + #define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 447 + #define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 448 + #define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 449 + #define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 450 + #define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 451 + #define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 452 + #define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 453 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 454 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 455 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 456 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 457 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 458 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff 459 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 460 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 461 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 462 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 463 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 464 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 465 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff 466 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 467 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 468 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a 469 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 470 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_DEFAULT 0x00000000 471 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_DEFAULT 0x00000000 472 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff 473 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff 474 + #define mmPCTL0_MISC_DEFAULT 0x00011000 475 + #define mmPCTL1_MISC_DEFAULT 0x00000800 476 + #define mmPCTL2_MISC_DEFAULT 0x00000800 477 + #define mmPCTL_PERFCOUNTER_LO_DEFAULT 0x00000000 478 + #define mmPCTL_PERFCOUNTER_HI_DEFAULT 0x00000000 479 + #define mmPCTL_PERFCOUNTER0_CFG_DEFAULT 0x00000000 480 + #define mmPCTL_PERFCOUNTER1_CFG_DEFAULT 0x00000000 481 + #define mmPCTL_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 482 + 483 + 484 + // addressBlock: mmhub_l1tlb_mmvml1pfdec 485 + #define mmMMMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 486 + #define mmMMMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 487 + #define mmMMMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 488 + #define mmMMMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 489 + #define mmMMMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 490 + #define mmMMMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 491 + #define mmMMMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 492 + #define mmMMMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 493 + 494 + 495 + // addressBlock: mmhub_l1tlb_mmvml1pldec 496 + #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 497 + #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 498 + #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 499 + #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 500 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 501 + 502 + 503 + // addressBlock: mmhub_l1tlb_mmvml1prdec 504 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 505 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 506 + 507 + 508 + // addressBlock: mmhub_mmutcl2_mmatcl2dec 509 + #define mmMM_ATC_L2_CNTL_DEFAULT 0x000001c0 510 + #define mmMM_ATC_L2_CNTL2_DEFAULT 0x00000100 511 + #define mmMM_ATC_L2_CACHE_DATA0_DEFAULT 0x00000000 512 + #define mmMM_ATC_L2_CACHE_DATA1_DEFAULT 0x00000000 513 + #define mmMM_ATC_L2_CACHE_DATA2_DEFAULT 0x00000000 514 + #define mmMM_ATC_L2_CNTL3_DEFAULT 0x000001f8 515 + #define mmMM_ATC_L2_STATUS_DEFAULT 0x00000000 516 + #define mmMM_ATC_L2_STATUS2_DEFAULT 0x00000000 517 + #define mmMM_ATC_L2_MISC_CG_DEFAULT 0x00000200 518 + #define mmMM_ATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 519 + #define mmMM_ATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 520 + #define mmMM_ATC_L2_SDPPORT_CTRL_DEFAULT 0x000003ff 521 + 522 + 523 + // addressBlock: mmhub_mmutcl2_mmvml2pfdec 524 + #define mmMMVM_L2_CNTL_DEFAULT 0x00080602 525 + #define mmMMVM_L2_CNTL2_DEFAULT 0x00000000 526 + #define mmMMVM_L2_CNTL3_DEFAULT 0x80100007 527 + #define mmMMVM_L2_STATUS_DEFAULT 0x00000000 528 + #define mmMMVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 529 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 530 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 531 + #define mmMMVM_INVALIDATE_CNTL_DEFAULT 0x0000010f 532 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc 533 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 534 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff 535 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff 536 + #define mmMMVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 537 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 538 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 539 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 540 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 541 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 542 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 543 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 544 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 545 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 546 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 547 + #define mmMMVM_L2_CNTL4_DEFAULT 0x000000c1 548 + #define mmMMVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 549 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 550 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 551 + #define mmMMVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 552 + #define mmMMVM_L2_IH_LOG_CNTL_DEFAULT 0x00000002 553 + #define mmMMVM_L2_IH_LOG_BUSY_DEFAULT 0x00000000 554 + #define mmMMVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 555 + #define mmMMVM_L2_CNTL5_DEFAULT 0x00003fe0 556 + #define mmMMVM_L2_GCR_CNTL_DEFAULT 0x00000000 557 + #define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_DEFAULT 0x00000000 558 + #define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 559 + #define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_DEFAULT 0x00000000 560 + #define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_DEFAULT 0x00000000 561 + 562 + 563 + // addressBlock: mmhub_mmutcl2_mmvml2vcdec 564 + #define mmMMVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 565 + #define mmMMVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 566 + #define mmMMVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 567 + #define mmMMVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 568 + #define mmMMVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 569 + #define mmMMVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 570 + #define mmMMVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 571 + #define mmMMVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 572 + #define mmMMVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 573 + #define mmMMVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 574 + #define mmMMVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 575 + #define mmMMVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 576 + #define mmMMVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 577 + #define mmMMVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 578 + #define mmMMVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 579 + #define mmMMVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 580 + #define mmMMVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 581 + #define mmMMVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 582 + #define mmMMVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 583 + #define mmMMVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 584 + #define mmMMVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 585 + #define mmMMVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 586 + #define mmMMVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 587 + #define mmMMVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 588 + #define mmMMVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 589 + #define mmMMVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 590 + #define mmMMVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 591 + #define mmMMVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 592 + #define mmMMVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 593 + #define mmMMVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 594 + #define mmMMVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 595 + #define mmMMVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 596 + #define mmMMVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 597 + #define mmMMVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 598 + #define mmMMVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 599 + #define mmMMVM_INVALIDATE_ENG0_REQ_DEFAULT 0x02f80000 600 + #define mmMMVM_INVALIDATE_ENG1_REQ_DEFAULT 0x02f80000 601 + #define mmMMVM_INVALIDATE_ENG2_REQ_DEFAULT 0x02f80000 602 + #define mmMMVM_INVALIDATE_ENG3_REQ_DEFAULT 0x02f80000 603 + #define mmMMVM_INVALIDATE_ENG4_REQ_DEFAULT 0x02f80000 604 + #define mmMMVM_INVALIDATE_ENG5_REQ_DEFAULT 0x02f80000 605 + #define mmMMVM_INVALIDATE_ENG6_REQ_DEFAULT 0x02f80000 606 + #define mmMMVM_INVALIDATE_ENG7_REQ_DEFAULT 0x02f80000 607 + #define mmMMVM_INVALIDATE_ENG8_REQ_DEFAULT 0x02f80000 608 + #define mmMMVM_INVALIDATE_ENG9_REQ_DEFAULT 0x02f80000 609 + #define mmMMVM_INVALIDATE_ENG10_REQ_DEFAULT 0x02f80000 610 + #define mmMMVM_INVALIDATE_ENG11_REQ_DEFAULT 0x02f80000 611 + #define mmMMVM_INVALIDATE_ENG12_REQ_DEFAULT 0x02f80000 612 + #define mmMMVM_INVALIDATE_ENG13_REQ_DEFAULT 0x02f80000 613 + #define mmMMVM_INVALIDATE_ENG14_REQ_DEFAULT 0x02f80000 614 + #define mmMMVM_INVALIDATE_ENG15_REQ_DEFAULT 0x02f80000 615 + #define mmMMVM_INVALIDATE_ENG16_REQ_DEFAULT 0x02f80000 616 + #define mmMMVM_INVALIDATE_ENG17_REQ_DEFAULT 0x02f80000 617 + #define mmMMVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 618 + #define mmMMVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 619 + #define mmMMVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 620 + #define mmMMVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 621 + #define mmMMVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 622 + #define mmMMVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 623 + #define mmMMVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 624 + #define mmMMVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 625 + #define mmMMVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 626 + #define mmMMVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 627 + #define mmMMVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 628 + #define mmMMVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 629 + #define mmMMVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 630 + #define mmMMVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 631 + #define mmMMVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 632 + #define mmMMVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 633 + #define mmMMVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 634 + #define mmMMVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 635 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 636 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 637 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 638 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 639 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 640 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 641 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 642 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 643 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 644 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 645 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 646 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 647 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 648 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 649 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 650 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 651 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 652 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 653 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 654 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 655 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 656 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 657 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 658 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 659 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 660 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 661 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 662 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 663 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 664 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 665 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 666 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 667 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 668 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 669 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 670 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 671 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 672 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 673 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 674 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 675 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 676 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 677 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 678 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 679 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 680 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 681 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 682 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 683 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 684 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 685 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 686 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 687 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 688 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 689 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 690 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 691 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 692 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 693 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 694 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 695 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 696 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 697 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 698 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 699 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 700 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 701 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 702 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 703 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 704 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 705 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 706 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 707 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 708 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 709 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 710 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 711 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 712 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 713 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 714 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 715 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 716 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 717 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 718 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 719 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 720 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 721 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 722 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 723 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 724 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 725 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 726 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 727 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 728 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 729 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 730 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 731 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 732 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 733 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 734 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 735 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 736 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 737 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 738 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 739 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 740 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 741 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 742 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 743 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 744 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 745 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 746 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 747 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 748 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 749 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 750 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 751 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 752 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 753 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 754 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 755 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 756 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 757 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 758 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 759 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 760 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 761 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 762 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 763 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 764 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 765 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 766 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 767 + 768 + 769 + // addressBlock: mmhub_mmutcl2_mmvml2pldec 770 + #define mmMMMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 771 + #define mmMMMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 772 + #define mmMMMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 773 + #define mmMMMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 774 + #define mmMMMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 775 + #define mmMMMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 776 + #define mmMMMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 777 + #define mmMMMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 778 + #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 779 + 780 + 781 + // addressBlock: mmhub_mmutcl2_mmvml2prdec 782 + #define mmMMMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 783 + #define mmMMMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 784 + 785 + 786 + // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 787 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 788 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 789 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 790 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 791 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 792 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 793 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 794 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 795 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 796 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 797 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 798 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 799 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 800 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 801 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 802 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 803 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF16_DEFAULT 0x00000000 804 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF17_DEFAULT 0x00000000 805 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF18_DEFAULT 0x00000000 806 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF19_DEFAULT 0x00000000 807 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF20_DEFAULT 0x00000000 808 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF21_DEFAULT 0x00000000 809 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF22_DEFAULT 0x00000000 810 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF23_DEFAULT 0x00000000 811 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF24_DEFAULT 0x00000000 812 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF25_DEFAULT 0x00000000 813 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF26_DEFAULT 0x00000000 814 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF27_DEFAULT 0x00000000 815 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF28_DEFAULT 0x00000000 816 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF29_DEFAULT 0x00000000 817 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF30_DEFAULT 0x00000000 818 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF31_DEFAULT 0x00000000 819 + #define mmMMVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 820 + #define mmMMMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 821 + #define mmMMMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 822 + #define mmMMMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 823 + #define mmMMMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 824 + #define mmMMMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 825 + #define mmMMMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 826 + #define mmMMMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 827 + #define mmMMMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 828 + #define mmMMMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 829 + #define mmMMMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 830 + #define mmMMMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 831 + #define mmMMMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 832 + #define mmMMMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 833 + #define mmMMMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 834 + #define mmMMMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 835 + #define mmMMMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 836 + #define mmMMMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 837 + #define mmMMMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 838 + #define mmMMMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 839 + #define mmMMMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 840 + #define mmMMMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 841 + #define mmMMMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 842 + #define mmMMMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 843 + #define mmMMMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 844 + #define mmMMVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 845 + #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 846 + #define mmMMVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 847 + #define mmMMVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 848 + #define mmMMVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 849 + #define mmMMVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 850 + #define mmMMVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 851 + #define mmMMVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 852 + #define mmMMVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 853 + #define mmMMVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 854 + #define mmMMVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 855 + #define mmMMVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 856 + #define mmMMVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 857 + #define mmMMVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 858 + #define mmMMVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 859 + #define mmMMVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 860 + #define mmMMVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 861 + #define mmMMVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 862 + #define mmMMVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 863 + #define mmMMVM_PCIE_ATS_CNTL_VF_16_DEFAULT 0x00000000 864 + #define mmMMVM_PCIE_ATS_CNTL_VF_17_DEFAULT 0x00000000 865 + #define mmMMVM_PCIE_ATS_CNTL_VF_18_DEFAULT 0x00000000 866 + #define mmMMVM_PCIE_ATS_CNTL_VF_19_DEFAULT 0x00000000 867 + #define mmMMVM_PCIE_ATS_CNTL_VF_20_DEFAULT 0x00000000 868 + #define mmMMVM_PCIE_ATS_CNTL_VF_21_DEFAULT 0x00000000 869 + #define mmMMVM_PCIE_ATS_CNTL_VF_22_DEFAULT 0x00000000 870 + #define mmMMVM_PCIE_ATS_CNTL_VF_23_DEFAULT 0x00000000 871 + #define mmMMVM_PCIE_ATS_CNTL_VF_24_DEFAULT 0x00000000 872 + #define mmMMVM_PCIE_ATS_CNTL_VF_25_DEFAULT 0x00000000 873 + #define mmMMVM_PCIE_ATS_CNTL_VF_26_DEFAULT 0x00000000 874 + #define mmMMVM_PCIE_ATS_CNTL_VF_27_DEFAULT 0x00000000 875 + #define mmMMVM_PCIE_ATS_CNTL_VF_28_DEFAULT 0x00000000 876 + #define mmMMVM_PCIE_ATS_CNTL_VF_29_DEFAULT 0x00000000 877 + #define mmMMVM_PCIE_ATS_CNTL_VF_30_DEFAULT 0x00000000 878 + #define mmMMVM_PCIE_ATS_CNTL_VF_31_DEFAULT 0x00000000 879 + #define mmMMUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 880 + #define mmMMMC_SHARED_ACTIVE_FCN_ID_DEFAULT 0x00000000 881 + 882 + 883 + // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 884 + #define mmMMMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 885 + #define mmMMMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 886 + #define mmMMMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 887 + #define mmMMMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 888 + #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 889 + #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 890 + #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 891 + #define mmMMMC_VM_FB_OFFSET_DEFAULT 0x00000000 892 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 893 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 894 + #define mmMMMC_VM_STEERING_DEFAULT 0x00000001 895 + #define mmMMMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 896 + #define mmMMMC_MEM_POWER_LS_DEFAULT 0x00000208 897 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 898 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 899 + #define mmMMMC_VM_APT_CNTL_DEFAULT 0x00000000 900 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 901 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 902 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff 903 + #define mmMMMC_SHARED_VIRT_RESET_REQ2_DEFAULT 0x00000000 904 + 905 + 906 + // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 907 + #define mmMMMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 908 + #define mmMMMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 909 + #define mmMMMC_VM_AGP_TOP_DEFAULT 0x00000000 910 + #define mmMMMC_VM_AGP_BOT_DEFAULT 0x00000000 911 + #define mmMMMC_VM_AGP_BASE_DEFAULT 0x00000000 912 + #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 913 + #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 914 + #define mmMMMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00000501 915 + 916 + 917 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 918 + #define mmMM_ATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 919 + #define mmMM_ATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 920 + 921 + 922 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 923 + #define mmMM_ATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 924 + #define mmMM_ATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 925 + #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 926 + 927 + #endif
+1799
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
··· 1 + /* 2 + * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _mmhub_2_0_0_OFFSET_HEADER 22 + #define _mmhub_2_0_0_OFFSET_HEADER 23 + 24 + 25 + 26 + // addressBlock: mmhub_dagbdec 27 + // base address: 0x68000 28 + #define mmDAGB0_RDCLI0 0x0000 29 + #define mmDAGB0_RDCLI0_BASE_IDX 0 30 + #define mmDAGB0_RDCLI1 0x0001 31 + #define mmDAGB0_RDCLI1_BASE_IDX 0 32 + #define mmDAGB0_RDCLI2 0x0002 33 + #define mmDAGB0_RDCLI2_BASE_IDX 0 34 + #define mmDAGB0_RDCLI3 0x0003 35 + #define mmDAGB0_RDCLI3_BASE_IDX 0 36 + #define mmDAGB0_RDCLI4 0x0004 37 + #define mmDAGB0_RDCLI4_BASE_IDX 0 38 + #define mmDAGB0_RDCLI5 0x0005 39 + #define mmDAGB0_RDCLI5_BASE_IDX 0 40 + #define mmDAGB0_RDCLI6 0x0006 41 + #define mmDAGB0_RDCLI6_BASE_IDX 0 42 + #define mmDAGB0_RDCLI7 0x0007 43 + #define mmDAGB0_RDCLI7_BASE_IDX 0 44 + #define mmDAGB0_RDCLI8 0x0008 45 + #define mmDAGB0_RDCLI8_BASE_IDX 0 46 + #define mmDAGB0_RDCLI9 0x0009 47 + #define mmDAGB0_RDCLI9_BASE_IDX 0 48 + #define mmDAGB0_RDCLI10 0x000a 49 + #define mmDAGB0_RDCLI10_BASE_IDX 0 50 + #define mmDAGB0_RDCLI11 0x000b 51 + #define mmDAGB0_RDCLI11_BASE_IDX 0 52 + #define mmDAGB0_RDCLI12 0x000c 53 + #define mmDAGB0_RDCLI12_BASE_IDX 0 54 + #define mmDAGB0_RDCLI13 0x000d 55 + #define mmDAGB0_RDCLI13_BASE_IDX 0 56 + #define mmDAGB0_RDCLI14 0x000e 57 + #define mmDAGB0_RDCLI14_BASE_IDX 0 58 + #define mmDAGB0_RDCLI15 0x000f 59 + #define mmDAGB0_RDCLI15_BASE_IDX 0 60 + #define mmDAGB0_RDCLI16 0x0010 61 + #define mmDAGB0_RDCLI16_BASE_IDX 0 62 + #define mmDAGB0_RDCLI17 0x0011 63 + #define mmDAGB0_RDCLI17_BASE_IDX 0 64 + #define mmDAGB0_RDCLI18 0x0012 65 + #define mmDAGB0_RDCLI18_BASE_IDX 0 66 + #define mmDAGB0_RD_CNTL 0x0013 67 + #define mmDAGB0_RD_CNTL_BASE_IDX 0 68 + #define mmDAGB0_RD_GMI_CNTL 0x0014 69 + #define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0 70 + #define mmDAGB0_RD_ADDR_DAGB 0x0015 71 + #define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0 72 + #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0016 73 + #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 74 + #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0017 75 + #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 76 + #define mmDAGB0_RD_CGTT_CLK_CTRL 0x0018 77 + #define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0 78 + #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0019 79 + #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0 80 + #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x001a 81 + #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0 82 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001b 83 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 84 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001c 85 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 86 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001d 87 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 88 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001e 89 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 90 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x001f 91 + #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 92 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0020 93 + #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 94 + #define mmDAGB0_RD_VC0_CNTL 0x0021 95 + #define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0 96 + #define mmDAGB0_RD_VC1_CNTL 0x0022 97 + #define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0 98 + #define mmDAGB0_RD_VC2_CNTL 0x0023 99 + #define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0 100 + #define mmDAGB0_RD_VC3_CNTL 0x0024 101 + #define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0 102 + #define mmDAGB0_RD_VC4_CNTL 0x0025 103 + #define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0 104 + #define mmDAGB0_RD_VC5_CNTL 0x0026 105 + #define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0 106 + #define mmDAGB0_RD_VC6_CNTL 0x0027 107 + #define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0 108 + #define mmDAGB0_RD_VC7_CNTL 0x0028 109 + #define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0 110 + #define mmDAGB0_RD_CNTL_MISC 0x0029 111 + #define mmDAGB0_RD_CNTL_MISC_BASE_IDX 0 112 + #define mmDAGB0_RD_TLB_CREDIT 0x002a 113 + #define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 0 114 + #define mmDAGB0_RDCLI_ASK_PENDING 0x002b 115 + #define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0 116 + #define mmDAGB0_RDCLI_GO_PENDING 0x002c 117 + #define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 0 118 + #define mmDAGB0_RDCLI_GBLSEND_PENDING 0x002d 119 + #define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0 120 + #define mmDAGB0_RDCLI_TLB_PENDING 0x002e 121 + #define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0 122 + #define mmDAGB0_RDCLI_OARB_PENDING 0x002f 123 + #define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0 124 + #define mmDAGB0_RDCLI_OSD_PENDING 0x0030 125 + #define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0 126 + #define mmDAGB0_WRCLI0 0x0031 127 + #define mmDAGB0_WRCLI0_BASE_IDX 0 128 + #define mmDAGB0_WRCLI1 0x0032 129 + #define mmDAGB0_WRCLI1_BASE_IDX 0 130 + #define mmDAGB0_WRCLI2 0x0033 131 + #define mmDAGB0_WRCLI2_BASE_IDX 0 132 + #define mmDAGB0_WRCLI3 0x0034 133 + #define mmDAGB0_WRCLI3_BASE_IDX 0 134 + #define mmDAGB0_WRCLI4 0x0035 135 + #define mmDAGB0_WRCLI4_BASE_IDX 0 136 + #define mmDAGB0_WRCLI5 0x0036 137 + #define mmDAGB0_WRCLI5_BASE_IDX 0 138 + #define mmDAGB0_WRCLI6 0x0037 139 + #define mmDAGB0_WRCLI6_BASE_IDX 0 140 + #define mmDAGB0_WRCLI7 0x0038 141 + #define mmDAGB0_WRCLI7_BASE_IDX 0 142 + #define mmDAGB0_WRCLI8 0x0039 143 + #define mmDAGB0_WRCLI8_BASE_IDX 0 144 + #define mmDAGB0_WRCLI9 0x003a 145 + #define mmDAGB0_WRCLI9_BASE_IDX 0 146 + #define mmDAGB0_WRCLI10 0x003b 147 + #define mmDAGB0_WRCLI10_BASE_IDX 0 148 + #define mmDAGB0_WRCLI11 0x003c 149 + #define mmDAGB0_WRCLI11_BASE_IDX 0 150 + #define mmDAGB0_WRCLI12 0x003d 151 + #define mmDAGB0_WRCLI12_BASE_IDX 0 152 + #define mmDAGB0_WRCLI13 0x003e 153 + #define mmDAGB0_WRCLI13_BASE_IDX 0 154 + #define mmDAGB0_WRCLI14 0x003f 155 + #define mmDAGB0_WRCLI14_BASE_IDX 0 156 + #define mmDAGB0_WRCLI15 0x0040 157 + #define mmDAGB0_WRCLI15_BASE_IDX 0 158 + #define mmDAGB0_WRCLI16 0x0041 159 + #define mmDAGB0_WRCLI16_BASE_IDX 0 160 + #define mmDAGB0_WRCLI17 0x0042 161 + #define mmDAGB0_WRCLI17_BASE_IDX 0 162 + #define mmDAGB0_WRCLI18 0x0043 163 + #define mmDAGB0_WRCLI18_BASE_IDX 0 164 + #define mmDAGB0_WR_CNTL 0x0044 165 + #define mmDAGB0_WR_CNTL_BASE_IDX 0 166 + #define mmDAGB0_WR_GMI_CNTL 0x0045 167 + #define mmDAGB0_WR_GMI_CNTL_BASE_IDX 0 168 + #define mmDAGB0_WR_ADDR_DAGB 0x0046 169 + #define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 0 170 + #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0047 171 + #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0 172 + #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0048 173 + #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0 174 + #define mmDAGB0_WR_CGTT_CLK_CTRL 0x0049 175 + #define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0 176 + #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x004a 177 + #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0 178 + #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x004b 179 + #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0 180 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x004c 181 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0 182 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x004d 183 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0 184 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x004e 185 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0 186 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x004f 187 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0 188 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x0050 189 + #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 0 190 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x0051 191 + #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0 192 + #define mmDAGB0_WR_DATA_DAGB 0x0052 193 + #define mmDAGB0_WR_DATA_DAGB_BASE_IDX 0 194 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0053 195 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0 196 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0054 197 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0 198 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0055 199 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0 200 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0056 201 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0 202 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0057 203 + #define mmDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 0 204 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0058 205 + #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 0 206 + #define mmDAGB0_WR_VC0_CNTL 0x0059 207 + #define mmDAGB0_WR_VC0_CNTL_BASE_IDX 0 208 + #define mmDAGB0_WR_VC1_CNTL 0x005a 209 + #define mmDAGB0_WR_VC1_CNTL_BASE_IDX 0 210 + #define mmDAGB0_WR_VC2_CNTL 0x005b 211 + #define mmDAGB0_WR_VC2_CNTL_BASE_IDX 0 212 + #define mmDAGB0_WR_VC3_CNTL 0x005c 213 + #define mmDAGB0_WR_VC3_CNTL_BASE_IDX 0 214 + #define mmDAGB0_WR_VC4_CNTL 0x005d 215 + #define mmDAGB0_WR_VC4_CNTL_BASE_IDX 0 216 + #define mmDAGB0_WR_VC5_CNTL 0x005e 217 + #define mmDAGB0_WR_VC5_CNTL_BASE_IDX 0 218 + #define mmDAGB0_WR_VC6_CNTL 0x005f 219 + #define mmDAGB0_WR_VC6_CNTL_BASE_IDX 0 220 + #define mmDAGB0_WR_VC7_CNTL 0x0060 221 + #define mmDAGB0_WR_VC7_CNTL_BASE_IDX 0 222 + #define mmDAGB0_WR_CNTL_MISC 0x0061 223 + #define mmDAGB0_WR_CNTL_MISC_BASE_IDX 0 224 + #define mmDAGB0_WR_TLB_CREDIT 0x0062 225 + #define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 0 226 + #define mmDAGB0_WR_DATA_CREDIT 0x0063 227 + #define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 0 228 + #define mmDAGB0_WR_MISC_CREDIT 0x0064 229 + #define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 0 230 + #define mmDAGB0_WRCLI_ASK_PENDING 0x0065 231 + #define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0 232 + #define mmDAGB0_WRCLI_GO_PENDING 0x0066 233 + #define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 0 234 + #define mmDAGB0_WRCLI_GBLSEND_PENDING 0x0067 235 + #define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0 236 + #define mmDAGB0_WRCLI_TLB_PENDING 0x0068 237 + #define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0 238 + #define mmDAGB0_WRCLI_OARB_PENDING 0x0069 239 + #define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0 240 + #define mmDAGB0_WRCLI_OSD_PENDING 0x006a 241 + #define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0 242 + #define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x006b 243 + #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0 244 + #define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x006c 245 + #define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0 246 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x006d 247 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0 248 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x006e 249 + #define mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0 250 + #define mmDAGB0_DAGB_DLY 0x006f 251 + #define mmDAGB0_DAGB_DLY_BASE_IDX 0 252 + #define mmDAGB0_CNTL_MISC 0x0070 253 + #define mmDAGB0_CNTL_MISC_BASE_IDX 0 254 + #define mmDAGB0_CNTL_MISC2 0x0071 255 + #define mmDAGB0_CNTL_MISC2_BASE_IDX 0 256 + #define mmDAGB0_FIFO_EMPTY 0x0072 257 + #define mmDAGB0_FIFO_EMPTY_BASE_IDX 0 258 + #define mmDAGB0_FIFO_FULL 0x0073 259 + #define mmDAGB0_FIFO_FULL_BASE_IDX 0 260 + #define mmDAGB0_WR_CREDITS_FULL 0x0074 261 + #define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 0 262 + #define mmDAGB0_RD_CREDITS_FULL 0x0075 263 + #define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 0 264 + #define mmDAGB0_PERFCOUNTER_LO 0x0076 265 + #define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 0 266 + #define mmDAGB0_PERFCOUNTER_HI 0x0077 267 + #define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 0 268 + #define mmDAGB0_PERFCOUNTER0_CFG 0x0078 269 + #define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0 270 + #define mmDAGB0_PERFCOUNTER1_CFG 0x0079 271 + #define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0 272 + #define mmDAGB0_PERFCOUNTER2_CFG 0x007a 273 + #define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0 274 + #define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x007b 275 + #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 276 + #define mmDAGB0_RESERVE0 0x007c 277 + #define mmDAGB0_RESERVE0_BASE_IDX 0 278 + #define mmDAGB0_RESERVE1 0x007d 279 + #define mmDAGB0_RESERVE1_BASE_IDX 0 280 + #define mmDAGB0_RESERVE2 0x007e 281 + #define mmDAGB0_RESERVE2_BASE_IDX 0 282 + #define mmDAGB0_RESERVE3 0x007f 283 + #define mmDAGB0_RESERVE3_BASE_IDX 0 284 + #define mmDAGB0_RESERVE4 0x0080 285 + #define mmDAGB0_RESERVE4_BASE_IDX 0 286 + #define mmDAGB0_RESERVE5 0x0081 287 + #define mmDAGB0_RESERVE5_BASE_IDX 0 288 + #define mmDAGB0_RESERVE6 0x0082 289 + #define mmDAGB0_RESERVE6_BASE_IDX 0 290 + #define mmDAGB0_RESERVE7 0x0083 291 + #define mmDAGB0_RESERVE7_BASE_IDX 0 292 + #define mmDAGB0_RESERVE8 0x0084 293 + #define mmDAGB0_RESERVE8_BASE_IDX 0 294 + #define mmDAGB0_RESERVE9 0x0085 295 + #define mmDAGB0_RESERVE9_BASE_IDX 0 296 + #define mmDAGB0_RESERVE10 0x0086 297 + #define mmDAGB0_RESERVE10_BASE_IDX 0 298 + #define mmDAGB0_RESERVE11 0x0087 299 + #define mmDAGB0_RESERVE11_BASE_IDX 0 300 + #define mmDAGB0_RESERVE12 0x0088 301 + #define mmDAGB0_RESERVE12_BASE_IDX 0 302 + #define mmDAGB0_RESERVE13 0x0089 303 + #define mmDAGB0_RESERVE13_BASE_IDX 0 304 + #define mmDAGB0_RESERVE14 0x008a 305 + #define mmDAGB0_RESERVE14_BASE_IDX 0 306 + #define mmDAGB0_RESERVE15 0x008b 307 + #define mmDAGB0_RESERVE15_BASE_IDX 0 308 + #define mmDAGB0_RESERVE16 0x008c 309 + #define mmDAGB0_RESERVE16_BASE_IDX 0 310 + #define mmDAGB0_RESERVE17 0x008d 311 + #define mmDAGB0_RESERVE17_BASE_IDX 0 312 + #define mmDAGB0_RESERVE18 0x008e 313 + #define mmDAGB0_RESERVE18_BASE_IDX 0 314 + #define mmDAGB0_RESERVE19 0x008f 315 + #define mmDAGB0_RESERVE19_BASE_IDX 0 316 + #define mmDAGB0_RESERVE20 0x0090 317 + #define mmDAGB0_RESERVE20_BASE_IDX 0 318 + #define mmDAGB0_RESERVE21 0x0091 319 + #define mmDAGB0_RESERVE21_BASE_IDX 0 320 + #define mmDAGB0_RESERVE22 0x0092 321 + #define mmDAGB0_RESERVE22_BASE_IDX 0 322 + #define mmDAGB0_RESERVE23 0x0093 323 + #define mmDAGB0_RESERVE23_BASE_IDX 0 324 + #define mmDAGB0_RESERVE24 0x0094 325 + #define mmDAGB0_RESERVE24_BASE_IDX 0 326 + #define mmDAGB0_RESERVE25 0x0095 327 + #define mmDAGB0_RESERVE25_BASE_IDX 0 328 + #define mmDAGB0_RESERVE26 0x0096 329 + #define mmDAGB0_RESERVE26_BASE_IDX 0 330 + #define mmDAGB0_RESERVE27 0x0097 331 + #define mmDAGB0_RESERVE27_BASE_IDX 0 332 + #define mmDAGB0_RESERVE28 0x0098 333 + #define mmDAGB0_RESERVE28_BASE_IDX 0 334 + #define mmDAGB0_RESERVE29 0x0099 335 + #define mmDAGB0_RESERVE29_BASE_IDX 0 336 + #define mmDAGB0_RESERVE30 0x009a 337 + #define mmDAGB0_RESERVE30_BASE_IDX 0 338 + #define mmDAGB0_RESERVE31 0x009b 339 + #define mmDAGB0_RESERVE31_BASE_IDX 0 340 + #define mmDAGB0_RESERVE32 0x009c 341 + #define mmDAGB0_RESERVE32_BASE_IDX 0 342 + #define mmDAGB0_RESERVE33 0x009d 343 + #define mmDAGB0_RESERVE33_BASE_IDX 0 344 + #define mmDAGB0_RESERVE34 0x009e 345 + #define mmDAGB0_RESERVE34_BASE_IDX 0 346 + #define mmDAGB0_RESERVE35 0x009f 347 + #define mmDAGB0_RESERVE35_BASE_IDX 0 348 + #define mmDAGB0_RESERVE36 0x00a0 349 + #define mmDAGB0_RESERVE36_BASE_IDX 0 350 + #define mmDAGB0_RESERVE37 0x00a1 351 + #define mmDAGB0_RESERVE37_BASE_IDX 0 352 + #define mmDAGB0_RESERVE38 0x00a2 353 + #define mmDAGB0_RESERVE38_BASE_IDX 0 354 + #define mmDAGB0_RESERVE39 0x00a3 355 + #define mmDAGB0_RESERVE39_BASE_IDX 0 356 + #define mmDAGB0_RESERVE40 0x00a4 357 + #define mmDAGB0_RESERVE40_BASE_IDX 0 358 + #define mmDAGB0_RESERVE41 0x00a5 359 + #define mmDAGB0_RESERVE41_BASE_IDX 0 360 + #define mmDAGB0_RESERVE42 0x00a6 361 + #define mmDAGB0_RESERVE42_BASE_IDX 0 362 + #define mmDAGB0_RESERVE43 0x00a7 363 + #define mmDAGB0_RESERVE43_BASE_IDX 0 364 + #define mmDAGB0_RESERVE44 0x00a8 365 + #define mmDAGB0_RESERVE44_BASE_IDX 0 366 + #define mmDAGB0_RESERVE45 0x00a9 367 + #define mmDAGB0_RESERVE45_BASE_IDX 0 368 + #define mmDAGB0_RESERVE46 0x00aa 369 + #define mmDAGB0_RESERVE46_BASE_IDX 0 370 + #define mmDAGB0_RESERVE47 0x00ab 371 + #define mmDAGB0_RESERVE47_BASE_IDX 0 372 + #define mmDAGB0_RESERVE48 0x00ac 373 + #define mmDAGB0_RESERVE48_BASE_IDX 0 374 + #define mmDAGB0_RESERVE49 0x00ad 375 + #define mmDAGB0_RESERVE49_BASE_IDX 0 376 + #define mmDAGB0_RESERVE50 0x00ae 377 + #define mmDAGB0_RESERVE50_BASE_IDX 0 378 + #define mmDAGB0_RESERVE51 0x00af 379 + #define mmDAGB0_RESERVE51_BASE_IDX 0 380 + #define mmDAGB0_RESERVE52 0x00b0 381 + #define mmDAGB0_RESERVE52_BASE_IDX 0 382 + #define mmDAGB0_RESERVE53 0x00b1 383 + #define mmDAGB0_RESERVE53_BASE_IDX 0 384 + #define mmDAGB0_RESERVE54 0x00b2 385 + #define mmDAGB0_RESERVE54_BASE_IDX 0 386 + #define mmDAGB0_RESERVE55 0x00b3 387 + #define mmDAGB0_RESERVE55_BASE_IDX 0 388 + #define mmDAGB0_RESERVE56 0x00b4 389 + #define mmDAGB0_RESERVE56_BASE_IDX 0 390 + #define mmDAGB0_RESERVE57 0x00b5 391 + #define mmDAGB0_RESERVE57_BASE_IDX 0 392 + #define mmDAGB0_RESERVE58 0x00b6 393 + #define mmDAGB0_RESERVE58_BASE_IDX 0 394 + #define mmDAGB0_RESERVE59 0x00b7 395 + #define mmDAGB0_RESERVE59_BASE_IDX 0 396 + #define mmDAGB0_RESERVE60 0x00b8 397 + #define mmDAGB0_RESERVE60_BASE_IDX 0 398 + #define mmDAGB0_RESERVE61 0x00b9 399 + #define mmDAGB0_RESERVE61_BASE_IDX 0 400 + #define mmDAGB0_RESERVE62 0x00ba 401 + #define mmDAGB0_RESERVE62_BASE_IDX 0 402 + #define mmDAGB0_RESERVE63 0x00bb 403 + #define mmDAGB0_RESERVE63_BASE_IDX 0 404 + #define mmDAGB0_RESERVE64 0x00bc 405 + #define mmDAGB0_RESERVE64_BASE_IDX 0 406 + #define mmDAGB0_RESERVE65 0x00bd 407 + #define mmDAGB0_RESERVE65_BASE_IDX 0 408 + #define mmDAGB0_RESERVE66 0x00be 409 + #define mmDAGB0_RESERVE66_BASE_IDX 0 410 + #define mmDAGB0_RESERVE67 0x00bf 411 + #define mmDAGB0_RESERVE67_BASE_IDX 0 412 + #define mmDAGB0_RESERVE68 0x00c0 413 + #define mmDAGB0_RESERVE68_BASE_IDX 0 414 + #define mmDAGB0_RESERVE69 0x00c1 415 + #define mmDAGB0_RESERVE69_BASE_IDX 0 416 + #define mmDAGB0_RESERVE70 0x00c2 417 + #define mmDAGB0_RESERVE70_BASE_IDX 0 418 + #define mmDAGB0_RESERVE71 0x00c3 419 + #define mmDAGB0_RESERVE71_BASE_IDX 0 420 + #define mmDAGB0_RESERVE72 0x00c4 421 + #define mmDAGB0_RESERVE72_BASE_IDX 0 422 + #define mmDAGB0_RESERVE73 0x00c5 423 + #define mmDAGB0_RESERVE73_BASE_IDX 0 424 + #define mmDAGB0_RESERVE74 0x00c6 425 + #define mmDAGB0_RESERVE74_BASE_IDX 0 426 + #define mmDAGB0_RESERVE75 0x00c7 427 + #define mmDAGB0_RESERVE75_BASE_IDX 0 428 + #define mmDAGB0_RESERVE76 0x00c8 429 + #define mmDAGB0_RESERVE76_BASE_IDX 0 430 + #define mmDAGB0_RESERVE77 0x00c9 431 + #define mmDAGB0_RESERVE77_BASE_IDX 0 432 + #define mmDAGB0_RESERVE78 0x00ca 433 + #define mmDAGB0_RESERVE78_BASE_IDX 0 434 + #define mmDAGB0_RESERVE79 0x00cb 435 + #define mmDAGB0_RESERVE79_BASE_IDX 0 436 + #define mmDAGB0_RESERVE80 0x00cc 437 + #define mmDAGB0_RESERVE80_BASE_IDX 0 438 + #define mmDAGB0_RESERVE81 0x00cd 439 + #define mmDAGB0_RESERVE81_BASE_IDX 0 440 + #define mmDAGB0_RESERVE82 0x00ce 441 + #define mmDAGB0_RESERVE82_BASE_IDX 0 442 + #define mmDAGB0_RESERVE83 0x00cf 443 + #define mmDAGB0_RESERVE83_BASE_IDX 0 444 + #define mmDAGB0_RESERVE84 0x00d0 445 + #define mmDAGB0_RESERVE84_BASE_IDX 0 446 + #define mmDAGB0_RESERVE85 0x00d1 447 + #define mmDAGB0_RESERVE85_BASE_IDX 0 448 + #define mmDAGB0_RESERVE86 0x00d2 449 + #define mmDAGB0_RESERVE86_BASE_IDX 0 450 + #define mmDAGB0_RESERVE87 0x00d3 451 + #define mmDAGB0_RESERVE87_BASE_IDX 0 452 + #define mmDAGB0_RESERVE88 0x00d4 453 + #define mmDAGB0_RESERVE88_BASE_IDX 0 454 + #define mmDAGB0_RESERVE89 0x00d5 455 + #define mmDAGB0_RESERVE89_BASE_IDX 0 456 + #define mmDAGB0_RESERVE90 0x00d6 457 + #define mmDAGB0_RESERVE90_BASE_IDX 0 458 + #define mmDAGB0_RESERVE91 0x00d7 459 + #define mmDAGB0_RESERVE91_BASE_IDX 0 460 + #define mmDAGB0_RESERVE92 0x00d8 461 + #define mmDAGB0_RESERVE92_BASE_IDX 0 462 + #define mmDAGB0_RESERVE93 0x00d9 463 + #define mmDAGB0_RESERVE93_BASE_IDX 0 464 + #define mmDAGB0_RESERVE94 0x00da 465 + #define mmDAGB0_RESERVE94_BASE_IDX 0 466 + #define mmDAGB0_RESERVE95 0x00db 467 + #define mmDAGB0_RESERVE95_BASE_IDX 0 468 + #define mmDAGB0_RESERVE96 0x00dc 469 + #define mmDAGB0_RESERVE96_BASE_IDX 0 470 + #define mmDAGB0_RESERVE97 0x00dd 471 + #define mmDAGB0_RESERVE97_BASE_IDX 0 472 + #define mmDAGB0_RESERVE98 0x00de 473 + #define mmDAGB0_RESERVE98_BASE_IDX 0 474 + #define mmDAGB0_RESERVE99 0x00df 475 + #define mmDAGB0_RESERVE99_BASE_IDX 0 476 + #define mmDAGB0_RESERVE100 0x00e0 477 + #define mmDAGB0_RESERVE100_BASE_IDX 0 478 + #define mmDAGB0_RESERVE101 0x00e1 479 + #define mmDAGB0_RESERVE101_BASE_IDX 0 480 + #define mmDAGB0_RESERVE102 0x00e2 481 + #define mmDAGB0_RESERVE102_BASE_IDX 0 482 + #define mmDAGB0_RESERVE103 0x00e3 483 + #define mmDAGB0_RESERVE103_BASE_IDX 0 484 + #define mmDAGB0_RESERVE104 0x00e4 485 + #define mmDAGB0_RESERVE104_BASE_IDX 0 486 + #define mmDAGB0_RESERVE105 0x00e5 487 + #define mmDAGB0_RESERVE105_BASE_IDX 0 488 + #define mmDAGB0_RESERVE106 0x00e6 489 + #define mmDAGB0_RESERVE106_BASE_IDX 0 490 + #define mmDAGB0_RESERVE107 0x00e7 491 + #define mmDAGB0_RESERVE107_BASE_IDX 0 492 + #define mmDAGB0_RESERVE108 0x00e8 493 + #define mmDAGB0_RESERVE108_BASE_IDX 0 494 + #define mmDAGB0_RESERVE109 0x00e9 495 + #define mmDAGB0_RESERVE109_BASE_IDX 0 496 + #define mmDAGB0_RESERVE110 0x00ea 497 + #define mmDAGB0_RESERVE110_BASE_IDX 0 498 + #define mmDAGB0_RESERVE111 0x00eb 499 + #define mmDAGB0_RESERVE111_BASE_IDX 0 500 + #define mmDAGB0_RESERVE112 0x00ec 501 + #define mmDAGB0_RESERVE112_BASE_IDX 0 502 + #define mmDAGB0_RESERVE113 0x00ed 503 + #define mmDAGB0_RESERVE113_BASE_IDX 0 504 + #define mmDAGB0_RESERVE114 0x00ee 505 + #define mmDAGB0_RESERVE114_BASE_IDX 0 506 + #define mmDAGB0_RESERVE115 0x00ef 507 + #define mmDAGB0_RESERVE115_BASE_IDX 0 508 + #define mmDAGB0_RESERVE116 0x00f0 509 + #define mmDAGB0_RESERVE116_BASE_IDX 0 510 + #define mmDAGB0_RESERVE117 0x00f1 511 + #define mmDAGB0_RESERVE117_BASE_IDX 0 512 + #define mmDAGB0_RESERVE118 0x00f2 513 + #define mmDAGB0_RESERVE118_BASE_IDX 0 514 + #define mmDAGB0_RESERVE119 0x00f3 515 + #define mmDAGB0_RESERVE119_BASE_IDX 0 516 + #define mmDAGB0_RESERVE120 0x00f4 517 + #define mmDAGB0_RESERVE120_BASE_IDX 0 518 + #define mmDAGB0_RESERVE121 0x00f5 519 + #define mmDAGB0_RESERVE121_BASE_IDX 0 520 + #define mmDAGB0_RESERVE122 0x00f6 521 + #define mmDAGB0_RESERVE122_BASE_IDX 0 522 + #define mmDAGB0_RESERVE123 0x00f7 523 + #define mmDAGB0_RESERVE123_BASE_IDX 0 524 + #define mmDAGB0_RESERVE124 0x00f8 525 + #define mmDAGB0_RESERVE124_BASE_IDX 0 526 + #define mmDAGB0_RESERVE125 0x00f9 527 + #define mmDAGB0_RESERVE125_BASE_IDX 0 528 + #define mmDAGB0_RESERVE126 0x00fa 529 + #define mmDAGB0_RESERVE126_BASE_IDX 0 530 + #define mmDAGB0_RESERVE127 0x00fb 531 + #define mmDAGB0_RESERVE127_BASE_IDX 0 532 + #define mmDAGB0_RESERVE128 0x00fc 533 + #define mmDAGB0_RESERVE128_BASE_IDX 0 534 + #define mmDAGB0_RESERVE129 0x00fd 535 + #define mmDAGB0_RESERVE129_BASE_IDX 0 536 + #define mmDAGB0_RESERVE130 0x00fe 537 + #define mmDAGB0_RESERVE130_BASE_IDX 0 538 + #define mmDAGB0_RESERVE131 0x00ff 539 + #define mmDAGB0_RESERVE131_BASE_IDX 0 540 + 541 + 542 + // addressBlock: mmhub_mmea_mmeadec 543 + // base address: 0x68400 544 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0100 545 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 0 546 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0101 547 + #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 0 548 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0102 549 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 0 550 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0103 551 + #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 0 552 + #define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0104 553 + #define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 0 554 + #define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0105 555 + #define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 0 556 + #define mmMMEA0_DRAM_RD_LAZY 0x0106 557 + #define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 0 558 + #define mmMMEA0_DRAM_WR_LAZY 0x0107 559 + #define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 0 560 + #define mmMMEA0_DRAM_RD_CAM_CNTL 0x0108 561 + #define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 0 562 + #define mmMMEA0_DRAM_WR_CAM_CNTL 0x0109 563 + #define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 0 564 + #define mmMMEA0_DRAM_PAGE_BURST 0x010a 565 + #define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 0 566 + #define mmMMEA0_DRAM_RD_PRI_AGE 0x010b 567 + #define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 0 568 + #define mmMMEA0_DRAM_WR_PRI_AGE 0x010c 569 + #define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 0 570 + #define mmMMEA0_DRAM_RD_PRI_QUEUING 0x010d 571 + #define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 0 572 + #define mmMMEA0_DRAM_WR_PRI_QUEUING 0x010e 573 + #define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 0 574 + #define mmMMEA0_DRAM_RD_PRI_FIXED 0x010f 575 + #define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 0 576 + #define mmMMEA0_DRAM_WR_PRI_FIXED 0x0110 577 + #define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 0 578 + #define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0111 579 + #define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 0 580 + #define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0112 581 + #define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 0 582 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0113 583 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 0 584 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0114 585 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 0 586 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0115 587 + #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 0 588 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0116 589 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 0 590 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0117 591 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 0 592 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0118 593 + #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 0 594 + #define mmMMEA0_ADDRNORM_BASE_ADDR0 0x0134 595 + #define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 0 596 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x0135 597 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 0 598 + #define mmMMEA0_ADDRNORM_BASE_ADDR1 0x0136 599 + #define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 0 600 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x0137 601 + #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 0 602 + #define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x0138 603 + #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 0 604 + #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x0143 605 + #define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 0 606 + #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0145 607 + #define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 0 608 + #define mmMMEA0_ADDRDEC_BANK_CFG 0x0147 609 + #define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 0 610 + #define mmMMEA0_ADDRDEC_MISC_CFG 0x0148 611 + #define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 0 612 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x0149 613 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 0 614 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x014a 615 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 0 616 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x014b 617 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 0 618 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x014c 619 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 0 620 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x014d 621 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 0 622 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x014e 623 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 0 624 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x014f 625 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 0 626 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x0150 627 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 0 628 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x0151 629 + #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 0 630 + #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x0152 631 + #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 0 632 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 0x0153 633 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX 0 634 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 0x0154 635 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX 0 636 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 0x0155 637 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX 0 638 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 0x0156 639 + #define mmMMEA0_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX 0 640 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x0165 641 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 0 642 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x0166 643 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 0 644 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x0167 645 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 0 646 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x0168 647 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 0 648 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x0169 649 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 0 650 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x016a 651 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 0 652 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x016b 653 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 0 654 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x016c 655 + #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 0 656 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x016d 657 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 0 658 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x016e 659 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 0 660 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x016f 661 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 0 662 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x0170 663 + #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 0 664 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x0171 665 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 0 666 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x0172 667 + #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 0 668 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x0173 669 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 0 670 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x0174 671 + #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 0 672 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x0175 673 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 0 674 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x0176 675 + #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 0 676 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x0177 677 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 0 678 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x0178 679 + #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 0 680 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x0179 681 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 0 682 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x017a 683 + #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 0 684 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x017b 685 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 0 686 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x017c 687 + #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 0 688 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x017d 689 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 0 690 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x017e 691 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 0 692 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x017f 693 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 0 694 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x0180 695 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 0 696 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x0181 697 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 0 698 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x0182 699 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 0 700 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x0183 701 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 0 702 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0184 703 + #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 0 704 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0185 705 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 0 706 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0186 707 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 0 708 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0187 709 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 0 710 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0188 711 + #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 0 712 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0189 713 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 0 714 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x018a 715 + #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 0 716 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x018b 717 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 0 718 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x018c 719 + #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 0 720 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x018d 721 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 0 722 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x018e 723 + #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 0 724 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x018f 725 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 0 726 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x0190 727 + #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 0 728 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x0191 729 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 0 730 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0192 731 + #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 0 732 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0193 733 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 0 734 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0194 735 + #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 0 736 + #define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x01dd 737 + #define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 0 738 + #define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x01de 739 + #define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 0 740 + #define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x01df 741 + #define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 0 742 + #define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x01e0 743 + #define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 0 744 + #define mmMMEA0_IO_RD_COMBINE_FLUSH 0x01e1 745 + #define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 0 746 + #define mmMMEA0_IO_WR_COMBINE_FLUSH 0x01e2 747 + #define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 0 748 + #define mmMMEA0_IO_GROUP_BURST 0x01e3 749 + #define mmMMEA0_IO_GROUP_BURST_BASE_IDX 0 750 + #define mmMMEA0_IO_RD_PRI_AGE 0x01e4 751 + #define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 0 752 + #define mmMMEA0_IO_WR_PRI_AGE 0x01e5 753 + #define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 0 754 + #define mmMMEA0_IO_RD_PRI_QUEUING 0x01e6 755 + #define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 0 756 + #define mmMMEA0_IO_WR_PRI_QUEUING 0x01e7 757 + #define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 0 758 + #define mmMMEA0_IO_RD_PRI_FIXED 0x01e8 759 + #define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 0 760 + #define mmMMEA0_IO_WR_PRI_FIXED 0x01e9 761 + #define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 0 762 + #define mmMMEA0_IO_RD_PRI_URGENCY 0x01ea 763 + #define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 0 764 + #define mmMMEA0_IO_WR_PRI_URGENCY 0x01eb 765 + #define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 0 766 + #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x01ec 767 + #define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 0 768 + #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x01ed 769 + #define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 0 770 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x01ee 771 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 0 772 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x01ef 773 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 0 774 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x01f0 775 + #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 0 776 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x01f1 777 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 778 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x01f2 779 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 0 780 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x01f3 781 + #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 0 782 + #define mmMMEA0_SDP_ARB_DRAM 0x01f4 783 + #define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 0 784 + #define mmMMEA0_SDP_ARB_FINAL 0x01f6 785 + #define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 0 786 + #define mmMMEA0_SDP_DRAM_PRIORITY 0x01f7 787 + #define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 0 788 + #define mmMMEA0_SDP_IO_PRIORITY 0x01f9 789 + #define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 0 790 + #define mmMMEA0_SDP_CREDITS 0x01fa 791 + #define mmMMEA0_SDP_CREDITS_BASE_IDX 0 792 + #define mmMMEA0_SDP_TAG_RESERVE0 0x01fb 793 + #define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 0 794 + #define mmMMEA0_SDP_TAG_RESERVE1 0x01fc 795 + #define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 0 796 + #define mmMMEA0_SDP_VCC_RESERVE0 0x01fd 797 + #define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 0 798 + #define mmMMEA0_SDP_VCC_RESERVE1 0x01fe 799 + #define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 0 800 + #define mmMMEA0_SDP_VCD_RESERVE0 0x01ff 801 + #define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 0 802 + #define mmMMEA0_SDP_VCD_RESERVE1 0x0200 803 + #define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 0 804 + #define mmMMEA0_SDP_REQ_CNTL 0x0201 805 + #define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 0 806 + #define mmMMEA0_MISC 0x0202 807 + #define mmMMEA0_MISC_BASE_IDX 0 808 + #define mmMMEA0_LATENCY_SAMPLING 0x0203 809 + #define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 0 810 + #define mmMMEA0_PERFCOUNTER_LO 0x0204 811 + #define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 0 812 + #define mmMMEA0_PERFCOUNTER_HI 0x0205 813 + #define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 0 814 + #define mmMMEA0_PERFCOUNTER0_CFG 0x0206 815 + #define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 0 816 + #define mmMMEA0_PERFCOUNTER1_CFG 0x0207 817 + #define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 818 + #define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0208 819 + #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 820 + #define mmMMEA0_EDC_CNT 0x020f 821 + #define mmMMEA0_EDC_CNT_BASE_IDX 0 822 + #define mmMMEA0_EDC_CNT2 0x0210 823 + #define mmMMEA0_EDC_CNT2_BASE_IDX 0 824 + #define mmMMEA0_DSM_CNTL 0x0211 825 + #define mmMMEA0_DSM_CNTL_BASE_IDX 0 826 + #define mmMMEA0_DSM_CNTLA 0x0212 827 + #define mmMMEA0_DSM_CNTLA_BASE_IDX 0 828 + #define mmMMEA0_DSM_CNTLB 0x0213 829 + #define mmMMEA0_DSM_CNTLB_BASE_IDX 0 830 + #define mmMMEA0_DSM_CNTL2 0x0214 831 + #define mmMMEA0_DSM_CNTL2_BASE_IDX 0 832 + #define mmMMEA0_DSM_CNTL2A 0x0215 833 + #define mmMMEA0_DSM_CNTL2A_BASE_IDX 0 834 + #define mmMMEA0_DSM_CNTL2B 0x0216 835 + #define mmMMEA0_DSM_CNTL2B_BASE_IDX 0 836 + #define mmMMEA0_CGTT_CLK_CTRL 0x0218 837 + #define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 0 838 + #define mmMMEA0_EDC_MODE 0x0219 839 + #define mmMMEA0_EDC_MODE_BASE_IDX 0 840 + #define mmMMEA0_ERR_STATUS 0x021a 841 + #define mmMMEA0_ERR_STATUS_BASE_IDX 0 842 + #define mmMMEA0_MISC2 0x021b 843 + #define mmMMEA0_MISC2_BASE_IDX 0 844 + #define mmMMEA0_ADDRDEC_SELECT 0x021c 845 + #define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 0 846 + 847 + 848 + // addressBlock: mmhub_pctldec 849 + // base address: 0x68e00 850 + #define mmPCTL_MISC 0x0380 851 + #define mmPCTL_MISC_BASE_IDX 0 852 + #define mmPCTL_MMHUB_DEEPSLEEP 0x0381 853 + #define mmPCTL_MMHUB_DEEPSLEEP_BASE_IDX 0 854 + #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 855 + #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 0 856 + #define mmPCTL_PG_IGNORE_DEEPSLEEP 0x0383 857 + #define mmPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 0 858 + #define mmPCTL_PG_DAGB 0x0384 859 + #define mmPCTL_PG_DAGB_BASE_IDX 0 860 + #define mmPCTL0_RENG_RAM_INDEX 0x0385 861 + #define mmPCTL0_RENG_RAM_INDEX_BASE_IDX 0 862 + #define mmPCTL0_RENG_RAM_DATA 0x0386 863 + #define mmPCTL0_RENG_RAM_DATA_BASE_IDX 0 864 + #define mmPCTL0_RENG_EXECUTE 0x0387 865 + #define mmPCTL0_RENG_EXECUTE_BASE_IDX 0 866 + #define mmPCTL1_RENG_RAM_INDEX 0x0388 867 + #define mmPCTL1_RENG_RAM_INDEX_BASE_IDX 0 868 + #define mmPCTL1_RENG_RAM_DATA 0x0389 869 + #define mmPCTL1_RENG_RAM_DATA_BASE_IDX 0 870 + #define mmPCTL1_RENG_EXECUTE 0x038a 871 + #define mmPCTL1_RENG_EXECUTE_BASE_IDX 0 872 + #define mmPCTL2_RENG_RAM_INDEX 0x038b 873 + #define mmPCTL2_RENG_RAM_INDEX_BASE_IDX 0 874 + #define mmPCTL2_RENG_RAM_DATA 0x038c 875 + #define mmPCTL2_RENG_RAM_DATA_BASE_IDX 0 876 + #define mmPCTL2_RENG_EXECUTE 0x038d 877 + #define mmPCTL2_RENG_EXECUTE_BASE_IDX 0 878 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0 0x038e 879 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 880 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1 0x038f 881 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 882 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2 0x0390 883 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 884 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3 0x0391 885 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 886 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4 0x0392 887 + #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 888 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 0x0393 889 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 890 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0394 891 + #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 892 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0 0x0395 893 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 894 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1 0x0396 895 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 896 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2 0x0397 897 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 898 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3 0x0398 899 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 900 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4 0x0399 901 + #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 902 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 0x039a 903 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 904 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x039b 905 + #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 906 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0 0x039c 907 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 0 908 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1 0x039d 909 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 0 910 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2 0x039e 911 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 0 912 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3 0x039f 913 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 0 914 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4 0x03a0 915 + #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 0 916 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 0x03a1 917 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_BASE_IDX 0 918 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a2 919 + #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 0 920 + #define mmPCTL0_MISC 0x03a3 921 + #define mmPCTL0_MISC_BASE_IDX 0 922 + #define mmPCTL1_MISC 0x03a4 923 + #define mmPCTL1_MISC_BASE_IDX 0 924 + #define mmPCTL2_MISC 0x03a5 925 + #define mmPCTL2_MISC_BASE_IDX 0 926 + #define mmPCTL_PERFCOUNTER_LO 0x03a6 927 + #define mmPCTL_PERFCOUNTER_LO_BASE_IDX 0 928 + #define mmPCTL_PERFCOUNTER_HI 0x03a7 929 + #define mmPCTL_PERFCOUNTER_HI_BASE_IDX 0 930 + #define mmPCTL_PERFCOUNTER0_CFG 0x03a8 931 + #define mmPCTL_PERFCOUNTER0_CFG_BASE_IDX 0 932 + #define mmPCTL_PERFCOUNTER1_CFG 0x03a9 933 + #define mmPCTL_PERFCOUNTER1_CFG_BASE_IDX 0 934 + #define mmPCTL_PERFCOUNTER_RSLT_CNTL 0x03aa 935 + #define mmPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 936 + 937 + 938 + // addressBlock: mmhub_l1tlb_mmvml1pfdec 939 + // base address: 0x69600 940 + #define mmMMMC_VM_MX_L1_TLB0_STATUS 0x0588 941 + #define mmMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 0 942 + #define mmMMMC_VM_MX_L1_TLB1_STATUS 0x0589 943 + #define mmMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 0 944 + #define mmMMMC_VM_MX_L1_TLB2_STATUS 0x058a 945 + #define mmMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 0 946 + #define mmMMMC_VM_MX_L1_TLB3_STATUS 0x058b 947 + #define mmMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 0 948 + #define mmMMMC_VM_MX_L1_TLB4_STATUS 0x058c 949 + #define mmMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 0 950 + #define mmMMMC_VM_MX_L1_TLB5_STATUS 0x058d 951 + #define mmMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 0 952 + #define mmMMMC_VM_MX_L1_TLB6_STATUS 0x058e 953 + #define mmMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 0 954 + #define mmMMMC_VM_MX_L1_TLB7_STATUS 0x058f 955 + #define mmMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 0 956 + 957 + 958 + // addressBlock: mmhub_l1tlb_mmvml1pldec 959 + // base address: 0x69650 960 + #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x0594 961 + #define mmMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 0 962 + #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x0595 963 + #define mmMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 0 964 + #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x0596 965 + #define mmMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 0 966 + #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x0597 967 + #define mmMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 0 968 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0598 969 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 970 + 971 + 972 + // addressBlock: mmhub_l1tlb_mmvml1prdec 973 + // base address: 0x69670 974 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO 0x059c 975 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 0 976 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI 0x059d 977 + #define mmMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0 978 + 979 + 980 + // addressBlock: mmhub_mmutcl2_mmatcl2dec 981 + // base address: 0x69900 982 + #define mmMM_ATC_L2_CNTL 0x0640 983 + #define mmMM_ATC_L2_CNTL_BASE_IDX 0 984 + #define mmMM_ATC_L2_CNTL2 0x0641 985 + #define mmMM_ATC_L2_CNTL2_BASE_IDX 0 986 + #define mmMM_ATC_L2_CACHE_DATA0 0x0644 987 + #define mmMM_ATC_L2_CACHE_DATA0_BASE_IDX 0 988 + #define mmMM_ATC_L2_CACHE_DATA1 0x0645 989 + #define mmMM_ATC_L2_CACHE_DATA1_BASE_IDX 0 990 + #define mmMM_ATC_L2_CACHE_DATA2 0x0646 991 + #define mmMM_ATC_L2_CACHE_DATA2_BASE_IDX 0 992 + #define mmMM_ATC_L2_CNTL3 0x0647 993 + #define mmMM_ATC_L2_CNTL3_BASE_IDX 0 994 + #define mmMM_ATC_L2_STATUS 0x0648 995 + #define mmMM_ATC_L2_STATUS_BASE_IDX 0 996 + #define mmMM_ATC_L2_STATUS2 0x0649 997 + #define mmMM_ATC_L2_STATUS2_BASE_IDX 0 998 + #define mmMM_ATC_L2_MISC_CG 0x064a 999 + #define mmMM_ATC_L2_MISC_CG_BASE_IDX 0 1000 + #define mmMM_ATC_L2_MEM_POWER_LS 0x064b 1001 + #define mmMM_ATC_L2_MEM_POWER_LS_BASE_IDX 0 1002 + #define mmMM_ATC_L2_CGTT_CLK_CTRL 0x064c 1003 + #define mmMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 0 1004 + #define mmMM_ATC_L2_SDPPORT_CTRL 0x064d 1005 + #define mmMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 0 1006 + 1007 + 1008 + // addressBlock: mmhub_mmutcl2_mmvml2pfdec 1009 + // base address: 0x69a00 1010 + #define mmMMVM_L2_CNTL 0x0680 1011 + #define mmMMVM_L2_CNTL_BASE_IDX 0 1012 + #define mmMMVM_L2_CNTL2 0x0681 1013 + #define mmMMVM_L2_CNTL2_BASE_IDX 0 1014 + #define mmMMVM_L2_CNTL3 0x0682 1015 + #define mmMMVM_L2_CNTL3_BASE_IDX 0 1016 + #define mmMMVM_L2_STATUS 0x0683 1017 + #define mmMMVM_L2_STATUS_BASE_IDX 0 1018 + #define mmMMVM_DUMMY_PAGE_FAULT_CNTL 0x0684 1019 + #define mmMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 1020 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0685 1021 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 1022 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0686 1023 + #define mmMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 1024 + #define mmMMVM_INVALIDATE_CNTL 0x0687 1025 + #define mmMMVM_INVALIDATE_CNTL_BASE_IDX 0 1026 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL 0x0688 1027 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 0 1028 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL2 0x0689 1029 + #define mmMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 1030 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x068a 1031 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 1032 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x068b 1033 + #define mmMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 1034 + #define mmMMVM_L2_PROTECTION_FAULT_STATUS 0x068c 1035 + #define mmMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 0 1036 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x068d 1037 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 1038 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x068e 1039 + #define mmMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 1040 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x068f 1041 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 1042 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0690 1043 + #define mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 1044 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0692 1045 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 1046 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0693 1047 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 1048 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0694 1049 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 1050 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0695 1051 + #define mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 1052 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0696 1053 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 1054 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0697 1055 + #define mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 1056 + #define mmMMVM_L2_CNTL4 0x0698 1057 + #define mmMMVM_L2_CNTL4_BASE_IDX 0 1058 + #define mmMMVM_L2_MM_GROUP_RT_CLASSES 0x0699 1059 + #define mmMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 1060 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID 0x069a 1061 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 1062 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2 0x069b 1063 + #define mmMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 1064 + #define mmMMVM_L2_CACHE_PARITY_CNTL 0x069c 1065 + #define mmMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 1066 + #define mmMMVM_L2_IH_LOG_CNTL 0x069d 1067 + #define mmMMVM_L2_IH_LOG_CNTL_BASE_IDX 0 1068 + #define mmMMVM_L2_IH_LOG_BUSY 0x069e 1069 + #define mmMMVM_L2_IH_LOG_BUSY_BASE_IDX 0 1070 + #define mmMMVM_L2_CGTT_CLK_CTRL 0x069f 1071 + #define mmMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 0 1072 + #define mmMMVM_L2_CNTL5 0x06a1 1073 + #define mmMMVM_L2_CNTL5_BASE_IDX 0 1074 + #define mmMMVM_L2_GCR_CNTL 0x06a2 1075 + #define mmMMVM_L2_GCR_CNTL_BASE_IDX 0 1076 + #define mmMMVML2_WALKER_MACRO_THROTTLE_TIME 0x06a3 1077 + #define mmMMVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 1078 + #define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x06a4 1079 + #define mmMMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 1080 + #define mmMMVML2_WALKER_MICRO_THROTTLE_TIME 0x06a5 1081 + #define mmMMVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 1082 + #define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x06a6 1083 + #define mmMMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 1084 + 1085 + 1086 + // addressBlock: mmhub_mmutcl2_mmvml2vcdec 1087 + // base address: 0x69b00 1088 + #define mmMMVM_CONTEXT0_CNTL 0x06c0 1089 + #define mmMMVM_CONTEXT0_CNTL_BASE_IDX 0 1090 + #define mmMMVM_CONTEXT1_CNTL 0x06c1 1091 + #define mmMMVM_CONTEXT1_CNTL_BASE_IDX 0 1092 + #define mmMMVM_CONTEXT2_CNTL 0x06c2 1093 + #define mmMMVM_CONTEXT2_CNTL_BASE_IDX 0 1094 + #define mmMMVM_CONTEXT3_CNTL 0x06c3 1095 + #define mmMMVM_CONTEXT3_CNTL_BASE_IDX 0 1096 + #define mmMMVM_CONTEXT4_CNTL 0x06c4 1097 + #define mmMMVM_CONTEXT4_CNTL_BASE_IDX 0 1098 + #define mmMMVM_CONTEXT5_CNTL 0x06c5 1099 + #define mmMMVM_CONTEXT5_CNTL_BASE_IDX 0 1100 + #define mmMMVM_CONTEXT6_CNTL 0x06c6 1101 + #define mmMMVM_CONTEXT6_CNTL_BASE_IDX 0 1102 + #define mmMMVM_CONTEXT7_CNTL 0x06c7 1103 + #define mmMMVM_CONTEXT7_CNTL_BASE_IDX 0 1104 + #define mmMMVM_CONTEXT8_CNTL 0x06c8 1105 + #define mmMMVM_CONTEXT8_CNTL_BASE_IDX 0 1106 + #define mmMMVM_CONTEXT9_CNTL 0x06c9 1107 + #define mmMMVM_CONTEXT9_CNTL_BASE_IDX 0 1108 + #define mmMMVM_CONTEXT10_CNTL 0x06ca 1109 + #define mmMMVM_CONTEXT10_CNTL_BASE_IDX 0 1110 + #define mmMMVM_CONTEXT11_CNTL 0x06cb 1111 + #define mmMMVM_CONTEXT11_CNTL_BASE_IDX 0 1112 + #define mmMMVM_CONTEXT12_CNTL 0x06cc 1113 + #define mmMMVM_CONTEXT12_CNTL_BASE_IDX 0 1114 + #define mmMMVM_CONTEXT13_CNTL 0x06cd 1115 + #define mmMMVM_CONTEXT13_CNTL_BASE_IDX 0 1116 + #define mmMMVM_CONTEXT14_CNTL 0x06ce 1117 + #define mmMMVM_CONTEXT14_CNTL_BASE_IDX 0 1118 + #define mmMMVM_CONTEXT15_CNTL 0x06cf 1119 + #define mmMMVM_CONTEXT15_CNTL_BASE_IDX 0 1120 + #define mmMMVM_CONTEXTS_DISABLE 0x06d0 1121 + #define mmMMVM_CONTEXTS_DISABLE_BASE_IDX 0 1122 + #define mmMMVM_INVALIDATE_ENG0_SEM 0x06d1 1123 + #define mmMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 1124 + #define mmMMVM_INVALIDATE_ENG1_SEM 0x06d2 1125 + #define mmMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 1126 + #define mmMMVM_INVALIDATE_ENG2_SEM 0x06d3 1127 + #define mmMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 1128 + #define mmMMVM_INVALIDATE_ENG3_SEM 0x06d4 1129 + #define mmMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 1130 + #define mmMMVM_INVALIDATE_ENG4_SEM 0x06d5 1131 + #define mmMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 1132 + #define mmMMVM_INVALIDATE_ENG5_SEM 0x06d6 1133 + #define mmMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 1134 + #define mmMMVM_INVALIDATE_ENG6_SEM 0x06d7 1135 + #define mmMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 1136 + #define mmMMVM_INVALIDATE_ENG7_SEM 0x06d8 1137 + #define mmMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 1138 + #define mmMMVM_INVALIDATE_ENG8_SEM 0x06d9 1139 + #define mmMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 1140 + #define mmMMVM_INVALIDATE_ENG9_SEM 0x06da 1141 + #define mmMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 1142 + #define mmMMVM_INVALIDATE_ENG10_SEM 0x06db 1143 + #define mmMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 1144 + #define mmMMVM_INVALIDATE_ENG11_SEM 0x06dc 1145 + #define mmMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 1146 + #define mmMMVM_INVALIDATE_ENG12_SEM 0x06dd 1147 + #define mmMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 1148 + #define mmMMVM_INVALIDATE_ENG13_SEM 0x06de 1149 + #define mmMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 1150 + #define mmMMVM_INVALIDATE_ENG14_SEM 0x06df 1151 + #define mmMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 1152 + #define mmMMVM_INVALIDATE_ENG15_SEM 0x06e0 1153 + #define mmMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 1154 + #define mmMMVM_INVALIDATE_ENG16_SEM 0x06e1 1155 + #define mmMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 1156 + #define mmMMVM_INVALIDATE_ENG17_SEM 0x06e2 1157 + #define mmMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 1158 + #define mmMMVM_INVALIDATE_ENG0_REQ 0x06e3 1159 + #define mmMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 1160 + #define mmMMVM_INVALIDATE_ENG1_REQ 0x06e4 1161 + #define mmMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 1162 + #define mmMMVM_INVALIDATE_ENG2_REQ 0x06e5 1163 + #define mmMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 1164 + #define mmMMVM_INVALIDATE_ENG3_REQ 0x06e6 1165 + #define mmMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 1166 + #define mmMMVM_INVALIDATE_ENG4_REQ 0x06e7 1167 + #define mmMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 1168 + #define mmMMVM_INVALIDATE_ENG5_REQ 0x06e8 1169 + #define mmMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 1170 + #define mmMMVM_INVALIDATE_ENG6_REQ 0x06e9 1171 + #define mmMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 1172 + #define mmMMVM_INVALIDATE_ENG7_REQ 0x06ea 1173 + #define mmMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 1174 + #define mmMMVM_INVALIDATE_ENG8_REQ 0x06eb 1175 + #define mmMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 1176 + #define mmMMVM_INVALIDATE_ENG9_REQ 0x06ec 1177 + #define mmMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 1178 + #define mmMMVM_INVALIDATE_ENG10_REQ 0x06ed 1179 + #define mmMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 1180 + #define mmMMVM_INVALIDATE_ENG11_REQ 0x06ee 1181 + #define mmMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 1182 + #define mmMMVM_INVALIDATE_ENG12_REQ 0x06ef 1183 + #define mmMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 1184 + #define mmMMVM_INVALIDATE_ENG13_REQ 0x06f0 1185 + #define mmMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 1186 + #define mmMMVM_INVALIDATE_ENG14_REQ 0x06f1 1187 + #define mmMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 1188 + #define mmMMVM_INVALIDATE_ENG15_REQ 0x06f2 1189 + #define mmMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 1190 + #define mmMMVM_INVALIDATE_ENG16_REQ 0x06f3 1191 + #define mmMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 1192 + #define mmMMVM_INVALIDATE_ENG17_REQ 0x06f4 1193 + #define mmMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 1194 + #define mmMMVM_INVALIDATE_ENG0_ACK 0x06f5 1195 + #define mmMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 1196 + #define mmMMVM_INVALIDATE_ENG1_ACK 0x06f6 1197 + #define mmMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 1198 + #define mmMMVM_INVALIDATE_ENG2_ACK 0x06f7 1199 + #define mmMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 1200 + #define mmMMVM_INVALIDATE_ENG3_ACK 0x06f8 1201 + #define mmMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 1202 + #define mmMMVM_INVALIDATE_ENG4_ACK 0x06f9 1203 + #define mmMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 1204 + #define mmMMVM_INVALIDATE_ENG5_ACK 0x06fa 1205 + #define mmMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 1206 + #define mmMMVM_INVALIDATE_ENG6_ACK 0x06fb 1207 + #define mmMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 1208 + #define mmMMVM_INVALIDATE_ENG7_ACK 0x06fc 1209 + #define mmMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 1210 + #define mmMMVM_INVALIDATE_ENG8_ACK 0x06fd 1211 + #define mmMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 1212 + #define mmMMVM_INVALIDATE_ENG9_ACK 0x06fe 1213 + #define mmMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 1214 + #define mmMMVM_INVALIDATE_ENG10_ACK 0x06ff 1215 + #define mmMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 1216 + #define mmMMVM_INVALIDATE_ENG11_ACK 0x0700 1217 + #define mmMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 1218 + #define mmMMVM_INVALIDATE_ENG12_ACK 0x0701 1219 + #define mmMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 1220 + #define mmMMVM_INVALIDATE_ENG13_ACK 0x0702 1221 + #define mmMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 1222 + #define mmMMVM_INVALIDATE_ENG14_ACK 0x0703 1223 + #define mmMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 1224 + #define mmMMVM_INVALIDATE_ENG15_ACK 0x0704 1225 + #define mmMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 1226 + #define mmMMVM_INVALIDATE_ENG16_ACK 0x0705 1227 + #define mmMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 1228 + #define mmMMVM_INVALIDATE_ENG17_ACK 0x0706 1229 + #define mmMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 1230 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0707 1231 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 1232 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0708 1233 + #define mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 1234 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0709 1235 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 1236 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x070a 1237 + #define mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 1238 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x070b 1239 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 1240 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x070c 1241 + #define mmMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 1242 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x070d 1243 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 1244 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x070e 1245 + #define mmMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 1246 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x070f 1247 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 1248 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0710 1249 + #define mmMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 1250 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0711 1251 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 1252 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0712 1253 + #define mmMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 1254 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0713 1255 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 1256 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0714 1257 + #define mmMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 1258 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0715 1259 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 1260 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0716 1261 + #define mmMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 1262 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0717 1263 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 1264 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0718 1265 + #define mmMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 1266 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0719 1267 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 1268 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x071a 1269 + #define mmMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 1270 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x071b 1271 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 1272 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x071c 1273 + #define mmMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 1274 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x071d 1275 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 1276 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x071e 1277 + #define mmMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 1278 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x071f 1279 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 1280 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0720 1281 + #define mmMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 1282 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0721 1283 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 1284 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0722 1285 + #define mmMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 1286 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0723 1287 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 1288 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0724 1289 + #define mmMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 1290 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0725 1291 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 1292 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0726 1293 + #define mmMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 1294 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 1295 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 1296 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 1297 + #define mmMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 1298 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0729 1299 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 1300 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x072a 1301 + #define mmMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 1302 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 1303 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1304 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 1305 + #define mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1306 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x072d 1307 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1308 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x072e 1309 + #define mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1310 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x072f 1311 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1312 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0730 1313 + #define mmMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1314 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0731 1315 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1316 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0732 1317 + #define mmMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1318 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0733 1319 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1320 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0734 1321 + #define mmMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1322 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0735 1323 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1324 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0736 1325 + #define mmMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1326 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0737 1327 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1328 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0738 1329 + #define mmMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1330 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0739 1331 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1332 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x073a 1333 + #define mmMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1334 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x073b 1335 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1336 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x073c 1337 + #define mmMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1338 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x073d 1339 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1340 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x073e 1341 + #define mmMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1342 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x073f 1343 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1344 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0740 1345 + #define mmMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1346 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0741 1347 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1348 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0742 1349 + #define mmMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1350 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0743 1351 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1352 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0744 1353 + #define mmMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1354 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0745 1355 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1356 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0746 1357 + #define mmMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1358 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0747 1359 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1360 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0748 1361 + #define mmMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1362 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0749 1363 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 1364 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x074a 1365 + #define mmMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 1366 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 1367 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1368 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 1369 + #define mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1370 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x074d 1371 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1372 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x074e 1373 + #define mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1374 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x074f 1375 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1376 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0750 1377 + #define mmMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1378 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0751 1379 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1380 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0752 1381 + #define mmMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1382 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0753 1383 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1384 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0754 1385 + #define mmMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1386 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0755 1387 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1388 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0756 1389 + #define mmMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1390 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0757 1391 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1392 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0758 1393 + #define mmMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1394 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0759 1395 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1396 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x075a 1397 + #define mmMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1398 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x075b 1399 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1400 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x075c 1401 + #define mmMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1402 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x075d 1403 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1404 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x075e 1405 + #define mmMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1406 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x075f 1407 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1408 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0760 1409 + #define mmMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1410 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0761 1411 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1412 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0762 1413 + #define mmMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1414 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0763 1415 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1416 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0764 1417 + #define mmMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1418 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0765 1419 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1420 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0766 1421 + #define mmMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1422 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0767 1423 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1424 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0768 1425 + #define mmMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1426 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0769 1427 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 1428 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x076a 1429 + #define mmMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 1430 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 1431 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1432 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 1433 + #define mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1434 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x076d 1435 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1436 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x076e 1437 + #define mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1438 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x076f 1439 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1440 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0770 1441 + #define mmMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1442 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0771 1443 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1444 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0772 1445 + #define mmMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1446 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0773 1447 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1448 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0774 1449 + #define mmMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1450 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0775 1451 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1452 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0776 1453 + #define mmMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1454 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0777 1455 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1456 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0778 1457 + #define mmMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1458 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0779 1459 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1460 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x077a 1461 + #define mmMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1462 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x077b 1463 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1464 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x077c 1465 + #define mmMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1466 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x077d 1467 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1468 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x077e 1469 + #define mmMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1470 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x077f 1471 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1472 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0780 1473 + #define mmMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1474 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0781 1475 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1476 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0782 1477 + #define mmMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1478 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0783 1479 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1480 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0784 1481 + #define mmMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1482 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0785 1483 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1484 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0786 1485 + #define mmMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1486 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0787 1487 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1488 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0788 1489 + #define mmMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1490 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0789 1491 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 1492 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x078a 1493 + #define mmMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 1494 + 1495 + 1496 + // addressBlock: mmhub_mmutcl2_mmvml2pldec 1497 + // base address: 0x69e90 1498 + #define mmMMMC_VM_L2_PERFCOUNTER0_CFG 0x07a4 1499 + #define mmMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1500 + #define mmMMMC_VM_L2_PERFCOUNTER1_CFG 0x07a5 1501 + #define mmMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1502 + #define mmMMMC_VM_L2_PERFCOUNTER2_CFG 0x07a6 1503 + #define mmMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 0 1504 + #define mmMMMC_VM_L2_PERFCOUNTER3_CFG 0x07a7 1505 + #define mmMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 0 1506 + #define mmMMMC_VM_L2_PERFCOUNTER4_CFG 0x07a8 1507 + #define mmMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 0 1508 + #define mmMMMC_VM_L2_PERFCOUNTER5_CFG 0x07a9 1509 + #define mmMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 0 1510 + #define mmMMMC_VM_L2_PERFCOUNTER6_CFG 0x07aa 1511 + #define mmMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 0 1512 + #define mmMMMC_VM_L2_PERFCOUNTER7_CFG 0x07ab 1513 + #define mmMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 0 1514 + #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x07ac 1515 + #define mmMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1516 + 1517 + 1518 + // addressBlock: mmhub_mmutcl2_mmvml2prdec 1519 + // base address: 0x69ee0 1520 + #define mmMMMC_VM_L2_PERFCOUNTER_LO 0x07b8 1521 + #define mmMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 0 1522 + #define mmMMMC_VM_L2_PERFCOUNTER_HI 0x07b9 1523 + #define mmMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 0 1524 + 1525 + 1526 + // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1527 + // base address: 0x69f30 1528 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF0 0x07cc 1529 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 0 1530 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF1 0x07cd 1531 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 0 1532 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF2 0x07ce 1533 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 0 1534 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF3 0x07cf 1535 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 0 1536 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF4 0x07d0 1537 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 0 1538 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF5 0x07d1 1539 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 0 1540 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF6 0x07d2 1541 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 0 1542 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF7 0x07d3 1543 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 0 1544 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF8 0x07d4 1545 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 0 1546 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF9 0x07d5 1547 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 0 1548 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF10 0x07d6 1549 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 0 1550 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF11 0x07d7 1551 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 0 1552 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF12 0x07d8 1553 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 0 1554 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF13 0x07d9 1555 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 0 1556 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF14 0x07da 1557 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 0 1558 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF15 0x07db 1559 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 0 1560 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF16 0x07dc 1561 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX 0 1562 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF17 0x07dd 1563 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX 0 1564 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF18 0x07de 1565 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX 0 1566 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF19 0x07df 1567 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX 0 1568 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF20 0x07e0 1569 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX 0 1570 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF21 0x07e1 1571 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX 0 1572 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF22 0x07e2 1573 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX 0 1574 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF23 0x07e3 1575 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX 0 1576 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF24 0x07e4 1577 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX 0 1578 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF25 0x07e5 1579 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX 0 1580 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF26 0x07e6 1581 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX 0 1582 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF27 0x07e7 1583 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX 0 1584 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF28 0x07e8 1585 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX 0 1586 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF29 0x07e9 1587 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX 0 1588 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF30 0x07ea 1589 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX 0 1590 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF31 0x07eb 1591 + #define mmMMMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX 0 1592 + #define mmMMVM_IOMMU_MMIO_CNTRL_1 0x07ec 1593 + #define mmMMVM_IOMMU_MMIO_CNTRL_1_BASE_IDX 0 1594 + #define mmMMMC_VM_MARC_BASE_LO_0 0x07ed 1595 + #define mmMMMC_VM_MARC_BASE_LO_0_BASE_IDX 0 1596 + #define mmMMMC_VM_MARC_BASE_LO_1 0x07ee 1597 + #define mmMMMC_VM_MARC_BASE_LO_1_BASE_IDX 0 1598 + #define mmMMMC_VM_MARC_BASE_LO_2 0x07ef 1599 + #define mmMMMC_VM_MARC_BASE_LO_2_BASE_IDX 0 1600 + #define mmMMMC_VM_MARC_BASE_LO_3 0x07f0 1601 + #define mmMMMC_VM_MARC_BASE_LO_3_BASE_IDX 0 1602 + #define mmMMMC_VM_MARC_BASE_HI_0 0x07f1 1603 + #define mmMMMC_VM_MARC_BASE_HI_0_BASE_IDX 0 1604 + #define mmMMMC_VM_MARC_BASE_HI_1 0x07f2 1605 + #define mmMMMC_VM_MARC_BASE_HI_1_BASE_IDX 0 1606 + #define mmMMMC_VM_MARC_BASE_HI_2 0x07f3 1607 + #define mmMMMC_VM_MARC_BASE_HI_2_BASE_IDX 0 1608 + #define mmMMMC_VM_MARC_BASE_HI_3 0x07f4 1609 + #define mmMMMC_VM_MARC_BASE_HI_3_BASE_IDX 0 1610 + #define mmMMMC_VM_MARC_RELOC_LO_0 0x07f5 1611 + #define mmMMMC_VM_MARC_RELOC_LO_0_BASE_IDX 0 1612 + #define mmMMMC_VM_MARC_RELOC_LO_1 0x07f6 1613 + #define mmMMMC_VM_MARC_RELOC_LO_1_BASE_IDX 0 1614 + #define mmMMMC_VM_MARC_RELOC_LO_2 0x07f7 1615 + #define mmMMMC_VM_MARC_RELOC_LO_2_BASE_IDX 0 1616 + #define mmMMMC_VM_MARC_RELOC_LO_3 0x07f8 1617 + #define mmMMMC_VM_MARC_RELOC_LO_3_BASE_IDX 0 1618 + #define mmMMMC_VM_MARC_RELOC_HI_0 0x07f9 1619 + #define mmMMMC_VM_MARC_RELOC_HI_0_BASE_IDX 0 1620 + #define mmMMMC_VM_MARC_RELOC_HI_1 0x07fa 1621 + #define mmMMMC_VM_MARC_RELOC_HI_1_BASE_IDX 0 1622 + #define mmMMMC_VM_MARC_RELOC_HI_2 0x07fb 1623 + #define mmMMMC_VM_MARC_RELOC_HI_2_BASE_IDX 0 1624 + #define mmMMMC_VM_MARC_RELOC_HI_3 0x07fc 1625 + #define mmMMMC_VM_MARC_RELOC_HI_3_BASE_IDX 0 1626 + #define mmMMMC_VM_MARC_LEN_LO_0 0x07fd 1627 + #define mmMMMC_VM_MARC_LEN_LO_0_BASE_IDX 0 1628 + #define mmMMMC_VM_MARC_LEN_LO_1 0x07fe 1629 + #define mmMMMC_VM_MARC_LEN_LO_1_BASE_IDX 0 1630 + #define mmMMMC_VM_MARC_LEN_LO_2 0x07ff 1631 + #define mmMMMC_VM_MARC_LEN_LO_2_BASE_IDX 0 1632 + #define mmMMMC_VM_MARC_LEN_LO_3 0x0800 1633 + #define mmMMMC_VM_MARC_LEN_LO_3_BASE_IDX 0 1634 + #define mmMMMC_VM_MARC_LEN_HI_0 0x0801 1635 + #define mmMMMC_VM_MARC_LEN_HI_0_BASE_IDX 0 1636 + #define mmMMMC_VM_MARC_LEN_HI_1 0x0802 1637 + #define mmMMMC_VM_MARC_LEN_HI_1_BASE_IDX 0 1638 + #define mmMMMC_VM_MARC_LEN_HI_2 0x0803 1639 + #define mmMMMC_VM_MARC_LEN_HI_2_BASE_IDX 0 1640 + #define mmMMMC_VM_MARC_LEN_HI_3 0x0804 1641 + #define mmMMMC_VM_MARC_LEN_HI_3_BASE_IDX 0 1642 + #define mmMMVM_IOMMU_CONTROL_REGISTER 0x0805 1643 + #define mmMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 0 1644 + #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0806 1645 + #define mmMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 0 1646 + #define mmMMVM_PCIE_ATS_CNTL 0x0807 1647 + #define mmMMVM_PCIE_ATS_CNTL_BASE_IDX 0 1648 + #define mmMMVM_PCIE_ATS_CNTL_VF_0 0x0808 1649 + #define mmMMVM_PCIE_ATS_CNTL_VF_0_BASE_IDX 0 1650 + #define mmMMVM_PCIE_ATS_CNTL_VF_1 0x0809 1651 + #define mmMMVM_PCIE_ATS_CNTL_VF_1_BASE_IDX 0 1652 + #define mmMMVM_PCIE_ATS_CNTL_VF_2 0x080a 1653 + #define mmMMVM_PCIE_ATS_CNTL_VF_2_BASE_IDX 0 1654 + #define mmMMVM_PCIE_ATS_CNTL_VF_3 0x080b 1655 + #define mmMMVM_PCIE_ATS_CNTL_VF_3_BASE_IDX 0 1656 + #define mmMMVM_PCIE_ATS_CNTL_VF_4 0x080c 1657 + #define mmMMVM_PCIE_ATS_CNTL_VF_4_BASE_IDX 0 1658 + #define mmMMVM_PCIE_ATS_CNTL_VF_5 0x080d 1659 + #define mmMMVM_PCIE_ATS_CNTL_VF_5_BASE_IDX 0 1660 + #define mmMMVM_PCIE_ATS_CNTL_VF_6 0x080e 1661 + #define mmMMVM_PCIE_ATS_CNTL_VF_6_BASE_IDX 0 1662 + #define mmMMVM_PCIE_ATS_CNTL_VF_7 0x080f 1663 + #define mmMMVM_PCIE_ATS_CNTL_VF_7_BASE_IDX 0 1664 + #define mmMMVM_PCIE_ATS_CNTL_VF_8 0x0810 1665 + #define mmMMVM_PCIE_ATS_CNTL_VF_8_BASE_IDX 0 1666 + #define mmMMVM_PCIE_ATS_CNTL_VF_9 0x0811 1667 + #define mmMMVM_PCIE_ATS_CNTL_VF_9_BASE_IDX 0 1668 + #define mmMMVM_PCIE_ATS_CNTL_VF_10 0x0812 1669 + #define mmMMVM_PCIE_ATS_CNTL_VF_10_BASE_IDX 0 1670 + #define mmMMVM_PCIE_ATS_CNTL_VF_11 0x0813 1671 + #define mmMMVM_PCIE_ATS_CNTL_VF_11_BASE_IDX 0 1672 + #define mmMMVM_PCIE_ATS_CNTL_VF_12 0x0814 1673 + #define mmMMVM_PCIE_ATS_CNTL_VF_12_BASE_IDX 0 1674 + #define mmMMVM_PCIE_ATS_CNTL_VF_13 0x0815 1675 + #define mmMMVM_PCIE_ATS_CNTL_VF_13_BASE_IDX 0 1676 + #define mmMMVM_PCIE_ATS_CNTL_VF_14 0x0816 1677 + #define mmMMVM_PCIE_ATS_CNTL_VF_14_BASE_IDX 0 1678 + #define mmMMVM_PCIE_ATS_CNTL_VF_15 0x0817 1679 + #define mmMMVM_PCIE_ATS_CNTL_VF_15_BASE_IDX 0 1680 + #define mmMMVM_PCIE_ATS_CNTL_VF_16 0x0818 1681 + #define mmMMVM_PCIE_ATS_CNTL_VF_16_BASE_IDX 0 1682 + #define mmMMVM_PCIE_ATS_CNTL_VF_17 0x0819 1683 + #define mmMMVM_PCIE_ATS_CNTL_VF_17_BASE_IDX 0 1684 + #define mmMMVM_PCIE_ATS_CNTL_VF_18 0x081a 1685 + #define mmMMVM_PCIE_ATS_CNTL_VF_18_BASE_IDX 0 1686 + #define mmMMVM_PCIE_ATS_CNTL_VF_19 0x081b 1687 + #define mmMMVM_PCIE_ATS_CNTL_VF_19_BASE_IDX 0 1688 + #define mmMMVM_PCIE_ATS_CNTL_VF_20 0x081c 1689 + #define mmMMVM_PCIE_ATS_CNTL_VF_20_BASE_IDX 0 1690 + #define mmMMVM_PCIE_ATS_CNTL_VF_21 0x081d 1691 + #define mmMMVM_PCIE_ATS_CNTL_VF_21_BASE_IDX 0 1692 + #define mmMMVM_PCIE_ATS_CNTL_VF_22 0x081e 1693 + #define mmMMVM_PCIE_ATS_CNTL_VF_22_BASE_IDX 0 1694 + #define mmMMVM_PCIE_ATS_CNTL_VF_23 0x081f 1695 + #define mmMMVM_PCIE_ATS_CNTL_VF_23_BASE_IDX 0 1696 + #define mmMMVM_PCIE_ATS_CNTL_VF_24 0x0820 1697 + #define mmMMVM_PCIE_ATS_CNTL_VF_24_BASE_IDX 0 1698 + #define mmMMVM_PCIE_ATS_CNTL_VF_25 0x0821 1699 + #define mmMMVM_PCIE_ATS_CNTL_VF_25_BASE_IDX 0 1700 + #define mmMMVM_PCIE_ATS_CNTL_VF_26 0x0822 1701 + #define mmMMVM_PCIE_ATS_CNTL_VF_26_BASE_IDX 0 1702 + #define mmMMVM_PCIE_ATS_CNTL_VF_27 0x0823 1703 + #define mmMMVM_PCIE_ATS_CNTL_VF_27_BASE_IDX 0 1704 + #define mmMMVM_PCIE_ATS_CNTL_VF_28 0x0824 1705 + #define mmMMVM_PCIE_ATS_CNTL_VF_28_BASE_IDX 0 1706 + #define mmMMVM_PCIE_ATS_CNTL_VF_29 0x0825 1707 + #define mmMMVM_PCIE_ATS_CNTL_VF_29_BASE_IDX 0 1708 + #define mmMMVM_PCIE_ATS_CNTL_VF_30 0x0826 1709 + #define mmMMVM_PCIE_ATS_CNTL_VF_30_BASE_IDX 0 1710 + #define mmMMVM_PCIE_ATS_CNTL_VF_31 0x0827 1711 + #define mmMMVM_PCIE_ATS_CNTL_VF_31_BASE_IDX 0 1712 + #define mmMMUTCL2_CGTT_CLK_CTRL 0x0828 1713 + #define mmMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 0 1714 + #define mmMMMC_SHARED_ACTIVE_FCN_ID 0x0829 1715 + #define mmMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 1716 + 1717 + 1718 + // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1719 + // base address: 0x6a140 1720 + #define mmMMMC_VM_NB_MMIOBASE 0x0850 1721 + #define mmMMMC_VM_NB_MMIOBASE_BASE_IDX 0 1722 + #define mmMMMC_VM_NB_MMIOLIMIT 0x0851 1723 + #define mmMMMC_VM_NB_MMIOLIMIT_BASE_IDX 0 1724 + #define mmMMMC_VM_NB_PCI_CTRL 0x0852 1725 + #define mmMMMC_VM_NB_PCI_CTRL_BASE_IDX 0 1726 + #define mmMMMC_VM_NB_PCI_ARB 0x0853 1727 + #define mmMMMC_VM_NB_PCI_ARB_BASE_IDX 0 1728 + #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x0854 1729 + #define mmMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 0 1730 + #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x0855 1731 + #define mmMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 0 1732 + #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x0856 1733 + #define mmMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 0 1734 + #define mmMMMC_VM_FB_OFFSET 0x0857 1735 + #define mmMMMC_VM_FB_OFFSET_BASE_IDX 0 1736 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0858 1737 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 1738 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0859 1739 + #define mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 1740 + #define mmMMMC_VM_STEERING 0x085a 1741 + #define mmMMMC_VM_STEERING_BASE_IDX 0 1742 + #define mmMMMC_SHARED_VIRT_RESET_REQ 0x085b 1743 + #define mmMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 0 1744 + #define mmMMMC_MEM_POWER_LS 0x085c 1745 + #define mmMMMC_MEM_POWER_LS_BASE_IDX 0 1746 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x085d 1747 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 1748 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x085e 1749 + #define mmMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 0 1750 + #define mmMMMC_VM_APT_CNTL 0x085f 1751 + #define mmMMMC_VM_APT_CNTL_BASE_IDX 0 1752 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0860 1753 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 0 1754 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START 0x0861 1755 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 0 1756 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END 0x0862 1757 + #define mmMMMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 0 1758 + #define mmMMMC_SHARED_VIRT_RESET_REQ2 0x0863 1759 + #define mmMMMC_SHARED_VIRT_RESET_REQ2_BASE_IDX 0 1760 + 1761 + 1762 + // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1763 + // base address: 0x6a1b0 1764 + #define mmMMMC_VM_FB_LOCATION_BASE 0x086c 1765 + #define mmMMMC_VM_FB_LOCATION_BASE_BASE_IDX 0 1766 + #define mmMMMC_VM_FB_LOCATION_TOP 0x086d 1767 + #define mmMMMC_VM_FB_LOCATION_TOP_BASE_IDX 0 1768 + #define mmMMMC_VM_AGP_TOP 0x086e 1769 + #define mmMMMC_VM_AGP_TOP_BASE_IDX 0 1770 + #define mmMMMC_VM_AGP_BOT 0x086f 1771 + #define mmMMMC_VM_AGP_BOT_BASE_IDX 0 1772 + #define mmMMMC_VM_AGP_BASE 0x0870 1773 + #define mmMMMC_VM_AGP_BASE_BASE_IDX 0 1774 + #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0871 1775 + #define mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 0 1776 + #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0872 1777 + #define mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 0 1778 + #define mmMMMC_VM_MX_L1_TLB_CNTL 0x0873 1779 + #define mmMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 1780 + 1781 + 1782 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1783 + // base address: 0x6a200 1784 + #define mmMM_ATC_L2_PERFCOUNTER_LO 0x0880 1785 + #define mmMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 0 1786 + #define mmMM_ATC_L2_PERFCOUNTER_HI 0x0881 1787 + #define mmMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 0 1788 + 1789 + 1790 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1791 + // base address: 0x6a220 1792 + #define mmMM_ATC_L2_PERFCOUNTER0_CFG 0x0888 1793 + #define mmMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 0 1794 + #define mmMM_ATC_L2_PERFCOUNTER1_CFG 0x0889 1795 + #define mmMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 0 1796 + #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x088a 1797 + #define mmMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 1798 + 1799 + #endif
+7567
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_sh_mask.h
··· 1 + /* 2 + * Copyright (C) 2019 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included 12 + * in all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 + */ 21 + #ifndef _mmhub_2_0_0_SH_MASK_HEADER 22 + #define _mmhub_2_0_0_SH_MASK_HEADER 23 + 24 + 25 + // addressBlock: mmhub_dagbdec 26 + //DAGB0_RDCLI0 27 + #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 28 + #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 + #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 30 + #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 31 + #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 + #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 33 + #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 + #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 35 + #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 + #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 37 + #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 38 + #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 39 + #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 40 + #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 41 + #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 42 + #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 43 + #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 44 + #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 45 + #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 46 + #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 47 + //DAGB0_RDCLI1 48 + #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 49 + #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 50 + #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 51 + #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 52 + #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 53 + #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 54 + #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 55 + #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 56 + #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 57 + #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 58 + #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 59 + #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 60 + #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 61 + #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 62 + #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 63 + #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 64 + #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 65 + #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 66 + #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 67 + #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 68 + //DAGB0_RDCLI2 69 + #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 70 + #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 71 + #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 72 + #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 73 + #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 74 + #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 75 + #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 76 + #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 77 + #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 78 + #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 79 + #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 80 + #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 81 + #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 82 + #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 83 + #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 84 + #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 85 + #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 86 + #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 87 + #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 88 + #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 89 + //DAGB0_RDCLI3 90 + #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 91 + #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 92 + #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 93 + #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 94 + #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 95 + #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 96 + #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 97 + #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 98 + #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 99 + #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 100 + #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 101 + #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 102 + #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 103 + #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 104 + #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 105 + #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 106 + #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 107 + #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 108 + #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 109 + #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 110 + //DAGB0_RDCLI4 111 + #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 112 + #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 113 + #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 114 + #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 115 + #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 116 + #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 117 + #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 118 + #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 119 + #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 120 + #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 121 + #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 122 + #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 123 + #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 124 + #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 125 + #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 126 + #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 127 + #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 128 + #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 129 + #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 130 + #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 131 + //DAGB0_RDCLI5 132 + #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 133 + #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 134 + #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 135 + #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 136 + #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 137 + #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 138 + #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 139 + #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 140 + #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 141 + #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 142 + #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 143 + #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 144 + #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 145 + #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 146 + #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 147 + #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 148 + #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 149 + #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 150 + #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 151 + #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 152 + //DAGB0_RDCLI6 153 + #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 154 + #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 155 + #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 156 + #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 157 + #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 158 + #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 159 + #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 160 + #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 161 + #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 162 + #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 163 + #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 164 + #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 165 + #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 166 + #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 167 + #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 168 + #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 169 + #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 170 + #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 171 + #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 172 + #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 173 + //DAGB0_RDCLI7 174 + #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 175 + #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 176 + #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 177 + #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 178 + #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 179 + #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 180 + #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 181 + #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 182 + #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 183 + #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 184 + #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 185 + #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 186 + #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 187 + #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 188 + #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 189 + #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 190 + #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 191 + #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 192 + #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 193 + #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 194 + //DAGB0_RDCLI8 195 + #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 196 + #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 197 + #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 198 + #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 199 + #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 200 + #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 201 + #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 202 + #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 203 + #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 204 + #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 205 + #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 206 + #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 207 + #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 208 + #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 209 + #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 210 + #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 211 + #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 212 + #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 213 + #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 214 + #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 215 + //DAGB0_RDCLI9 216 + #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 217 + #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 218 + #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 219 + #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 220 + #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 221 + #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 222 + #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 223 + #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 224 + #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 225 + #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 226 + #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 227 + #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 228 + #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 229 + #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 230 + #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 231 + #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 232 + #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 233 + #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 234 + #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 235 + #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 236 + //DAGB0_RDCLI10 237 + #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 238 + #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 239 + #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 240 + #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 241 + #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 242 + #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 243 + #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 244 + #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 245 + #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 246 + #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 247 + #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 248 + #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 249 + #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 250 + #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 251 + #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 252 + #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 253 + #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 254 + #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 255 + #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 256 + #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 257 + //DAGB0_RDCLI11 258 + #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 259 + #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 260 + #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 261 + #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 262 + #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 263 + #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 264 + #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 265 + #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 266 + #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 267 + #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 268 + #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 269 + #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 270 + #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 271 + #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 272 + #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 273 + #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 274 + #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 275 + #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 276 + #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 277 + #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 278 + //DAGB0_RDCLI12 279 + #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 280 + #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 281 + #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 282 + #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 283 + #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 284 + #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 285 + #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 286 + #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 287 + #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 288 + #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 289 + #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 290 + #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 291 + #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 292 + #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 293 + #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 294 + #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 295 + #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 296 + #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 297 + #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 298 + #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 299 + //DAGB0_RDCLI13 300 + #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 301 + #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 302 + #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 303 + #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 304 + #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 305 + #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 306 + #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 307 + #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 308 + #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 309 + #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 310 + #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 311 + #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 312 + #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 313 + #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 314 + #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 315 + #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 316 + #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 317 + #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 318 + #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 319 + #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 320 + //DAGB0_RDCLI14 321 + #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 322 + #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 323 + #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 324 + #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 325 + #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 326 + #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 327 + #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 328 + #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 329 + #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 330 + #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 331 + #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 332 + #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 333 + #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 334 + #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 335 + #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 336 + #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 337 + #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 338 + #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 339 + #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 340 + #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 341 + //DAGB0_RDCLI15 342 + #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 343 + #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 344 + #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 345 + #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 346 + #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 347 + #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 348 + #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 349 + #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 350 + #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 351 + #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 352 + #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 353 + #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 354 + #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 355 + #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 356 + #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 357 + #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 358 + #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 359 + #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 360 + #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 361 + #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 362 + //DAGB0_RDCLI16 363 + #define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 364 + #define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 365 + #define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 366 + #define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 367 + #define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 368 + #define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 369 + #define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 370 + #define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 371 + #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 372 + #define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 373 + #define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 374 + #define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 375 + #define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 376 + #define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 377 + #define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 378 + #define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 379 + #define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 380 + #define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 381 + #define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 382 + #define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 383 + //DAGB0_RDCLI17 384 + #define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 385 + #define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 386 + #define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 387 + #define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 388 + #define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 389 + #define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 390 + #define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 391 + #define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 392 + #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 393 + #define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 394 + #define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 395 + #define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 396 + #define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 397 + #define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 398 + #define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 399 + #define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 400 + #define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 401 + #define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 402 + #define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 403 + #define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 404 + //DAGB0_RDCLI18 405 + #define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 406 + #define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 407 + #define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 408 + #define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 409 + #define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 410 + #define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 411 + #define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 412 + #define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 413 + #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 414 + #define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 415 + #define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 416 + #define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 417 + #define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 418 + #define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 419 + #define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 420 + #define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 421 + #define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 422 + #define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 423 + #define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 424 + #define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 425 + //DAGB0_RD_CNTL 426 + #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 427 + #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 428 + #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 429 + #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 430 + #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 431 + #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 432 + #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 433 + #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 434 + #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 435 + #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 436 + #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 437 + #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 438 + #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 439 + #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 440 + //DAGB0_RD_GMI_CNTL 441 + #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 442 + #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 443 + #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 444 + #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 445 + #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 446 + #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 447 + #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 448 + #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 449 + //DAGB0_RD_ADDR_DAGB 450 + #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 451 + #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 452 + #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 453 + #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 454 + #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 455 + #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 456 + #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 457 + #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 458 + //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 459 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 460 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 461 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 462 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 463 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 464 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 465 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 466 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 467 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 468 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 469 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 470 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 471 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 472 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 473 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 474 + #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 475 + //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 476 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 477 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 478 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 479 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 480 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 481 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 482 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 483 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 484 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 485 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 486 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 487 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 488 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 489 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 490 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 491 + #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 492 + //DAGB0_RD_CGTT_CLK_CTRL 493 + #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 494 + #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 495 + #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 496 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 497 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 498 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 499 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 500 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 501 + #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 502 + #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 503 + #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 504 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 505 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 506 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 507 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 508 + #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 509 + //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 510 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 511 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 512 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 513 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 514 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 515 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 516 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 517 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 518 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 519 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 520 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 521 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 522 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 523 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 524 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 525 + #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 526 + //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 527 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 528 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 529 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 530 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 531 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 532 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 533 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 534 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 535 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 536 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 537 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 538 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 539 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 540 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 541 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 542 + #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 543 + //DAGB0_RD_ADDR_DAGB_MAX_BURST0 544 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 545 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 546 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 547 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 548 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 549 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 550 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 551 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 552 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 553 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 554 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 555 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 556 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 557 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 558 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 559 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 560 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 561 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 562 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 563 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 564 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 565 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 566 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 567 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 568 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 569 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 570 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 571 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 572 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 573 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 574 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 575 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 576 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 577 + //DAGB0_RD_ADDR_DAGB_MAX_BURST1 578 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 579 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 580 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 581 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 582 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 583 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 584 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 585 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 586 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 587 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 588 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 589 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 590 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 591 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 592 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 593 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 594 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 595 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 596 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 597 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 598 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 599 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 600 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 601 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 602 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 603 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 604 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 605 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 606 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 607 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 608 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 609 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 610 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 611 + //DAGB0_RD_ADDR_DAGB_MAX_BURST2 612 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 613 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 614 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 615 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 616 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 617 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 618 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 619 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 620 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 621 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 622 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 623 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 624 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 625 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 626 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 627 + #define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 628 + //DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 629 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 630 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 631 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 632 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 633 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 634 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 635 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 636 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 637 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 638 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 639 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 640 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 641 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 642 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 643 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 644 + #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 645 + //DAGB0_RD_VC0_CNTL 646 + #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 647 + #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 648 + #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 649 + #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 650 + #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 651 + #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 652 + #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 653 + #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 654 + #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 655 + #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 656 + #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 657 + #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 658 + #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 659 + #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 660 + #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 661 + #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 662 + //DAGB0_RD_VC1_CNTL 663 + #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 664 + #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 665 + #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 666 + #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 667 + #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 668 + #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 669 + #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 670 + #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 671 + #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 672 + #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 673 + #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 674 + #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 675 + #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 676 + #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 677 + #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 678 + #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 679 + //DAGB0_RD_VC2_CNTL 680 + #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 681 + #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 682 + #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 683 + #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 684 + #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 685 + #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 686 + #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 687 + #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 688 + #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 689 + #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 690 + #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 691 + #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 692 + #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 693 + #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 694 + #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 695 + #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 696 + //DAGB0_RD_VC3_CNTL 697 + #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 698 + #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 699 + #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 700 + #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 701 + #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 702 + #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 703 + #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 704 + #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 705 + #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 706 + #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 707 + #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 708 + #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 709 + #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 710 + #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 711 + #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 712 + #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 713 + //DAGB0_RD_VC4_CNTL 714 + #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 715 + #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 716 + #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 717 + #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 718 + #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 719 + #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 720 + #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 721 + #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 722 + #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 723 + #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 724 + #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 725 + #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 726 + #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 727 + #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 728 + #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 729 + #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 730 + //DAGB0_RD_VC5_CNTL 731 + #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 732 + #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 733 + #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 734 + #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 735 + #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 736 + #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 737 + #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 738 + #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 739 + #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 740 + #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 741 + #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 742 + #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 743 + #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 744 + #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 745 + #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 746 + #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 747 + //DAGB0_RD_VC6_CNTL 748 + #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 749 + #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 750 + #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 751 + #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 752 + #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 753 + #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 754 + #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 755 + #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 756 + #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 757 + #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 758 + #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 759 + #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 760 + #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 761 + #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 762 + #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 763 + #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 764 + //DAGB0_RD_VC7_CNTL 765 + #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 766 + #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 767 + #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 768 + #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 769 + #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 770 + #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 771 + #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 772 + #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 773 + #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 774 + #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 775 + #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 776 + #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 777 + #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 778 + #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 779 + #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 780 + #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 781 + //DAGB0_RD_CNTL_MISC 782 + #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 783 + #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 784 + #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 785 + #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 786 + #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 787 + #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 788 + #define DAGB0_RD_CNTL_MISC__HDP_CID__SHIFT 0x1a 789 + #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 790 + #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 791 + #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 792 + #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 793 + #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 794 + #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 795 + #define DAGB0_RD_CNTL_MISC__HDP_CID_MASK 0x7C000000L 796 + //DAGB0_RD_TLB_CREDIT 797 + #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 798 + #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 799 + #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 800 + #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 801 + #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 802 + #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 803 + #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 804 + #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 805 + #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 806 + #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 807 + #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 808 + #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 809 + //DAGB0_RDCLI_ASK_PENDING 810 + #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 811 + #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 812 + //DAGB0_RDCLI_GO_PENDING 813 + #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 814 + #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 815 + //DAGB0_RDCLI_GBLSEND_PENDING 816 + #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 817 + #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 818 + //DAGB0_RDCLI_TLB_PENDING 819 + #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 820 + #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 821 + //DAGB0_RDCLI_OARB_PENDING 822 + #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 823 + #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 824 + //DAGB0_RDCLI_OSD_PENDING 825 + #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 826 + #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 827 + //DAGB0_WRCLI0 828 + #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 829 + #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 830 + #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 831 + #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 832 + #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 833 + #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 834 + #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 835 + #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 836 + #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 837 + #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 838 + #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 839 + #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 840 + #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 841 + #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 842 + #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 843 + #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 844 + #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 845 + #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 846 + #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 847 + #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 848 + //DAGB0_WRCLI1 849 + #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 850 + #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 851 + #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 852 + #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 853 + #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 854 + #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 855 + #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 856 + #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 857 + #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 858 + #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 859 + #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 860 + #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 861 + #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 862 + #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 863 + #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 864 + #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 865 + #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 866 + #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 867 + #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 868 + #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 869 + //DAGB0_WRCLI2 870 + #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 871 + #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 872 + #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 873 + #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 874 + #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 875 + #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 876 + #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 877 + #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 878 + #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 879 + #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 880 + #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 881 + #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 882 + #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 883 + #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 884 + #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 885 + #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 886 + #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 887 + #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 888 + #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 889 + #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 890 + //DAGB0_WRCLI3 891 + #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 892 + #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 893 + #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 894 + #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 895 + #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 896 + #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 897 + #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 898 + #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 899 + #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 900 + #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 901 + #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 902 + #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 903 + #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 904 + #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 905 + #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 906 + #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 907 + #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 908 + #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 909 + #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 910 + #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 911 + //DAGB0_WRCLI4 912 + #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 913 + #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 914 + #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 915 + #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 916 + #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 917 + #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 918 + #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 919 + #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 920 + #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 921 + #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 922 + #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 923 + #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 924 + #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 925 + #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 926 + #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 927 + #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 928 + #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 929 + #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 930 + #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 931 + #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 932 + //DAGB0_WRCLI5 933 + #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 934 + #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 935 + #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 936 + #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 937 + #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 938 + #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 939 + #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 940 + #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 941 + #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 942 + #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 943 + #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 944 + #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 945 + #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 946 + #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 947 + #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 948 + #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 949 + #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 950 + #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 951 + #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 952 + #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 953 + //DAGB0_WRCLI6 954 + #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 955 + #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 956 + #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 957 + #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 958 + #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 959 + #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 960 + #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 961 + #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 962 + #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 963 + #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 964 + #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 965 + #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 966 + #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 967 + #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 968 + #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 969 + #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 970 + #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 971 + #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 972 + #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 973 + #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 974 + //DAGB0_WRCLI7 975 + #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 976 + #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 977 + #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 978 + #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 979 + #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 980 + #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 981 + #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 982 + #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 983 + #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 984 + #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 985 + #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 986 + #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 987 + #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 988 + #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 989 + #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 990 + #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 991 + #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 992 + #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 993 + #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 994 + #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 995 + //DAGB0_WRCLI8 996 + #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 997 + #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 998 + #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 999 + #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1000 + #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1001 + #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1002 + #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1003 + #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1004 + #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1005 + #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1006 + #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1007 + #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1008 + #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1009 + #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1010 + #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1011 + #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1012 + #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1013 + #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1014 + #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1015 + #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1016 + //DAGB0_WRCLI9 1017 + #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1018 + #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1019 + #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1020 + #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1021 + #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1022 + #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1023 + #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1024 + #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1025 + #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1026 + #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1027 + #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1028 + #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1029 + #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1030 + #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1031 + #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1032 + #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1033 + #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1034 + #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1035 + #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1036 + #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1037 + //DAGB0_WRCLI10 1038 + #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1039 + #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1040 + #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1041 + #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1042 + #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1043 + #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1044 + #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1045 + #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1046 + #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1047 + #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1048 + #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1049 + #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1050 + #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1051 + #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1052 + #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1053 + #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1054 + #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1055 + #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1056 + #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1057 + #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1058 + //DAGB0_WRCLI11 1059 + #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1060 + #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1061 + #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1062 + #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1063 + #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1064 + #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1065 + #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1066 + #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1067 + #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1068 + #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1069 + #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1070 + #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1071 + #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1072 + #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1073 + #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1074 + #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1075 + #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1076 + #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1077 + #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1078 + #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1079 + //DAGB0_WRCLI12 1080 + #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1081 + #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1082 + #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1083 + #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1084 + #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1085 + #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1086 + #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1087 + #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1088 + #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1089 + #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1090 + #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1091 + #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1092 + #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1093 + #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1094 + #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1095 + #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1096 + #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1097 + #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1098 + #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1099 + #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1100 + //DAGB0_WRCLI13 1101 + #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1102 + #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1103 + #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1104 + #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1105 + #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1106 + #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1107 + #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1108 + #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1109 + #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1110 + #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1111 + #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1112 + #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1113 + #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1114 + #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1115 + #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1116 + #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1117 + #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1118 + #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1119 + #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1120 + #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1121 + //DAGB0_WRCLI14 1122 + #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1123 + #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1124 + #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1125 + #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1126 + #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1127 + #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1128 + #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1129 + #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1130 + #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1131 + #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1132 + #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1133 + #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1134 + #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1135 + #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1136 + #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1137 + #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1138 + #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1139 + #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1140 + #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1141 + #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1142 + //DAGB0_WRCLI15 1143 + #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1144 + #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1145 + #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1146 + #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1147 + #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1148 + #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1149 + #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1150 + #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1151 + #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1152 + #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1153 + #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1154 + #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1155 + #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1156 + #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1157 + #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1158 + #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1159 + #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1160 + #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1161 + #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1162 + #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1163 + //DAGB0_WRCLI16 1164 + #define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1165 + #define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1166 + #define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1167 + #define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1168 + #define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1169 + #define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1170 + #define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1171 + #define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1172 + #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1173 + #define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1174 + #define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1175 + #define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1176 + #define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1177 + #define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1178 + #define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1179 + #define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1180 + #define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1181 + #define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1182 + #define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1183 + #define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1184 + //DAGB0_WRCLI17 1185 + #define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1186 + #define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1187 + #define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1188 + #define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1189 + #define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1190 + #define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1191 + #define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1192 + #define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1193 + #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1194 + #define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1195 + #define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1196 + #define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1197 + #define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1198 + #define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1199 + #define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1200 + #define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1201 + #define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1202 + #define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1203 + #define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1204 + #define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1205 + //DAGB0_WRCLI18 1206 + #define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1207 + #define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1208 + #define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1209 + #define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1210 + #define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1211 + #define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1212 + #define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1213 + #define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1214 + #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1215 + #define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1216 + #define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1217 + #define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1218 + #define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1219 + #define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1220 + #define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1221 + #define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1222 + #define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1223 + #define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1224 + #define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1225 + #define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1226 + //DAGB0_WR_CNTL 1227 + #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1228 + #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1229 + #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1230 + #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1231 + #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1232 + #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1233 + #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1234 + #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1235 + #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1236 + #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1237 + #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1238 + #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1239 + #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1240 + #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1241 + //DAGB0_WR_GMI_CNTL 1242 + #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1243 + #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1244 + #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1245 + #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1246 + #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1247 + #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1248 + #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1249 + #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1250 + //DAGB0_WR_ADDR_DAGB 1251 + #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1252 + #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1253 + #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1254 + #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1255 + #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1256 + #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1257 + #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1258 + #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1259 + //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1260 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1261 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1262 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1263 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1264 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1265 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1266 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1267 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1268 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1269 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1270 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1271 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1272 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1273 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1274 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1275 + #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1276 + //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1277 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1278 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1279 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1280 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1281 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1282 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1283 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1284 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1285 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1286 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1287 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1288 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1289 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1290 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1291 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1292 + #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1293 + //DAGB0_WR_CGTT_CLK_CTRL 1294 + #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1295 + #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1296 + #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1297 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1298 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1299 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1300 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1301 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1302 + #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1303 + #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1304 + #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1305 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1306 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1307 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1308 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1309 + #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1310 + //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1311 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1312 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1313 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1314 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1315 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1316 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1317 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1318 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1319 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1320 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1321 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1322 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1323 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1324 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1325 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1326 + #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1327 + //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1328 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1329 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1330 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1331 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1332 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1333 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1334 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1335 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1336 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1337 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1338 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1339 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1340 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1341 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1342 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1343 + #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1344 + //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1345 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1346 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1347 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1348 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1349 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1350 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1351 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1352 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1353 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1354 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1355 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1356 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1357 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1358 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1359 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1360 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1361 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1362 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1363 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1364 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1365 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1366 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1367 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1368 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1369 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1370 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1371 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1372 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1373 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1374 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1375 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1376 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1377 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1378 + //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1379 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1380 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1381 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1382 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1383 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1384 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1385 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1386 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1387 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1388 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1389 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1390 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1391 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1392 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1393 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1394 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1395 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1396 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1397 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1398 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1399 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1400 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1401 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1402 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1403 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1404 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1405 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1406 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1407 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1408 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1409 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1410 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1411 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1412 + //DAGB0_WR_ADDR_DAGB_MAX_BURST2 1413 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1414 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1415 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1416 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1417 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1418 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1419 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1420 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1421 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1422 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1423 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1424 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1425 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1426 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1427 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1428 + #define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1429 + //DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 1430 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1431 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1432 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1433 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1434 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1435 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1436 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1437 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1438 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1439 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1440 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1441 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1442 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1443 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1444 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1445 + #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1446 + //DAGB0_WR_DATA_DAGB 1447 + #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1448 + #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1449 + #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1450 + #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1451 + #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1452 + #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1453 + #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1454 + #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1455 + //DAGB0_WR_DATA_DAGB_MAX_BURST0 1456 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1457 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1458 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1459 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1460 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1461 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1462 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1463 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1464 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1465 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1466 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1467 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1468 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1469 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1470 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1471 + #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1472 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1473 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1474 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1475 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1476 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1477 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1478 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1479 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1480 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1481 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1482 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1483 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1484 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1485 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1486 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1487 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1488 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1489 + //DAGB0_WR_DATA_DAGB_MAX_BURST1 1490 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1491 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1492 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1493 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1494 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1495 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1496 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1497 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1498 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1499 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1500 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1501 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1502 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1503 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1504 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1505 + #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1506 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1507 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1508 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1509 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1510 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1511 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1512 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1513 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1514 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1515 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1516 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1517 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1518 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1519 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1520 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1521 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1522 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1523 + //DAGB0_WR_DATA_DAGB_MAX_BURST2 1524 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1525 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1526 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1527 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1528 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1529 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1530 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 1531 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 1532 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 1533 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 1534 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 1535 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 1536 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 1537 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 1538 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 1539 + #define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 1540 + //DAGB0_WR_DATA_DAGB_LAZY_TIMER2 1541 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 1542 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 1543 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 1544 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 1545 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 1546 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 1547 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 1548 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 1549 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 1550 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 1551 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 1552 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 1553 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 1554 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 1555 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 1556 + #define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 1557 + //DAGB0_WR_VC0_CNTL 1558 + #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1559 + #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1560 + #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1561 + #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1562 + #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1563 + #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1564 + #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1565 + #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1566 + #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1567 + #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1568 + #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1569 + #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1570 + #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1571 + #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1572 + #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1573 + #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1574 + //DAGB0_WR_VC1_CNTL 1575 + #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1576 + #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1577 + #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1578 + #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1579 + #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1580 + #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1581 + #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1582 + #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1583 + #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1584 + #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1585 + #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1586 + #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1587 + #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1588 + #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1589 + #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1590 + #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1591 + //DAGB0_WR_VC2_CNTL 1592 + #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1593 + #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1594 + #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1595 + #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1596 + #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1597 + #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1598 + #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1599 + #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1600 + #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1601 + #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1602 + #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1603 + #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1604 + #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1605 + #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1606 + #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1607 + #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1608 + //DAGB0_WR_VC3_CNTL 1609 + #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1610 + #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1611 + #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1612 + #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1613 + #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1614 + #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1615 + #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1616 + #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1617 + #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1618 + #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1619 + #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1620 + #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1621 + #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1622 + #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1623 + #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1624 + #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1625 + //DAGB0_WR_VC4_CNTL 1626 + #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1627 + #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1628 + #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1629 + #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1630 + #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1631 + #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1632 + #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1633 + #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1634 + #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1635 + #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1636 + #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1637 + #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1638 + #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1639 + #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1640 + #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1641 + #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1642 + //DAGB0_WR_VC5_CNTL 1643 + #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1644 + #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1645 + #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1646 + #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1647 + #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1648 + #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1649 + #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1650 + #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1651 + #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1652 + #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1653 + #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1654 + #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1655 + #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1656 + #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1657 + #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1658 + #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1659 + //DAGB0_WR_VC6_CNTL 1660 + #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1661 + #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1662 + #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1663 + #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1664 + #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1665 + #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1666 + #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1667 + #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1668 + #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1669 + #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1670 + #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1671 + #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1672 + #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1673 + #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1674 + #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1675 + #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1676 + //DAGB0_WR_VC7_CNTL 1677 + #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1678 + #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1679 + #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1680 + #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1681 + #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1682 + #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1683 + #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1684 + #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1685 + #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1686 + #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1687 + #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1688 + #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1689 + #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1690 + #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1691 + #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1692 + #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1693 + //DAGB0_WR_CNTL_MISC 1694 + #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1695 + #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1696 + #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1697 + #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1698 + #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1699 + #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1700 + #define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT 0x1a 1701 + #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1702 + #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1703 + #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1704 + #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1705 + #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1706 + #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1707 + #define DAGB0_WR_CNTL_MISC__HDP_CID_MASK 0x7C000000L 1708 + //DAGB0_WR_TLB_CREDIT 1709 + #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1710 + #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1711 + #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1712 + #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1713 + #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1714 + #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1715 + #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1716 + #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1717 + #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1718 + #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1719 + #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1720 + #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1721 + //DAGB0_WR_DATA_CREDIT 1722 + #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1723 + #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1724 + #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1725 + #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1726 + #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1727 + #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1728 + #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1729 + #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1730 + //DAGB0_WR_MISC_CREDIT 1731 + #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1732 + #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1733 + #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1734 + #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1735 + #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1736 + #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1737 + #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1738 + #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1739 + //DAGB0_WRCLI_ASK_PENDING 1740 + #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1741 + #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1742 + //DAGB0_WRCLI_GO_PENDING 1743 + #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1744 + #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1745 + //DAGB0_WRCLI_GBLSEND_PENDING 1746 + #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1747 + #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1748 + //DAGB0_WRCLI_TLB_PENDING 1749 + #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1750 + #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1751 + //DAGB0_WRCLI_OARB_PENDING 1752 + #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1753 + #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1754 + //DAGB0_WRCLI_OSD_PENDING 1755 + #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1756 + #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1757 + //DAGB0_WRCLI_DBUS_ASK_PENDING 1758 + #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1759 + #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1760 + //DAGB0_WRCLI_DBUS_GO_PENDING 1761 + #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1762 + #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1763 + //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 1764 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 1765 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1766 + //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 1767 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 1768 + #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 1769 + //DAGB0_DAGB_DLY 1770 + #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1771 + #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1772 + #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1773 + #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1774 + #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1775 + #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1776 + //DAGB0_CNTL_MISC 1777 + #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1778 + #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1779 + #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1780 + #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1781 + #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1782 + #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1783 + #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1784 + #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1785 + #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1786 + #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1787 + #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1788 + #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1789 + #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1790 + #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1791 + #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1792 + #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1793 + #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1794 + #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1795 + #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1796 + #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1797 + //DAGB0_CNTL_MISC2 1798 + #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1799 + #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1800 + #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1801 + #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1802 + #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1803 + #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1804 + #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1805 + #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1806 + #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1807 + #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1808 + #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1809 + #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT 0xb 1810 + #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1811 + #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1812 + #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1813 + #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1814 + #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1815 + #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1816 + #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1817 + #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1818 + #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1819 + #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1820 + #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1821 + #define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK 0x00000800L 1822 + //DAGB0_FIFO_EMPTY 1823 + #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1824 + #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1825 + //DAGB0_FIFO_FULL 1826 + #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1827 + #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1828 + //DAGB0_WR_CREDITS_FULL 1829 + #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1830 + #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 1831 + //DAGB0_RD_CREDITS_FULL 1832 + #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1833 + #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1834 + //DAGB0_PERFCOUNTER_LO 1835 + #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1836 + #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1837 + //DAGB0_PERFCOUNTER_HI 1838 + #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1839 + #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1840 + #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1841 + #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1842 + //DAGB0_PERFCOUNTER0_CFG 1843 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1844 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1845 + #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1846 + #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1847 + #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1848 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1849 + #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1850 + #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1851 + #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1852 + #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1853 + //DAGB0_PERFCOUNTER1_CFG 1854 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1855 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1856 + #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1857 + #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1858 + #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1859 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1860 + #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1861 + #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1862 + #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1863 + #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1864 + //DAGB0_PERFCOUNTER2_CFG 1865 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1866 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1867 + #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1868 + #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1869 + #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1870 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1871 + #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1872 + #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1873 + #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1874 + #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1875 + //DAGB0_PERFCOUNTER_RSLT_CNTL 1876 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1877 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1878 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1879 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1880 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1881 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1882 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1883 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1884 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1885 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1886 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1887 + #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1888 + //DAGB0_RESERVE0 1889 + #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1890 + #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1891 + //DAGB0_RESERVE1 1892 + #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1893 + #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1894 + //DAGB0_RESERVE2 1895 + #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1896 + #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1897 + //DAGB0_RESERVE3 1898 + #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1899 + #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1900 + //DAGB0_RESERVE4 1901 + #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1902 + #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1903 + //DAGB0_RESERVE5 1904 + #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 1905 + #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 1906 + //DAGB0_RESERVE6 1907 + #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 1908 + #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 1909 + //DAGB0_RESERVE7 1910 + #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 1911 + #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 1912 + //DAGB0_RESERVE8 1913 + #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 1914 + #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 1915 + //DAGB0_RESERVE9 1916 + #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 1917 + #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 1918 + //DAGB0_RESERVE10 1919 + #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 1920 + #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 1921 + //DAGB0_RESERVE11 1922 + #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 1923 + #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 1924 + //DAGB0_RESERVE12 1925 + #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 1926 + #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 1927 + //DAGB0_RESERVE13 1928 + #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 1929 + #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 1930 + //DAGB0_RESERVE14 1931 + #define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 1932 + #define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 1933 + //DAGB0_RESERVE15 1934 + #define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 1935 + #define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 1936 + //DAGB0_RESERVE16 1937 + #define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 1938 + #define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 1939 + //DAGB0_RESERVE17 1940 + #define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 1941 + #define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 1942 + //DAGB0_RESERVE18 1943 + #define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 1944 + #define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL 1945 + //DAGB0_RESERVE19 1946 + #define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 1947 + #define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL 1948 + //DAGB0_RESERVE20 1949 + #define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 1950 + #define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL 1951 + //DAGB0_RESERVE21 1952 + #define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 1953 + #define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL 1954 + //DAGB0_RESERVE22 1955 + #define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 1956 + #define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL 1957 + //DAGB0_RESERVE23 1958 + #define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 1959 + #define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL 1960 + //DAGB0_RESERVE24 1961 + #define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 1962 + #define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL 1963 + //DAGB0_RESERVE25 1964 + #define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 1965 + #define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL 1966 + //DAGB0_RESERVE26 1967 + #define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 1968 + #define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL 1969 + //DAGB0_RESERVE27 1970 + #define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 1971 + #define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL 1972 + //DAGB0_RESERVE28 1973 + #define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 1974 + #define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL 1975 + //DAGB0_RESERVE29 1976 + #define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 1977 + #define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL 1978 + //DAGB0_RESERVE30 1979 + #define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 1980 + #define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL 1981 + //DAGB0_RESERVE31 1982 + #define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 1983 + #define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL 1984 + //DAGB0_RESERVE32 1985 + #define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 1986 + #define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL 1987 + //DAGB0_RESERVE33 1988 + #define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 1989 + #define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL 1990 + //DAGB0_RESERVE34 1991 + #define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 1992 + #define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL 1993 + //DAGB0_RESERVE35 1994 + #define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 1995 + #define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL 1996 + //DAGB0_RESERVE36 1997 + #define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 1998 + #define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL 1999 + //DAGB0_RESERVE37 2000 + #define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 2001 + #define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL 2002 + //DAGB0_RESERVE38 2003 + #define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 2004 + #define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL 2005 + //DAGB0_RESERVE39 2006 + #define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 2007 + #define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL 2008 + //DAGB0_RESERVE40 2009 + #define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 2010 + #define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL 2011 + //DAGB0_RESERVE41 2012 + #define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 2013 + #define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL 2014 + //DAGB0_RESERVE42 2015 + #define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 2016 + #define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL 2017 + //DAGB0_RESERVE43 2018 + #define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 2019 + #define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL 2020 + //DAGB0_RESERVE44 2021 + #define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 2022 + #define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL 2023 + //DAGB0_RESERVE45 2024 + #define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 2025 + #define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL 2026 + //DAGB0_RESERVE46 2027 + #define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 2028 + #define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL 2029 + //DAGB0_RESERVE47 2030 + #define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 2031 + #define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL 2032 + //DAGB0_RESERVE48 2033 + #define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 2034 + #define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL 2035 + //DAGB0_RESERVE49 2036 + #define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 2037 + #define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL 2038 + //DAGB0_RESERVE50 2039 + #define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 2040 + #define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL 2041 + //DAGB0_RESERVE51 2042 + #define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 2043 + #define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL 2044 + //DAGB0_RESERVE52 2045 + #define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 2046 + #define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL 2047 + //DAGB0_RESERVE53 2048 + #define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 2049 + #define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL 2050 + //DAGB0_RESERVE54 2051 + #define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 2052 + #define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL 2053 + //DAGB0_RESERVE55 2054 + #define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 2055 + #define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL 2056 + //DAGB0_RESERVE56 2057 + #define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 2058 + #define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL 2059 + //DAGB0_RESERVE57 2060 + #define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 2061 + #define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL 2062 + //DAGB0_RESERVE58 2063 + #define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 2064 + #define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL 2065 + //DAGB0_RESERVE59 2066 + #define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 2067 + #define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL 2068 + //DAGB0_RESERVE60 2069 + #define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 2070 + #define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL 2071 + //DAGB0_RESERVE61 2072 + #define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 2073 + #define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL 2074 + //DAGB0_RESERVE62 2075 + #define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 2076 + #define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL 2077 + //DAGB0_RESERVE63 2078 + #define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 2079 + #define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL 2080 + //DAGB0_RESERVE64 2081 + #define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 2082 + #define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL 2083 + //DAGB0_RESERVE65 2084 + #define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 2085 + #define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL 2086 + //DAGB0_RESERVE66 2087 + #define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 2088 + #define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL 2089 + //DAGB0_RESERVE67 2090 + #define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 2091 + #define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL 2092 + //DAGB0_RESERVE68 2093 + #define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 2094 + #define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL 2095 + //DAGB0_RESERVE69 2096 + #define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 2097 + #define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL 2098 + //DAGB0_RESERVE70 2099 + #define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 2100 + #define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL 2101 + //DAGB0_RESERVE71 2102 + #define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 2103 + #define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL 2104 + //DAGB0_RESERVE72 2105 + #define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 2106 + #define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL 2107 + //DAGB0_RESERVE73 2108 + #define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 2109 + #define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL 2110 + //DAGB0_RESERVE74 2111 + #define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 2112 + #define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL 2113 + //DAGB0_RESERVE75 2114 + #define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 2115 + #define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL 2116 + //DAGB0_RESERVE76 2117 + #define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 2118 + #define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL 2119 + //DAGB0_RESERVE77 2120 + #define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 2121 + #define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL 2122 + //DAGB0_RESERVE78 2123 + #define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 2124 + #define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL 2125 + //DAGB0_RESERVE79 2126 + #define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 2127 + #define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL 2128 + //DAGB0_RESERVE80 2129 + #define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 2130 + #define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL 2131 + //DAGB0_RESERVE81 2132 + #define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 2133 + #define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL 2134 + //DAGB0_RESERVE82 2135 + #define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 2136 + #define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL 2137 + //DAGB0_RESERVE83 2138 + #define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 2139 + #define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL 2140 + //DAGB0_RESERVE84 2141 + #define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 2142 + #define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL 2143 + //DAGB0_RESERVE85 2144 + #define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 2145 + #define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL 2146 + //DAGB0_RESERVE86 2147 + #define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 2148 + #define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL 2149 + //DAGB0_RESERVE87 2150 + #define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 2151 + #define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL 2152 + //DAGB0_RESERVE88 2153 + #define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 2154 + #define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL 2155 + //DAGB0_RESERVE89 2156 + #define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 2157 + #define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL 2158 + //DAGB0_RESERVE90 2159 + #define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 2160 + #define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL 2161 + //DAGB0_RESERVE91 2162 + #define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 2163 + #define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL 2164 + //DAGB0_RESERVE92 2165 + #define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 2166 + #define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL 2167 + //DAGB0_RESERVE93 2168 + #define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 2169 + #define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL 2170 + //DAGB0_RESERVE94 2171 + #define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 2172 + #define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL 2173 + //DAGB0_RESERVE95 2174 + #define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 2175 + #define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL 2176 + //DAGB0_RESERVE96 2177 + #define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 2178 + #define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL 2179 + //DAGB0_RESERVE97 2180 + #define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 2181 + #define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL 2182 + //DAGB0_RESERVE98 2183 + #define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 2184 + #define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL 2185 + //DAGB0_RESERVE99 2186 + #define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 2187 + #define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL 2188 + //DAGB0_RESERVE100 2189 + #define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 2190 + #define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL 2191 + //DAGB0_RESERVE101 2192 + #define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 2193 + #define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL 2194 + //DAGB0_RESERVE102 2195 + #define DAGB0_RESERVE102__RESERVE__SHIFT 0x0 2196 + #define DAGB0_RESERVE102__RESERVE_MASK 0xFFFFFFFFL 2197 + //DAGB0_RESERVE103 2198 + #define DAGB0_RESERVE103__RESERVE__SHIFT 0x0 2199 + #define DAGB0_RESERVE103__RESERVE_MASK 0xFFFFFFFFL 2200 + //DAGB0_RESERVE104 2201 + #define DAGB0_RESERVE104__RESERVE__SHIFT 0x0 2202 + #define DAGB0_RESERVE104__RESERVE_MASK 0xFFFFFFFFL 2203 + //DAGB0_RESERVE105 2204 + #define DAGB0_RESERVE105__RESERVE__SHIFT 0x0 2205 + #define DAGB0_RESERVE105__RESERVE_MASK 0xFFFFFFFFL 2206 + //DAGB0_RESERVE106 2207 + #define DAGB0_RESERVE106__RESERVE__SHIFT 0x0 2208 + #define DAGB0_RESERVE106__RESERVE_MASK 0xFFFFFFFFL 2209 + //DAGB0_RESERVE107 2210 + #define DAGB0_RESERVE107__RESERVE__SHIFT 0x0 2211 + #define DAGB0_RESERVE107__RESERVE_MASK 0xFFFFFFFFL 2212 + //DAGB0_RESERVE108 2213 + #define DAGB0_RESERVE108__RESERVE__SHIFT 0x0 2214 + #define DAGB0_RESERVE108__RESERVE_MASK 0xFFFFFFFFL 2215 + //DAGB0_RESERVE109 2216 + #define DAGB0_RESERVE109__RESERVE__SHIFT 0x0 2217 + #define DAGB0_RESERVE109__RESERVE_MASK 0xFFFFFFFFL 2218 + //DAGB0_RESERVE110 2219 + #define DAGB0_RESERVE110__RESERVE__SHIFT 0x0 2220 + #define DAGB0_RESERVE110__RESERVE_MASK 0xFFFFFFFFL 2221 + //DAGB0_RESERVE111 2222 + #define DAGB0_RESERVE111__RESERVE__SHIFT 0x0 2223 + #define DAGB0_RESERVE111__RESERVE_MASK 0xFFFFFFFFL 2224 + //DAGB0_RESERVE112 2225 + #define DAGB0_RESERVE112__RESERVE__SHIFT 0x0 2226 + #define DAGB0_RESERVE112__RESERVE_MASK 0xFFFFFFFFL 2227 + //DAGB0_RESERVE113 2228 + #define DAGB0_RESERVE113__RESERVE__SHIFT 0x0 2229 + #define DAGB0_RESERVE113__RESERVE_MASK 0xFFFFFFFFL 2230 + //DAGB0_RESERVE114 2231 + #define DAGB0_RESERVE114__RESERVE__SHIFT 0x0 2232 + #define DAGB0_RESERVE114__RESERVE_MASK 0xFFFFFFFFL 2233 + //DAGB0_RESERVE115 2234 + #define DAGB0_RESERVE115__RESERVE__SHIFT 0x0 2235 + #define DAGB0_RESERVE115__RESERVE_MASK 0xFFFFFFFFL 2236 + //DAGB0_RESERVE116 2237 + #define DAGB0_RESERVE116__RESERVE__SHIFT 0x0 2238 + #define DAGB0_RESERVE116__RESERVE_MASK 0xFFFFFFFFL 2239 + //DAGB0_RESERVE117 2240 + #define DAGB0_RESERVE117__RESERVE__SHIFT 0x0 2241 + #define DAGB0_RESERVE117__RESERVE_MASK 0xFFFFFFFFL 2242 + //DAGB0_RESERVE118 2243 + #define DAGB0_RESERVE118__RESERVE__SHIFT 0x0 2244 + #define DAGB0_RESERVE118__RESERVE_MASK 0xFFFFFFFFL 2245 + //DAGB0_RESERVE119 2246 + #define DAGB0_RESERVE119__RESERVE__SHIFT 0x0 2247 + #define DAGB0_RESERVE119__RESERVE_MASK 0xFFFFFFFFL 2248 + //DAGB0_RESERVE120 2249 + #define DAGB0_RESERVE120__RESERVE__SHIFT 0x0 2250 + #define DAGB0_RESERVE120__RESERVE_MASK 0xFFFFFFFFL 2251 + //DAGB0_RESERVE121 2252 + #define DAGB0_RESERVE121__RESERVE__SHIFT 0x0 2253 + #define DAGB0_RESERVE121__RESERVE_MASK 0xFFFFFFFFL 2254 + //DAGB0_RESERVE122 2255 + #define DAGB0_RESERVE122__RESERVE__SHIFT 0x0 2256 + #define DAGB0_RESERVE122__RESERVE_MASK 0xFFFFFFFFL 2257 + //DAGB0_RESERVE123 2258 + #define DAGB0_RESERVE123__RESERVE__SHIFT 0x0 2259 + #define DAGB0_RESERVE123__RESERVE_MASK 0xFFFFFFFFL 2260 + //DAGB0_RESERVE124 2261 + #define DAGB0_RESERVE124__RESERVE__SHIFT 0x0 2262 + #define DAGB0_RESERVE124__RESERVE_MASK 0xFFFFFFFFL 2263 + //DAGB0_RESERVE125 2264 + #define DAGB0_RESERVE125__RESERVE__SHIFT 0x0 2265 + #define DAGB0_RESERVE125__RESERVE_MASK 0xFFFFFFFFL 2266 + //DAGB0_RESERVE126 2267 + #define DAGB0_RESERVE126__RESERVE__SHIFT 0x0 2268 + #define DAGB0_RESERVE126__RESERVE_MASK 0xFFFFFFFFL 2269 + //DAGB0_RESERVE127 2270 + #define DAGB0_RESERVE127__RESERVE__SHIFT 0x0 2271 + #define DAGB0_RESERVE127__RESERVE_MASK 0xFFFFFFFFL 2272 + //DAGB0_RESERVE128 2273 + #define DAGB0_RESERVE128__RESERVE__SHIFT 0x0 2274 + #define DAGB0_RESERVE128__RESERVE_MASK 0xFFFFFFFFL 2275 + //DAGB0_RESERVE129 2276 + #define DAGB0_RESERVE129__RESERVE__SHIFT 0x0 2277 + #define DAGB0_RESERVE129__RESERVE_MASK 0xFFFFFFFFL 2278 + //DAGB0_RESERVE130 2279 + #define DAGB0_RESERVE130__RESERVE__SHIFT 0x0 2280 + #define DAGB0_RESERVE130__RESERVE_MASK 0xFFFFFFFFL 2281 + //DAGB0_RESERVE131 2282 + #define DAGB0_RESERVE131__RESERVE__SHIFT 0x0 2283 + #define DAGB0_RESERVE131__RESERVE_MASK 0xFFFFFFFFL 2284 + 2285 + 2286 + // addressBlock: mmhub_mmea_mmeadec 2287 + //MMEA0_DRAM_RD_CLI2GRP_MAP0 2288 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2289 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2290 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2291 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2292 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2293 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2294 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2295 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2296 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2297 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2298 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2299 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2300 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2301 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2302 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2303 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2304 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2305 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2306 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2307 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2308 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2309 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2310 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2311 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2312 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2313 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2314 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2315 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2316 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2317 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2318 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2319 + #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2320 + //MMEA0_DRAM_RD_CLI2GRP_MAP1 2321 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2322 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2323 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2324 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2325 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2326 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2327 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2328 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2329 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2330 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2331 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2332 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2333 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2334 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2335 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2336 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2337 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2338 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2339 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2340 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2341 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2342 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2343 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2344 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2345 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2346 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2347 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2348 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2349 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2350 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2351 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2352 + #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2353 + //MMEA0_DRAM_WR_CLI2GRP_MAP0 2354 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2355 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2356 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2357 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2358 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2359 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2360 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2361 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2362 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2363 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2364 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2365 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2366 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2367 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2368 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2369 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2370 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2371 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2372 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2373 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2374 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2375 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2376 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2377 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2378 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2379 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2380 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2381 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2382 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2383 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2384 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2385 + #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2386 + //MMEA0_DRAM_WR_CLI2GRP_MAP1 2387 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2388 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2389 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2390 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2391 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2392 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2393 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2394 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2395 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2396 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2397 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2398 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2399 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2400 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2401 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2402 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2403 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2404 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2405 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2406 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2407 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2408 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2409 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2410 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2411 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2412 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2413 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2414 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2415 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2416 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2417 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2418 + #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2419 + //MMEA0_DRAM_RD_GRP2VC_MAP 2420 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2421 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2422 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2423 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2424 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2425 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2426 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2427 + #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2428 + //MMEA0_DRAM_WR_GRP2VC_MAP 2429 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2430 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2431 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2432 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2433 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2434 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2435 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2436 + #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2437 + //MMEA0_DRAM_RD_LAZY 2438 + #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 2439 + #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 2440 + #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 2441 + #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 2442 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2443 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2444 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2445 + #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 2446 + #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 2447 + #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2448 + #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2449 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2450 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2451 + #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2452 + //MMEA0_DRAM_WR_LAZY 2453 + #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 2454 + #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 2455 + #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 2456 + #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 2457 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 2458 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 2459 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 2460 + #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 2461 + #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 2462 + #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2463 + #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2464 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 2465 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 2466 + #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 2467 + //MMEA0_DRAM_RD_CAM_CNTL 2468 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2469 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2470 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2471 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2472 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2473 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2474 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2475 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2476 + #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2477 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2478 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2479 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2480 + #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2481 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2482 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2483 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2484 + #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2485 + #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2486 + //MMEA0_DRAM_WR_CAM_CNTL 2487 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 2488 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 2489 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 2490 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 2491 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 2492 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 2493 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 2494 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 2495 + #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 2496 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 2497 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 2498 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 2499 + #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 2500 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 2501 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 2502 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 2503 + #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 2504 + #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 2505 + //MMEA0_DRAM_PAGE_BURST 2506 + #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 2507 + #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 2508 + #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 2509 + #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 2510 + #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 2511 + #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 2512 + #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 2513 + #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 2514 + //MMEA0_DRAM_RD_PRI_AGE 2515 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2516 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2517 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2518 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2519 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2520 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2521 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2522 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2523 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2524 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2525 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2526 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2527 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2528 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2529 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2530 + #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2531 + //MMEA0_DRAM_WR_PRI_AGE 2532 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 2533 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 2534 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 2535 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 2536 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 2537 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 2538 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 2539 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 2540 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 2541 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 2542 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 2543 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 2544 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 2545 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 2546 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 2547 + #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 2548 + //MMEA0_DRAM_RD_PRI_QUEUING 2549 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2550 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2551 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2552 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2553 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2554 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2555 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2556 + #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2557 + //MMEA0_DRAM_WR_PRI_QUEUING 2558 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 2559 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 2560 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 2561 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 2562 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 2563 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 2564 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 2565 + #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 2566 + //MMEA0_DRAM_RD_PRI_FIXED 2567 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2568 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2569 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2570 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2571 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2572 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2573 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2574 + #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2575 + //MMEA0_DRAM_WR_PRI_FIXED 2576 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 2577 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 2578 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 2579 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 2580 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 2581 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 2582 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 2583 + #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 2584 + //MMEA0_DRAM_RD_PRI_URGENCY 2585 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2586 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2587 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2588 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2589 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2590 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2591 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2592 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2593 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2594 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2595 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2596 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2597 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2598 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2599 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2600 + #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2601 + //MMEA0_DRAM_WR_PRI_URGENCY 2602 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 2603 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 2604 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 2605 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 2606 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 2607 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 2608 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 2609 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 2610 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 2611 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 2612 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 2613 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 2614 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 2615 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 2616 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 2617 + #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 2618 + //MMEA0_DRAM_RD_PRI_QUANT_PRI1 2619 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2620 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2621 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2622 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2623 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2624 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2625 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2626 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2627 + //MMEA0_DRAM_RD_PRI_QUANT_PRI2 2628 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2629 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2630 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2631 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 2632 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 2633 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 2634 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 2635 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 2636 + //MMEA0_DRAM_RD_PRI_QUANT_PRI3 2637 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 2638 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 2639 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 2640 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 2641 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 2642 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 2643 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 2644 + #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 2645 + //MMEA0_DRAM_WR_PRI_QUANT_PRI1 2646 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 2647 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 2648 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 2649 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 2650 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 2651 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 2652 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 2653 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 2654 + //MMEA0_DRAM_WR_PRI_QUANT_PRI2 2655 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 2656 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 2657 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 2658 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 2659 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 2660 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 2661 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 2662 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 2663 + //MMEA0_DRAM_WR_PRI_QUANT_PRI3 2664 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 2665 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 2666 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 2667 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 2668 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 2669 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 2670 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 2671 + #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 2672 + //MMEA0_ADDRNORM_BASE_ADDR0 2673 + #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 2674 + #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 2675 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 2676 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 2677 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 2678 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 2679 + #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 2680 + #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 2681 + #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 2682 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL 2683 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L 2684 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 2685 + #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 2686 + #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 2687 + //MMEA0_ADDRNORM_LIMIT_ADDR0 2688 + #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 2689 + #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 2690 + #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 2691 + #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 2692 + //MMEA0_ADDRNORM_BASE_ADDR1 2693 + #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 2694 + #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 2695 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 2696 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 2697 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 2698 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 2699 + #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 2700 + #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 2701 + #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 2702 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL 2703 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L 2704 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 2705 + #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 2706 + #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 2707 + //MMEA0_ADDRNORM_LIMIT_ADDR1 2708 + #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 2709 + #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 2710 + #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 2711 + #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 2712 + //MMEA0_ADDRNORM_OFFSET_ADDR1 2713 + #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 2714 + #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 2715 + #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 2716 + #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 2717 + //MMEA0_ADDRNORMDRAM_HOLE_CNTL 2718 + #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 2719 + #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 2720 + #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 2721 + #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 2722 + //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 2723 + #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 2724 + #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 2725 + #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 2726 + #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 2727 + //MMEA0_ADDRDEC_BANK_CFG 2728 + #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 2729 + #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 2730 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 2731 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 2732 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 2733 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 2734 + #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 2735 + #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 2736 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 2737 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 2738 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 2739 + #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 2740 + //MMEA0_ADDRDEC_MISC_CFG 2741 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 2742 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 2743 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 2744 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 2745 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 2746 + #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 2747 + #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 2748 + #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 2749 + #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 2750 + #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 2751 + #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 2752 + #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 2753 + #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 2754 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 2755 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 2756 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 2757 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 2758 + #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 2759 + #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 2760 + #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 2761 + #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 2762 + #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 2763 + #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 2764 + #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 2765 + #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 2766 + #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 2767 + //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 2768 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 2769 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 2770 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 2771 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 2772 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 2773 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 2774 + //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 2775 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 2776 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 2777 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 2778 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 2779 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 2780 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 2781 + //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 2782 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 2783 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 2784 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 2785 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 2786 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 2787 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 2788 + //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 2789 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 2790 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 2791 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 2792 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 2793 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 2794 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 2795 + //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 2796 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 2797 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 2798 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 2799 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 2800 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 2801 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 2802 + //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 2803 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 2804 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 2805 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 2806 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 2807 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 2808 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 2809 + //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 2810 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 2811 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 2812 + //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 2813 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 2814 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 2815 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 2816 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 2817 + //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 2818 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 2819 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 2820 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 2821 + #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 2822 + //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 2823 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 2824 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 2825 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 2826 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 2827 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 2828 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 2829 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 2830 + #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 2831 + //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0 2832 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0 2833 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c 2834 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL 2835 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L 2836 + //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0 2837 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0 2838 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL 2839 + //MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1 2840 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0 2841 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c 2842 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL 2843 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L 2844 + //MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1 2845 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0 2846 + #define MMEA0_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL 2847 + //MMEA0_ADDRDEC0_BASE_ADDR_CS0 2848 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 2849 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 2850 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 2851 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 2852 + //MMEA0_ADDRDEC0_BASE_ADDR_CS1 2853 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 2854 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 2855 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 2856 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 2857 + //MMEA0_ADDRDEC0_BASE_ADDR_CS2 2858 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 2859 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 2860 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 2861 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 2862 + //MMEA0_ADDRDEC0_BASE_ADDR_CS3 2863 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 2864 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 2865 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 2866 + #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 2867 + //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 2868 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 2869 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 2870 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 2871 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 2872 + //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 2873 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 2874 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 2875 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 2876 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 2877 + //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 2878 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 2879 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 2880 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 2881 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 2882 + //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 2883 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 2884 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 2885 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 2886 + #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 2887 + //MMEA0_ADDRDEC0_ADDR_MASK_CS01 2888 + #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 2889 + #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 2890 + //MMEA0_ADDRDEC0_ADDR_MASK_CS23 2891 + #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 2892 + #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 2893 + //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 2894 + #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 2895 + #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 2896 + //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 2897 + #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 2898 + #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 2899 + //MMEA0_ADDRDEC0_ADDR_CFG_CS01 2900 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 2901 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 2902 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 2903 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 2904 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 2905 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 2906 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 2907 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 2908 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 2909 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 2910 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 2911 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 2912 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 2913 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 2914 + //MMEA0_ADDRDEC0_ADDR_CFG_CS23 2915 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 2916 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 2917 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 2918 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 2919 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 2920 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 2921 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 2922 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 2923 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 2924 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 2925 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 2926 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 2927 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 2928 + #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 2929 + //MMEA0_ADDRDEC0_ADDR_SEL_CS01 2930 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 2931 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 2932 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 2933 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 2934 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 2935 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 2936 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 2937 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 2938 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 2939 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 2940 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 2941 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 2942 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 2943 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 2944 + //MMEA0_ADDRDEC0_ADDR_SEL_CS23 2945 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 2946 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 2947 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 2948 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 2949 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 2950 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 2951 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 2952 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 2953 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 2954 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 2955 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 2956 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 2957 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 2958 + #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 2959 + //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 2960 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 2961 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 2962 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 2963 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 2964 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 2965 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 2966 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 2967 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 2968 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 2969 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 2970 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 2971 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 2972 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 2973 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 2974 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 2975 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 2976 + //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 2977 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 2978 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 2979 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 2980 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 2981 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 2982 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 2983 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 2984 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 2985 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 2986 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 2987 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 2988 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 2989 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 2990 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 2991 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 2992 + #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 2993 + //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 2994 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 2995 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 2996 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 2997 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 2998 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 2999 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3000 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3001 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3002 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3003 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3004 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3005 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3006 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3007 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3008 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3009 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3010 + //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 3011 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3012 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3013 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3014 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3015 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3016 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3017 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3018 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3019 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3020 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3021 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3022 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3023 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3024 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3025 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3026 + #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3027 + //MMEA0_ADDRDEC0_RM_SEL_CS01 3028 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 3029 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 3030 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 3031 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3032 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3033 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3034 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 3035 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 3036 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 3037 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3038 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3039 + #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3040 + //MMEA0_ADDRDEC0_RM_SEL_CS23 3041 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 3042 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 3043 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 3044 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3045 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3046 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3047 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 3048 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 3049 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 3050 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3051 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3052 + #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3053 + //MMEA0_ADDRDEC0_RM_SEL_SECCS01 3054 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 3055 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 3056 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 3057 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3058 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3059 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3060 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3061 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3062 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3063 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3064 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3065 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3066 + //MMEA0_ADDRDEC0_RM_SEL_SECCS23 3067 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 3068 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 3069 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 3070 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3071 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3072 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3073 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3074 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3075 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3076 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3077 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3078 + #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3079 + //MMEA0_ADDRDEC1_BASE_ADDR_CS0 3080 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 3081 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3082 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 3083 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3084 + //MMEA0_ADDRDEC1_BASE_ADDR_CS1 3085 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 3086 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3087 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 3088 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3089 + //MMEA0_ADDRDEC1_BASE_ADDR_CS2 3090 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 3091 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3092 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 3093 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3094 + //MMEA0_ADDRDEC1_BASE_ADDR_CS3 3095 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 3096 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3097 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 3098 + #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3099 + //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 3100 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 3101 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3102 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 3103 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3104 + //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 3105 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 3106 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3107 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 3108 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3109 + //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 3110 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 3111 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3112 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 3113 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3114 + //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 3115 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 3116 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3117 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 3118 + #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3119 + //MMEA0_ADDRDEC1_ADDR_MASK_CS01 3120 + #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3121 + #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3122 + //MMEA0_ADDRDEC1_ADDR_MASK_CS23 3123 + #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3124 + #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3125 + //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 3126 + #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3127 + #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3128 + //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 3129 + #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3130 + #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3131 + //MMEA0_ADDRDEC1_ADDR_CFG_CS01 3132 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3133 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3134 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3135 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3136 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3137 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3138 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 3139 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3140 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3141 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3142 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3143 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3144 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3145 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 3146 + //MMEA0_ADDRDEC1_ADDR_CFG_CS23 3147 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3148 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3149 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3150 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3151 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3152 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3153 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 3154 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3155 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3156 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3157 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3158 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3159 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3160 + #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 3161 + //MMEA0_ADDRDEC1_ADDR_SEL_CS01 3162 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3163 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3164 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3165 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3166 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3167 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3168 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3169 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3170 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3171 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3172 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3173 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 3174 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3175 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3176 + //MMEA0_ADDRDEC1_ADDR_SEL_CS23 3177 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3178 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3179 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3180 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3181 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3182 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3183 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3184 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3185 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3186 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3187 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3188 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 3189 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3190 + #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3191 + //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 3192 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3193 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3194 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3195 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3196 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3197 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3198 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3199 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3200 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3201 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3202 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3203 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3204 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3205 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3206 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3207 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3208 + //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 3209 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3210 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3211 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3212 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3213 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3214 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3215 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3216 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3217 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3218 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3219 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3220 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3221 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3222 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3223 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3224 + #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3225 + //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 3226 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3227 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3228 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3229 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3230 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3231 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3232 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3233 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3234 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3235 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3236 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3237 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3238 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3239 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3240 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3241 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3242 + //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 3243 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3244 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3245 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3246 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3247 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3248 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3249 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3250 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3251 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3252 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3253 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3254 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3255 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3256 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3257 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3258 + #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3259 + //MMEA0_ADDRDEC1_RM_SEL_CS01 3260 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 3261 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 3262 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 3263 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3264 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3265 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3266 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 3267 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 3268 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 3269 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3270 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3271 + #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3272 + //MMEA0_ADDRDEC1_RM_SEL_CS23 3273 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 3274 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 3275 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 3276 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3277 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3278 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3279 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 3280 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 3281 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 3282 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3283 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3284 + #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3285 + //MMEA0_ADDRDEC1_RM_SEL_SECCS01 3286 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 3287 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 3288 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 3289 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3290 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3291 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3292 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3293 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3294 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3295 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3296 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3297 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3298 + //MMEA0_ADDRDEC1_RM_SEL_SECCS23 3299 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 3300 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 3301 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 3302 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3303 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3304 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3305 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3306 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3307 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3308 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3309 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3310 + #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3311 + //MMEA0_IO_RD_CLI2GRP_MAP0 3312 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3313 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3314 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3315 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3316 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3317 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3318 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3319 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3320 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3321 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3322 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3323 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3324 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3325 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3326 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3327 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3328 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3329 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3330 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3331 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3332 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3333 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3334 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3335 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3336 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3337 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3338 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3339 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3340 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3341 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3342 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3343 + #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3344 + //MMEA0_IO_RD_CLI2GRP_MAP1 3345 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3346 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3347 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3348 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3349 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3350 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3351 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3352 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3353 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3354 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3355 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3356 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3357 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3358 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3359 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3360 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3361 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3362 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3363 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3364 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3365 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3366 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3367 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3368 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3369 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3370 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3371 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3372 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3373 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3374 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3375 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3376 + #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3377 + //MMEA0_IO_WR_CLI2GRP_MAP0 3378 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3379 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3380 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3381 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3382 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3383 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3384 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3385 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3386 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3387 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3388 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3389 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3390 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3391 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3392 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3393 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3394 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3395 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3396 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3397 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3398 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3399 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3400 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3401 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3402 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3403 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3404 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3405 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3406 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3407 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3408 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3409 + #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3410 + //MMEA0_IO_WR_CLI2GRP_MAP1 3411 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3412 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3413 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3414 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3415 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3416 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3417 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3418 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3419 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3420 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3421 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3422 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3423 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3424 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3425 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3426 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3427 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3428 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3429 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3430 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3431 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3432 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3433 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3434 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3435 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3436 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3437 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3438 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3439 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3440 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3441 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3442 + #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3443 + //MMEA0_IO_RD_COMBINE_FLUSH 3444 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3445 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3446 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3447 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3448 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3449 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3450 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3451 + #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3452 + //MMEA0_IO_WR_COMBINE_FLUSH 3453 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3454 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3455 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3456 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3457 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3458 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3459 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3460 + #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3461 + //MMEA0_IO_GROUP_BURST 3462 + #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 3463 + #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 3464 + #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 3465 + #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 3466 + #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3467 + #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3468 + #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3469 + #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3470 + //MMEA0_IO_RD_PRI_AGE 3471 + #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3472 + #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3473 + #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3474 + #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3475 + #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3476 + #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3477 + #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3478 + #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3479 + #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3480 + #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3481 + #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3482 + #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3483 + #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3484 + #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3485 + #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3486 + #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3487 + //MMEA0_IO_WR_PRI_AGE 3488 + #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3489 + #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3490 + #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3491 + #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3492 + #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3493 + #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3494 + #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3495 + #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3496 + #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3497 + #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3498 + #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3499 + #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3500 + #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3501 + #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3502 + #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3503 + #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3504 + //MMEA0_IO_RD_PRI_QUEUING 3505 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3506 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3507 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3508 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3509 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3510 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3511 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3512 + #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3513 + //MMEA0_IO_WR_PRI_QUEUING 3514 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3515 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3516 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3517 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3518 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3519 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3520 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3521 + #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3522 + //MMEA0_IO_RD_PRI_FIXED 3523 + #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3524 + #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3525 + #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3526 + #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3527 + #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3528 + #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3529 + #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3530 + #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3531 + //MMEA0_IO_WR_PRI_FIXED 3532 + #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3533 + #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3534 + #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3535 + #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3536 + #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3537 + #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3538 + #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3539 + #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3540 + //MMEA0_IO_RD_PRI_URGENCY 3541 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3542 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3543 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3544 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3545 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3546 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3547 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3548 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3549 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3550 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3551 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3552 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3553 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3554 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3555 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3556 + #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3557 + //MMEA0_IO_WR_PRI_URGENCY 3558 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3559 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3560 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3561 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3562 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3563 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3564 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3565 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3566 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3567 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3568 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3569 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3570 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3571 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3572 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3573 + #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3574 + //MMEA0_IO_RD_PRI_URGENCY_MASKING 3575 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 3576 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 3577 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 3578 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 3579 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 3580 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 3581 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 3582 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 3583 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 3584 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 3585 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 3586 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 3587 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 3588 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 3589 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 3590 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 3591 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 3592 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 3593 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 3594 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 3595 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 3596 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 3597 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 3598 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 3599 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 3600 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 3601 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 3602 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 3603 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 3604 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 3605 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 3606 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 3607 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 3608 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 3609 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 3610 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 3611 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 3612 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 3613 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 3614 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 3615 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 3616 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 3617 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 3618 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 3619 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 3620 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 3621 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 3622 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 3623 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 3624 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 3625 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 3626 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 3627 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 3628 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 3629 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 3630 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 3631 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 3632 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 3633 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 3634 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 3635 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 3636 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 3637 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 3638 + #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 3639 + //MMEA0_IO_WR_PRI_URGENCY_MASKING 3640 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 3641 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 3642 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 3643 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 3644 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 3645 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 3646 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 3647 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 3648 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 3649 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 3650 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 3651 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 3652 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 3653 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 3654 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 3655 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 3656 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 3657 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 3658 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 3659 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 3660 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 3661 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 3662 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 3663 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 3664 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 3665 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 3666 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 3667 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 3668 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 3669 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 3670 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 3671 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 3672 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 3673 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 3674 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 3675 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 3676 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 3677 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 3678 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 3679 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 3680 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 3681 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 3682 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 3683 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 3684 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 3685 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 3686 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 3687 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 3688 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 3689 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 3690 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 3691 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 3692 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 3693 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 3694 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 3695 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 3696 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 3697 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 3698 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 3699 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 3700 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 3701 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 3702 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 3703 + #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 3704 + //MMEA0_IO_RD_PRI_QUANT_PRI1 3705 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3706 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3707 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3708 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3709 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3710 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3711 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3712 + #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3713 + //MMEA0_IO_RD_PRI_QUANT_PRI2 3714 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3715 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3716 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3717 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3718 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3719 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3720 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3721 + #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3722 + //MMEA0_IO_RD_PRI_QUANT_PRI3 3723 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3724 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3725 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3726 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3727 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3728 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3729 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3730 + #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3731 + //MMEA0_IO_WR_PRI_QUANT_PRI1 3732 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3733 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3734 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3735 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3736 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3737 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3738 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3739 + #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3740 + //MMEA0_IO_WR_PRI_QUANT_PRI2 3741 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3742 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3743 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3744 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3745 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3746 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3747 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3748 + #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3749 + //MMEA0_IO_WR_PRI_QUANT_PRI3 3750 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3751 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3752 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3753 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3754 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3755 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3756 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3757 + #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3758 + //MMEA0_SDP_ARB_DRAM 3759 + #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 3760 + #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 3761 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 3762 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 3763 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 3764 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 3765 + #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 3766 + #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 3767 + #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 3768 + #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 3769 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 3770 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 3771 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 3772 + #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 3773 + #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 3774 + #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 3775 + //MMEA0_SDP_ARB_FINAL 3776 + #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 3777 + #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 3778 + #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 3779 + #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 3780 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 3781 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 3782 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 3783 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 3784 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 3785 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 3786 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 3787 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 3788 + #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 3789 + #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 3790 + #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 3791 + #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 3792 + #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 3793 + #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 3794 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 3795 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 3796 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 3797 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 3798 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 3799 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 3800 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 3801 + #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 3802 + #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 3803 + #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 3804 + //MMEA0_SDP_DRAM_PRIORITY 3805 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 3806 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 3807 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 3808 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 3809 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 3810 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 3811 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 3812 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 3813 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 3814 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 3815 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 3816 + #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 3817 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 3818 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 3819 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 3820 + #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 3821 + //MMEA0_SDP_IO_PRIORITY 3822 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 3823 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 3824 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 3825 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 3826 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 3827 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 3828 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 3829 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 3830 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 3831 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 3832 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 3833 + #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 3834 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 3835 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 3836 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 3837 + #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 3838 + //MMEA0_SDP_CREDITS 3839 + #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 3840 + #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 3841 + #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 3842 + #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 3843 + #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 3844 + #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 3845 + //MMEA0_SDP_TAG_RESERVE0 3846 + #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 3847 + #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 3848 + #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 3849 + #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 3850 + #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 3851 + #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 3852 + #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 3853 + #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 3854 + //MMEA0_SDP_TAG_RESERVE1 3855 + #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 3856 + #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 3857 + #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 3858 + #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 3859 + #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 3860 + #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 3861 + #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 3862 + #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 3863 + //MMEA0_SDP_VCC_RESERVE0 3864 + #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 3865 + #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 3866 + #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 3867 + #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 3868 + #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 3869 + #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3870 + #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3871 + #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3872 + #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3873 + #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3874 + //MMEA0_SDP_VCC_RESERVE1 3875 + #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 3876 + #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 3877 + #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 3878 + #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3879 + #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3880 + #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3881 + #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3882 + #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3883 + //MMEA0_SDP_VCD_RESERVE0 3884 + #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 3885 + #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 3886 + #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 3887 + #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 3888 + #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 3889 + #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 3890 + #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 3891 + #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 3892 + #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 3893 + #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 3894 + //MMEA0_SDP_VCD_RESERVE1 3895 + #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 3896 + #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 3897 + #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 3898 + #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 3899 + #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 3900 + #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 3901 + #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 3902 + #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 3903 + //MMEA0_SDP_REQ_CNTL 3904 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 3905 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 3906 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 3907 + #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 3908 + #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 3909 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 3910 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 3911 + #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 3912 + #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 3913 + #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 3914 + //MMEA0_MISC 3915 + #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 3916 + #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 3917 + #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 3918 + #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 3919 + #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 3920 + #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 3921 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 3922 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 3923 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 3924 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 3925 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 3926 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 3927 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 3928 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 3929 + #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 3930 + #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 3931 + #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 3932 + #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 3933 + #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 3934 + #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 3935 + #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 3936 + #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 3937 + #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 3938 + #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 3939 + #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 3940 + #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 3941 + #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 3942 + #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 3943 + #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 3944 + #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 3945 + #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 3946 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 3947 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 3948 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 3949 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 3950 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 3951 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 3952 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 3953 + #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 3954 + #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 3955 + #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 3956 + #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 3957 + #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 3958 + #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 3959 + #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 3960 + #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 3961 + #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 3962 + #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 3963 + #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 3964 + #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 3965 + //MMEA0_LATENCY_SAMPLING 3966 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 3967 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 3968 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 3969 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 3970 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 3971 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 3972 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 3973 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 3974 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 3975 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 3976 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 3977 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 3978 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 3979 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 3980 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 3981 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 3982 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 3983 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 3984 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 3985 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 3986 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 3987 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 3988 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 3989 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 3990 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 3991 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 3992 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 3993 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 3994 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 3995 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 3996 + #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 3997 + #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 3998 + //MMEA0_PERFCOUNTER_LO 3999 + #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4000 + #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4001 + //MMEA0_PERFCOUNTER_HI 4002 + #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4003 + #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4004 + #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4005 + #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4006 + //MMEA0_PERFCOUNTER0_CFG 4007 + #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4008 + #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4009 + #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4010 + #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4011 + #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4012 + #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4013 + #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4014 + #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4015 + #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4016 + #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4017 + //MMEA0_PERFCOUNTER1_CFG 4018 + #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4019 + #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4020 + #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4021 + #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4022 + #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4023 + #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4024 + #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4025 + #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4026 + #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4027 + #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4028 + //MMEA0_PERFCOUNTER_RSLT_CNTL 4029 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4030 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4031 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4032 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4033 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4034 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4035 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4036 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4037 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4038 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4039 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4040 + #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4041 + //MMEA0_EDC_CNT 4042 + #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4043 + #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 4044 + #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4045 + #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 4046 + #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4047 + #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 4048 + #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 4049 + #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 4050 + #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 4051 + #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 4052 + #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 4053 + #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 4054 + #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 4055 + #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 4056 + #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 4057 + #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4058 + #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4059 + #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4060 + #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4061 + #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4062 + #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4063 + #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 4064 + #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 4065 + #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 4066 + #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 4067 + #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 4068 + #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 4069 + #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 4070 + #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 4071 + #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 4072 + //MMEA0_EDC_CNT2 4073 + #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4074 + #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 4075 + #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4076 + #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 4077 + #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4078 + #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 4079 + #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 4080 + #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 4081 + #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4082 + #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4083 + #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4084 + #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4085 + #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4086 + #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4087 + #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 4088 + #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 4089 + //MMEA0_DSM_CNTL 4090 + #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4091 + #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4092 + #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4093 + #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4094 + #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4095 + #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4096 + #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4097 + #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4098 + #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4099 + #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4100 + #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4101 + #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4102 + #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4103 + #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4104 + #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 4105 + #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 4106 + #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4107 + #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4108 + #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4109 + #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4110 + #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4111 + #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4112 + #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4113 + #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4114 + #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4115 + #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4116 + #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4117 + #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4118 + #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4119 + #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4120 + #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 4121 + #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 4122 + //MMEA0_DSM_CNTLA 4123 + #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4124 + #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4125 + #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4126 + #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4127 + #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4128 + #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4129 + #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4130 + #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4131 + #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4132 + #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4133 + #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4134 + #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4135 + #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4136 + #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4137 + #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4138 + #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4139 + #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4140 + #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4141 + #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4142 + #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4143 + #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4144 + #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4145 + #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4146 + #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4147 + #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4148 + #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4149 + #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4150 + #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4151 + //MMEA0_DSM_CNTL2 4152 + #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4153 + #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4154 + #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4155 + #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4156 + #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4157 + #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4158 + #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4159 + #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4160 + #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4161 + #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4162 + #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4163 + #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4164 + #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4165 + #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4166 + #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 4167 + #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 4168 + #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 4169 + #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4170 + #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4171 + #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4172 + #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4173 + #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4174 + #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4175 + #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4176 + #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4177 + #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4178 + #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4179 + #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4180 + #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4181 + #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4182 + #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4183 + #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 4184 + #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 4185 + #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 4186 + //MMEA0_DSM_CNTL2A 4187 + #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4188 + #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4189 + #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4190 + #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4191 + #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4192 + #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4193 + #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4194 + #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4195 + #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4196 + #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4197 + #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4198 + #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4199 + #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4200 + #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4201 + #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4202 + #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4203 + #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4204 + #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4205 + #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4206 + #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4207 + #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4208 + #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4209 + #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4210 + #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4211 + #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4212 + #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4213 + #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4214 + #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4215 + //MMEA0_CGTT_CLK_CTRL 4216 + #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4217 + #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4218 + #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 4219 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 4220 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 4221 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 4222 + #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 4223 + #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4224 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 4225 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 4226 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 4227 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 4228 + #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4229 + #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4230 + #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 4231 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 4232 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 4233 + #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 4234 + #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 4235 + #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4236 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 4237 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 4238 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 4239 + #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 4240 + //MMEA0_EDC_MODE 4241 + #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 4242 + #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 4243 + #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 4244 + #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 4245 + #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 4246 + #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 4247 + #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 4248 + #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 4249 + #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 4250 + #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 4251 + //MMEA0_ERR_STATUS 4252 + #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 4253 + #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 4254 + #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 4255 + #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 4256 + #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 4257 + #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 4258 + #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 4259 + #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 4260 + #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 4261 + #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 4262 + #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 4263 + #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 4264 + #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 4265 + #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 4266 + //MMEA0_MISC2 4267 + #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 4268 + #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 4269 + #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 4270 + #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 4271 + #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 4272 + #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd 4273 + #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 4274 + #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 4275 + #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 4276 + #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 4277 + #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 4278 + #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 4279 + //MMEA0_ADDRDEC_SELECT 4280 + #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 4281 + #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 4282 + #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 4283 + #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 4284 + #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14 4285 + #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15 4286 + #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16 4287 + #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17 4288 + #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 4289 + #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 4290 + #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 4291 + #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 4292 + #define MMEA0_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L 4293 + #define MMEA0_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L 4294 + #define MMEA0_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L 4295 + #define MMEA0_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L 4296 + 4297 + 4298 + // addressBlock: mmhub_pctldec 4299 + //PCTL_MISC 4300 + #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 4301 + #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 4302 + #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 4303 + #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 4304 + #define PCTL_MISC__OVR_EA0_SDP_PARTACK__SHIFT 0xc 4305 + #define PCTL_MISC__OVR_EA1_SDP_PARTACK__SHIFT 0xd 4306 + #define PCTL_MISC__OVR_EA0_SDP_FULLACK__SHIFT 0xe 4307 + #define PCTL_MISC__OVR_EA1_SDP_FULLACK__SHIFT 0xf 4308 + #define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0x10 4309 + #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 4310 + #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 4311 + #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 4312 + #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 4313 + #define PCTL_MISC__OVR_EA0_SDP_PARTACK_MASK 0x00001000L 4314 + #define PCTL_MISC__OVR_EA1_SDP_PARTACK_MASK 0x00002000L 4315 + #define PCTL_MISC__OVR_EA0_SDP_FULLACK_MASK 0x00004000L 4316 + #define PCTL_MISC__OVR_EA1_SDP_FULLACK_MASK 0x00008000L 4317 + #define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x00030000L 4318 + //PCTL_MMHUB_DEEPSLEEP 4319 + #define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 4320 + #define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 4321 + #define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 4322 + #define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 4323 + #define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 4324 + #define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 4325 + #define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 4326 + #define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 4327 + #define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 4328 + #define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 4329 + #define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 4330 + #define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 4331 + #define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 4332 + #define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 4333 + #define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 4334 + #define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 4335 + #define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 4336 + #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 4337 + #define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 4338 + #define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 4339 + #define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 4340 + #define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 4341 + #define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 4342 + #define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 4343 + #define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 4344 + #define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 4345 + #define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 4346 + #define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 4347 + #define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 4348 + #define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 4349 + #define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 4350 + #define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 4351 + #define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 4352 + #define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 4353 + #define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 4354 + #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 4355 + //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 4356 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 4357 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 4358 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 4359 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 4360 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 4361 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 4362 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 4363 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 4364 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 4365 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 4366 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 4367 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 4368 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 4369 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 4370 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 4371 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 4372 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 4373 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 4374 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 4375 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 4376 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 4377 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 4378 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 4379 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 4380 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 4381 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 4382 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 4383 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 4384 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 4385 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 4386 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 4387 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 4388 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 4389 + #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 4390 + //PCTL_PG_IGNORE_DEEPSLEEP 4391 + #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 4392 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 4393 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 4394 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 4395 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 4396 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 4397 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 4398 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 4399 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 4400 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 4401 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 4402 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 4403 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 4404 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 4405 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 4406 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 4407 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 4408 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 4409 + #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 4410 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 4411 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 4412 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 4413 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 4414 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 4415 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 4416 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 4417 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 4418 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 4419 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 4420 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 4421 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 4422 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 4423 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 4424 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 4425 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 4426 + #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 4427 + //PCTL_PG_DAGB 4428 + #define PCTL_PG_DAGB__DS0__SHIFT 0x0 4429 + #define PCTL_PG_DAGB__DS1__SHIFT 0x1 4430 + #define PCTL_PG_DAGB__DS2__SHIFT 0x2 4431 + #define PCTL_PG_DAGB__DS3__SHIFT 0x3 4432 + #define PCTL_PG_DAGB__DS4__SHIFT 0x4 4433 + #define PCTL_PG_DAGB__DS5__SHIFT 0x5 4434 + #define PCTL_PG_DAGB__DS6__SHIFT 0x6 4435 + #define PCTL_PG_DAGB__DS7__SHIFT 0x7 4436 + #define PCTL_PG_DAGB__DS8__SHIFT 0x8 4437 + #define PCTL_PG_DAGB__DS9__SHIFT 0x9 4438 + #define PCTL_PG_DAGB__DS10__SHIFT 0xa 4439 + #define PCTL_PG_DAGB__DS11__SHIFT 0xb 4440 + #define PCTL_PG_DAGB__DS12__SHIFT 0xc 4441 + #define PCTL_PG_DAGB__DS13__SHIFT 0xd 4442 + #define PCTL_PG_DAGB__DS14__SHIFT 0xe 4443 + #define PCTL_PG_DAGB__DS15__SHIFT 0xf 4444 + #define PCTL_PG_DAGB__DS16__SHIFT 0x10 4445 + #define PCTL_PG_DAGB__DS0_MASK 0x00000001L 4446 + #define PCTL_PG_DAGB__DS1_MASK 0x00000002L 4447 + #define PCTL_PG_DAGB__DS2_MASK 0x00000004L 4448 + #define PCTL_PG_DAGB__DS3_MASK 0x00000008L 4449 + #define PCTL_PG_DAGB__DS4_MASK 0x00000010L 4450 + #define PCTL_PG_DAGB__DS5_MASK 0x00000020L 4451 + #define PCTL_PG_DAGB__DS6_MASK 0x00000040L 4452 + #define PCTL_PG_DAGB__DS7_MASK 0x00000080L 4453 + #define PCTL_PG_DAGB__DS8_MASK 0x00000100L 4454 + #define PCTL_PG_DAGB__DS9_MASK 0x00000200L 4455 + #define PCTL_PG_DAGB__DS10_MASK 0x00000400L 4456 + #define PCTL_PG_DAGB__DS11_MASK 0x00000800L 4457 + #define PCTL_PG_DAGB__DS12_MASK 0x00001000L 4458 + #define PCTL_PG_DAGB__DS13_MASK 0x00002000L 4459 + #define PCTL_PG_DAGB__DS14_MASK 0x00004000L 4460 + #define PCTL_PG_DAGB__DS15_MASK 0x00008000L 4461 + #define PCTL_PG_DAGB__DS16_MASK 0x00010000L 4462 + //PCTL0_RENG_RAM_INDEX 4463 + #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4464 + #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 4465 + //PCTL0_RENG_RAM_DATA 4466 + #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4467 + #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4468 + //PCTL0_RENG_EXECUTE 4469 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4470 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4471 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4472 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 4473 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4474 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4475 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FFCL 4476 + #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x00FFE000L 4477 + //PCTL1_RENG_RAM_INDEX 4478 + #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4479 + #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4480 + //PCTL1_RENG_RAM_DATA 4481 + #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4482 + #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4483 + //PCTL1_RENG_EXECUTE 4484 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4485 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4486 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4487 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4488 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4489 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4490 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4491 + #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4492 + //PCTL2_RENG_RAM_INDEX 4493 + #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 4494 + #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 4495 + //PCTL2_RENG_RAM_DATA 4496 + #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 4497 + #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 4498 + //PCTL2_RENG_EXECUTE 4499 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x0 4500 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x1 4501 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2 4502 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xc 4503 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000001L 4504 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000002L 4505 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00000FFCL 4506 + #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x003FF000L 4507 + //PCTL0_STCTRL_REGISTER_SAVE_RANGE0 4508 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4509 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4510 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4511 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4512 + //PCTL0_STCTRL_REGISTER_SAVE_RANGE1 4513 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4514 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4515 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4516 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4517 + //PCTL0_STCTRL_REGISTER_SAVE_RANGE2 4518 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4519 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4520 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4521 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4522 + //PCTL0_STCTRL_REGISTER_SAVE_RANGE3 4523 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4524 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4525 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4526 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4527 + //PCTL0_STCTRL_REGISTER_SAVE_RANGE4 4528 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4529 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4530 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4531 + #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4532 + //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 4533 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4534 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4535 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4536 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4537 + //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 4538 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4539 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4540 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4541 + #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4542 + //PCTL1_STCTRL_REGISTER_SAVE_RANGE0 4543 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4544 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4545 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4546 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4547 + //PCTL1_STCTRL_REGISTER_SAVE_RANGE1 4548 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4549 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4550 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4551 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4552 + //PCTL1_STCTRL_REGISTER_SAVE_RANGE2 4553 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4554 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4555 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4556 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4557 + //PCTL1_STCTRL_REGISTER_SAVE_RANGE3 4558 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4559 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4560 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4561 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4562 + //PCTL1_STCTRL_REGISTER_SAVE_RANGE4 4563 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4564 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4565 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4566 + #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4567 + //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 4568 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4569 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4570 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4571 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4572 + //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 4573 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4574 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4575 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4576 + #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4577 + //PCTL2_STCTRL_REGISTER_SAVE_RANGE0 4578 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4579 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4580 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4581 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4582 + //PCTL2_STCTRL_REGISTER_SAVE_RANGE1 4583 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4584 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4585 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4586 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4587 + //PCTL2_STCTRL_REGISTER_SAVE_RANGE2 4588 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4589 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4590 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4591 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4592 + //PCTL2_STCTRL_REGISTER_SAVE_RANGE3 4593 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4594 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4595 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4596 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4597 + //PCTL2_STCTRL_REGISTER_SAVE_RANGE4 4598 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 4599 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 4600 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 4601 + #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 4602 + //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 4603 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 4604 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 4605 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 4606 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 4607 + //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 4608 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 4609 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 4610 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 4611 + #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 4612 + //PCTL0_MISC 4613 + #define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 4614 + #define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 4615 + #define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 4616 + #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 4617 + #define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4618 + #define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4619 + #define PCTL0_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4620 + #define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 4621 + #define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 4622 + #define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 4623 + #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 4624 + #define PCTL0_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4625 + #define PCTL0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4626 + #define PCTL0_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4627 + //PCTL1_MISC 4628 + #define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4629 + #define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4630 + #define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4631 + #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4632 + #define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4633 + #define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4634 + #define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4635 + #define PCTL1_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4636 + #define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4637 + #define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4638 + #define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4639 + #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4640 + #define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4641 + #define PCTL1_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4642 + #define PCTL1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4643 + #define PCTL1_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4644 + //PCTL2_MISC 4645 + #define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 4646 + #define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 4647 + #define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 4648 + #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 4649 + #define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 4650 + #define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x11 4651 + #define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x12 4652 + #define PCTL2_MISC__RD_TIMER_ENABLE__SHIFT 0x13 4653 + #define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 4654 + #define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 4655 + #define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 4656 + #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 4657 + #define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 4658 + #define PCTL2_MISC__RENG_EXECUTE_ON_PWR_UP_MASK 0x00020000L 4659 + #define PCTL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00040000L 4660 + #define PCTL2_MISC__RD_TIMER_ENABLE_MASK 0x00080000L 4661 + //PCTL_PERFCOUNTER_LO 4662 + #define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4663 + #define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4664 + //PCTL_PERFCOUNTER_HI 4665 + #define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4666 + #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4667 + #define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4668 + #define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4669 + //PCTL_PERFCOUNTER0_CFG 4670 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4671 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4672 + #define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4673 + #define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4674 + #define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4675 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4676 + #define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4677 + #define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4678 + #define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4679 + #define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4680 + //PCTL_PERFCOUNTER1_CFG 4681 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4682 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4683 + #define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4684 + #define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4685 + #define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4686 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4687 + #define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4688 + #define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4689 + #define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4690 + #define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4691 + //PCTL_PERFCOUNTER_RSLT_CNTL 4692 + #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4693 + #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4694 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4695 + #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4696 + #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4697 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4698 + #define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4699 + #define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4700 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4701 + #define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4702 + #define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4703 + #define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4704 + 4705 + 4706 + // addressBlock: mmhub_l1tlb_mmvml1pfdec 4707 + //MMMC_VM_MX_L1_TLB0_STATUS 4708 + #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 4709 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4710 + #define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 4711 + #define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4712 + //MMMC_VM_MX_L1_TLB1_STATUS 4713 + #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 4714 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4715 + #define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 4716 + #define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4717 + //MMMC_VM_MX_L1_TLB2_STATUS 4718 + #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 4719 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4720 + #define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 4721 + #define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4722 + //MMMC_VM_MX_L1_TLB3_STATUS 4723 + #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 4724 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4725 + #define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 4726 + #define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4727 + //MMMC_VM_MX_L1_TLB4_STATUS 4728 + #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 4729 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4730 + #define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 4731 + #define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4732 + //MMMC_VM_MX_L1_TLB5_STATUS 4733 + #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 4734 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4735 + #define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 4736 + #define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4737 + //MMMC_VM_MX_L1_TLB6_STATUS 4738 + #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 4739 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4740 + #define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 4741 + #define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4742 + //MMMC_VM_MX_L1_TLB7_STATUS 4743 + #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 4744 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 4745 + #define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 4746 + #define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 4747 + 4748 + 4749 + // addressBlock: mmhub_l1tlb_mmvml1pldec 4750 + //MMMC_VM_MX_L1_PERFCOUNTER0_CFG 4751 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4752 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4753 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4754 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4755 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4756 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4757 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4758 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4759 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4760 + #define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4761 + //MMMC_VM_MX_L1_PERFCOUNTER1_CFG 4762 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4763 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4764 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4765 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4766 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4767 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4768 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4769 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4770 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4771 + #define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4772 + //MMMC_VM_MX_L1_PERFCOUNTER2_CFG 4773 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 4774 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 4775 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 4776 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 4777 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 4778 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 4779 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 4780 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 4781 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 4782 + #define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 4783 + //MMMC_VM_MX_L1_PERFCOUNTER3_CFG 4784 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 4785 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 4786 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 4787 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 4788 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 4789 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 4790 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 4791 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 4792 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 4793 + #define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 4794 + //MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 4795 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4796 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4797 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4798 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4799 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4800 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4801 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4802 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4803 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4804 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4805 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4806 + #define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4807 + 4808 + 4809 + // addressBlock: mmhub_l1tlb_mmvml1prdec 4810 + //MMMC_VM_MX_L1_PERFCOUNTER_LO 4811 + #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4812 + #define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4813 + //MMMC_VM_MX_L1_PERFCOUNTER_HI 4814 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4815 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4816 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4817 + #define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4818 + 4819 + 4820 + // addressBlock: mmhub_mmutcl2_mmatcl2dec 4821 + //MM_ATC_L2_CNTL 4822 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 4823 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 4824 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 4825 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 4826 + #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 4827 + #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4828 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 4829 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 4830 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 4831 + #define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 4832 + #define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 4833 + #define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4834 + //MM_ATC_L2_CNTL2 4835 + #define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 4836 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4837 + #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 4838 + #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 4839 + #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 4840 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 4841 + #define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 4842 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4843 + #define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 4844 + #define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 4845 + #define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 4846 + #define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 4847 + //MM_ATC_L2_CACHE_DATA0 4848 + #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 4849 + #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 4850 + #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 4851 + #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 4852 + #define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 4853 + #define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 4854 + #define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL 4855 + #define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L 4856 + //MM_ATC_L2_CACHE_DATA1 4857 + #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 4858 + #define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 4859 + //MM_ATC_L2_CACHE_DATA2 4860 + #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 4861 + #define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 4862 + //MM_ATC_L2_CNTL3 4863 + #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 4864 + #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 4865 + #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 4866 + #define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 4867 + #define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 4868 + #define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L 4869 + //MM_ATC_L2_STATUS 4870 + #define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 4871 + #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 4872 + #define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L 4873 + #define MM_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 4874 + //MM_ATC_L2_STATUS2 4875 + #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 4876 + #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 4877 + #define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 4878 + #define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 4879 + //MM_ATC_L2_MISC_CG 4880 + #define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 4881 + #define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 4882 + #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 4883 + #define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 4884 + #define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 4885 + #define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 4886 + //MM_ATC_L2_MEM_POWER_LS 4887 + #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 4888 + #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 4889 + #define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 4890 + #define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 4891 + //MM_ATC_L2_CGTT_CLK_CTRL 4892 + #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4893 + #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4894 + #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 4895 + #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 4896 + #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 4897 + #define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4898 + #define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4899 + #define MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 4900 + #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 4901 + #define MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 4902 + //MM_ATC_L2_SDPPORT_CTRL 4903 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 4904 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 4905 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 4906 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 4907 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 4908 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 4909 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 4910 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 4911 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 4912 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 4913 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L 4914 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L 4915 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L 4916 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L 4917 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L 4918 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L 4919 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L 4920 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L 4921 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L 4922 + #define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L 4923 + 4924 + 4925 + // addressBlock: mmhub_mmutcl2_mmvml2pfdec 4926 + //MMVM_L2_CNTL 4927 + #define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 4928 + #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 4929 + #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 4930 + #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 4931 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 4932 + #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 4933 + #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 4934 + #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 4935 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 4936 + #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 4937 + #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 4938 + #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 4939 + #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 4940 + #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 4941 + #define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 4942 + #define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 4943 + #define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 4944 + #define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 4945 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 4946 + #define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 4947 + #define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 4948 + #define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 4949 + #define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 4950 + #define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 4951 + #define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 4952 + #define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 4953 + #define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 4954 + #define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 4955 + //MMVM_L2_CNTL2 4956 + #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 4957 + #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 4958 + #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 4959 + #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 4960 + #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 4961 + #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 4962 + #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 4963 + #define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 4964 + #define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 4965 + #define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 4966 + #define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 4967 + #define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 4968 + #define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 4969 + #define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 4970 + //MMVM_L2_CNTL3 4971 + #define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 4972 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 4973 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 4974 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 4975 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 4976 + #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 4977 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 4978 + #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 4979 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 4980 + #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 4981 + #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 4982 + #define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 4983 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 4984 + #define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 4985 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 4986 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 4987 + #define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 4988 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 4989 + #define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 4990 + #define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 4991 + #define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 4992 + #define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 4993 + //MMVM_L2_STATUS 4994 + #define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 4995 + #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 4996 + #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 4997 + #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 4998 + #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 4999 + #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 5000 + #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 5001 + #define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L 5002 + #define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 5003 + #define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 5004 + #define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 5005 + #define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 5006 + #define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 5007 + #define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 5008 + //MMVM_DUMMY_PAGE_FAULT_CNTL 5009 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 5010 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 5011 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 5012 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 5013 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 5014 + #define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 5015 + //MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 5016 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 5017 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5018 + //MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 5019 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 5020 + #define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 5021 + //MMVM_INVALIDATE_CNTL 5022 + #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 5023 + #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 5024 + #define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL 5025 + #define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L 5026 + //MMVM_L2_PROTECTION_FAULT_CNTL 5027 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 5028 + #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 5029 + #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 5030 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 5031 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 5032 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 5033 + #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 5034 + #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 5035 + #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 5036 + #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 5037 + #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5038 + #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 5039 + #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5040 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 5041 + #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 5042 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 5043 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 5044 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 5045 + #define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 5046 + #define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 5047 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 5048 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 5049 + #define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 5050 + #define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 5051 + #define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 5052 + #define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 5053 + #define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 5054 + #define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5055 + #define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 5056 + #define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5057 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 5058 + #define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 5059 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 5060 + #define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 5061 + //MMVM_L2_PROTECTION_FAULT_CNTL2 5062 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 5063 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 5064 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 5065 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 5066 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 5067 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 5068 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 5069 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 5070 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 5071 + #define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 5072 + //MMVM_L2_PROTECTION_FAULT_MM_CNTL3 5073 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 5074 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 5075 + //MMVM_L2_PROTECTION_FAULT_MM_CNTL4 5076 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 5077 + #define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 5078 + //MMVM_L2_PROTECTION_FAULT_STATUS 5079 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 5080 + #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 5081 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 5082 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 5083 + #define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 5084 + #define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 5085 + #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 5086 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 5087 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 5088 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 5089 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 5090 + #define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 5091 + #define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 5092 + #define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 5093 + #define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 5094 + #define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 5095 + #define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 5096 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 5097 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 5098 + #define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L 5099 + //MMVM_L2_PROTECTION_FAULT_ADDR_LO32 5100 + #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 5101 + #define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5102 + //MMVM_L2_PROTECTION_FAULT_ADDR_HI32 5103 + #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 5104 + #define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 5105 + //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 5106 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 5107 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 5108 + //MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 5109 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 5110 + #define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 5111 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 5112 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5113 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5114 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 5115 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5116 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5117 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 5118 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 5119 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 5120 + //MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 5121 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 5122 + #define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 5123 + //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 5124 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 5125 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 5126 + //MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 5127 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 5128 + #define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 5129 + //MMVM_L2_CNTL4 5130 + #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 5131 + #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 5132 + #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 5133 + #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 5134 + #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 5135 + #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 5136 + #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 5137 + #define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 5138 + #define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 5139 + #define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 5140 + #define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 5141 + #define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 5142 + #define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 5143 + #define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 5144 + //MMVM_L2_MM_GROUP_RT_CLASSES 5145 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 5146 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 5147 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 5148 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 5149 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 5150 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 5151 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 5152 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 5153 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 5154 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 5155 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 5156 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 5157 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 5158 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 5159 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 5160 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 5161 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 5162 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 5163 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 5164 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 5165 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 5166 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 5167 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 5168 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 5169 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 5170 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 5171 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 5172 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 5173 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 5174 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 5175 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 5176 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 5177 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 5178 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 5179 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 5180 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 5181 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 5182 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 5183 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 5184 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 5185 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 5186 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 5187 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 5188 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 5189 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 5190 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 5191 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 5192 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 5193 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 5194 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 5195 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 5196 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 5197 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 5198 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 5199 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 5200 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 5201 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 5202 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 5203 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 5204 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 5205 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 5206 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 5207 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 5208 + #define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 5209 + //MMVM_L2_BANK_SELECT_RESERVED_CID 5210 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5211 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5212 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 5213 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5214 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5215 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5216 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5217 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5218 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 5219 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5220 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5221 + #define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5222 + //MMVM_L2_BANK_SELECT_RESERVED_CID2 5223 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 5224 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 5225 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 5226 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 5227 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 5228 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a 5229 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 5230 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 5231 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 5232 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 5233 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 5234 + #define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L 5235 + //MMVM_L2_CACHE_PARITY_CNTL 5236 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 5237 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 5238 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 5239 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 5240 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 5241 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 5242 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 5243 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 5244 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 5245 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 5246 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 5247 + #define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 5248 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 5249 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 5250 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 5251 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 5252 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 5253 + #define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 5254 + //MMVM_L2_IH_LOG_CNTL 5255 + #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING__SHIFT 0x0 5256 + #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT__SHIFT 0x1 5257 + #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS__SHIFT 0x2 5258 + #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS__SHIFT 0x14 5259 + #define MMVM_L2_IH_LOG_CNTL__ENABLE_LOGGING_MASK 0x00000001L 5260 + #define MMVM_L2_IH_LOG_CNTL__USE_L_BIT_MASK 0x00000002L 5261 + #define MMVM_L2_IH_LOG_CNTL__REGISTER_ADDRESS_MASK 0x000FFFFCL 5262 + #define MMVM_L2_IH_LOG_CNTL__LOG_ALL_TRANSLATIONS_MASK 0x00100000L 5263 + //MMVM_L2_IH_LOG_BUSY 5264 + #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY__SHIFT 0x0 5265 + #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY__SHIFT 0x10 5266 + #define MMVM_L2_IH_LOG_BUSY__PER_VMID_TRANSLATION_BUSY_MASK 0x0000FFFFL 5267 + #define MMVM_L2_IH_LOG_BUSY__PER_VMID_INVALIDATION_BUSY_MASK 0xFFFF0000L 5268 + //MMVM_L2_CGTT_CLK_CTRL 5269 + #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5270 + #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5271 + #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 5272 + #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 5273 + #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 5274 + #define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5275 + #define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5276 + #define MMVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 5277 + #define MMVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 5278 + #define MMVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 5279 + //MMVM_L2_CNTL5 5280 + #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 5281 + #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 5282 + #define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL 5283 + #define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L 5284 + //MMVM_L2_GCR_CNTL 5285 + #define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 5286 + #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 5287 + #define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L 5288 + #define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL 5289 + //MMVML2_WALKER_MACRO_THROTTLE_TIME 5290 + #define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 5291 + #define MMVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL 5292 + //MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 5293 + #define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 5294 + #define MMVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL 5295 + //MMVML2_WALKER_MICRO_THROTTLE_TIME 5296 + #define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 5297 + #define MMVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL 5298 + //MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 5299 + #define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 5300 + #define MMVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL 5301 + 5302 + 5303 + // addressBlock: mmhub_mmutcl2_mmvml2vcdec 5304 + //MMVM_CONTEXT0_CNTL 5305 + #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5306 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5307 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5308 + #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5309 + #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5310 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5311 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5312 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5313 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5314 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5315 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5316 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5317 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5318 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5319 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5320 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5321 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5322 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5323 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5324 + #define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5325 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5326 + #define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5327 + #define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5328 + #define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5329 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5330 + #define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5331 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5332 + #define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5333 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5334 + #define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5335 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5336 + #define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5337 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5338 + #define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5339 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5340 + #define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5341 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5342 + #define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5343 + //MMVM_CONTEXT1_CNTL 5344 + #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5345 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5346 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5347 + #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5348 + #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5349 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5350 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5351 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5352 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5353 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5354 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5355 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5356 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5357 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5358 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5359 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5360 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5361 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5362 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5363 + #define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5364 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5365 + #define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5366 + #define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5367 + #define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5368 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5369 + #define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5370 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5371 + #define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5372 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5373 + #define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5374 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5375 + #define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5376 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5377 + #define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5378 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5379 + #define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5380 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5381 + #define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5382 + //MMVM_CONTEXT2_CNTL 5383 + #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5384 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5385 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5386 + #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5387 + #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5388 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5389 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5390 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5391 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5392 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5393 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5394 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5395 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5396 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5397 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5398 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5399 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5400 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5401 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5402 + #define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5403 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5404 + #define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5405 + #define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5406 + #define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5407 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5408 + #define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5409 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5410 + #define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5411 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5412 + #define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5413 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5414 + #define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5415 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5416 + #define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5417 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5418 + #define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5419 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5420 + #define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5421 + //MMVM_CONTEXT3_CNTL 5422 + #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5423 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5424 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5425 + #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5426 + #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5427 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5428 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5429 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5430 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5431 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5432 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5433 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5434 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5435 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5436 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5437 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5438 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5439 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5440 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5441 + #define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5442 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5443 + #define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5444 + #define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5445 + #define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5446 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5447 + #define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5448 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5449 + #define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5450 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5451 + #define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5452 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5453 + #define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5454 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5455 + #define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5456 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5457 + #define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5458 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5459 + #define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5460 + //MMVM_CONTEXT4_CNTL 5461 + #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5462 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5463 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5464 + #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5465 + #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5466 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5467 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5468 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5469 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5470 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5471 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5472 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5473 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5474 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5475 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5476 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5477 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5478 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5479 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5480 + #define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5481 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5482 + #define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5483 + #define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5484 + #define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5485 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5486 + #define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5487 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5488 + #define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5489 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5490 + #define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5491 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5492 + #define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5493 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5494 + #define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5495 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5496 + #define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5497 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5498 + #define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5499 + //MMVM_CONTEXT5_CNTL 5500 + #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5501 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5502 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5503 + #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5504 + #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5505 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5506 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5507 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5508 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5509 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5510 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5511 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5512 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5513 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5514 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5515 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5516 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5517 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5518 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5519 + #define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5520 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5521 + #define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5522 + #define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5523 + #define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5524 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5525 + #define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5526 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5527 + #define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5528 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5529 + #define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5530 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5531 + #define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5532 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5533 + #define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5534 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5535 + #define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5536 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5537 + #define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5538 + //MMVM_CONTEXT6_CNTL 5539 + #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5540 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5541 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5542 + #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5543 + #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5544 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5545 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5546 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5547 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5548 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5549 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5550 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5551 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5552 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5553 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5554 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5555 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5556 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5557 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5558 + #define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5559 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5560 + #define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5561 + #define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5562 + #define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5563 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5564 + #define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5565 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5566 + #define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5567 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5568 + #define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5569 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5570 + #define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5571 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5572 + #define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5573 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5574 + #define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5575 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5576 + #define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5577 + //MMVM_CONTEXT7_CNTL 5578 + #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5579 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5580 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5581 + #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5582 + #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5583 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5584 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5585 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5586 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5587 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5588 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5589 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5590 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5591 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5592 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5593 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5594 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5595 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5596 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5597 + #define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5598 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5599 + #define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5600 + #define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5601 + #define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5602 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5603 + #define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5604 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5605 + #define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5606 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5607 + #define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5608 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5609 + #define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5610 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5611 + #define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5612 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5613 + #define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5614 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5615 + #define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5616 + //MMVM_CONTEXT8_CNTL 5617 + #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5618 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5619 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5620 + #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5621 + #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5622 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5623 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5624 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5625 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5626 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5627 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5628 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5629 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5630 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5631 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5632 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5633 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5634 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5635 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5636 + #define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5637 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5638 + #define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5639 + #define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5640 + #define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5641 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5642 + #define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5643 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5644 + #define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5645 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5646 + #define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5647 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5648 + #define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5649 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5650 + #define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5651 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5652 + #define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5653 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5654 + #define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5655 + //MMVM_CONTEXT9_CNTL 5656 + #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5657 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5658 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5659 + #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5660 + #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5661 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5662 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5663 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5664 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5665 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5666 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5667 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5668 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5669 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5670 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5671 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5672 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5673 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5674 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5675 + #define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5676 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5677 + #define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5678 + #define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5679 + #define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5680 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5681 + #define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5682 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5683 + #define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5684 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5685 + #define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5686 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5687 + #define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5688 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5689 + #define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5690 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5691 + #define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5692 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5693 + #define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5694 + //MMVM_CONTEXT10_CNTL 5695 + #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5696 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5697 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5698 + #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5699 + #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5700 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5701 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5702 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5703 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5704 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5705 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5706 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5707 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5708 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5709 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5710 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5711 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5712 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5713 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5714 + #define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5715 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5716 + #define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5717 + #define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5718 + #define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5719 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5720 + #define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5721 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5722 + #define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5723 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5724 + #define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5725 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5726 + #define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5727 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5728 + #define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5729 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5730 + #define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5731 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5732 + #define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5733 + //MMVM_CONTEXT11_CNTL 5734 + #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5735 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5736 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5737 + #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5738 + #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5739 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5740 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5741 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5742 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5743 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5744 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5745 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5746 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5747 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5748 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5749 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5750 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5751 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5752 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5753 + #define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5754 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5755 + #define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5756 + #define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5757 + #define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5758 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5759 + #define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5760 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5761 + #define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5762 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5763 + #define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5764 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5765 + #define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5766 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5767 + #define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5768 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5769 + #define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5770 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5771 + #define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5772 + //MMVM_CONTEXT12_CNTL 5773 + #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5774 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5775 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5776 + #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5777 + #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5778 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5779 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5780 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5781 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5782 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5783 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5784 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5785 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5786 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5787 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5788 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5789 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5790 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5791 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5792 + #define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5793 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5794 + #define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5795 + #define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5796 + #define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5797 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5798 + #define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5799 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5800 + #define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5801 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5802 + #define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5803 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5804 + #define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5805 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5806 + #define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5807 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5808 + #define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5809 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5810 + #define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5811 + //MMVM_CONTEXT13_CNTL 5812 + #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5813 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5814 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5815 + #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5816 + #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5817 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5818 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5819 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5820 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5821 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5822 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5823 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5824 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5825 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5826 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5827 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5828 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5829 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5830 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5831 + #define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5832 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5833 + #define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5834 + #define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5835 + #define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5836 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5837 + #define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5838 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5839 + #define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5840 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5841 + #define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5842 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5843 + #define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5844 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5845 + #define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5846 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5847 + #define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5848 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5849 + #define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5850 + //MMVM_CONTEXT14_CNTL 5851 + #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5852 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5853 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5854 + #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5855 + #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5856 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5857 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5858 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5859 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5860 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5861 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5862 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5863 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5864 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5865 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5866 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5867 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5868 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5869 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5870 + #define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5871 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5872 + #define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5873 + #define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5874 + #define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5875 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5876 + #define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5877 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5878 + #define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5879 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5880 + #define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5881 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5882 + #define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5883 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5884 + #define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5885 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5886 + #define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5887 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5888 + #define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5889 + //MMVM_CONTEXT15_CNTL 5890 + #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 5891 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 5892 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 5893 + #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 5894 + #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 5895 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 5896 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 5897 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 5898 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 5899 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 5900 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 5901 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 5902 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 5903 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 5904 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 5905 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 5906 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 5907 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 5908 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 5909 + #define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 5910 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 5911 + #define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 5912 + #define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 5913 + #define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 5914 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 5915 + #define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 5916 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 5917 + #define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 5918 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 5919 + #define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 5920 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 5921 + #define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 5922 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 5923 + #define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 5924 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 5925 + #define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 5926 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 5927 + #define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 5928 + //MMVM_CONTEXTS_DISABLE 5929 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 5930 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 5931 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 5932 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 5933 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 5934 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 5935 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 5936 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 5937 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 5938 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 5939 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 5940 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 5941 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 5942 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 5943 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 5944 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 5945 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 5946 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 5947 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 5948 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 5949 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 5950 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 5951 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 5952 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 5953 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 5954 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 5955 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 5956 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 5957 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 5958 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 5959 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 5960 + #define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 5961 + //MMVM_INVALIDATE_ENG0_SEM 5962 + #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 5963 + #define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 5964 + //MMVM_INVALIDATE_ENG1_SEM 5965 + #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 5966 + #define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 5967 + //MMVM_INVALIDATE_ENG2_SEM 5968 + #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 5969 + #define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 5970 + //MMVM_INVALIDATE_ENG3_SEM 5971 + #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 5972 + #define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 5973 + //MMVM_INVALIDATE_ENG4_SEM 5974 + #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 5975 + #define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 5976 + //MMVM_INVALIDATE_ENG5_SEM 5977 + #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 5978 + #define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 5979 + //MMVM_INVALIDATE_ENG6_SEM 5980 + #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 5981 + #define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 5982 + //MMVM_INVALIDATE_ENG7_SEM 5983 + #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 5984 + #define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 5985 + //MMVM_INVALIDATE_ENG8_SEM 5986 + #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 5987 + #define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 5988 + //MMVM_INVALIDATE_ENG9_SEM 5989 + #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 5990 + #define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 5991 + //MMVM_INVALIDATE_ENG10_SEM 5992 + #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 5993 + #define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 5994 + //MMVM_INVALIDATE_ENG11_SEM 5995 + #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 5996 + #define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 5997 + //MMVM_INVALIDATE_ENG12_SEM 5998 + #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 5999 + #define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 6000 + //MMVM_INVALIDATE_ENG13_SEM 6001 + #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 6002 + #define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 6003 + //MMVM_INVALIDATE_ENG14_SEM 6004 + #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 6005 + #define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 6006 + //MMVM_INVALIDATE_ENG15_SEM 6007 + #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 6008 + #define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 6009 + //MMVM_INVALIDATE_ENG16_SEM 6010 + #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 6011 + #define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 6012 + //MMVM_INVALIDATE_ENG17_SEM 6013 + #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 6014 + #define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 6015 + //MMVM_INVALIDATE_ENG0_REQ 6016 + #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6017 + #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 6018 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6019 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6020 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6021 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6022 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6023 + #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6024 + #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 6025 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6026 + #define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6027 + #define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L 6028 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6029 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6030 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6031 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6032 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6033 + #define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6034 + #define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L 6035 + #define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6036 + //MMVM_INVALIDATE_ENG1_REQ 6037 + #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6038 + #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 6039 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6040 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6041 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6042 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6043 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6044 + #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6045 + #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 6046 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6047 + #define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6048 + #define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L 6049 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6050 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6051 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6052 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6053 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6054 + #define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6055 + #define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L 6056 + #define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6057 + //MMVM_INVALIDATE_ENG2_REQ 6058 + #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6059 + #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 6060 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6061 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6062 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6063 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6064 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6065 + #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6066 + #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 6067 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6068 + #define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6069 + #define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L 6070 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6071 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6072 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6073 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6074 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6075 + #define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6076 + #define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L 6077 + #define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6078 + //MMVM_INVALIDATE_ENG3_REQ 6079 + #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6080 + #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 6081 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6082 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6083 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6084 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6085 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6086 + #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6087 + #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 6088 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6089 + #define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6090 + #define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L 6091 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6092 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6093 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6094 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6095 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6096 + #define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6097 + #define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L 6098 + #define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6099 + //MMVM_INVALIDATE_ENG4_REQ 6100 + #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6101 + #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 6102 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6103 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6104 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6105 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6106 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6107 + #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6108 + #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 6109 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6110 + #define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6111 + #define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L 6112 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6113 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6114 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6115 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6116 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6117 + #define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6118 + #define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L 6119 + #define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6120 + //MMVM_INVALIDATE_ENG5_REQ 6121 + #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6122 + #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 6123 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6124 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6125 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6126 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6127 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6128 + #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6129 + #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 6130 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6131 + #define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6132 + #define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L 6133 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6134 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6135 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6136 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6137 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6138 + #define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6139 + #define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L 6140 + #define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6141 + //MMVM_INVALIDATE_ENG6_REQ 6142 + #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6143 + #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 6144 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6145 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6146 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6147 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6148 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6149 + #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6150 + #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 6151 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6152 + #define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6153 + #define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L 6154 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6155 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6156 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6157 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6158 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6159 + #define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6160 + #define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L 6161 + #define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6162 + //MMVM_INVALIDATE_ENG7_REQ 6163 + #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6164 + #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 6165 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6166 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6167 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6168 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6169 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6170 + #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6171 + #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 6172 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6173 + #define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6174 + #define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L 6175 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6176 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6177 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6178 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6179 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6180 + #define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6181 + #define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L 6182 + #define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6183 + //MMVM_INVALIDATE_ENG8_REQ 6184 + #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6185 + #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 6186 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6187 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6188 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6189 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6190 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6191 + #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6192 + #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 6193 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6194 + #define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6195 + #define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L 6196 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6197 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6198 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6199 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6200 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6201 + #define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6202 + #define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L 6203 + #define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6204 + //MMVM_INVALIDATE_ENG9_REQ 6205 + #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6206 + #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 6207 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6208 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6209 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6210 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6211 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6212 + #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6213 + #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 6214 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6215 + #define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6216 + #define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L 6217 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6218 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6219 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6220 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6221 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6222 + #define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6223 + #define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L 6224 + #define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6225 + //MMVM_INVALIDATE_ENG10_REQ 6226 + #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6227 + #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 6228 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6229 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6230 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6231 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6232 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6233 + #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6234 + #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 6235 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6236 + #define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6237 + #define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L 6238 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6239 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6240 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6241 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6242 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6243 + #define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6244 + #define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L 6245 + #define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6246 + //MMVM_INVALIDATE_ENG11_REQ 6247 + #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6248 + #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 6249 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6250 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6251 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6252 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6253 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6254 + #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6255 + #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 6256 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6257 + #define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6258 + #define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L 6259 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6260 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6261 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6262 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6263 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6264 + #define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6265 + #define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L 6266 + #define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6267 + //MMVM_INVALIDATE_ENG12_REQ 6268 + #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6269 + #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 6270 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6271 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6272 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6273 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6274 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6275 + #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6276 + #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 6277 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6278 + #define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6279 + #define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L 6280 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6281 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6282 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6283 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6284 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6285 + #define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6286 + #define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L 6287 + #define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6288 + //MMVM_INVALIDATE_ENG13_REQ 6289 + #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6290 + #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 6291 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6292 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6293 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6294 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6295 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6296 + #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6297 + #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 6298 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6299 + #define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6300 + #define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L 6301 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6302 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6303 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6304 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6305 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6306 + #define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6307 + #define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L 6308 + #define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6309 + //MMVM_INVALIDATE_ENG14_REQ 6310 + #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6311 + #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 6312 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6313 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6314 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6315 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6316 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6317 + #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6318 + #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 6319 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6320 + #define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6321 + #define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L 6322 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6323 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6324 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6325 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6326 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6327 + #define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6328 + #define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L 6329 + #define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6330 + //MMVM_INVALIDATE_ENG15_REQ 6331 + #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6332 + #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 6333 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6334 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6335 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6336 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6337 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6338 + #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6339 + #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 6340 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6341 + #define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6342 + #define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L 6343 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6344 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6345 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6346 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6347 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6348 + #define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6349 + #define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L 6350 + #define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6351 + //MMVM_INVALIDATE_ENG16_REQ 6352 + #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6353 + #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 6354 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6355 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6356 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6357 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6358 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6359 + #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6360 + #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 6361 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6362 + #define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6363 + #define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L 6364 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6365 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6366 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6367 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6368 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6369 + #define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6370 + #define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L 6371 + #define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6372 + //MMVM_INVALIDATE_ENG17_REQ 6373 + #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 6374 + #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 6375 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 6376 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 6377 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 6378 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 6379 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 6380 + #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 6381 + #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 6382 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a 6383 + #define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 6384 + #define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L 6385 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L 6386 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L 6387 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L 6388 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L 6389 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L 6390 + #define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L 6391 + #define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L 6392 + #define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L 6393 + //MMVM_INVALIDATE_ENG0_ACK 6394 + #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6395 + #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 6396 + #define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6397 + #define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 6398 + //MMVM_INVALIDATE_ENG1_ACK 6399 + #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6400 + #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 6401 + #define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6402 + #define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 6403 + //MMVM_INVALIDATE_ENG2_ACK 6404 + #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6405 + #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 6406 + #define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6407 + #define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 6408 + //MMVM_INVALIDATE_ENG3_ACK 6409 + #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6410 + #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 6411 + #define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6412 + #define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 6413 + //MMVM_INVALIDATE_ENG4_ACK 6414 + #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6415 + #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 6416 + #define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6417 + #define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 6418 + //MMVM_INVALIDATE_ENG5_ACK 6419 + #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6420 + #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 6421 + #define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6422 + #define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 6423 + //MMVM_INVALIDATE_ENG6_ACK 6424 + #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6425 + #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 6426 + #define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6427 + #define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 6428 + //MMVM_INVALIDATE_ENG7_ACK 6429 + #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6430 + #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 6431 + #define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6432 + #define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 6433 + //MMVM_INVALIDATE_ENG8_ACK 6434 + #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6435 + #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 6436 + #define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6437 + #define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 6438 + //MMVM_INVALIDATE_ENG9_ACK 6439 + #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6440 + #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 6441 + #define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6442 + #define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 6443 + //MMVM_INVALIDATE_ENG10_ACK 6444 + #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6445 + #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 6446 + #define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6447 + #define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 6448 + //MMVM_INVALIDATE_ENG11_ACK 6449 + #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6450 + #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 6451 + #define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6452 + #define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 6453 + //MMVM_INVALIDATE_ENG12_ACK 6454 + #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6455 + #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 6456 + #define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6457 + #define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 6458 + //MMVM_INVALIDATE_ENG13_ACK 6459 + #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6460 + #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 6461 + #define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6462 + #define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 6463 + //MMVM_INVALIDATE_ENG14_ACK 6464 + #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6465 + #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 6466 + #define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6467 + #define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 6468 + //MMVM_INVALIDATE_ENG15_ACK 6469 + #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6470 + #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 6471 + #define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6472 + #define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 6473 + //MMVM_INVALIDATE_ENG16_ACK 6474 + #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6475 + #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 6476 + #define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6477 + #define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 6478 + //MMVM_INVALIDATE_ENG17_ACK 6479 + #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 6480 + #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 6481 + #define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 6482 + #define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 6483 + //MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 6484 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6485 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6486 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6487 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6488 + //MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 6489 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6490 + #define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6491 + //MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 6492 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6493 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6494 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6495 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6496 + //MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 6497 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6498 + #define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6499 + //MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 6500 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6501 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6502 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6503 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6504 + //MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 6505 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6506 + #define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6507 + //MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 6508 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6509 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6510 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6511 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6512 + //MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 6513 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6514 + #define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6515 + //MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 6516 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6517 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6518 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6519 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6520 + //MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 6521 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6522 + #define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6523 + //MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 6524 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6525 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6526 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6527 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6528 + //MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 6529 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6530 + #define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6531 + //MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 6532 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6533 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6534 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6535 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6536 + //MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 6537 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6538 + #define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6539 + //MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 6540 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6541 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6542 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6543 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6544 + //MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 6545 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6546 + #define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6547 + //MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 6548 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6549 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6550 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6551 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6552 + //MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 6553 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6554 + #define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6555 + //MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 6556 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6557 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6558 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6559 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6560 + //MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 6561 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6562 + #define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6563 + //MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 6564 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6565 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6566 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6567 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6568 + //MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 6569 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6570 + #define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6571 + //MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 6572 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6573 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6574 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6575 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6576 + //MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 6577 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6578 + #define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6579 + //MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 6580 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6581 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6582 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6583 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6584 + //MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 6585 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6586 + #define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6587 + //MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 6588 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6589 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6590 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6591 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6592 + //MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 6593 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6594 + #define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6595 + //MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 6596 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6597 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6598 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6599 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6600 + //MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 6601 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6602 + #define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6603 + //MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 6604 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6605 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6606 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6607 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6608 + //MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 6609 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6610 + #define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6611 + //MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 6612 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6613 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6614 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6615 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6616 + //MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 6617 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6618 + #define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6619 + //MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 6620 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 6621 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 6622 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 6623 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 6624 + //MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 6625 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 6626 + #define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 6627 + //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 6628 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6629 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6630 + //MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 6631 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6632 + #define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6633 + //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 6634 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6635 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6636 + //MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 6637 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6638 + #define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6639 + //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 6640 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6641 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6642 + //MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 6643 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6644 + #define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6645 + //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 6646 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6647 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6648 + //MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 6649 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6650 + #define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6651 + //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 6652 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6653 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6654 + //MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 6655 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6656 + #define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6657 + //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 6658 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6659 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6660 + //MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 6661 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6662 + #define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6663 + //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 6664 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6665 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6666 + //MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 6667 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6668 + #define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6669 + //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 6670 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6671 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6672 + //MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 6673 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6674 + #define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6675 + //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 6676 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6677 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6678 + //MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 6679 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6680 + #define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6681 + //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 6682 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6683 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6684 + //MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 6685 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6686 + #define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6687 + //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 6688 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6689 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6690 + //MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 6691 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6692 + #define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6693 + //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 6694 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6695 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6696 + //MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 6697 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6698 + #define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6699 + //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 6700 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6701 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6702 + //MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 6703 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6704 + #define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6705 + //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 6706 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6707 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6708 + //MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 6709 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6710 + #define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6711 + //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 6712 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6713 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6714 + //MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 6715 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6716 + #define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6717 + //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 6718 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 6719 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 6720 + //MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 6721 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 6722 + #define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 6723 + //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 6724 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6725 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6726 + //MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 6727 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6728 + #define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6729 + //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 6730 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6731 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6732 + //MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 6733 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6734 + #define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6735 + //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 6736 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6737 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6738 + //MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 6739 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6740 + #define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6741 + //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 6742 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6743 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6744 + //MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 6745 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6746 + #define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6747 + //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 6748 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6749 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6750 + //MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 6751 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6752 + #define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6753 + //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 6754 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6755 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6756 + //MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 6757 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6758 + #define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6759 + //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 6760 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6761 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6762 + //MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 6763 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6764 + #define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6765 + //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 6766 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6767 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6768 + //MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 6769 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6770 + #define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6771 + //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 6772 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6773 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6774 + //MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 6775 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6776 + #define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6777 + //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 6778 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6779 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6780 + //MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 6781 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6782 + #define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6783 + //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 6784 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6785 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6786 + //MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 6787 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6788 + #define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6789 + //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 6790 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6791 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6792 + //MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 6793 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6794 + #define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6795 + //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 6796 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6797 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6798 + //MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 6799 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6800 + #define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6801 + //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 6802 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6803 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6804 + //MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 6805 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6806 + #define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6807 + //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 6808 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6809 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6810 + //MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 6811 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6812 + #define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6813 + //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 6814 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6815 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6816 + //MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 6817 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6818 + #define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6819 + //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 6820 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6821 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6822 + //MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 6823 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6824 + #define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6825 + //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 6826 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6827 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6828 + //MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 6829 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6830 + #define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6831 + //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 6832 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6833 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6834 + //MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 6835 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6836 + #define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6837 + //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 6838 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6839 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6840 + //MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 6841 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6842 + #define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6843 + //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 6844 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6845 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6846 + //MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 6847 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6848 + #define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6849 + //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 6850 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6851 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6852 + //MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 6853 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6854 + #define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6855 + //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 6856 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6857 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6858 + //MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 6859 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6860 + #define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6861 + //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 6862 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6863 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6864 + //MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 6865 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6866 + #define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6867 + //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 6868 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6869 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6870 + //MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 6871 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6872 + #define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6873 + //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 6874 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6875 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6876 + //MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 6877 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6878 + #define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6879 + //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 6880 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6881 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6882 + //MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 6883 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6884 + #define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6885 + //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 6886 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6887 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6888 + //MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 6889 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6890 + #define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6891 + //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 6892 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6893 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6894 + //MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 6895 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6896 + #define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6897 + //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 6898 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6899 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6900 + //MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 6901 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6902 + #define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6903 + //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 6904 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6905 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6906 + //MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 6907 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6908 + #define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6909 + //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 6910 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6911 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6912 + //MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 6913 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6914 + #define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6915 + 6916 + 6917 + // addressBlock: mmhub_mmutcl2_mmvml2pldec 6918 + //MMMC_VM_L2_PERFCOUNTER0_CFG 6919 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6920 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6921 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6922 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6923 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6924 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6925 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6926 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6927 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6928 + #define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6929 + //MMMC_VM_L2_PERFCOUNTER1_CFG 6930 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6931 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6932 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6933 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6934 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6935 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6936 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6937 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6938 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6939 + #define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6940 + //MMMC_VM_L2_PERFCOUNTER2_CFG 6941 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 6942 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 6943 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 6944 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 6945 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 6946 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 6947 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 6948 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 6949 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 6950 + #define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 6951 + //MMMC_VM_L2_PERFCOUNTER3_CFG 6952 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 6953 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 6954 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 6955 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 6956 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 6957 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 6958 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 6959 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 6960 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 6961 + #define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 6962 + //MMMC_VM_L2_PERFCOUNTER4_CFG 6963 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 6964 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 6965 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 6966 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 6967 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 6968 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 6969 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 6970 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 6971 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 6972 + #define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 6973 + //MMMC_VM_L2_PERFCOUNTER5_CFG 6974 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 6975 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 6976 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 6977 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 6978 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 6979 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 6980 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 6981 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 6982 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 6983 + #define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 6984 + //MMMC_VM_L2_PERFCOUNTER6_CFG 6985 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 6986 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 6987 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 6988 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 6989 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 6990 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 6991 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 6992 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 6993 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 6994 + #define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 6995 + //MMMC_VM_L2_PERFCOUNTER7_CFG 6996 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 6997 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 6998 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 6999 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 7000 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 7001 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 7002 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 7003 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 7004 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 7005 + #define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 7006 + //MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 7007 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7008 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7009 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7010 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7011 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7012 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7013 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7014 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7015 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7016 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7017 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7018 + #define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7019 + 7020 + 7021 + // addressBlock: mmhub_mmutcl2_mmvml2prdec 7022 + //MMMC_VM_L2_PERFCOUNTER_LO 7023 + #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7024 + #define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7025 + //MMMC_VM_L2_PERFCOUNTER_HI 7026 + #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7027 + #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7028 + #define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7029 + #define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7030 + 7031 + 7032 + // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 7033 + //MMMC_VM_FB_SIZE_OFFSET_VF0 7034 + #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 7035 + #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 7036 + #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 7037 + #define MMMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 7038 + //MMMC_VM_FB_SIZE_OFFSET_VF1 7039 + #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 7040 + #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 7041 + #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 7042 + #define MMMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 7043 + //MMMC_VM_FB_SIZE_OFFSET_VF2 7044 + #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 7045 + #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 7046 + #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 7047 + #define MMMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 7048 + //MMMC_VM_FB_SIZE_OFFSET_VF3 7049 + #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 7050 + #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 7051 + #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 7052 + #define MMMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 7053 + //MMMC_VM_FB_SIZE_OFFSET_VF4 7054 + #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 7055 + #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 7056 + #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 7057 + #define MMMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 7058 + //MMMC_VM_FB_SIZE_OFFSET_VF5 7059 + #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 7060 + #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 7061 + #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 7062 + #define MMMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 7063 + //MMMC_VM_FB_SIZE_OFFSET_VF6 7064 + #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 7065 + #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 7066 + #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 7067 + #define MMMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 7068 + //MMMC_VM_FB_SIZE_OFFSET_VF7 7069 + #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 7070 + #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 7071 + #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 7072 + #define MMMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 7073 + //MMMC_VM_FB_SIZE_OFFSET_VF8 7074 + #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 7075 + #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 7076 + #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 7077 + #define MMMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 7078 + //MMMC_VM_FB_SIZE_OFFSET_VF9 7079 + #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 7080 + #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 7081 + #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 7082 + #define MMMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 7083 + //MMMC_VM_FB_SIZE_OFFSET_VF10 7084 + #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 7085 + #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 7086 + #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 7087 + #define MMMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 7088 + //MMMC_VM_FB_SIZE_OFFSET_VF11 7089 + #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 7090 + #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 7091 + #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 7092 + #define MMMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 7093 + //MMMC_VM_FB_SIZE_OFFSET_VF12 7094 + #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 7095 + #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 7096 + #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 7097 + #define MMMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 7098 + //MMMC_VM_FB_SIZE_OFFSET_VF13 7099 + #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 7100 + #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 7101 + #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 7102 + #define MMMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 7103 + //MMMC_VM_FB_SIZE_OFFSET_VF14 7104 + #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 7105 + #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 7106 + #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 7107 + #define MMMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 7108 + //MMMC_VM_FB_SIZE_OFFSET_VF15 7109 + #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 7110 + #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 7111 + #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 7112 + #define MMMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 7113 + //MMMC_VM_FB_SIZE_OFFSET_VF16 7114 + #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 7115 + #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 7116 + #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL 7117 + #define MMMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L 7118 + //MMMC_VM_FB_SIZE_OFFSET_VF17 7119 + #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 7120 + #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 7121 + #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL 7122 + #define MMMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L 7123 + //MMMC_VM_FB_SIZE_OFFSET_VF18 7124 + #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 7125 + #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 7126 + #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL 7127 + #define MMMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L 7128 + //MMMC_VM_FB_SIZE_OFFSET_VF19 7129 + #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 7130 + #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 7131 + #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL 7132 + #define MMMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L 7133 + //MMMC_VM_FB_SIZE_OFFSET_VF20 7134 + #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 7135 + #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 7136 + #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL 7137 + #define MMMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L 7138 + //MMMC_VM_FB_SIZE_OFFSET_VF21 7139 + #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 7140 + #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 7141 + #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL 7142 + #define MMMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L 7143 + //MMMC_VM_FB_SIZE_OFFSET_VF22 7144 + #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 7145 + #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 7146 + #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL 7147 + #define MMMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L 7148 + //MMMC_VM_FB_SIZE_OFFSET_VF23 7149 + #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 7150 + #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 7151 + #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL 7152 + #define MMMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L 7153 + //MMMC_VM_FB_SIZE_OFFSET_VF24 7154 + #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 7155 + #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 7156 + #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL 7157 + #define MMMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L 7158 + //MMMC_VM_FB_SIZE_OFFSET_VF25 7159 + #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 7160 + #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 7161 + #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL 7162 + #define MMMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L 7163 + //MMMC_VM_FB_SIZE_OFFSET_VF26 7164 + #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 7165 + #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 7166 + #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL 7167 + #define MMMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L 7168 + //MMMC_VM_FB_SIZE_OFFSET_VF27 7169 + #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 7170 + #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 7171 + #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL 7172 + #define MMMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L 7173 + //MMMC_VM_FB_SIZE_OFFSET_VF28 7174 + #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 7175 + #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 7176 + #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL 7177 + #define MMMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L 7178 + //MMMC_VM_FB_SIZE_OFFSET_VF29 7179 + #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 7180 + #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 7181 + #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL 7182 + #define MMMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L 7183 + //MMMC_VM_FB_SIZE_OFFSET_VF30 7184 + #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 7185 + #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 7186 + #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL 7187 + #define MMMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L 7188 + //MMMC_VM_FB_SIZE_OFFSET_VF31 7189 + #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 7190 + #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 7191 + #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL 7192 + #define MMMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L 7193 + //MMVM_IOMMU_MMIO_CNTRL_1 7194 + #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 7195 + #define MMVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 7196 + //MMMC_VM_MARC_BASE_LO_0 7197 + #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 7198 + #define MMMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 7199 + //MMMC_VM_MARC_BASE_LO_1 7200 + #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 7201 + #define MMMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 7202 + //MMMC_VM_MARC_BASE_LO_2 7203 + #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 7204 + #define MMMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 7205 + //MMMC_VM_MARC_BASE_LO_3 7206 + #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 7207 + #define MMMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 7208 + //MMMC_VM_MARC_BASE_HI_0 7209 + #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 7210 + #define MMMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 7211 + //MMMC_VM_MARC_BASE_HI_1 7212 + #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 7213 + #define MMMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 7214 + //MMMC_VM_MARC_BASE_HI_2 7215 + #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 7216 + #define MMMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 7217 + //MMMC_VM_MARC_BASE_HI_3 7218 + #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 7219 + #define MMMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 7220 + //MMMC_VM_MARC_RELOC_LO_0 7221 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 7222 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 7223 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 7224 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 7225 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 7226 + #define MMMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 7227 + //MMMC_VM_MARC_RELOC_LO_1 7228 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 7229 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 7230 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 7231 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 7232 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 7233 + #define MMMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 7234 + //MMMC_VM_MARC_RELOC_LO_2 7235 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 7236 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 7237 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 7238 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 7239 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 7240 + #define MMMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 7241 + //MMMC_VM_MARC_RELOC_LO_3 7242 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 7243 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 7244 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 7245 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 7246 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 7247 + #define MMMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 7248 + //MMMC_VM_MARC_RELOC_HI_0 7249 + #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 7250 + #define MMMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 7251 + //MMMC_VM_MARC_RELOC_HI_1 7252 + #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 7253 + #define MMMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 7254 + //MMMC_VM_MARC_RELOC_HI_2 7255 + #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 7256 + #define MMMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 7257 + //MMMC_VM_MARC_RELOC_HI_3 7258 + #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 7259 + #define MMMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 7260 + //MMMC_VM_MARC_LEN_LO_0 7261 + #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 7262 + #define MMMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 7263 + //MMMC_VM_MARC_LEN_LO_1 7264 + #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 7265 + #define MMMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 7266 + //MMMC_VM_MARC_LEN_LO_2 7267 + #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 7268 + #define MMMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 7269 + //MMMC_VM_MARC_LEN_LO_3 7270 + #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 7271 + #define MMMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 7272 + //MMMC_VM_MARC_LEN_HI_0 7273 + #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 7274 + #define MMMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 7275 + //MMMC_VM_MARC_LEN_HI_1 7276 + #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 7277 + #define MMMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 7278 + //MMMC_VM_MARC_LEN_HI_2 7279 + #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 7280 + #define MMMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 7281 + //MMMC_VM_MARC_LEN_HI_3 7282 + #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 7283 + #define MMMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 7284 + //MMVM_IOMMU_CONTROL_REGISTER 7285 + #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 7286 + #define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 7287 + //MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 7288 + #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 7289 + #define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 7290 + //MMVM_PCIE_ATS_CNTL 7291 + #define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 7292 + #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 7293 + #define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 7294 + #define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 7295 + //MMVM_PCIE_ATS_CNTL_VF_0 7296 + #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 7297 + #define MMVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 7298 + //MMVM_PCIE_ATS_CNTL_VF_1 7299 + #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 7300 + #define MMVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 7301 + //MMVM_PCIE_ATS_CNTL_VF_2 7302 + #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 7303 + #define MMVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 7304 + //MMVM_PCIE_ATS_CNTL_VF_3 7305 + #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 7306 + #define MMVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 7307 + //MMVM_PCIE_ATS_CNTL_VF_4 7308 + #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 7309 + #define MMVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 7310 + //MMVM_PCIE_ATS_CNTL_VF_5 7311 + #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 7312 + #define MMVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 7313 + //MMVM_PCIE_ATS_CNTL_VF_6 7314 + #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 7315 + #define MMVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 7316 + //MMVM_PCIE_ATS_CNTL_VF_7 7317 + #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 7318 + #define MMVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 7319 + //MMVM_PCIE_ATS_CNTL_VF_8 7320 + #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 7321 + #define MMVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 7322 + //MMVM_PCIE_ATS_CNTL_VF_9 7323 + #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 7324 + #define MMVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 7325 + //MMVM_PCIE_ATS_CNTL_VF_10 7326 + #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 7327 + #define MMVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 7328 + //MMVM_PCIE_ATS_CNTL_VF_11 7329 + #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 7330 + #define MMVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 7331 + //MMVM_PCIE_ATS_CNTL_VF_12 7332 + #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 7333 + #define MMVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 7334 + //MMVM_PCIE_ATS_CNTL_VF_13 7335 + #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 7336 + #define MMVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 7337 + //MMVM_PCIE_ATS_CNTL_VF_14 7338 + #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 7339 + #define MMVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 7340 + //MMVM_PCIE_ATS_CNTL_VF_15 7341 + #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 7342 + #define MMVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 7343 + //MMVM_PCIE_ATS_CNTL_VF_16 7344 + #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f 7345 + #define MMVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L 7346 + //MMVM_PCIE_ATS_CNTL_VF_17 7347 + #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f 7348 + #define MMVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L 7349 + //MMVM_PCIE_ATS_CNTL_VF_18 7350 + #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f 7351 + #define MMVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L 7352 + //MMVM_PCIE_ATS_CNTL_VF_19 7353 + #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f 7354 + #define MMVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L 7355 + //MMVM_PCIE_ATS_CNTL_VF_20 7356 + #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f 7357 + #define MMVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L 7358 + //MMVM_PCIE_ATS_CNTL_VF_21 7359 + #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f 7360 + #define MMVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L 7361 + //MMVM_PCIE_ATS_CNTL_VF_22 7362 + #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f 7363 + #define MMVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L 7364 + //MMVM_PCIE_ATS_CNTL_VF_23 7365 + #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f 7366 + #define MMVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L 7367 + //MMVM_PCIE_ATS_CNTL_VF_24 7368 + #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f 7369 + #define MMVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L 7370 + //MMVM_PCIE_ATS_CNTL_VF_25 7371 + #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f 7372 + #define MMVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L 7373 + //MMVM_PCIE_ATS_CNTL_VF_26 7374 + #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f 7375 + #define MMVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L 7376 + //MMVM_PCIE_ATS_CNTL_VF_27 7377 + #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f 7378 + #define MMVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L 7379 + //MMVM_PCIE_ATS_CNTL_VF_28 7380 + #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f 7381 + #define MMVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L 7382 + //MMVM_PCIE_ATS_CNTL_VF_29 7383 + #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f 7384 + #define MMVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L 7385 + //MMVM_PCIE_ATS_CNTL_VF_30 7386 + #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f 7387 + #define MMVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L 7388 + //MMVM_PCIE_ATS_CNTL_VF_31 7389 + #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f 7390 + #define MMVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L 7391 + //MMUTCL2_CGTT_CLK_CTRL 7392 + #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7393 + #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7394 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 7395 + #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7396 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7397 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7398 + #define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7399 + #define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7400 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 7401 + #define MMUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7402 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7403 + #define MMUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7404 + //MMMC_SHARED_ACTIVE_FCN_ID 7405 + #define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 7406 + #define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 7407 + #define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 7408 + #define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 7409 + 7410 + 7411 + // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 7412 + //MMMC_VM_NB_MMIOBASE 7413 + #define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 7414 + #define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 7415 + //MMMC_VM_NB_MMIOLIMIT 7416 + #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 7417 + #define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 7418 + //MMMC_VM_NB_PCI_CTRL 7419 + #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 7420 + #define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 7421 + //MMMC_VM_NB_PCI_ARB 7422 + #define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 7423 + #define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 7424 + //MMMC_VM_NB_TOP_OF_DRAM_SLOT1 7425 + #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 7426 + #define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 7427 + //MMMC_VM_NB_LOWER_TOP_OF_DRAM2 7428 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 7429 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 7430 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 7431 + #define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 7432 + //MMMC_VM_NB_UPPER_TOP_OF_DRAM2 7433 + #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 7434 + #define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 7435 + //MMMC_VM_FB_OFFSET 7436 + #define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 7437 + #define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 7438 + //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 7439 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 7440 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 7441 + //MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 7442 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 7443 + #define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 7444 + //MMMC_VM_STEERING 7445 + #define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 7446 + #define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 7447 + //MMMC_SHARED_VIRT_RESET_REQ 7448 + #define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 7449 + #define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 7450 + #define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL 7451 + #define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 7452 + //MMMC_MEM_POWER_LS 7453 + #define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7454 + #define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7455 + #define MMMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7456 + #define MMMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7457 + //MMMC_VM_CACHEABLE_DRAM_ADDRESS_START 7458 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 7459 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7460 + //MMMC_VM_CACHEABLE_DRAM_ADDRESS_END 7461 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 7462 + #define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7463 + //MMMC_VM_APT_CNTL 7464 + #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 7465 + #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 7466 + #define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 7467 + #define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 7468 + //MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 7469 + #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 7470 + #define MMMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 7471 + //MMMC_VM_LOCAL_HBM_ADDRESS_START 7472 + #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 7473 + #define MMMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 7474 + //MMMC_VM_LOCAL_HBM_ADDRESS_END 7475 + #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 7476 + #define MMMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 7477 + //MMMC_SHARED_VIRT_RESET_REQ2 7478 + #define MMMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 7479 + #define MMMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L 7480 + 7481 + 7482 + // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 7483 + //MMMC_VM_FB_LOCATION_BASE 7484 + #define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 7485 + #define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 7486 + //MMMC_VM_FB_LOCATION_TOP 7487 + #define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 7488 + #define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 7489 + //MMMC_VM_AGP_TOP 7490 + #define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 7491 + #define MMMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 7492 + //MMMC_VM_AGP_BOT 7493 + #define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 7494 + #define MMMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 7495 + //MMMC_VM_AGP_BASE 7496 + #define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 7497 + #define MMMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 7498 + //MMMC_VM_SYSTEM_APERTURE_LOW_ADDR 7499 + #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 7500 + #define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7501 + //MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 7502 + #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 7503 + #define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 7504 + //MMMC_VM_MX_L1_TLB_CNTL 7505 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 7506 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 7507 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 7508 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 7509 + #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 7510 + #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 7511 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 7512 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 7513 + #define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 7514 + #define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 7515 + #define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 7516 + #define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L 7517 + 7518 + 7519 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 7520 + //MM_ATC_L2_PERFCOUNTER_LO 7521 + #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7522 + #define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7523 + //MM_ATC_L2_PERFCOUNTER_HI 7524 + #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7525 + #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7526 + #define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7527 + #define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7528 + 7529 + 7530 + // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 7531 + //MM_ATC_L2_PERFCOUNTER0_CFG 7532 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7533 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7534 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7535 + #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7536 + #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7537 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7538 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7539 + #define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7540 + #define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7541 + #define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7542 + //MM_ATC_L2_PERFCOUNTER1_CFG 7543 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7544 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7545 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7546 + #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7547 + #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7548 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7549 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7550 + #define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7551 + #define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7552 + #define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7553 + //MM_ATC_L2_PERFCOUNTER_RSLT_CNTL 7554 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7555 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7556 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7557 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7558 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7559 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7560 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7561 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7562 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7563 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7564 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7565 + #define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7566 + 7567 + #endif