tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: rockchip: rk3568: Add PLL rate for 724 MHz
This rate allows to provide a low-jitter 72,4 MHz pixelclock
for a custom eDP panel from the VPLL.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Lucas Stach
and committed by
Heiko Stuebner
f513991b
947b8f2a
+1
+1
drivers/clk/rockchip/clk-rk3568.c
+1
drivers/clk/rockchip/clk-rk3568.c
···
64
64
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
65
65
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
66
66
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
67
+
RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0),
67
68
RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
68
69
RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
69
70
RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),