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ARM: sun8i: Move A23 AHB1 gates out of common DTSI
The AHB1 gates were assumed to be identical between the A23 and the A33,
which turned out to be wrong. Move the A23 gates definition to the A23
DTSI.
Reported-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+25
-25
-25
arch/arm/boot/dts/sun8i-a23-a33.dtsi
-25
arch/arm/boot/dts/sun8i-a23-a33.dtsi
···
175
175
clock-output-names = "apb1";
176
176
};
177
177
178
-
ahb1_gates: clk@01c20060 {
179
-
#clock-cells = <1>;
180
-
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
181
-
reg = <0x01c20060 0x8>;
182
-
clocks = <&ahb1>;
183
-
clock-indices = <1>, <6>,
184
-
<8>, <9>, <10>,
185
-
<13>, <14>,
186
-
<19>, <20>,
187
-
<21>, <24>, <26>,
188
-
<29>, <32>, <36>,
189
-
<40>, <44>, <46>,
190
-
<52>, <54>,
191
-
<57>;
192
-
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
193
-
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
194
-
"ahb1_nand", "ahb1_sdram",
195
-
"ahb1_hstimer", "ahb1_spi0",
196
-
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
197
-
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
198
-
"ahb1_csi", "ahb1_be", "ahb1_fe",
199
-
"ahb1_gpu", "ahb1_spinlock",
200
-
"ahb1_drc";
201
-
};
202
-
203
178
apb1_gates: clk@01c20068 {
204
179
#clock-cells = <1>;
205
180
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
+25
arch/arm/boot/dts/sun8i-a23.dtsi
+25
arch/arm/boot/dts/sun8i-a23.dtsi
···
50
50
};
51
51
52
52
clocks {
53
+
ahb1_gates: clk@01c20060 {
54
+
#clock-cells = <1>;
55
+
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
56
+
reg = <0x01c20060 0x8>;
57
+
clocks = <&ahb1>;
58
+
clock-indices = <1>, <6>,
59
+
<8>, <9>, <10>,
60
+
<13>, <14>,
61
+
<19>, <20>,
62
+
<21>, <24>, <26>,
63
+
<29>, <32>, <36>,
64
+
<40>, <44>, <46>,
65
+
<52>, <54>,
66
+
<57>;
67
+
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
68
+
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
69
+
"ahb1_nand", "ahb1_sdram",
70
+
"ahb1_hstimer", "ahb1_spi0",
71
+
"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
72
+
"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
73
+
"ahb1_csi", "ahb1_be", "ahb1_fe",
74
+
"ahb1_gpu", "ahb1_spinlock",
75
+
"ahb1_drc";
76
+
};
77
+
53
78
mbus_clk: clk@01c2015c {
54
79
#clock-cells = <0>;
55
80
compatible = "allwinner,sun8i-a23-mbus-clk";