drm/amdgpu: add athub v3_0_0 ip headers v6

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add athub v3_0_0 register offset and shift masks
header files (Hawking)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by

Alex Deucher 3 years ago f41c9639 55a800da

+1505

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

athub

athub_3_0_0_offset.h

athub_3_0_0_sh_mask.h

+259

drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_offset.h

+1246

drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h

··· 1 + /* 2 + * Copyright 2021 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _athub_3_0_0_SH_MASK_HEADER 24 + #define _athub_3_0_0_SH_MASK_HEADER 25 + 26 + 27 + // addressBlock: athub_xpbdec 28 + //XPB_RTR_SRC_APRTR0 29 + #define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0 30 + #define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL 31 + //XPB_RTR_SRC_APRTR1 32 + #define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0 33 + #define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL 34 + //XPB_RTR_SRC_APRTR2 35 + #define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0 36 + #define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL 37 + //XPB_RTR_SRC_APRTR3 38 + #define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0 39 + #define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL 40 + //XPB_RTR_SRC_APRTR4 41 + #define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0 42 + #define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL 43 + //XPB_RTR_SRC_APRTR5 44 + #define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0 45 + #define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL 46 + //XPB_RTR_SRC_APRTR6 47 + #define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0 48 + #define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL 49 + //XPB_RTR_SRC_APRTR7 50 + #define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0 51 + #define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL 52 + //XPB_RTR_SRC_APRTR8 53 + #define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0 54 + #define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL 55 + //XPB_RTR_SRC_APRTR9 56 + #define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0 57 + #define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL 58 + //XPB_RTR_SRC_APRTR10 59 + #define XPB_RTR_SRC_APRTR10__BASE_ADDR__SHIFT 0x0 60 + #define XPB_RTR_SRC_APRTR10__BASE_ADDR_MASK 0x7FFFFFFFL 61 + //XPB_RTR_SRC_APRTR11 62 + #define XPB_RTR_SRC_APRTR11__BASE_ADDR__SHIFT 0x0 63 + #define XPB_RTR_SRC_APRTR11__BASE_ADDR_MASK 0x7FFFFFFFL 64 + //XPB_RTR_SRC_APRTR12 65 + #define XPB_RTR_SRC_APRTR12__BASE_ADDR__SHIFT 0x0 66 + #define XPB_RTR_SRC_APRTR12__BASE_ADDR_MASK 0x7FFFFFFFL 67 + //XPB_RTR_SRC_APRTR13 68 + #define XPB_RTR_SRC_APRTR13__BASE_ADDR__SHIFT 0x0 69 + #define XPB_RTR_SRC_APRTR13__BASE_ADDR_MASK 0x7FFFFFFFL 70 + //XPB_RTR_DEST_MAP0 71 + #define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0 72 + #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 73 + #define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14 74 + #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18 75 + #define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19 76 + #define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a 77 + #define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L 78 + #define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL 79 + #define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L 80 + #define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L 81 + #define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L 82 + #define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L 83 + //XPB_RTR_DEST_MAP1 84 + #define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0 85 + #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 86 + #define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14 87 + #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18 88 + #define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19 89 + #define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a 90 + #define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L 91 + #define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL 92 + #define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L 93 + #define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L 94 + #define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L 95 + #define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L 96 + //XPB_RTR_DEST_MAP2 97 + #define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0 98 + #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 99 + #define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14 100 + #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18 101 + #define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19 102 + #define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a 103 + #define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L 104 + #define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL 105 + #define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L 106 + #define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L 107 + #define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L 108 + #define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L 109 + //XPB_RTR_DEST_MAP3 110 + #define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0 111 + #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 112 + #define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14 113 + #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18 114 + #define XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19 115 + #define XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a 116 + #define XPB_RTR_DEST_MAP3__NMR_MASK 0x00000001L 117 + #define XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0x000FFFFEL 118 + #define XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0x00F00000L 119 + #define XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x01000000L 120 + #define XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x02000000L 121 + #define XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7C000000L 122 + //XPB_RTR_DEST_MAP4 123 + #define XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0 124 + #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 125 + #define XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14 126 + #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18 127 + #define XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19 128 + #define XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a 129 + #define XPB_RTR_DEST_MAP4__NMR_MASK 0x00000001L 130 + #define XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0x000FFFFEL 131 + #define XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0x00F00000L 132 + #define XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x01000000L 133 + #define XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x02000000L 134 + #define XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7C000000L 135 + //XPB_RTR_DEST_MAP5 136 + #define XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0 137 + #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 138 + #define XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14 139 + #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18 140 + #define XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19 141 + #define XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a 142 + #define XPB_RTR_DEST_MAP5__NMR_MASK 0x00000001L 143 + #define XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0x000FFFFEL 144 + #define XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0x00F00000L 145 + #define XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x01000000L 146 + #define XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x02000000L 147 + #define XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7C000000L 148 + //XPB_RTR_DEST_MAP6 149 + #define XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0 150 + #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 151 + #define XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14 152 + #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18 153 + #define XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19 154 + #define XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a 155 + #define XPB_RTR_DEST_MAP6__NMR_MASK 0x00000001L 156 + #define XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0x000FFFFEL 157 + #define XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0x00F00000L 158 + #define XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x01000000L 159 + #define XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x02000000L 160 + #define XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7C000000L 161 + //XPB_RTR_DEST_MAP7 162 + #define XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0 163 + #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 164 + #define XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14 165 + #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18 166 + #define XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19 167 + #define XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a 168 + #define XPB_RTR_DEST_MAP7__NMR_MASK 0x00000001L 169 + #define XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0x000FFFFEL 170 + #define XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0x00F00000L 171 + #define XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x01000000L 172 + #define XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x02000000L 173 + #define XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7C000000L 174 + //XPB_RTR_DEST_MAP8 175 + #define XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0 176 + #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 177 + #define XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14 178 + #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18 179 + #define XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19 180 + #define XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a 181 + #define XPB_RTR_DEST_MAP8__NMR_MASK 0x00000001L 182 + #define XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0x000FFFFEL 183 + #define XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0x00F00000L 184 + #define XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x01000000L 185 + #define XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x02000000L 186 + #define XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7C000000L 187 + //XPB_RTR_DEST_MAP9 188 + #define XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0 189 + #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 190 + #define XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14 191 + #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18 192 + #define XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19 193 + #define XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a 194 + #define XPB_RTR_DEST_MAP9__NMR_MASK 0x00000001L 195 + #define XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0x000FFFFEL 196 + #define XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0x00F00000L 197 + #define XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x01000000L 198 + #define XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x02000000L 199 + #define XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7C000000L 200 + //XPB_RTR_DEST_MAP10 201 + #define XPB_RTR_DEST_MAP10__NMR__SHIFT 0x0 202 + #define XPB_RTR_DEST_MAP10__DEST_OFFSET__SHIFT 0x1 203 + #define XPB_RTR_DEST_MAP10__DEST_SEL__SHIFT 0x14 204 + #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB__SHIFT 0x18 205 + #define XPB_RTR_DEST_MAP10__SIDE_OK__SHIFT 0x19 206 + #define XPB_RTR_DEST_MAP10__APRTR_SIZE__SHIFT 0x1a 207 + #define XPB_RTR_DEST_MAP10__NMR_MASK 0x00000001L 208 + #define XPB_RTR_DEST_MAP10__DEST_OFFSET_MASK 0x000FFFFEL 209 + #define XPB_RTR_DEST_MAP10__DEST_SEL_MASK 0x00F00000L 210 + #define XPB_RTR_DEST_MAP10__DEST_SEL_RPB_MASK 0x01000000L 211 + #define XPB_RTR_DEST_MAP10__SIDE_OK_MASK 0x02000000L 212 + #define XPB_RTR_DEST_MAP10__APRTR_SIZE_MASK 0x7C000000L 213 + //XPB_RTR_DEST_MAP11 214 + #define XPB_RTR_DEST_MAP11__NMR__SHIFT 0x0 215 + #define XPB_RTR_DEST_MAP11__DEST_OFFSET__SHIFT 0x1 216 + #define XPB_RTR_DEST_MAP11__DEST_SEL__SHIFT 0x14 217 + #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB__SHIFT 0x18 218 + #define XPB_RTR_DEST_MAP11__SIDE_OK__SHIFT 0x19 219 + #define XPB_RTR_DEST_MAP11__APRTR_SIZE__SHIFT 0x1a 220 + #define XPB_RTR_DEST_MAP11__NMR_MASK 0x00000001L 221 + #define XPB_RTR_DEST_MAP11__DEST_OFFSET_MASK 0x000FFFFEL 222 + #define XPB_RTR_DEST_MAP11__DEST_SEL_MASK 0x00F00000L 223 + #define XPB_RTR_DEST_MAP11__DEST_SEL_RPB_MASK 0x01000000L 224 + #define XPB_RTR_DEST_MAP11__SIDE_OK_MASK 0x02000000L 225 + #define XPB_RTR_DEST_MAP11__APRTR_SIZE_MASK 0x7C000000L 226 + //XPB_RTR_DEST_MAP12 227 + #define XPB_RTR_DEST_MAP12__NMR__SHIFT 0x0 228 + #define XPB_RTR_DEST_MAP12__DEST_OFFSET__SHIFT 0x1 229 + #define XPB_RTR_DEST_MAP12__DEST_SEL__SHIFT 0x14 230 + #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB__SHIFT 0x18 231 + #define XPB_RTR_DEST_MAP12__SIDE_OK__SHIFT 0x19 232 + #define XPB_RTR_DEST_MAP12__APRTR_SIZE__SHIFT 0x1a 233 + #define XPB_RTR_DEST_MAP12__NMR_MASK 0x00000001L 234 + #define XPB_RTR_DEST_MAP12__DEST_OFFSET_MASK 0x000FFFFEL 235 + #define XPB_RTR_DEST_MAP12__DEST_SEL_MASK 0x00F00000L 236 + #define XPB_RTR_DEST_MAP12__DEST_SEL_RPB_MASK 0x01000000L 237 + #define XPB_RTR_DEST_MAP12__SIDE_OK_MASK 0x02000000L 238 + #define XPB_RTR_DEST_MAP12__APRTR_SIZE_MASK 0x7C000000L 239 + //XPB_RTR_DEST_MAP13 240 + #define XPB_RTR_DEST_MAP13__NMR__SHIFT 0x0 241 + #define XPB_RTR_DEST_MAP13__DEST_OFFSET__SHIFT 0x1 242 + #define XPB_RTR_DEST_MAP13__DEST_SEL__SHIFT 0x14 243 + #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB__SHIFT 0x18 244 + #define XPB_RTR_DEST_MAP13__SIDE_OK__SHIFT 0x19 245 + #define XPB_RTR_DEST_MAP13__APRTR_SIZE__SHIFT 0x1a 246 + #define XPB_RTR_DEST_MAP13__NMR_MASK 0x00000001L 247 + #define XPB_RTR_DEST_MAP13__DEST_OFFSET_MASK 0x000FFFFEL 248 + #define XPB_RTR_DEST_MAP13__DEST_SEL_MASK 0x00F00000L 249 + #define XPB_RTR_DEST_MAP13__DEST_SEL_RPB_MASK 0x01000000L 250 + #define XPB_RTR_DEST_MAP13__SIDE_OK_MASK 0x02000000L 251 + #define XPB_RTR_DEST_MAP13__APRTR_SIZE_MASK 0x7C000000L 252 + //XPB_CLG_CFG0 253 + #define XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0 254 + #define XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4 255 + #define XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7 256 + #define XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa 257 + #define XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe 258 + #define XPB_CLG_CFG0__WCB_NUM_MASK 0x0000000FL 259 + #define XPB_CLG_CFG0__LB_TYPE_MASK 0x00000070L 260 + #define XPB_CLG_CFG0__P2P_BAR_MASK 0x00000380L 261 + #define XPB_CLG_CFG0__HOST_FLUSH_MASK 0x00003C00L 262 + #define XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x0003C000L 263 + //XPB_CLG_CFG1 264 + #define XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0 265 + #define XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4 266 + #define XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7 267 + #define XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa 268 + #define XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe 269 + #define XPB_CLG_CFG1__WCB_NUM_MASK 0x0000000FL 270 + #define XPB_CLG_CFG1__LB_TYPE_MASK 0x00000070L 271 + #define XPB_CLG_CFG1__P2P_BAR_MASK 0x00000380L 272 + #define XPB_CLG_CFG1__HOST_FLUSH_MASK 0x00003C00L 273 + #define XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x0003C000L 274 + //XPB_CLG_CFG2 275 + #define XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0 276 + #define XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4 277 + #define XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7 278 + #define XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa 279 + #define XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe 280 + #define XPB_CLG_CFG2__WCB_NUM_MASK 0x0000000FL 281 + #define XPB_CLG_CFG2__LB_TYPE_MASK 0x00000070L 282 + #define XPB_CLG_CFG2__P2P_BAR_MASK 0x00000380L 283 + #define XPB_CLG_CFG2__HOST_FLUSH_MASK 0x00003C00L 284 + #define XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x0003C000L 285 + //XPB_CLG_CFG3 286 + #define XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0 287 + #define XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4 288 + #define XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7 289 + #define XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa 290 + #define XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe 291 + #define XPB_CLG_CFG3__WCB_NUM_MASK 0x0000000FL 292 + #define XPB_CLG_CFG3__LB_TYPE_MASK 0x00000070L 293 + #define XPB_CLG_CFG3__P2P_BAR_MASK 0x00000380L 294 + #define XPB_CLG_CFG3__HOST_FLUSH_MASK 0x00003C00L 295 + #define XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x0003C000L 296 + //XPB_CLG_CFG4 297 + #define XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0 298 + #define XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4 299 + #define XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7 300 + #define XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa 301 + #define XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe 302 + #define XPB_CLG_CFG4__WCB_NUM_MASK 0x0000000FL 303 + #define XPB_CLG_CFG4__LB_TYPE_MASK 0x00000070L 304 + #define XPB_CLG_CFG4__P2P_BAR_MASK 0x00000380L 305 + #define XPB_CLG_CFG4__HOST_FLUSH_MASK 0x00003C00L 306 + #define XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x0003C000L 307 + //XPB_CLG_CFG5 308 + #define XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0 309 + #define XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4 310 + #define XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7 311 + #define XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa 312 + #define XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe 313 + #define XPB_CLG_CFG5__WCB_NUM_MASK 0x0000000FL 314 + #define XPB_CLG_CFG5__LB_TYPE_MASK 0x00000070L 315 + #define XPB_CLG_CFG5__P2P_BAR_MASK 0x00000380L 316 + #define XPB_CLG_CFG5__HOST_FLUSH_MASK 0x00003C00L 317 + #define XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x0003C000L 318 + //XPB_CLG_CFG6 319 + #define XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0 320 + #define XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4 321 + #define XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7 322 + #define XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa 323 + #define XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe 324 + #define XPB_CLG_CFG6__WCB_NUM_MASK 0x0000000FL 325 + #define XPB_CLG_CFG6__LB_TYPE_MASK 0x00000070L 326 + #define XPB_CLG_CFG6__P2P_BAR_MASK 0x00000380L 327 + #define XPB_CLG_CFG6__HOST_FLUSH_MASK 0x00003C00L 328 + #define XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x0003C000L 329 + //XPB_CLG_CFG7 330 + #define XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0 331 + #define XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4 332 + #define XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7 333 + #define XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa 334 + #define XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe 335 + #define XPB_CLG_CFG7__WCB_NUM_MASK 0x0000000FL 336 + #define XPB_CLG_CFG7__LB_TYPE_MASK 0x00000070L 337 + #define XPB_CLG_CFG7__P2P_BAR_MASK 0x00000380L 338 + #define XPB_CLG_CFG7__HOST_FLUSH_MASK 0x00003C00L 339 + #define XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x0003C000L 340 + //XPB_CLG_EXTRA 341 + #define XPB_CLG_EXTRA__CMP0_HIGH__SHIFT 0x0 342 + #define XPB_CLG_EXTRA__CMP0_LOW__SHIFT 0x6 343 + #define XPB_CLG_EXTRA__VLD0__SHIFT 0xb 344 + #define XPB_CLG_EXTRA__CLG0_NUM__SHIFT 0xc 345 + #define XPB_CLG_EXTRA__CMP1_HIGH__SHIFT 0xf 346 + #define XPB_CLG_EXTRA__CMP1_LOW__SHIFT 0x15 347 + #define XPB_CLG_EXTRA__VLD1__SHIFT 0x1a 348 + #define XPB_CLG_EXTRA__CLG1_NUM__SHIFT 0x1b 349 + #define XPB_CLG_EXTRA__CMP0_HIGH_MASK 0x0000003FL 350 + #define XPB_CLG_EXTRA__CMP0_LOW_MASK 0x000007C0L 351 + #define XPB_CLG_EXTRA__VLD0_MASK 0x00000800L 352 + #define XPB_CLG_EXTRA__CLG0_NUM_MASK 0x00007000L 353 + #define XPB_CLG_EXTRA__CMP1_HIGH_MASK 0x001F8000L 354 + #define XPB_CLG_EXTRA__CMP1_LOW_MASK 0x03E00000L 355 + #define XPB_CLG_EXTRA__VLD1_MASK 0x04000000L 356 + #define XPB_CLG_EXTRA__CLG1_NUM_MASK 0x38000000L 357 + //XPB_CLG_EXTRA_MSK 358 + #define XPB_CLG_EXTRA_MSK__MSK0_HIGH__SHIFT 0x0 359 + #define XPB_CLG_EXTRA_MSK__MSK0_LOW__SHIFT 0x6 360 + #define XPB_CLG_EXTRA_MSK__MSK1_HIGH__SHIFT 0xb 361 + #define XPB_CLG_EXTRA_MSK__MSK1_LOW__SHIFT 0x11 362 + #define XPB_CLG_EXTRA_MSK__MSK0_HIGH_MASK 0x0000003FL 363 + #define XPB_CLG_EXTRA_MSK__MSK0_LOW_MASK 0x000007C0L 364 + #define XPB_CLG_EXTRA_MSK__MSK1_HIGH_MASK 0x0001F800L 365 + #define XPB_CLG_EXTRA_MSK__MSK1_LOW_MASK 0x003E0000L 366 + //XPB_LB_ADDR 367 + #define XPB_LB_ADDR__CMP0__SHIFT 0x0 368 + #define XPB_LB_ADDR__MASK0__SHIFT 0xa 369 + #define XPB_LB_ADDR__CMP1__SHIFT 0x14 370 + #define XPB_LB_ADDR__MASK1__SHIFT 0x1a 371 + #define XPB_LB_ADDR__CMP0_MASK 0x000003FFL 372 + #define XPB_LB_ADDR__MASK0_MASK 0x000FFC00L 373 + #define XPB_LB_ADDR__CMP1_MASK 0x03F00000L 374 + #define XPB_LB_ADDR__MASK1_MASK 0xFC000000L 375 + //XPB_WCB_STS 376 + #define XPB_WCB_STS__PBUF_VLD__SHIFT 0x0 377 + #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10 378 + #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17 379 + #define XPB_WCB_STS__PBUF_VLD_MASK 0x0000FFFFL 380 + #define XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x007F0000L 381 + #define XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3F800000L 382 + //XPB_HST_CFG 383 + #define XPB_HST_CFG__BAR_UP_WR_CMD__SHIFT 0x0 384 + #define XPB_HST_CFG__BAR_UP_WR_CMD_MASK 0x00000001L 385 + //XPB_P2P_BAR_CFG 386 + #define XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0 387 + #define XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4 388 + #define XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6 389 + #define XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7 390 + #define XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8 391 + #define XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9 392 + #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa 393 + #define XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb 394 + #define XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc 395 + #define XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0x0000000FL 396 + #define XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x00000030L 397 + #define XPB_P2P_BAR_CFG__SNOOP_MASK 0x00000040L 398 + #define XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x00000080L 399 + #define XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x00000100L 400 + #define XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x00000200L 401 + #define XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x00000400L 402 + #define XPB_P2P_BAR_CFG__RD_EN_MASK 0x00000800L 403 + #define XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x00001000L 404 + //XPB_P2P_BAR0 405 + #define XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0 406 + #define XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4 407 + #define XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8 408 + #define XPB_P2P_BAR0__VALID__SHIFT 0xc 409 + #define XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd 410 + #define XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe 411 + #define XPB_P2P_BAR0__RESERVE__SHIFT 0xf 412 + #define XPB_P2P_BAR0__ADDRESS__SHIFT 0x10 413 + #define XPB_P2P_BAR0__HOST_FLUSH_MASK 0x0000000FL 414 + #define XPB_P2P_BAR0__REG_SYS_BAR_MASK 0x000000F0L 415 + #define XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0x00000F00L 416 + #define XPB_P2P_BAR0__VALID_MASK 0x00001000L 417 + #define XPB_P2P_BAR0__SEND_DIS_MASK 0x00002000L 418 + #define XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x00004000L 419 + #define XPB_P2P_BAR0__RESERVE_MASK 0x00008000L 420 + #define XPB_P2P_BAR0__ADDRESS_MASK 0xFFFF0000L 421 + //XPB_P2P_BAR1 422 + #define XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0 423 + #define XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4 424 + #define XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8 425 + #define XPB_P2P_BAR1__VALID__SHIFT 0xc 426 + #define XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd 427 + #define XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe 428 + #define XPB_P2P_BAR1__RESERVE__SHIFT 0xf 429 + #define XPB_P2P_BAR1__ADDRESS__SHIFT 0x10 430 + #define XPB_P2P_BAR1__HOST_FLUSH_MASK 0x0000000FL 431 + #define XPB_P2P_BAR1__REG_SYS_BAR_MASK 0x000000F0L 432 + #define XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0x00000F00L 433 + #define XPB_P2P_BAR1__VALID_MASK 0x00001000L 434 + #define XPB_P2P_BAR1__SEND_DIS_MASK 0x00002000L 435 + #define XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x00004000L 436 + #define XPB_P2P_BAR1__RESERVE_MASK 0x00008000L 437 + #define XPB_P2P_BAR1__ADDRESS_MASK 0xFFFF0000L 438 + //XPB_P2P_BAR2 439 + #define XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0 440 + #define XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4 441 + #define XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8 442 + #define XPB_P2P_BAR2__VALID__SHIFT 0xc 443 + #define XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd 444 + #define XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe 445 + #define XPB_P2P_BAR2__RESERVE__SHIFT 0xf 446 + #define XPB_P2P_BAR2__ADDRESS__SHIFT 0x10 447 + #define XPB_P2P_BAR2__HOST_FLUSH_MASK 0x0000000FL 448 + #define XPB_P2P_BAR2__REG_SYS_BAR_MASK 0x000000F0L 449 + #define XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0x00000F00L 450 + #define XPB_P2P_BAR2__VALID_MASK 0x00001000L 451 + #define XPB_P2P_BAR2__SEND_DIS_MASK 0x00002000L 452 + #define XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x00004000L 453 + #define XPB_P2P_BAR2__RESERVE_MASK 0x00008000L 454 + #define XPB_P2P_BAR2__ADDRESS_MASK 0xFFFF0000L 455 + //XPB_P2P_BAR3 456 + #define XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0 457 + #define XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4 458 + #define XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8 459 + #define XPB_P2P_BAR3__VALID__SHIFT 0xc 460 + #define XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd 461 + #define XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe 462 + #define XPB_P2P_BAR3__RESERVE__SHIFT 0xf 463 + #define XPB_P2P_BAR3__ADDRESS__SHIFT 0x10 464 + #define XPB_P2P_BAR3__HOST_FLUSH_MASK 0x0000000FL 465 + #define XPB_P2P_BAR3__REG_SYS_BAR_MASK 0x000000F0L 466 + #define XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0x00000F00L 467 + #define XPB_P2P_BAR3__VALID_MASK 0x00001000L 468 + #define XPB_P2P_BAR3__SEND_DIS_MASK 0x00002000L 469 + #define XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x00004000L 470 + #define XPB_P2P_BAR3__RESERVE_MASK 0x00008000L 471 + #define XPB_P2P_BAR3__ADDRESS_MASK 0xFFFF0000L 472 + //XPB_P2P_BAR4 473 + #define XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0 474 + #define XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4 475 + #define XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8 476 + #define XPB_P2P_BAR4__VALID__SHIFT 0xc 477 + #define XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd 478 + #define XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe 479 + #define XPB_P2P_BAR4__RESERVE__SHIFT 0xf 480 + #define XPB_P2P_BAR4__ADDRESS__SHIFT 0x10 481 + #define XPB_P2P_BAR4__HOST_FLUSH_MASK 0x0000000FL 482 + #define XPB_P2P_BAR4__REG_SYS_BAR_MASK 0x000000F0L 483 + #define XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0x00000F00L 484 + #define XPB_P2P_BAR4__VALID_MASK 0x00001000L 485 + #define XPB_P2P_BAR4__SEND_DIS_MASK 0x00002000L 486 + #define XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x00004000L 487 + #define XPB_P2P_BAR4__RESERVE_MASK 0x00008000L 488 + #define XPB_P2P_BAR4__ADDRESS_MASK 0xFFFF0000L 489 + //XPB_P2P_BAR5 490 + #define XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0 491 + #define XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4 492 + #define XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8 493 + #define XPB_P2P_BAR5__VALID__SHIFT 0xc 494 + #define XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd 495 + #define XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe 496 + #define XPB_P2P_BAR5__RESERVE__SHIFT 0xf 497 + #define XPB_P2P_BAR5__ADDRESS__SHIFT 0x10 498 + #define XPB_P2P_BAR5__HOST_FLUSH_MASK 0x0000000FL 499 + #define XPB_P2P_BAR5__REG_SYS_BAR_MASK 0x000000F0L 500 + #define XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0x00000F00L 501 + #define XPB_P2P_BAR5__VALID_MASK 0x00001000L 502 + #define XPB_P2P_BAR5__SEND_DIS_MASK 0x00002000L 503 + #define XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x00004000L 504 + #define XPB_P2P_BAR5__RESERVE_MASK 0x00008000L 505 + #define XPB_P2P_BAR5__ADDRESS_MASK 0xFFFF0000L 506 + //XPB_P2P_BAR6 507 + #define XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0 508 + #define XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4 509 + #define XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8 510 + #define XPB_P2P_BAR6__VALID__SHIFT 0xc 511 + #define XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd 512 + #define XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe 513 + #define XPB_P2P_BAR6__RESERVE__SHIFT 0xf 514 + #define XPB_P2P_BAR6__ADDRESS__SHIFT 0x10 515 + #define XPB_P2P_BAR6__HOST_FLUSH_MASK 0x0000000FL 516 + #define XPB_P2P_BAR6__REG_SYS_BAR_MASK 0x000000F0L 517 + #define XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0x00000F00L 518 + #define XPB_P2P_BAR6__VALID_MASK 0x00001000L 519 + #define XPB_P2P_BAR6__SEND_DIS_MASK 0x00002000L 520 + #define XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x00004000L 521 + #define XPB_P2P_BAR6__RESERVE_MASK 0x00008000L 522 + #define XPB_P2P_BAR6__ADDRESS_MASK 0xFFFF0000L 523 + //XPB_P2P_BAR7 524 + #define XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0 525 + #define XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4 526 + #define XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8 527 + #define XPB_P2P_BAR7__VALID__SHIFT 0xc 528 + #define XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd 529 + #define XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe 530 + #define XPB_P2P_BAR7__RESERVE__SHIFT 0xf 531 + #define XPB_P2P_BAR7__ADDRESS__SHIFT 0x10 532 + #define XPB_P2P_BAR7__HOST_FLUSH_MASK 0x0000000FL 533 + #define XPB_P2P_BAR7__REG_SYS_BAR_MASK 0x000000F0L 534 + #define XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0x00000F00L 535 + #define XPB_P2P_BAR7__VALID_MASK 0x00001000L 536 + #define XPB_P2P_BAR7__SEND_DIS_MASK 0x00002000L 537 + #define XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x00004000L 538 + #define XPB_P2P_BAR7__RESERVE_MASK 0x00008000L 539 + #define XPB_P2P_BAR7__ADDRESS_MASK 0xFFFF0000L 540 + //XPB_P2P_BAR_SETUP 541 + #define XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0 542 + #define XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8 543 + #define XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc 544 + #define XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd 545 + #define XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe 546 + #define XPB_P2P_BAR_SETUP__RESERVE__SHIFT 0xf 547 + #define XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10 548 + #define XPB_P2P_BAR_SETUP__SEL_MASK 0x000000FFL 549 + #define XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0x00000F00L 550 + #define XPB_P2P_BAR_SETUP__VALID_MASK 0x00001000L 551 + #define XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x00002000L 552 + #define XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x00004000L 553 + #define XPB_P2P_BAR_SETUP__RESERVE_MASK 0x00008000L 554 + #define XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xFFFF0000L 555 + //XPB_P2P_BAR_DELTA_ABOVE 556 + #define XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0 557 + #define XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8 558 + #define XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0x000000FFL 559 + #define XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0x0FFFFF00L 560 + //XPB_P2P_BAR_DELTA_BELOW 561 + #define XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0 562 + #define XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8 563 + #define XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0x000000FFL 564 + #define XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0x0FFFFF00L 565 + //XPB_PEER_SYS_BAR0 566 + #define XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0 567 + #define XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x1 568 + #define XPB_PEER_SYS_BAR0__VALID_MASK 0x00000001L 569 + #define XPB_PEER_SYS_BAR0__ADDR_MASK 0xFFFFFFFEL 570 + //XPB_PEER_SYS_BAR1 571 + #define XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0 572 + #define XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x1 573 + #define XPB_PEER_SYS_BAR1__VALID_MASK 0x00000001L 574 + #define XPB_PEER_SYS_BAR1__ADDR_MASK 0xFFFFFFFEL 575 + //XPB_PEER_SYS_BAR2 576 + #define XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0 577 + #define XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x1 578 + #define XPB_PEER_SYS_BAR2__VALID_MASK 0x00000001L 579 + #define XPB_PEER_SYS_BAR2__ADDR_MASK 0xFFFFFFFEL 580 + //XPB_PEER_SYS_BAR3 581 + #define XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0 582 + #define XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x1 583 + #define XPB_PEER_SYS_BAR3__VALID_MASK 0x00000001L 584 + #define XPB_PEER_SYS_BAR3__ADDR_MASK 0xFFFFFFFEL 585 + //XPB_PEER_SYS_BAR4 586 + #define XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0 587 + #define XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x1 588 + #define XPB_PEER_SYS_BAR4__VALID_MASK 0x00000001L 589 + #define XPB_PEER_SYS_BAR4__ADDR_MASK 0xFFFFFFFEL 590 + //XPB_PEER_SYS_BAR5 591 + #define XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0 592 + #define XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x1 593 + #define XPB_PEER_SYS_BAR5__VALID_MASK 0x00000001L 594 + #define XPB_PEER_SYS_BAR5__ADDR_MASK 0xFFFFFFFEL 595 + //XPB_PEER_SYS_BAR6 596 + #define XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0 597 + #define XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x1 598 + #define XPB_PEER_SYS_BAR6__VALID_MASK 0x00000001L 599 + #define XPB_PEER_SYS_BAR6__ADDR_MASK 0xFFFFFFFEL 600 + //XPB_PEER_SYS_BAR7 601 + #define XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0 602 + #define XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x1 603 + #define XPB_PEER_SYS_BAR7__VALID_MASK 0x00000001L 604 + #define XPB_PEER_SYS_BAR7__ADDR_MASK 0xFFFFFFFEL 605 + //XPB_PEER_SYS_BAR8 606 + #define XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0 607 + #define XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x1 608 + #define XPB_PEER_SYS_BAR8__VALID_MASK 0x00000001L 609 + #define XPB_PEER_SYS_BAR8__ADDR_MASK 0xFFFFFFFEL 610 + //XPB_PEER_SYS_BAR9 611 + #define XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0 612 + #define XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x1 613 + #define XPB_PEER_SYS_BAR9__VALID_MASK 0x00000001L 614 + #define XPB_PEER_SYS_BAR9__ADDR_MASK 0xFFFFFFFEL 615 + //XPB_PEER_SYS_BAR10 616 + #define XPB_PEER_SYS_BAR10__VALID__SHIFT 0x0 617 + #define XPB_PEER_SYS_BAR10__ADDR__SHIFT 0x1 618 + #define XPB_PEER_SYS_BAR10__VALID_MASK 0x00000001L 619 + #define XPB_PEER_SYS_BAR10__ADDR_MASK 0xFFFFFFFEL 620 + //XPB_PEER_SYS_BAR11 621 + #define XPB_PEER_SYS_BAR11__VALID__SHIFT 0x0 622 + #define XPB_PEER_SYS_BAR11__ADDR__SHIFT 0x1 623 + #define XPB_PEER_SYS_BAR11__VALID_MASK 0x00000001L 624 + #define XPB_PEER_SYS_BAR11__ADDR_MASK 0xFFFFFFFEL 625 + //XPB_PEER_SYS_BAR12 626 + #define XPB_PEER_SYS_BAR12__VALID__SHIFT 0x0 627 + #define XPB_PEER_SYS_BAR12__ADDR__SHIFT 0x1 628 + #define XPB_PEER_SYS_BAR12__VALID_MASK 0x00000001L 629 + #define XPB_PEER_SYS_BAR12__ADDR_MASK 0xFFFFFFFEL 630 + //XPB_PEER_SYS_BAR13 631 + #define XPB_PEER_SYS_BAR13__VALID__SHIFT 0x0 632 + #define XPB_PEER_SYS_BAR13__ADDR__SHIFT 0x1 633 + #define XPB_PEER_SYS_BAR13__VALID_MASK 0x00000001L 634 + #define XPB_PEER_SYS_BAR13__ADDR_MASK 0xFFFFFFFEL 635 + //XPB_CLK_GAT 636 + #define XPB_CLK_GAT__ONDLY__SHIFT 0x0 637 + #define XPB_CLK_GAT__OFFDLY__SHIFT 0x6 638 + #define XPB_CLK_GAT__RDYDLY__SHIFT 0xc 639 + #define XPB_CLK_GAT__ENABLE__SHIFT 0x12 640 + #define XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13 641 + #define XPB_CLK_GAT__ONDLY_MASK 0x0000003FL 642 + #define XPB_CLK_GAT__OFFDLY_MASK 0x00000FC0L 643 + #define XPB_CLK_GAT__RDYDLY_MASK 0x0003F000L 644 + #define XPB_CLK_GAT__ENABLE_MASK 0x00040000L 645 + #define XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x00080000L 646 + //XPB_INTF_CFG 647 + #define XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0 648 + #define XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8 649 + #define XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10 650 + #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK__SHIFT 0x17 651 + #define XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b 652 + #define XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d 653 + #define XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e 654 + #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA__SHIFT 0x1f 655 + #define XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0x000000FFL 656 + #define XPB_INTF_CFG__MC_WRRET_ASK_MASK 0x0000FF00L 657 + #define XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x007F0000L 658 + #define XPB_INTF_CFG__P2P_WR_CHAIN_BREAK_MASK 0x00800000L 659 + #define XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000L 660 + #define XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000L 661 + #define XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000L 662 + #define XPB_INTF_CFG__QUALIFY_P2P_FOR_GPA_MASK 0x80000000L 663 + //XPB_INTF_STS 664 + #define XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0 665 + #define XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8 666 + #define XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf 667 + #define XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10 668 + #define XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11 669 + #define XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12 670 + #define XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13 671 + #define XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0x000000FFL 672 + #define XPB_INTF_STS__XSP_REQ_CRD_MASK 0x00007F00L 673 + #define XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x00008000L 674 + #define XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x00010000L 675 + #define XPB_INTF_STS__CNS_BUF_FULL_MASK 0x00020000L 676 + #define XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x00040000L 677 + #define XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x07F80000L 678 + //XPB_PIPE_STS 679 + #define XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0 680 + #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1 681 + #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8 682 + #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf 683 + #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10 684 + #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11 685 + #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12 686 + #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13 687 + #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14 688 + #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15 689 + #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16 690 + #define XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17 691 + #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18 692 + #define XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x00000001L 693 + #define XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0x000000FEL 694 + #define XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x00007F00L 695 + #define XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x00008000L 696 + #define XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x00010000L 697 + #define XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x00020000L 698 + #define XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x00040000L 699 + #define XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x00080000L 700 + #define XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x00100000L 701 + #define XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x00200000L 702 + #define XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x00400000L 703 + #define XPB_PIPE_STS__RET_BUF_FULL_MASK 0x00800000L 704 + #define XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xFF000000L 705 + //XPB_SUB_CTRL 706 + #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0 707 + #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1 708 + #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2 709 + #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3 710 + #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4 711 + #define XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5 712 + #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6 713 + #define XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7 714 + #define XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8 715 + #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9 716 + #define XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa 717 + #define XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb 718 + #define XPB_SUB_CTRL__RESET_RET__SHIFT 0xc 719 + #define XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd 720 + #define XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe 721 + #define XPB_SUB_CTRL__RESET_HST__SHIFT 0xf 722 + #define XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10 723 + #define XPB_SUB_CTRL__RESET_SID__SHIFT 0x11 724 + #define XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12 725 + #define XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13 726 + #define XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x00000001L 727 + #define XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x00000002L 728 + #define XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x00000004L 729 + #define XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x00000008L 730 + #define XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x00000010L 731 + #define XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x00000020L 732 + #define XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x00000040L 733 + #define XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x00000080L 734 + #define XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x00000100L 735 + #define XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x00000200L 736 + #define XPB_SUB_CTRL__RESET_CNS_MASK 0x00000400L 737 + #define XPB_SUB_CTRL__RESET_RTR_MASK 0x00000800L 738 + #define XPB_SUB_CTRL__RESET_RET_MASK 0x00001000L 739 + #define XPB_SUB_CTRL__RESET_MAP_MASK 0x00002000L 740 + #define XPB_SUB_CTRL__RESET_WCB_MASK 0x00004000L 741 + #define XPB_SUB_CTRL__RESET_HST_MASK 0x00008000L 742 + #define XPB_SUB_CTRL__RESET_HOP_MASK 0x00010000L 743 + #define XPB_SUB_CTRL__RESET_SID_MASK 0x00020000L 744 + #define XPB_SUB_CTRL__RESET_SRB_MASK 0x00040000L 745 + #define XPB_SUB_CTRL__RESET_CGR_MASK 0x00080000L 746 + //XPB_MAP_INVERT_FLUSH_NUM_LSB 747 + #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0 748 + #define XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0x0000FFFFL 749 + //XPB_PERF_KNOBS 750 + #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0 751 + #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6 752 + #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc 753 + #define XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x0000003FL 754 + #define XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0x00000FC0L 755 + #define XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x0003F000L 756 + //XPB_STICKY 757 + #define XPB_STICKY__BITS__SHIFT 0x0 758 + #define XPB_STICKY__BITS_MASK 0xFFFFFFFFL 759 + //XPB_STICKY_W1C 760 + #define XPB_STICKY_W1C__BITS__SHIFT 0x0 761 + #define XPB_STICKY_W1C__BITS_MASK 0xFFFFFFFFL 762 + //XPB_MISC_CFG 763 + #define XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0 764 + #define XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8 765 + #define XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10 766 + #define XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18 767 + #define XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f 768 + #define XPB_MISC_CFG__FIELDNAME0_MASK 0x000000FFL 769 + #define XPB_MISC_CFG__FIELDNAME1_MASK 0x0000FF00L 770 + #define XPB_MISC_CFG__FIELDNAME2_MASK 0x00FF0000L 771 + #define XPB_MISC_CFG__FIELDNAME3_MASK 0x7F000000L 772 + #define XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000L 773 + //XPB_INTF_CFG2 774 + #define XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0 775 + #define XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0x000000FFL 776 + //XPB_CLG_EXTRA_RD 777 + #define XPB_CLG_EXTRA_RD__CMP0_HIGH__SHIFT 0x0 778 + #define XPB_CLG_EXTRA_RD__CMP0_LOW__SHIFT 0x6 779 + #define XPB_CLG_EXTRA_RD__VLD0__SHIFT 0xb 780 + #define XPB_CLG_EXTRA_RD__CLG0_NUM__SHIFT 0xc 781 + #define XPB_CLG_EXTRA_RD__CMP1_HIGH__SHIFT 0xf 782 + #define XPB_CLG_EXTRA_RD__CMP1_LOW__SHIFT 0x15 783 + #define XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x1a 784 + #define XPB_CLG_EXTRA_RD__CLG1_NUM__SHIFT 0x1b 785 + #define XPB_CLG_EXTRA_RD__CMP0_HIGH_MASK 0x0000003FL 786 + #define XPB_CLG_EXTRA_RD__CMP0_LOW_MASK 0x000007C0L 787 + #define XPB_CLG_EXTRA_RD__VLD0_MASK 0x00000800L 788 + #define XPB_CLG_EXTRA_RD__CLG0_NUM_MASK 0x00007000L 789 + #define XPB_CLG_EXTRA_RD__CMP1_HIGH_MASK 0x001F8000L 790 + #define XPB_CLG_EXTRA_RD__CMP1_LOW_MASK 0x03E00000L 791 + #define XPB_CLG_EXTRA_RD__VLD1_MASK 0x04000000L 792 + #define XPB_CLG_EXTRA_RD__CLG1_NUM_MASK 0x38000000L 793 + //XPB_CLG_EXTRA_MSK_RD 794 + #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH__SHIFT 0x0 795 + #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW__SHIFT 0x6 796 + #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH__SHIFT 0xb 797 + #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW__SHIFT 0x11 798 + #define XPB_CLG_EXTRA_MSK_RD__MSK0_HIGH_MASK 0x0000003FL 799 + #define XPB_CLG_EXTRA_MSK_RD__MSK0_LOW_MASK 0x000007C0L 800 + #define XPB_CLG_EXTRA_MSK_RD__MSK1_HIGH_MASK 0x0001F800L 801 + #define XPB_CLG_EXTRA_MSK_RD__MSK1_LOW_MASK 0x003E0000L 802 + //XPB_CLG_GFX_MATCH 803 + #define XPB_CLG_GFX_MATCH__FARBIRC0_ID__SHIFT 0x0 804 + #define XPB_CLG_GFX_MATCH__FARBIRC1_ID__SHIFT 0x6 805 + #define XPB_CLG_GFX_MATCH__FARBIRC2_ID__SHIFT 0xc 806 + #define XPB_CLG_GFX_MATCH__FARBIRC3_ID__SHIFT 0x12 807 + #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD__SHIFT 0x18 808 + #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD__SHIFT 0x19 809 + #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD__SHIFT 0x1a 810 + #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD__SHIFT 0x1b 811 + #define XPB_CLG_GFX_MATCH__FARBIRC0_ID_MASK 0x0000003FL 812 + #define XPB_CLG_GFX_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 813 + #define XPB_CLG_GFX_MATCH__FARBIRC2_ID_MASK 0x0003F000L 814 + #define XPB_CLG_GFX_MATCH__FARBIRC3_ID_MASK 0x00FC0000L 815 + #define XPB_CLG_GFX_MATCH__FARBIRC0_VLD_MASK 0x01000000L 816 + #define XPB_CLG_GFX_MATCH__FARBIRC1_VLD_MASK 0x02000000L 817 + #define XPB_CLG_GFX_MATCH__FARBIRC2_VLD_MASK 0x04000000L 818 + #define XPB_CLG_GFX_MATCH__FARBIRC3_VLD_MASK 0x08000000L 819 + //XPB_CLG_GFX_MATCH_MSK 820 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 821 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 822 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK__SHIFT 0xc 823 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK__SHIFT 0x12 824 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 825 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 826 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC2_ID_MSK_MASK 0x0003F000L 827 + #define XPB_CLG_GFX_MATCH_MSK__FARBIRC3_ID_MSK_MASK 0x00FC0000L 828 + //XPB_CLG_MM_MATCH 829 + #define XPB_CLG_MM_MATCH__FARBIRC0_ID__SHIFT 0x0 830 + #define XPB_CLG_MM_MATCH__FARBIRC1_ID__SHIFT 0x6 831 + #define XPB_CLG_MM_MATCH__FARBIRC0_VLD__SHIFT 0xc 832 + #define XPB_CLG_MM_MATCH__FARBIRC1_VLD__SHIFT 0xd 833 + #define XPB_CLG_MM_MATCH__FARBIRC0_ID_MASK 0x0000003FL 834 + #define XPB_CLG_MM_MATCH__FARBIRC1_ID_MASK 0x00000FC0L 835 + #define XPB_CLG_MM_MATCH__FARBIRC0_VLD_MASK 0x00001000L 836 + #define XPB_CLG_MM_MATCH__FARBIRC1_VLD_MASK 0x00002000L 837 + //XPB_CLG_MM_MATCH_MSK 838 + #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 839 + #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK__SHIFT 0x6 840 + #define XPB_CLG_MM_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 841 + #define XPB_CLG_MM_MATCH_MSK__FARBIRC1_ID_MSK_MASK 0x00000FC0L 842 + //XPB_CLG_GUS_MATCH 843 + #define XPB_CLG_GUS_MATCH__FARBIRC0_ID__SHIFT 0x0 844 + #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD__SHIFT 0x6 845 + #define XPB_CLG_GUS_MATCH__FARBIRC0_ID_MASK 0x0000003FL 846 + #define XPB_CLG_GUS_MATCH__FARBIRC0_VLD_MASK 0x00000040L 847 + //XPB_CLG_GUS_MATCH_MSK 848 + #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK__SHIFT 0x0 849 + #define XPB_CLG_GUS_MATCH_MSK__FARBIRC0_ID_MSK_MASK 0x0000003FL 850 + 851 + 852 + // addressBlock: athub_rpbdec 853 + //RPB_PASSPW_CONF 854 + #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT 0x0 855 + #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT 0x1 856 + #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE__SHIFT 0x2 857 + #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN__SHIFT 0x3 858 + #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE__SHIFT 0x4 859 + #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN__SHIFT 0x5 860 + #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE__SHIFT 0x6 861 + #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN__SHIFT 0x7 862 + #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE__SHIFT 0x8 863 + #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN__SHIFT 0x9 864 + #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT 0xa 865 + #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT 0xb 866 + #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE__SHIFT 0xc 867 + #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN__SHIFT 0xd 868 + #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT 0xe 869 + #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT 0xf 870 + #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT 0x10 871 + #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT 0x11 872 + #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT 0x12 873 + #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT 0x13 874 + #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT 0x14 875 + #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT 0x15 876 + #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT 0x16 877 + #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT 0x17 878 + #define RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK 0x00000001L 879 + #define RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK 0x00000002L 880 + #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_MASK 0x00000004L 881 + #define RPB_PASSPW_CONF__ATC_VC5_TR_PASSPW_OVERRIDE_EN_MASK 0x00000008L 882 + #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_MASK 0x00000010L 883 + #define RPB_PASSPW_CONF__ATC_VC5_RSPPASSPW_OVERRIDE_EN_MASK 0x00000020L 884 + #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_MASK 0x00000040L 885 + #define RPB_PASSPW_CONF__ATC_VC0_TR_PASSPW_OVERRIDE_EN_MASK 0x00000080L 886 + #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_MASK 0x00000100L 887 + #define RPB_PASSPW_CONF__ATC_VC0_RSPPASSPW_OVERRIDE_EN_MASK 0x00000200L 888 + #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK 0x00000400L 889 + #define RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK 0x00000800L 890 + #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_MASK 0x00001000L 891 + #define RPB_PASSPW_CONF__ATC_PAGE_RSPPASSPW_OVERRIDE_EN_MASK 0x00002000L 892 + #define RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK 0x00004000L 893 + #define RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK 0x00008000L 894 + #define RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK 0x00010000L 895 + #define RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK 0x00020000L 896 + #define RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK 0x00040000L 897 + #define RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK 0x00080000L 898 + #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK 0x00100000L 899 + #define RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK 0x00200000L 900 + #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK 0x00400000L 901 + #define RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK 0x00800000L 902 + //RPB_BLOCKLEVEL_CONF 903 + #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT 0x0 904 + #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x2 905 + #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL__SHIFT 0x3 906 + #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL__SHIFT 0x5 907 + #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT 0x7 908 + #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT 0x9 909 + #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT 0xb 910 + #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0xd 911 + #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT 0xe 912 + #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x10 913 + #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT 0x11 914 + #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT 0x13 915 + #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK 0x00000003L 916 + #define RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00000004L 917 + #define RPB_BLOCKLEVEL_CONF__ATC_VC5_TR_BLOCKLEVEL_MASK 0x00000018L 918 + #define RPB_BLOCKLEVEL_CONF__ATC_VC0_TR_BLOCKLEVEL_MASK 0x00000060L 919 + #define RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK 0x00000180L 920 + #define RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK 0x00000600L 921 + #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK 0x00001800L 922 + #define RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00002000L 923 + #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK 0x0000C000L 924 + #define RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00010000L 925 + #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK 0x00060000L 926 + #define RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK 0x00080000L 927 + //RPB_TAG_CONF 928 + #define RPB_TAG_CONF__RPB_IO_RD__SHIFT 0x0 929 + #define RPB_TAG_CONF__RPB_IO_WR__SHIFT 0xa 930 + #define RPB_TAG_CONF__RPB_IO_RD_MASK 0x000003FFL 931 + #define RPB_TAG_CONF__RPB_IO_WR_MASK 0x000FFC00L 932 + //RPB_ARB_CNTL 933 + #define RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x0 934 + #define RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x8 935 + #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT 0x10 936 + #define RPB_ARB_CNTL__ARB_MODE__SHIFT 0x18 937 + #define RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT 0x19 938 + #define RPB_ARB_CNTL__RPB_VC0_CRD__SHIFT 0x1a 939 + #define RPB_ARB_CNTL__DISABLE_FED__SHIFT 0x1f 940 + #define RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0x000000FFL 941 + #define RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0x0000FF00L 942 + #define RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK 0x00FF0000L 943 + #define RPB_ARB_CNTL__ARB_MODE_MASK 0x01000000L 944 + #define RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK 0x02000000L 945 + #define RPB_ARB_CNTL__RPB_VC0_CRD_MASK 0x7C000000L 946 + #define RPB_ARB_CNTL__DISABLE_FED_MASK 0x80000000L 947 + //RPB_ARB_CNTL2 948 + #define RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT 0x0 949 + #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT 0x8 950 + #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT 0x10 951 + #define RPB_ARB_CNTL2__RPB_VC1_CRD__SHIFT 0x18 952 + #define RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK 0x000000FFL 953 + #define RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK 0x0000FF00L 954 + #define RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK 0x00FF0000L 955 + #define RPB_ARB_CNTL2__RPB_VC1_CRD_MASK 0x1F000000L 956 + //RPB_BIF_CNTL 957 + #define RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT 0x0 958 + #define RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT 0x8 959 + #define RPB_BIF_CNTL__VC2_SWITCH_NUM__SHIFT 0x10 960 + #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT 0x18 961 + #define RPB_BIF_CNTL__TR_QOS_VC__SHIFT 0x19 962 + #define RPB_BIF_CNTL__FATAL_ERROR_ENABLE__SHIFT 0x1c 963 + #define RPB_BIF_CNTL__RESERVE__SHIFT 0x1d 964 + #define RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK 0x000000FFL 965 + #define RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK 0x0000FF00L 966 + #define RPB_BIF_CNTL__VC2_SWITCH_NUM_MASK 0x00FF0000L 967 + #define RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK 0x01000000L 968 + #define RPB_BIF_CNTL__TR_QOS_VC_MASK 0x0E000000L 969 + #define RPB_BIF_CNTL__FATAL_ERROR_ENABLE_MASK 0x10000000L 970 + #define RPB_BIF_CNTL__RESERVE_MASK 0xE0000000L 971 + //RPB_BIF_CNTL2 972 + #define RPB_BIF_CNTL2__ARB_MODE__SHIFT 0x0 973 + #define RPB_BIF_CNTL2__DRAIN_VC_NUM__SHIFT 0x1 974 + #define RPB_BIF_CNTL2__SWITCH_ENABLE__SHIFT 0x3 975 + #define RPB_BIF_CNTL2__SWITCH_THRESHOLD__SHIFT 0x4 976 + #define RPB_BIF_CNTL2__PAGE_PRI_EN__SHIFT 0xc 977 + #define RPB_BIF_CNTL2__VC5_TR_PRI_EN__SHIFT 0xd 978 + #define RPB_BIF_CNTL2__VC0_TR_PRI_EN__SHIFT 0xe 979 + #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE__SHIFT 0xf 980 + #define RPB_BIF_CNTL2__PARITY_CHECK_EN__SHIFT 0x10 981 + #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT 0x11 982 + #define RPB_BIF_CNTL2__RESERVE__SHIFT 0x19 983 + #define RPB_BIF_CNTL2__ARB_MODE_MASK 0x00000001L 984 + #define RPB_BIF_CNTL2__DRAIN_VC_NUM_MASK 0x00000006L 985 + #define RPB_BIF_CNTL2__SWITCH_ENABLE_MASK 0x00000008L 986 + #define RPB_BIF_CNTL2__SWITCH_THRESHOLD_MASK 0x00000FF0L 987 + #define RPB_BIF_CNTL2__PAGE_PRI_EN_MASK 0x00001000L 988 + #define RPB_BIF_CNTL2__VC5_TR_PRI_EN_MASK 0x00002000L 989 + #define RPB_BIF_CNTL2__VC0_TR_PRI_EN_MASK 0x00004000L 990 + #define RPB_BIF_CNTL2__VC0_CHAINED_OVERRIDE_MASK 0x00008000L 991 + #define RPB_BIF_CNTL2__PARITY_CHECK_EN_MASK 0x00010000L 992 + #define RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK 0x00020000L 993 + #define RPB_BIF_CNTL2__RESERVE_MASK 0xFE000000L 994 + //ATHUB_MISC_CNTL 995 + #define ATHUB_MISC_CNTL__CG_OFFDLY__SHIFT 0x0 996 + #define ATHUB_MISC_CNTL__CG_ENABLE__SHIFT 0x6 997 + #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE__SHIFT 0x7 998 + #define ATHUB_MISC_CNTL__PG_ENABLE__SHIFT 0x8 999 + #define ATHUB_MISC_CNTL__PG_OFFDLY__SHIFT 0x9 1000 + #define ATHUB_MISC_CNTL__ALWAYS_BUSY__SHIFT 0xf 1001 + #define ATHUB_MISC_CNTL__CG_STATUS__SHIFT 0x10 1002 + #define ATHUB_MISC_CNTL__PG_STATUS__SHIFT 0x11 1003 + #define ATHUB_MISC_CNTL__RPB_BUSY__SHIFT 0x12 1004 + #define ATHUB_MISC_CNTL__XPB_BUSY__SHIFT 0x13 1005 + #define ATHUB_MISC_CNTL__ATS_BUSY__SHIFT 0x14 1006 + #define ATHUB_MISC_CNTL__SDPNCS_BUSY__SHIFT 0x15 1007 + #define ATHUB_MISC_CNTL__DFPORT_BUSY__SHIFT 0x16 1008 + #define ATHUB_MISC_CNTL__SWITCH_CNTL__SHIFT 0x17 1009 + #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE__SHIFT 0x18 1010 + #define ATHUB_MISC_CNTL__LS_DELAY_TIME__SHIFT 0x19 1011 + #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE__SHIFT 0x1e 1012 + #define ATHUB_MISC_CNTL__RM_VALID_ENABLE__SHIFT 0x1f 1013 + #define ATHUB_MISC_CNTL__CG_OFFDLY_MASK 0x0000003FL 1014 + #define ATHUB_MISC_CNTL__CG_ENABLE_MASK 0x00000040L 1015 + #define ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK 0x00000080L 1016 + #define ATHUB_MISC_CNTL__PG_ENABLE_MASK 0x00000100L 1017 + #define ATHUB_MISC_CNTL__PG_OFFDLY_MASK 0x00007E00L 1018 + #define ATHUB_MISC_CNTL__ALWAYS_BUSY_MASK 0x00008000L 1019 + #define ATHUB_MISC_CNTL__CG_STATUS_MASK 0x00010000L 1020 + #define ATHUB_MISC_CNTL__PG_STATUS_MASK 0x00020000L 1021 + #define ATHUB_MISC_CNTL__RPB_BUSY_MASK 0x00040000L 1022 + #define ATHUB_MISC_CNTL__XPB_BUSY_MASK 0x00080000L 1023 + #define ATHUB_MISC_CNTL__ATS_BUSY_MASK 0x00100000L 1024 + #define ATHUB_MISC_CNTL__SDPNCS_BUSY_MASK 0x00200000L 1025 + #define ATHUB_MISC_CNTL__DFPORT_BUSY_MASK 0x00400000L 1026 + #define ATHUB_MISC_CNTL__SWITCH_CNTL_MASK 0x00800000L 1027 + #define ATHUB_MISC_CNTL__LS_DELAY_ENABLE_MASK 0x01000000L 1028 + #define ATHUB_MISC_CNTL__LS_DELAY_TIME_MASK 0x3E000000L 1029 + #define ATHUB_MISC_CNTL__RESETB_PG_CLK_GATING_ENABLE_MASK 0x40000000L 1030 + #define ATHUB_MISC_CNTL__RM_VALID_ENABLE_MASK 0x80000000L 1031 + //ATHUB_MEM_POWER_LS 1032 + #define ATHUB_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 1033 + #define ATHUB_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 1034 + #define ATHUB_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 1035 + #define ATHUB_MEM_POWER_LS__LS_HOLD_MASK 0x0007FFC0L 1036 + //RPB_SDPPORT_CNTL 1037 + #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT 0x0 1038 + #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT 0x1 1039 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT 0x3 1040 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT 0x4 1041 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT 0x5 1042 + #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT 0x6 1043 + #define RPB_SDPPORT_CNTL__RESERVE1__SHIFT 0xa 1044 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT 0x16 1045 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT 0x17 1046 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT 0x18 1047 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x19 1048 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT 0x1a 1049 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT 0x1b 1050 + #define RPB_SDPPORT_CNTL__CG_BUSY_PORT__SHIFT 0x1c 1051 + #define RPB_SDPPORT_CNTL__RESERVE__SHIFT 0x1d 1052 + #define RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK 0x00000001L 1053 + #define RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK 0x00000006L 1054 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK 0x00000008L 1055 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK 0x00000010L 1056 + #define RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK 0x00000020L 1057 + #define RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK 0x000003C0L 1058 + #define RPB_SDPPORT_CNTL__RESERVE1_MASK 0x003FFC00L 1059 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK 0x00400000L 1060 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK 0x00800000L 1061 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK 0x01000000L 1062 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK 0x02000000L 1063 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK 0x04000000L 1064 + #define RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK 0x08000000L 1065 + #define RPB_SDPPORT_CNTL__CG_BUSY_PORT_MASK 0x10000000L 1066 + #define RPB_SDPPORT_CNTL__RESERVE_MASK 0xE0000000L 1067 + //RPB_NBIF_SDPPORT_CNTL 1068 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT 0x0 1069 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT 0x8 1070 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT 0x10 1071 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT 0x18 1072 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK 0x000000FFL 1073 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK 0x0000FF00L 1074 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK 0x00FF0000L 1075 + #define RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK 0xFF000000L 1076 + //RPB_DEINTRLV_COMBINE_CNTL 1077 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT 0x0 1078 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT 0x4 1079 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT 0x5 1080 + #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT 0x6 1081 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN__SHIFT 0xe 1082 + #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE__SHIFT 0xf 1083 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK 0x0000000FL 1084 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK 0x00000010L 1085 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK 0x00000020L 1086 + #define RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK 0x00003FC0L 1087 + #define RPB_DEINTRLV_COMBINE_CNTL__WC_CLI_INTLV_EN_MASK 0x00004000L 1088 + #define RPB_DEINTRLV_COMBINE_CNTL__RESERVE_MASK 0xFFFF8000L 1089 + //RPB_VC_SWITCH_RDWR 1090 + #define RPB_VC_SWITCH_RDWR__MODE__SHIFT 0x0 1091 + #define RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT 0x2 1092 + #define RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT 0xa 1093 + #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT 0x12 1094 + #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN__SHIFT 0x1a 1095 + #define RPB_VC_SWITCH_RDWR__MODE_MASK 0x00000003L 1096 + #define RPB_VC_SWITCH_RDWR__NUM_RD_MASK 0x000003FCL 1097 + #define RPB_VC_SWITCH_RDWR__NUM_WR_MASK 0x0003FC00L 1098 + #define RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK 0x03FC0000L 1099 + #define RPB_VC_SWITCH_RDWR__CENTER_MARGIN_MASK 0xFC000000L 1100 + //RPB_PERF_COUNTER_CNTL 1101 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1102 + #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2 1103 + #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3 1104 + #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4 1105 + #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5 1106 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9 1107 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe 1108 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13 1109 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18 1110 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x00000003L 1111 + #define RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x00000004L 1112 + #define RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x00000008L 1113 + #define RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x00000010L 1114 + #define RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x000001E0L 1115 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x00003E00L 1116 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x0007C000L 1117 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0x00F80000L 1118 + #define RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1F000000L 1119 + //RPB_PERF_COUNTER_STATUS 1120 + #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0 1121 + #define RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xFFFFFFFFL 1122 + //RPB_PERFCOUNTER_LO 1123 + #define RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1124 + #define RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1125 + //RPB_PERFCOUNTER_HI 1126 + #define RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1127 + #define RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1128 + #define RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1129 + #define RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1130 + //RPB_PERFCOUNTER0_CFG 1131 + #define RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1132 + #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1133 + #define RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1134 + #define RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1135 + #define RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1136 + #define RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1137 + #define RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1138 + #define RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1139 + #define RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1140 + #define RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1141 + //RPB_PERFCOUNTER1_CFG 1142 + #define RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1143 + #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1144 + #define RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1145 + #define RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1146 + #define RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1147 + #define RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1148 + #define RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1149 + #define RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1150 + #define RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1151 + #define RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1152 + //RPB_PERFCOUNTER2_CFG 1153 + #define RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1154 + #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1155 + #define RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1156 + #define RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1157 + #define RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1158 + #define RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1159 + #define RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1160 + #define RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1161 + #define RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1162 + #define RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1163 + //RPB_PERFCOUNTER3_CFG 1164 + #define RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 1165 + #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 1166 + #define RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 1167 + #define RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 1168 + #define RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 1169 + #define RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 1170 + #define RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 1171 + #define RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 1172 + #define RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 1173 + #define RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 1174 + //RPB_PERFCOUNTER_RSLT_CNTL 1175 + #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1176 + #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1177 + #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1178 + #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1179 + #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1180 + #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1181 + #define RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1182 + #define RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1183 + #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1184 + #define RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1185 + #define RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1186 + #define RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1187 + //RPB_ATS_CNTL3 1188 + #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR__SHIFT 0x0 1189 + #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR__SHIFT 0x9 1190 + #define RPB_ATS_CNTL3__RPB_ATS_PR__SHIFT 0x12 1191 + #define RPB_ATS_CNTL3__RPB_ATS_VC5_TR_MASK 0x000001FFL 1192 + #define RPB_ATS_CNTL3__RPB_ATS_VC0_TR_MASK 0x0003FE00L 1193 + #define RPB_ATS_CNTL3__RPB_ATS_PR_MASK 0x07FC0000L 1194 + //RPB_DF_SDPPORT_CNTL 1195 + #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT 0x0 1196 + #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT 0x6 1197 + #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT 0xc 1198 + #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE__SHIFT 0x10 1199 + #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR__SHIFT 0x11 1200 + #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN__SHIFT 0x12 1201 + #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER__SHIFT 0x13 1202 + #define RPB_DF_SDPPORT_CNTL__RESERVE__SHIFT 0x1b 1203 + #define RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK 0x0000003FL 1204 + #define RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK 0x00000FC0L 1205 + #define RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK 0x0000F000L 1206 + #define RPB_DF_SDPPORT_CNTL__DF_RELEASE_CREDIT_MODE_MASK 0x00010000L 1207 + #define RPB_DF_SDPPORT_CNTL__DF_INSERT_PARITY_ERR_MASK 0x00020000L 1208 + #define RPB_DF_SDPPORT_CNTL__DF_BUSY_INCLUDE_CONN_MASK 0x00040000L 1209 + #define RPB_DF_SDPPORT_CNTL__DF_ORIG_ACK_TIMER_MASK 0x07F80000L 1210 + #define RPB_DF_SDPPORT_CNTL__RESERVE_MASK 0xF8000000L 1211 + //RPB_ATS_CNTL 1212 + #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT 0x0 1213 + #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT 0x1 1214 + #define RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT 0x2 1215 + #define RPB_ATS_CNTL__TIME_SLICE__SHIFT 0x7 1216 + #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM__SHIFT 0xf 1217 + #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT 0x13 1218 + #define RPB_ATS_CNTL__WR_AT__SHIFT 0x17 1219 + #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE__SHIFT 0x19 1220 + #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE__SHIFT 0x1a 1221 + #define RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK 0x00000001L 1222 + #define RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK 0x00000002L 1223 + #define RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK 0x0000007CL 1224 + #define RPB_ATS_CNTL__TIME_SLICE_MASK 0x00007F80L 1225 + #define RPB_ATS_CNTL__ATCTR_VC0_SWITCH_NUM_MASK 0x00078000L 1226 + #define RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK 0x00780000L 1227 + #define RPB_ATS_CNTL__WR_AT_MASK 0x01800000L 1228 + #define RPB_ATS_CNTL__MM_TRANS_VC5_ENABLE_MASK 0x02000000L 1229 + #define RPB_ATS_CNTL__GC_TRANS_VC5_ENABLE_MASK 0x04000000L 1230 + //RPB_ATS_CNTL2 1231 + #define RPB_ATS_CNTL2__INVAL_COM_CMD__SHIFT 0x0 1232 + #define RPB_ATS_CNTL2__TRANS_CMD__SHIFT 0x6 1233 + #define RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT 0xc 1234 + #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT 0x12 1235 + #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT 0x15 1236 + #define RPB_ATS_CNTL2__VENDOR_ID__SHIFT 0x18 1237 + #define RPB_ATS_CNTL2__RPB_VC5_CRD__SHIFT 0x1a 1238 + #define RPB_ATS_CNTL2__INVAL_COM_CMD_MASK 0x0000003FL 1239 + #define RPB_ATS_CNTL2__TRANS_CMD_MASK 0x00000FC0L 1240 + #define RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK 0x0003F000L 1241 + #define RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK 0x001C0000L 1242 + #define RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK 0x00E00000L 1243 + #define RPB_ATS_CNTL2__VENDOR_ID_MASK 0x03000000L 1244 + #define RPB_ATS_CNTL2__RPB_VC5_CRD_MASK 0x7C000000L 1245 + 1246 + #endif