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MIPS: R46000: Fix Micro-assembler field overflow for R4600 V2

Fix uasm warning, which triggered because of workaround for R4600 V2 CPUs.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6716/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by Thomas Bogendoerfer and committed by Ralf Baechle f3f0d951 57c7ea51

options
unified split
Changed files
+2 -2
arch
mips
mm
page.c
+2 -2
arch/mips/mm/page.c
··· 273 273 uasm_i_ori(&buf, A2, A0, off); 274 274 275 275 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 276 - uasm_i_lui(&buf, AT, 0xa000); 276 + uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000)); 277 277 278 278 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) 279 279 * cache_line_size : 0; ··· 424 424 uasm_i_ori(&buf, A2, A0, off); 425 425 426 426 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 427 - uasm_i_lui(&buf, AT, 0xa000); 427 + uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000)); 428 428 429 429 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * 430 430 cache_line_size : 0;