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pinctrl: Add mux options 3 and 4 for rockchip pinctrl
Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Doug Anderson
and committed by
Linus Walleij
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Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
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Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
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The Rockchip Pinmux Controller, enables the IC
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to share one PAD to several functional blocks. The sharing is done by
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multiplexing the PAD input/output signals. For each PAD there are up to
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4 muxing options with option 0 being the use as a GPIO.
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multiplexing the PAD input/output signals. For each PAD there are several
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muxing options with option 0 being the use as a GPIO.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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Required properties for pin configuration node:
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- rockchip,pins: 3 integers array, represents a group of pins mux and config
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setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
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The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
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The MUX 0 means gpio and MUX 1 to N mean the specific device function.
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The phandle of a node containing the generic pinconfig options
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to use, as described in pinctrl-bindings.txt in this directory.
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