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linux
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
authored by
Stephen Boyd
and committed by
Michael Turquette
f37753e2
4641d6a5
+10
-3
+10
-3
drivers/clk/clk-stm32f4.c
+10
-3
drivers/clk/clk-stm32f4.c
···
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{ 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
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};
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+
static const struct clk_div_table pll_divq_table[] = {
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+
{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
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+
{ 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
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+
{ 14, 14 }, { 15, 15 },
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+
{ 0 }
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+
};
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+
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static const struct clk_div_table pll_divr_table[] = {
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{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
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};
···
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#define MAX_PLL_DIV 3
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static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
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-
{ 16, 2, 0, pll_divp_table },
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-
{ 24, 4, CLK_DIVIDER_ONE_BASED, NULL },
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-
{ 28, 3, 0, pll_divr_table },
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+
{ 16, 2, 0, pll_divp_table },
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+
{ 24, 4, 0, pll_divq_table },
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+
{ 28, 3, 0, pll_divr_table },
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};
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struct stm32f4_pll_data {