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dt-bindings: i2c: stm32: Migrate i2c-stm32 documentation to yaml

The document was migrated to Yaml format and renamed st,stm32-i2c.yaml

Signed-off-by: Alain Volmat <alain.volmat@st.com>
Signed-off-by: Rob Herring <robh@kernel.org>

authored by

Alain Volmat and committed by
Rob Herring
f33dabf5 1e25c5f5

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-65
Documentation/devicetree/bindings/i2c/i2c-stm32.txt
··· 1 - * I2C controller embedded in STMicroelectronics STM32 I2C platform 2 - 3 - Required properties: 4 - - compatible: Must be one of the following 5 - - "st,stm32f4-i2c" 6 - - "st,stm32f7-i2c" 7 - - reg: Offset and length of the register set for the device 8 - - interrupts: Must contain the interrupt id for I2C event and then the 9 - interrupt id for I2C error. 10 - - resets: Must contain the phandle to the reset controller. 11 - - clocks: Must contain the input clock of the I2C instance. 12 - - A pinctrl state named "default" must be defined to set pins in mode of 13 - operation for I2C transfer 14 - - #address-cells = <1>; 15 - - #size-cells = <0>; 16 - 17 - Optional properties: 18 - - clock-frequency: Desired I2C bus clock frequency in Hz. If not specified, 19 - the default 100 kHz frequency will be used. 20 - For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are 21 - 100000 and 400000. 22 - For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, Fast-mode and Fast-mode 23 - Plus are supported, possible values are 100000, 400000 and 1000000. 24 - - dmas: List of phandles to rx and tx DMA channels. Refer to stm32-dma.txt. 25 - - dma-names: List of dma names. Valid names are: "rx" and "tx". 26 - - i2c-scl-rising-time-ns: I2C SCL Rising time for the board (default: 25) 27 - For STM32F7, STM32H7 and STM32MP1 only. 28 - - i2c-scl-falling-time-ns: I2C SCL Falling time for the board (default: 10) 29 - For STM32F7, STM32H7 and STM32MP1 only. 30 - I2C Timings are derived from these 2 values 31 - - st,syscfg-fmp: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode 32 - Plus speed is selected by slave. 33 - 1st cell: phandle to syscfg 34 - 2nd cell: register offset within SYSCFG 35 - 3rd cell: register bitmask for FMP bit 36 - For STM32F7, STM32H7 and STM32MP1 only. 37 - 38 - Example: 39 - 40 - i2c@40005400 { 41 - compatible = "st,stm32f4-i2c"; 42 - #address-cells = <1>; 43 - #size-cells = <0>; 44 - reg = <0x40005400 0x400>; 45 - interrupts = <31>, 46 - <32>; 47 - resets = <&rcc 277>; 48 - clocks = <&rcc 0 149>; 49 - pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; 50 - pinctrl-names = "default"; 51 - }; 52 - 53 - i2c@40005400 { 54 - compatible = "st,stm32f7-i2c"; 55 - #address-cells = <1>; 56 - #size-cells = <0>; 57 - reg = <0x40005400 0x400>; 58 - interrupts = <31>, 59 - <32>; 60 - resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 61 - clocks = <&rcc 1 CLK_I2C1>; 62 - pinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>; 63 - pinctrl-names = "default"; 64 - st,syscfg-fmp = <&syscfg 0x4 0x1>; 65 - };
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Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: I2C controller embedded in STMicroelectronics STM32 I2C platform 8 + 9 + maintainers: 10 + - Pierre-Yves MORDRET <pierre-yves.mordret@st.com> 11 + 12 + allOf: 13 + - $ref: /schemas/i2c/i2c-controller.yaml# 14 + - if: 15 + properties: 16 + compatible: 17 + contains: 18 + enum: 19 + - st,stm32f7-i2c 20 + then: 21 + properties: 22 + i2c-scl-rising-time-ns: 23 + default: 25 24 + 25 + i2c-scl-falling-time-ns: 26 + default: 10 27 + 28 + st,syscfg-fmp: 29 + description: Use to set Fast Mode Plus bit within SYSCFG when 30 + Fast Mode Plus speed is selected by slave. 31 + Format is phandle to syscfg / register offset within 32 + syscfg / register bitmask for FMP bit. 33 + allOf: 34 + - $ref: "/schemas/types.yaml#/definitions/phandle-array" 35 + - items: 36 + minItems: 3 37 + maxItems: 3 38 + 39 + - if: 40 + properties: 41 + compatible: 42 + contains: 43 + enum: 44 + - st,stm32f4-i2c 45 + then: 46 + properties: 47 + clock-frequency: 48 + enum: [100000, 400000] 49 + 50 + properties: 51 + compatible: 52 + enum: 53 + - st,stm32f4-i2c 54 + - st,stm32f7-i2c 55 + 56 + reg: 57 + maxItems: 1 58 + 59 + interrupts: 60 + items: 61 + - description: interrupt ID for I2C event 62 + - description: interrupt ID for I2C error 63 + 64 + resets: 65 + maxItems: 1 66 + 67 + clocks: 68 + maxItems: 1 69 + 70 + dmas: 71 + items: 72 + - description: RX DMA Channel phandle 73 + - description: TX DMA Channel phandle 74 + 75 + dma-names: 76 + items: 77 + - const: rx 78 + - const: tx 79 + 80 + clock-frequency: 81 + description: Desired I2C bus clock frequency in Hz. If not specified, 82 + the default 100 kHz frequency will be used. 83 + For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, 84 + Fast-mode and Fast-mode Plus are supported, possible 85 + values are 100000, 400000 and 1000000. 86 + default: 100000 87 + enum: [100000, 400000, 1000000] 88 + 89 + required: 90 + - compatible 91 + - reg 92 + - interrupts 93 + - resets 94 + - clocks 95 + 96 + examples: 97 + - | 98 + #include <dt-bindings/mfd/stm32f7-rcc.h> 99 + #include <dt-bindings/clock/stm32fx-clock.h> 100 + //Example 1 (with st,stm32f4-i2c compatible) 101 + i2c@40005400 { 102 + compatible = "st,stm32f4-i2c"; 103 + #address-cells = <1>; 104 + #size-cells = <0>; 105 + reg = <0x40005400 0x400>; 106 + interrupts = <31>, 107 + <32>; 108 + resets = <&rcc 277>; 109 + clocks = <&rcc 0 149>; 110 + }; 111 + 112 + //Example 2 (with st,stm32f7-i2c compatible) 113 + i2c@40005800 { 114 + compatible = "st,stm32f7-i2c"; 115 + #address-cells = <1>; 116 + #size-cells = <0>; 117 + reg = <0x40005800 0x400>; 118 + interrupts = <31>, 119 + <32>; 120 + resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 121 + clocks = <&rcc 1 CLK_I2C1>; 122 + }; 123 + 124 + //Example 3 (with st,stm32f7-i2c compatible on stm32mp) 125 + #include <dt-bindings/interrupt-controller/arm-gic.h> 126 + #include <dt-bindings/clock/stm32mp1-clks.h> 127 + #include <dt-bindings/reset/stm32mp1-resets.h> 128 + i2c@40013000 { 129 + compatible = "st,stm32f7-i2c"; 130 + #address-cells = <1>; 131 + #size-cells = <0>; 132 + reg = <0x40013000 0x400>; 133 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 134 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 135 + clocks = <&rcc I2C2_K>; 136 + resets = <&rcc I2C2_R>; 137 + i2c-scl-rising-time-ns = <185>; 138 + i2c-scl-falling-time-ns = <20>; 139 + st,syscfg-fmp = <&syscfg 0x4 0x2>; 140 + }; 141 + ...