powerpc/of: add eSPI controller dts bindings and DTS modification

Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

authored by Mingkai Hu and committed by Grant Likely f3016fa5 8b60d6c2

+79 -8
+23 -1
Documentation/powerpc/dts-bindings/fsl/spi.txt
··· 1 1 * SPI (Serial Peripheral Interface) 2 2 3 3 Required properties: 4 - - cell-index : SPI controller index. 4 + - cell-index : QE SPI subblock index. 5 + 0: QE subblock SPI1 6 + 1: QE subblock SPI2 5 7 - compatible : should be "fsl,spi". 6 8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 7 9 - reg : Offset and length of the register set for the device ··· 30 28 mode = "cpu"; 31 29 gpios = <&gpio 18 1 // device reg=<0> 32 30 &gpio 19 1>; // device reg=<1> 31 + }; 32 + 33 + 34 + * eSPI (Enhanced Serial Peripheral Interface) 35 + 36 + Required properties: 37 + - compatible : should be "fsl,mpc8536-espi". 38 + - reg : Offset and length of the register set for the device. 39 + - interrupts : should contain eSPI interrupt, the device has one interrupt. 40 + - fsl,espi-num-chipselects : the number of the chipselect signals. 41 + 42 + Example: 43 + spi@110000 { 44 + #address-cells = <1>; 45 + #size-cells = <0>; 46 + compatible = "fsl,mpc8536-espi"; 47 + reg = <0x110000 0x1000>; 48 + interrupts = <53 0x2>; 49 + interrupt-parent = <&mpic>; 50 + fsl,espi-num-chipselects = <4>; 33 51 };
+52
arch/powerpc/boot/dts/mpc8536ds.dts
··· 108 108 }; 109 109 }; 110 110 111 + spi@7000 { 112 + #address-cells = <1>; 113 + #size-cells = <0>; 114 + compatible = "fsl,mpc8536-espi"; 115 + reg = <0x7000 0x1000>; 116 + interrupts = <59 0x2>; 117 + interrupt-parent = <&mpic>; 118 + fsl,espi-num-chipselects = <4>; 119 + 120 + flash@0 { 121 + #address-cells = <1>; 122 + #size-cells = <1>; 123 + compatible = "spansion,s25sl12801"; 124 + reg = <0>; 125 + spi-max-frequency = <40000000>; 126 + partition@u-boot { 127 + label = "u-boot"; 128 + reg = <0x00000000 0x00100000>; 129 + read-only; 130 + }; 131 + partition@kernel { 132 + label = "kernel"; 133 + reg = <0x00100000 0x00500000>; 134 + read-only; 135 + }; 136 + partition@dtb { 137 + label = "dtb"; 138 + reg = <0x00600000 0x00100000>; 139 + read-only; 140 + }; 141 + partition@fs { 142 + label = "file system"; 143 + reg = <0x00700000 0x00900000>; 144 + }; 145 + }; 146 + flash@1 { 147 + compatible = "spansion,s25sl12801"; 148 + reg = <1>; 149 + spi-max-frequency = <40000000>; 150 + }; 151 + flash@2 { 152 + compatible = "spansion,s25sl12801"; 153 + reg = <2>; 154 + spi-max-frequency = <40000000>; 155 + }; 156 + flash@3 { 157 + compatible = "spansion,s25sl12801"; 158 + reg = <3>; 159 + spi-max-frequency = <40000000>; 160 + }; 161 + }; 162 + 111 163 dma@21300 { 112 164 #address-cells = <1>; 113 165 #size-cells = <1>;
+4 -7
arch/powerpc/boot/dts/p4080ds.dts
··· 236 236 }; 237 237 238 238 spi@110000 { 239 - cell-index = <0>; 240 239 #address-cells = <1>; 241 240 #size-cells = <0>; 242 - compatible = "fsl,espi"; 241 + compatible = "fsl,p4080-espi", "fsl,mpc8536-espi"; 243 242 reg = <0x110000 0x1000>; 244 243 interrupts = <53 0x2>; 245 244 interrupt-parent = <&mpic>; 246 - espi,num-ss-bits = <4>; 247 - mode = "cpu"; 245 + fsl,espi-num-chipselects = <4>; 248 246 249 - fsl_m25p80@0 { 247 + flash@0 { 250 248 #address-cells = <1>; 251 249 #size-cells = <1>; 252 - compatible = "fsl,espi-flash"; 250 + compatible = "spansion,s25sl12801"; 253 251 reg = <0>; 254 - linux,modalias = "fsl_m25p80"; 255 252 spi-max-frequency = <40000000>; /* input clock */ 256 253 partition@u-boot { 257 254 label = "u-boot";