Merge tag 'mailbox-v6.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration

+1

Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml

··· 21 21 - mediatek,mt8173-gce 22 22 - mediatek,mt8183-gce 23 23 - mediatek,mt8186-gce 24 + - mediatek,mt8188-gce 24 25 - mediatek,mt8192-gce 25 26 - mediatek,mt8195-gce 26 27

+1

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml

··· 28 28 - qcom,sc8180x-apss-shared 29 29 - qcom,sdm660-apcs-hmss-global 30 30 - qcom,sdm845-apss-shared 31 + - qcom,sm4250-apcs-hmss-global 31 32 - qcom,sm6125-apcs-hmss-global 32 33 - qcom,sm6115-apcs-hmss-global 33 34 - qcom,sm8150-apss-shared

+3 -1

Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml

··· 24 24 compatible: 25 25 items: 26 26 - enum: 27 + - qcom,sc7280-ipcc 28 + - qcom,sc8280xp-ipcc 27 29 - qcom,sm6350-ipcc 28 30 - qcom,sm6375-ipcc 29 31 - qcom,sm8250-ipcc 30 32 - qcom,sm8350-ipcc 31 33 - qcom,sm8450-ipcc 32 - - qcom,sc7280-ipcc 34 + - qcom,sm8550-ipcc 33 35 - const: qcom,ipcc 34 36 35 37 reg:

+1

drivers/mailbox/Kconfig

··· 136 136 config TI_MESSAGE_MANAGER 137 137 tristate "Texas Instruments Message Manager Driver" 138 138 depends on ARCH_KEYSTONE || ARCH_K3 139 + default ARCH_K3 139 140 help 140 141 An implementation of Message Manager slave driver for Keystone 141 142 and K3 architecture SoCs from Texas Instruments. Message Manager

+2 -2

drivers/mailbox/arm_mhuv2.c

··· 1062 1062 int ret = -EINVAL; 1063 1063 1064 1064 reg = devm_of_iomap(dev, dev->of_node, 0, NULL); 1065 - if (!reg) 1066 - return -ENOMEM; 1065 + if (IS_ERR(reg)) 1066 + return PTR_ERR(reg); 1067 1067 1068 1068 mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); 1069 1069 if (!mhu)

+28 -3

drivers/mailbox/mailbox-mpfs.c

··· 2 2 /* 3 3 * Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver 4 4 * 5 - * Copyright (c) 2020 Microchip Corporation. All rights reserved. 5 + * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved. 6 6 * 7 7 * Author: Conor Dooley <conor.dooley@microchip.com> 8 8 * ··· 56 56 #define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY) 57 57 58 58 #define SCB_STATUS_POS (16) 59 - #define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS) 59 + #define SCB_STATUS_MASK GENMASK(SCB_STATUS_POS + SCB_MASK_WIDTH - 1, SCB_STATUS_POS) 60 60 61 61 struct mpfs_mbox { 62 62 struct mbox_controller controller; ··· 130 130 struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; 131 131 struct mpfs_mss_response *response = mbox->response; 132 132 u16 num_words = ALIGN((response->resp_size), (4)) / 4U; 133 - u32 i; 133 + u32 i, status; 134 134 135 135 if (!response->resp_msg) { 136 136 dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM); 137 137 return; 138 138 } 139 + 140 + /* 141 + * The status is stored in bits 31:16 of the SERVICES_SR register. 142 + * It is only valid when BUSY == 0. 143 + * We should *never* get an interrupt while the controller is 144 + * still in the busy state. If we do, something has gone badly 145 + * wrong & the content of the mailbox would not be valid. 146 + */ 147 + if (mpfs_mbox_busy(mbox)) { 148 + dev_err(mbox->dev, "got an interrupt but system controller is busy\n"); 149 + response->resp_status = 0xDEAD; 150 + return; 151 + } 152 + 153 + status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); 154 + 155 + /* 156 + * If the status of the individual servers is non-zero, the service has 157 + * failed. The contents of the mailbox at this point are not be valid, 158 + * so don't bother reading them. Set the status so that the driver 159 + * implementing the service can handle the result. 160 + */ 161 + response->resp_status = (status & SCB_STATUS_MASK) >> SCB_STATUS_POS; 162 + if (response->resp_status) 163 + return; 139 164 140 165 if (!mpfs_mbox_busy(mbox)) { 141 166 for (i = 0; i < num_words; i++) {

+82 -48

drivers/mailbox/mtk-cmdq-mailbox.c

··· 38 38 #define CMDQ_THR_PRIORITY 0x40 39 39 40 40 #define GCE_GCTL_VALUE 0x48 41 + #define GCE_CTRL_BY_SW GENMASK(2, 0) 42 + #define GCE_DDR_EN GENMASK(18, 16) 41 43 42 44 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 43 45 #define CMDQ_THR_ENABLED 0x1 ··· 75 73 struct mbox_controller mbox; 76 74 void __iomem *base; 77 75 int irq; 78 - u32 thread_nr; 79 76 u32 irq_mask; 77 + const struct gce_plat *pdata; 80 78 struct cmdq_thread *thread; 81 79 struct clk_bulk_data clocks[CMDQ_GCE_NUM_MAX]; 82 80 bool suspended; 83 - u8 shift_pa; 84 - bool control_by_sw; 85 - u32 gce_num; 86 81 }; 87 82 88 83 struct gce_plat { 89 84 u32 thread_nr; 90 85 u8 shift; 91 86 bool control_by_sw; 87 + bool sw_ddr_en; 92 88 u32 gce_num; 93 89 }; 90 + 91 + static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) 92 + { 93 + WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); 94 + 95 + if (enable) 96 + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); 97 + else 98 + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); 99 + 100 + clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); 101 + } 94 102 95 103 u8 cmdq_get_shift_pa(struct mbox_chan *chan) 96 104 { 97 105 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); 98 106 99 - return cmdq->shift_pa; 107 + return cmdq->pdata->shift; 100 108 } 101 109 EXPORT_SYMBOL(cmdq_get_shift_pa); 102 110 ··· 138 126 static void cmdq_init(struct cmdq *cmdq) 139 127 { 140 128 int i; 129 + u32 gctl_regval = 0; 141 130 142 - WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); 143 - if (cmdq->control_by_sw) 144 - writel(0x7, cmdq->base + GCE_GCTL_VALUE); 131 + WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); 132 + if (cmdq->pdata->control_by_sw) 133 + gctl_regval = GCE_CTRL_BY_SW; 134 + if (cmdq->pdata->sw_ddr_en) 135 + gctl_regval |= GCE_DDR_EN; 136 + 137 + if (gctl_regval) 138 + writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE); 139 + 145 140 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); 146 141 for (i = 0; i <= CMDQ_MAX_EVENT; i++) 147 142 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); 148 - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); 143 + clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); 149 144 } 150 145 151 146 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) ··· 197 178 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 198 179 prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] = 199 180 (u64)CMDQ_JUMP_BY_PA << 32 | 200 - (task->pa_base >> task->cmdq->shift_pa); 181 + (task->pa_base >> task->cmdq->pdata->shift); 201 182 dma_sync_single_for_device(dev, prev_task->pa_base, 202 183 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE); 203 184 ··· 231 212 next_task = list_first_entry_or_null(&thread->task_busy_list, 232 213 struct cmdq_task, list_entry); 233 214 if (next_task) 234 - writel(next_task->pa_base >> cmdq->shift_pa, 215 + writel(next_task->pa_base >> cmdq->pdata->shift, 235 216 thread->base + CMDQ_THR_CURR_ADDR); 236 217 cmdq_thread_resume(thread); 237 218 } ··· 262 243 else 263 244 return; 264 245 265 - curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa; 246 + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift; 266 247 267 248 list_for_each_entry_safe(task, tmp, &thread->task_busy_list, 268 249 list_entry) { ··· 285 266 286 267 if (list_empty(&thread->task_busy_list)) { 287 268 cmdq_thread_disable(cmdq, thread); 288 - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); 269 + clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); 289 270 } 290 271 } 291 272 ··· 299 280 if (!(irq_status ^ cmdq->irq_mask)) 300 281 return IRQ_NONE; 301 282 302 - for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) { 283 + for_each_clear_bit(bit, &irq_status, cmdq->pdata->thread_nr) { 303 284 struct cmdq_thread *thread = &cmdq->thread[bit]; 304 285 305 286 spin_lock_irqsave(&thread->chan->lock, flags); ··· 319 300 320 301 cmdq->suspended = true; 321 302 322 - for (i = 0; i < cmdq->thread_nr; i++) { 303 + for (i = 0; i < cmdq->pdata->thread_nr; i++) { 323 304 thread = &cmdq->thread[i]; 324 305 if (!list_empty(&thread->task_busy_list)) { 325 306 task_running = true; ··· 330 311 if (task_running) 331 312 dev_warn(dev, "exist running task(s) in suspend\n"); 332 313 333 - clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); 314 + if (cmdq->pdata->sw_ddr_en) 315 + cmdq_sw_ddr_enable(cmdq, false); 316 + 317 + clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks); 334 318 335 319 return 0; 336 320 } ··· 342 320 { 343 321 struct cmdq *cmdq = dev_get_drvdata(dev); 344 322 345 - WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); 323 + WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks)); 346 324 cmdq->suspended = false; 325 + 326 + if (cmdq->pdata->sw_ddr_en) 327 + cmdq_sw_ddr_enable(cmdq, true); 328 + 347 329 return 0; 348 330 } 349 331 ··· 355 329 { 356 330 struct cmdq *cmdq = platform_get_drvdata(pdev); 357 331 358 - clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); 332 + if (cmdq->pdata->sw_ddr_en) 333 + cmdq_sw_ddr_enable(cmdq, false); 334 + 335 + clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks); 359 336 return 0; 360 337 } 361 338 ··· 384 355 task->pkt = pkt; 385 356 386 357 if (list_empty(&thread->task_busy_list)) { 387 - WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); 358 + WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); 388 359 389 360 /* 390 361 * The thread reset will clear thread related register to 0, ··· 394 365 */ 395 366 WARN_ON(cmdq_thread_reset(cmdq, thread) < 0); 396 367 397 - writel(task->pa_base >> cmdq->shift_pa, 368 + writel(task->pa_base >> cmdq->pdata->shift, 398 369 thread->base + CMDQ_THR_CURR_ADDR); 399 - writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 370 + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift, 400 371 thread->base + CMDQ_THR_END_ADDR); 401 372 402 373 writel(thread->priority, thread->base + CMDQ_THR_PRIORITY); ··· 405 376 } else { 406 377 WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0); 407 378 curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << 408 - cmdq->shift_pa; 379 + cmdq->pdata->shift; 409 380 end_pa = readl(thread->base + CMDQ_THR_END_ADDR) << 410 - cmdq->shift_pa; 381 + cmdq->pdata->shift; 411 382 /* check boundary */ 412 383 if (curr_pa == end_pa - CMDQ_INST_SIZE || 413 384 curr_pa == end_pa) { 414 385 /* set to this task directly */ 415 - writel(task->pa_base >> cmdq->shift_pa, 386 + writel(task->pa_base >> cmdq->pdata->shift, 416 387 thread->base + CMDQ_THR_CURR_ADDR); 417 388 } else { 418 389 cmdq_task_insert_into_thread(task); 419 390 smp_mb(); /* modify jump before enable thread */ 420 391 } 421 - writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa, 392 + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift, 422 393 thread->base + CMDQ_THR_END_ADDR); 423 394 cmdq_thread_resume(thread); 424 395 } ··· 457 428 } 458 429 459 430 cmdq_thread_disable(cmdq, thread); 460 - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); 431 + clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); 461 432 462 433 done: 463 434 /* ··· 497 468 498 469 cmdq_thread_resume(thread); 499 470 cmdq_thread_disable(cmdq, thread); 500 - clk_bulk_disable(cmdq->gce_num, cmdq->clocks); 471 + clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); 501 472 502 473 out: 503 474 spin_unlock_irqrestore(&thread->chan->lock, flags); ··· 544 515 struct device *dev = &pdev->dev; 545 516 struct cmdq *cmdq; 546 517 int err, i; 547 - struct gce_plat *plat_data; 548 518 struct device_node *phandle = dev->of_node; 549 519 struct device_node *node; 550 520 int alias_id = 0; ··· 562 534 if (cmdq->irq < 0) 563 535 return cmdq->irq; 564 536 565 - plat_data = (struct gce_plat *)of_device_get_match_data(dev); 566 - if (!plat_data) { 537 + cmdq->pdata = device_get_match_data(dev); 538 + if (!cmdq->pdata) { 567 539 dev_err(dev, "failed to get match data\n"); 568 540 return -EINVAL; 569 541 } 570 542 571 - cmdq->thread_nr = plat_data->thread_nr; 572 - cmdq->shift_pa = plat_data->shift; 573 - cmdq->control_by_sw = plat_data->control_by_sw; 574 - cmdq->gce_num = plat_data->gce_num; 575 - cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); 576 - err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 577 - "mtk_cmdq", cmdq); 578 - if (err < 0) { 579 - dev_err(dev, "failed to register ISR (%d)\n", err); 580 - return err; 581 - } 543 + cmdq->irq_mask = GENMASK(cmdq->pdata->thread_nr - 1, 0); 582 544 583 545 dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n", 584 546 dev, cmdq->base, cmdq->irq); 585 547 586 - if (cmdq->gce_num > 1) { 548 + if (cmdq->pdata->gce_num > 1) { 587 549 for_each_child_of_node(phandle->parent, node) { 588 550 alias_id = of_alias_get_id(node, clk_name); 589 - if (alias_id >= 0 && alias_id < cmdq->gce_num) { 551 + if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) { 590 552 cmdq->clocks[alias_id].id = clk_names[alias_id]; 591 553 cmdq->clocks[alias_id].clk = of_clk_get(node, 0); 592 554 if (IS_ERR(cmdq->clocks[alias_id].clk)) { ··· 598 580 } 599 581 600 582 cmdq->mbox.dev = dev; 601 - cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, 583 + cmdq->mbox.chans = devm_kcalloc(dev, cmdq->pdata->thread_nr, 602 584 sizeof(*cmdq->mbox.chans), GFP_KERNEL); 603 585 if (!cmdq->mbox.chans) 604 586 return -ENOMEM; 605 587 606 - cmdq->mbox.num_chans = cmdq->thread_nr; 588 + cmdq->mbox.num_chans = cmdq->pdata->thread_nr; 607 589 cmdq->mbox.ops = &cmdq_mbox_chan_ops; 608 590 cmdq->mbox.of_xlate = cmdq_xlate; 609 591 ··· 611 593 cmdq->mbox.txdone_irq = false; 612 594 cmdq->mbox.txdone_poll = false; 613 595 614 - cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, 596 + cmdq->thread = devm_kcalloc(dev, cmdq->pdata->thread_nr, 615 597 sizeof(*cmdq->thread), GFP_KERNEL); 616 598 if (!cmdq->thread) 617 599 return -ENOMEM; 618 600 619 - for (i = 0; i < cmdq->thread_nr; i++) { 601 + for (i = 0; i < cmdq->pdata->thread_nr; i++) { 620 602 cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + 621 603 CMDQ_THR_SIZE * i; 622 604 INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list); ··· 631 613 632 614 platform_set_drvdata(pdev, cmdq); 633 615 634 - WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); 616 + WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks)); 635 617 636 618 cmdq_init(cmdq); 619 + 620 + err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, 621 + "mtk_cmdq", cmdq); 622 + if (err < 0) { 623 + dev_err(dev, "failed to register ISR (%d)\n", err); 624 + return err; 625 + } 637 626 638 627 return 0; 639 628 } ··· 685 660 .gce_num = 2 686 661 }; 687 662 663 + static const struct gce_plat gce_plat_v7 = { 664 + .thread_nr = 24, 665 + .shift = 3, 666 + .control_by_sw = true, 667 + .sw_ddr_en = true, 668 + .gce_num = 1 669 + }; 670 + 688 671 static const struct of_device_id cmdq_of_ids[] = { 689 672 {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, 690 673 {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, 674 + {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7}, 691 675 {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, 692 676 {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, 693 677 {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},

+1

drivers/mailbox/qcom-apcs-ipc-mailbox.c

··· 156 156 { .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data }, 157 157 { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &msm8994_apcs_data }, 158 158 { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data }, 159 + { .compatible = "qcom,sm4250-apcs-hmss-global", .data = &msm8994_apcs_data }, 159 160 { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &msm8994_apcs_data }, 160 161 { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data }, 161 162 { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },

+1 -3

drivers/mailbox/rockchip-mailbox.c

··· 164 164 static int rockchip_mbox_probe(struct platform_device *pdev) 165 165 { 166 166 struct rockchip_mbox *mb; 167 - const struct of_device_id *match; 168 167 const struct rockchip_mbox_data *drv_data; 169 168 struct resource *res; 170 169 int ret, irq, i; ··· 171 172 if (!pdev->dev.of_node) 172 173 return -ENODEV; 173 174 174 - match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node); 175 - drv_data = (const struct rockchip_mbox_data *)match->data; 175 + drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev); 176 176 177 177 mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL); 178 178 if (!mb)

+3 -1

drivers/mailbox/zynqmp-ipi-mailbox.c

··· 493 493 ret = device_register(&ipi_mbox->dev); 494 494 if (ret) { 495 495 dev_err(dev, "Failed to register ipi mbox dev.\n"); 496 + put_device(&ipi_mbox->dev); 496 497 return ret; 497 498 } 498 499 mdev = &ipi_mbox->dev; ··· 620 619 ipi_mbox = &pdata->ipi_mboxes[i]; 621 620 if (ipi_mbox->dev.parent) { 622 621 mbox_controller_unregister(&ipi_mbox->mbox); 623 - device_unregister(&ipi_mbox->dev); 622 + if (device_is_registered(&ipi_mbox->dev)) 623 + device_unregister(&ipi_mbox->dev); 624 624 } 625 625 } 626 626 }

+967

include/dt-bindings/mailbox/mediatek,mt8188-gce.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2 + /* 3 + * Copyright (c) 2022 MediaTek Inc. 4 + * 5 + */ 6 + #ifndef _DT_BINDINGS_GCE_MT8188_H 7 + #define _DT_BINDINGS_GCE_MT8188_H 8 + 9 + #define CMDQ_THR_PRIO_LOWEST 0 10 + #define CMDQ_THR_PRIO_1 1 11 + #define CMDQ_THR_PRIO_2 2 12 + #define CMDQ_THR_PRIO_3 3 13 + #define CMDQ_THR_PRIO_4 4 14 + #define CMDQ_THR_PRIO_5 5 15 + #define CMDQ_THR_PRIO_6 6 16 + #define CMDQ_THR_PRIO_HIGHEST 7 17 + 18 + #define SUBSYS_1400XXXX 0 19 + #define SUBSYS_1401XXXX 1 20 + #define SUBSYS_1402XXXX 2 21 + #define SUBSYS_1c00XXXX 3 22 + #define SUBSYS_1c01XXXX 4 23 + #define SUBSYS_1c02XXXX 5 24 + #define SUBSYS_1c10XXXX 6 25 + #define SUBSYS_1c11XXXX 7 26 + #define SUBSYS_1c12XXXX 8 27 + #define SUBSYS_14f0XXXX 9 28 + #define SUBSYS_14f1XXXX 10 29 + #define SUBSYS_14f2XXXX 11 30 + #define SUBSYS_1800XXXX 12 31 + #define SUBSYS_1801XXXX 13 32 + #define SUBSYS_1802XXXX 14 33 + #define SUBSYS_1803XXXX 15 34 + #define SUBSYS_1032XXXX 16 35 + #define SUBSYS_1033XXXX 17 36 + #define SUBSYS_1600XXXX 18 37 + #define SUBSYS_1601XXXX 19 38 + #define SUBSYS_14e0XXXX 20 39 + #define SUBSYS_1c20XXXX 21 40 + #define SUBSYS_1c30XXXX 22 41 + #define SUBSYS_1c40XXXX 23 42 + #define SUBSYS_1c50XXXX 24 43 + #define SUBSYS_1c60XXXX 25 44 + #define SUBSYS_NO_SUPPORT 99 45 + 46 + #define CMDQ_EVENT_IMG_SOF 0 47 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_0 1 48 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_1 2 49 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_2 3 50 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_3 4 51 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_4 5 52 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_5 6 53 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_6 7 54 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_7 8 55 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_8 9 56 + #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_9 10 57 + #define CMDQ_EVENT_IMG_TRAW0_DMA_ERROR_INT 11 58 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_0 12 59 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_1 13 60 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_2 14 61 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_3 15 62 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_4 16 63 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_5 17 64 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_6 18 65 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_7 19 66 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_8 20 67 + #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_9 21 68 + #define CMDQ_EVENT_IMG_TRAW1_DMA_ERROR_INT 22 69 + #define CMDQ_EVENT_IMG_ADL_RESERVED 23 70 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_0 24 71 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_1 25 72 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_2 26 73 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_3 27 74 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_4 28 75 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_5 29 76 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_6 30 77 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_7 31 78 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_8 32 79 + #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_9 33 80 + #define CMDQ_EVENT_IMG_DIP_DMA_ERR 34 81 + #define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR 35 82 + #define CMDQ_EVENT_DIP_DUMMY_0 36 83 + #define CMDQ_EVENT_DIP_DUMMY_1 37 84 + #define CMDQ_EVENT_DIP_DUMMY_2 38 85 + #define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 39 86 + #define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 40 87 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_0 41 88 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_1 42 89 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_2 43 90 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_3 44 91 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_4 45 92 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_5 46 93 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_6 47 94 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_7 48 95 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_8 49 96 + #define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_9 50 97 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_0 51 98 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_1 52 99 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_2 53 100 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_3 54 101 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_4 55 102 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_5 56 103 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_6 57 104 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_7 58 105 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_8 59 106 + #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_9 60 107 + #define CMDQ_EVENT_IMG_PQDIP_A_DMA_ERR 61 108 + #define CMDQ_EVENT_WPE0_DUMMY_0 62 109 + #define CMDQ_EVENT_WPE0_DUMMY_1 63 110 + #define CMDQ_EVENT_WPE0_DUMMY_2 64 111 + #define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 65 112 + #define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 66 113 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_0 67 114 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_1 68 115 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_2 69 116 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_3 70 117 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_4 71 118 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_5 72 119 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_6 73 120 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_7 74 121 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_8 75 122 + #define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_9 76 123 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_0 77 124 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_1 78 125 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_2 79 126 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_3 80 127 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_4 81 128 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_5 82 129 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_6 83 130 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_7 84 131 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_8 85 132 + #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_9 86 133 + #define CMDQ_EVENT_IMG_PQDIP_B_DMA_ERR 87 134 + #define CMDQ_EVENT_WPE1_DUMMY_0 88 135 + #define CMDQ_EVENT_WPE1_DUMMY_1 89 136 + #define CMDQ_EVENT_WPE1_DUMMY_2 90 137 + #define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 91 138 + #define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 92 139 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_0 93 140 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_1 94 141 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_2 95 142 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_3 96 143 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_4 97 144 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_5 98 145 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_6 99 146 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_7 100 147 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_8 101 148 + #define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_9 102 149 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_0 103 150 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_1 104 151 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_2 105 152 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_3 106 153 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_4 107 154 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_5 108 155 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_6 109 156 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_7 110 157 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_8 111 158 + #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_9 112 159 + #define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT 113 160 + #define CMDQ_EVENT_WPE2_DUMMY_0 114 161 + #define CMDQ_EVENT_WPE2_DUMMY_1 115 162 + #define CMDQ_EVENT_WPE2_DUMMY_2 116 163 + #define CMDQ_EVENT_IMG_IMGSYS_IPE_DUMMY 117 164 + #define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT_DONE 118 165 + #define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 119 166 + #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE 120 167 + #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE 121 168 + #define CMDQ_EVENT_FDVT1_RESERVED 122 169 + #define CMDQ_EVENT_IMG_ENG_EVENT 123 170 + #define CMDQ_EVENT_CAMSUBA_SW_PASS1_DONE 129 171 + #define CMDQ_EVENT_CAMSUBB_SW_PASS1_DONE 130 172 + #define CMDQ_EVENT_CAMSUBC_SW_PASS1_DONE 131 173 + #define CMDQ_EVENT_GCAMSV_A_1_SW_PASS1_DONE 132 174 + #define CMDQ_EVENT_GCAMSV_A_2_SW_PASS1_DONE 133 175 + #define CMDQ_EVENT_GCAMSV_B_1_SW_PASS1_DONE 134 176 + #define CMDQ_EVENT_GCAMSV_B_2_SW_PASS1_DONE 135 177 + #define CMDQ_EVENT_GCAMSV_C_1_SW_PASS1_DONE 136 178 + #define CMDQ_EVENT_GCAMSV_C_2_SW_PASS1_DONE 137 179 + #define CMDQ_EVENT_GCAMSV_D_1_SW_PASS1_DONE 138 180 + #define CMDQ_EVENT_GCAMSV_D_2_SW_PASS1_DONE 139 181 + #define CMDQ_EVENT_GCAMSV_E_1_SW_PASS1_DONE 140 182 + #define CMDQ_EVENT_GCAMSV_E_2_SW_PASS1_DONE 141 183 + #define CMDQ_EVENT_GCAMSV_F_1_SW_PASS1_DONE 142 184 + #define CMDQ_EVENT_GCAMSV_F_2_SW_PASS1_DONE 143 185 + #define CMDQ_EVENT_GCAMSV_G_1_SW_PASS1_DONE 144 186 + #define CMDQ_EVENT_GCAMSV_G_2_SW_PASS1_DONE 145 187 + #define CMDQ_EVENT_GCAMSV_H_1_SW_PASS1_DONE 146 188 + #define CMDQ_EVENT_GCAMSV_H_2_SW_PASS1_DONE 147 189 + #define CMDQ_EVENT_GCAMSV_I_1_SW_PASS1_DONE 148 190 + #define CMDQ_EVENT_GCAMSV_I_2_SW_PASS1_DONE 149 191 + #define CMDQ_EVENT_GCAMSV_J_1_SW_PASS1_DONE 150 192 + #define CMDQ_EVENT_GCAMSV_J_2_SW_PASS1_DONE 151 193 + #define CMDQ_EVENT_MRAW_0_SW_PASS1_DONE 152 194 + #define CMDQ_EVENT_MRAW_1_SW_PASS1_DONE 153 195 + #define CMDQ_EVENT_MRAW_2_SW_PASS1_DONE 154 196 + #define CMDQ_EVENT_MRAW_3_SW_PASS1_DONE 155 197 + #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 156 198 + #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 157 199 + #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 158 200 + #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 159 201 + #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 160 202 + #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 161 203 + #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 162 204 + #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 163 205 + #define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 164 206 + #define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 165 207 + #define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 166 208 + #define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 167 209 + #define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 168 210 + #define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL 169 211 + #define CMDQ_EVENT_SENINF_CAM14_FIFO_FULL 170 212 + #define CMDQ_EVENT_SENINF_CAM15_FIFO_FULL 171 213 + #define CMDQ_EVENT_SENINF_CAM16_FIFO_FULL 172 214 + #define CMDQ_EVENT_SENINF_CAM17_FIFO_FULL 173 215 + #define CMDQ_EVENT_SENINF_CAM18_FIFO_FULL 174 216 + #define CMDQ_EVENT_SENINF_CAM19_FIFO_FULL 175 217 + #define CMDQ_EVENT_SENINF_CAM20_FIFO_FULL 176 218 + #define CMDQ_EVENT_SENINF_CAM21_FIFO_FULL 177 219 + #define CMDQ_EVENT_SENINF_CAM22_FIFO_FULL 178 220 + #define CMDQ_EVENT_SENINF_CAM23_FIFO_FULL 179 221 + #define CMDQ_EVENT_SENINF_CAM24_FIFO_FULL 180 222 + #define CMDQ_EVENT_SENINF_CAM25_FIFO_FULL 181 223 + #define CMDQ_EVENT_SENINF_CAM26_FIFO_FULL 182 224 + #define CMDQ_EVENT_TG_OVRUN_MRAW0_INT 183 225 + #define CMDQ_EVENT_TG_OVRUN_MRAW1_INT 184 226 + #define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 185 227 + #define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 186 228 + #define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 187 229 + #define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 188 230 + #define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 189 231 + #define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 190 232 + #define CMDQ_EVENT_PDA0_IRQO_EVENT_DONE_D1 191 233 + #define CMDQ_EVENT_PDA1_IRQO_EVENT_DONE_D1 192 234 + #define CMDQ_EVENT_CAM_SUBA_TG_INT1 193 235 + #define CMDQ_EVENT_CAM_SUBA_TG_INT2 194 236 + #define CMDQ_EVENT_CAM_SUBA_TG_INT3 195 237 + #define CMDQ_EVENT_CAM_SUBA_TG_INT4 196 238 + #define CMDQ_EVENT_CAM_SUBB_TG_INT1 197 239 + #define CMDQ_EVENT_CAM_SUBB_TG_INT2 198 240 + #define CMDQ_EVENT_CAM_SUBB_TG_INT3 199 241 + #define CMDQ_EVENT_CAM_SUBB_TG_INT4 200 242 + #define CMDQ_EVENT_CAM_SUBC_TG_INT1 201 243 + #define CMDQ_EVENT_CAM_SUBC_TG_INT2 202 244 + #define CMDQ_EVENT_CAM_SUBC_TG_INT3 203 245 + #define CMDQ_EVENT_CAM_SUBC_TG_INT4 204 246 + #define CMDQ_EVENT_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 205 247 + #define CMDQ_EVENT_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 206 248 + #define CMDQ_EVENT_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 207 249 + #define CMDQ_EVENT_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 208 250 + #define CMDQ_EVENT_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 209 251 + #define CMDQ_EVENT_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 210 252 + #define CMDQ_EVENT_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 211 253 + #define CMDQ_EVENT_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 212 254 + #define CMDQ_EVENT_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 213 255 + #define CMDQ_EVENT_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 214 256 + #define CMDQ_EVENT_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 215 257 + #define CMDQ_EVENT_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 216 258 + #define CMDQ_EVENT_RAW_SEL_SOF_SUBA 217 259 + #define CMDQ_EVENT_RAW_SEL_SOF_SUBB 218 260 + #define CMDQ_EVENT_RAW_SEL_SOF_SUBC 219 261 + #define CMDQ_EVENT_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 220 262 + #define CMDQ_EVENT_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 221 263 + #define CMDQ_EVENT_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 222 264 + #define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256 265 + #define CMDQ_EVENT_VPP0_MDP_FG_SOF 257 266 + #define CMDQ_EVENT_VPP0_STITCH_SOF 258 267 + #define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259 268 + #define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260 269 + #define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261 270 + #define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262 271 + #define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263 272 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264 273 + #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265 274 + #define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266 275 + #define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267 276 + #define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269 277 + #define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270 278 + #define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271 279 + #define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272 280 + #define CMDQ_EVENT_VPP0_DISP_RDMA_SOF 273 281 + #define CMDQ_EVENT_VPP0_DISP_WDMA_SOF 274 282 + #define CMDQ_EVENT_VPP0_MDP_HMS_SOF 275 283 + #define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288 284 + #define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289 285 + #define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290 286 + #define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291 287 + #define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292 288 + #define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293 289 + #define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294 290 + #define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295 291 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296 292 + #define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297 293 + #define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298 294 + #define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299 295 + #define CMDQ_EVENT_VPP0_DISP_RDMA_FRAME_DONE 305 296 + #define CMDQ_EVENT_VPP0_DISP_WDMA_FRAME_DONE 306 297 + #define CMDQ_EVENT_VPP0_MDP_HMS_FRAME_DONE 307 298 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_0 320 299 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_1 321 300 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_2 322 301 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_3 323 302 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_4 324 303 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_5 325 304 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_6 326 305 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_7 327 306 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_8 328 307 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_9 329 308 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_10 330 309 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_11 331 310 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_12 332 311 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_13 333 312 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_14 334 313 + #define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_15 335 314 + #define CMDQ_EVENT_VPP0_DISP_RDMA_0_UNDERRUN 336 315 + #define CMDQ_EVENT_VPP0_DISP_RDMA_1_UNDERRUN 337 316 + #define CMDQ_EVENT_VPP0_U_MERGE4_UNDERRUN 338 317 + #define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_0_OVERFLOW 339 318 + #define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_1_OVERFLOW 340 319 + #define CMDQ_EVENT_VPP0_DSI_0_UNDERRUN 341 320 + #define CMDQ_EVENT_VPP0_DSI_1_UNDERRUN 342 321 + #define CMDQ_EVENT_VPP0_DP_INTF_0 343 322 + #define CMDQ_EVENT_VPP0_DP_INTF_1 344 323 + #define CMDQ_EVENT_VPP0_DPI_0 345 324 + #define CMDQ_EVENT_VPP0_DPI_1 346 325 + #define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352 326 + #define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID_EVENT 353 327 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354 328 + #define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355 329 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_0 356 330 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_1 357 331 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_2 358 332 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_3 359 333 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_4 360 334 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_5 361 335 + #define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_6 362 336 + #define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_VALID_EVENT 363 337 + #define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_TARGET_LINE_EVENT 364 338 + #define CMDQ_EVENT_VPP0_DISP_WDMA_SW_RST_DONE 365 339 + #define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_VALID_EVENT 366 340 + #define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_TARGET_LINE_EVENT 367 341 + #define CMDQ_EVENT_VPP1_HDMI_META_SOF 384 342 + #define CMDQ_EVENT_VPP1_DGI_SOF 385 343 + #define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386 344 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387 345 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388 346 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389 347 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390 348 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391 349 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392 350 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393 351 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394 352 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395 353 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396 354 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397 355 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398 356 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399 357 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400 358 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401 359 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402 360 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_SOF 403 361 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_SOF 404 362 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_SOF 405 363 + #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406 364 + #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407 365 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408 366 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409 367 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410 368 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411 369 + #define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412 370 + #define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413 371 + #define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414 372 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415 373 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416 374 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417 375 + #define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418 376 + #define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419 377 + #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420 378 + #define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421 379 + #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422 380 + #define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423 381 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424 382 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425 383 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426 384 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427 385 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428 386 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429 387 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430 388 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431 389 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432 390 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433 391 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 434 392 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 435 393 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 436 394 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_FRAME_DONE 437 395 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_FRAME_DONE 438 396 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_FRAME_DONE 439 397 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_FRAME_DONE 440 398 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_FRAME_DONE 441 399 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_FRAME_DONE 442 400 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_FRAME_DONE 443 401 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_FRAME_DONE 444 402 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_FRAME_DONE 445 403 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_FRAME_DONE 446 404 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_FRAME_DONE 447 405 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_FRAME_DONE 448 406 + #define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_FRAME_DONE 449 407 + #define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_FRAME_DONE 450 408 + #define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_FRAME_DONE 451 409 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_FRAME_DONE 452 410 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_0 456 411 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_1 457 412 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_2 458 413 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_3 459 414 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_4 460 415 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_5 461 416 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_6 462 417 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_7 463 418 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_8 464 419 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_9 465 420 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_10 466 421 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_11 467 422 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_12 468 423 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_13 469 424 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_14 470 425 + #define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_15 471 426 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_0 472 427 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_1 473 428 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_2 474 429 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_3 475 430 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_4 476 431 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_5 477 432 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_6 478 433 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_7 479 434 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_8 480 435 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_9 481 436 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_10 482 437 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_11 483 438 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_12 484 439 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_13 485 440 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_14 486 441 + #define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_15 487 442 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_0 488 443 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_1 489 444 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_2 490 445 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_3 491 446 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_4 492 447 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_5 493 448 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_6 494 449 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_7 495 450 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_8 496 451 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_9 497 452 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_10 498 453 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_11 499 454 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_12 500 455 + #define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_13 501 456 + #define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_GCE_EVENT 502 457 + #define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_GCE_EVENT 503 458 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_GCE_EVENT 504 459 + #define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI_GCE_EVENT 505 460 + #define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI_GCE_EVENT 506 461 + #define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE_GCE_EVENT 507 462 + #define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE_GCE_EVENT 508 463 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE_GCE_EVENT 509 464 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_0 510 465 + #define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_1 511 466 + #define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512 467 + #define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513 468 + #define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514 469 + #define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515 470 + #define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516 471 + #define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517 472 + #define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518 473 + #define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519 474 + #define CMDQ_EVENT_VDO0_DSI0_SOF 520 475 + #define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521 476 + #define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522 477 + #define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523 478 + #define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524 479 + #define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525 480 + #define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526 481 + #define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527 482 + #define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528 483 + #define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529 484 + #define CMDQ_EVENT_VDO0_DSI1_SOF 530 485 + #define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531 486 + #define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532 487 + #define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533 488 + #define CMDQ_EVENT_VDO0_DISP_DPI0_SOF 534 489 + #define CMDQ_EVENT_VDO0_DISP_DPI1_SOF 535 490 + #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_SOF 536 491 + #define CMDQ_EVENT_VDO0_MDP_WROT0_SOF 537 492 + #define CMDQ_EVENT_VDO0_DISP_RSZ0_SOF 538 493 + #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 539 494 + #define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 540 495 + #define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 541 496 + #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 542 497 + #define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 543 498 + #define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 544 499 + #define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 545 500 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_DONE 546 501 + #define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 547 502 + #define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 548 503 + #define CMDQ_EVENT_VDO0_DISP_COLOR0_O_FRAME_DONE 549 504 + #define CMDQ_EVENT_VDO0_DISP_CCORR0_O_FRAME_DONE 550 505 + #define CMDQ_EVENT_VDO0_DISP_AAL0_O_FRAME_DONE 551 506 + #define CMDQ_EVENT_VDO0_DISP_GAMMA0_O_FRAME_DONE 552 507 + #define CMDQ_EVENT_VDO0_DISP_DITHER0_O_FRAME_DONE 553 508 + #define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 554 509 + #define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_0 555 510 + #define CMDQ_EVENT_VDO0_DISP_OVL1_O_FRAME_DONE 556 511 + #define CMDQ_EVENT_VDO0_DISP_WDMA1_O_FRAME_DONE 557 512 + #define CMDQ_EVENT_VDO0_DISP_RDMA1_O_FRAME_DONE 558 513 + #define CMDQ_EVENT_VDO0_DISP_COLOR1_O_FRAME_DONE 559 514 + #define CMDQ_EVENT_VDO0_DISP_CCORR1_O_FRAME_DONE 560 515 + #define CMDQ_EVENT_VDO0_DISP_AAL1_O_FRAME_DONE 561 516 + #define CMDQ_EVENT_VDO0_DISP_GAMMA1_O_FRAME_DONE 562 517 + #define CMDQ_EVENT_VDO0_DISP_DITHER1_O_FRAME_DONE 563 518 + #define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 564 519 + #define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_1 565 520 + #define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 567 521 + #define CMDQ_EVENT_VDO0_DISP_DPI0_O_FRAME_DONE 568 522 + #define CMDQ_EVENT_VDO0_DISP_DPI1_O_FRAME_DONE 569 523 + #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_DONE 570 524 + #define CMDQ_EVENT_VDO0_MDP_WROT0_O_FRAME_DONE 571 525 + #define CMDQ_EVENT_VDO0_DISP_RSZ0_O_FRAME_DONE 572 526 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 574 527 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 575 528 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 576 529 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 577 530 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 578 531 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 579 532 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 580 533 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 581 534 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 582 535 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 583 536 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 584 537 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 585 538 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 586 539 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 587 540 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 588 541 + #define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 589 542 + #define CMDQ_EVENT_VDO0_DISP_RDMA_0_UNDERRUN 590 543 + #define CMDQ_EVENT_VDO0_DISP_RDMA_1_UNDERRUN 591 544 + #define CMDQ_EVENT_VDO0_U_MERGE4_UNDERRUN 592 545 + #define CMDQ_EVENT_VDO0_DSI_0_UNDERRUN 595 546 + #define CMDQ_EVENT_VDO0_DSI_1_UNDERRUN 596 547 + #define CMDQ_EVENT_VDO0_DP_INTF_0 597 548 + #define CMDQ_EVENT_VDO0_DP_INTF_1 598 549 + #define CMDQ_EVENT_VDO0_DPI_0 599 550 + #define CMDQ_EVENT_VDO0_DPI_1 600 551 + #define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG_EVENT 606 552 + #define CMDQ_EVENT_VDO0_DSI0_O_DSI_IRQ_EVENT_MM 607 553 + #define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 608 554 + #define CMDQ_EVENT_VDO0_DSI0_O_DSI_DONE_EVENT_MM 609 555 + #define CMDQ_EVENT_VDO0_DSI0_O_DSI_VACTL_EVENT_MM 610 556 + #define CMDQ_EVENT_VDO0_DSI1_O_DSI_IRQ_EVENT_MM 611 557 + #define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 612 558 + #define CMDQ_EVENT_VDO0_DSI1_O_DSI_DONE_EVENT_MM 613 559 + #define CMDQ_EVENT_VDO0_DSI1_O_DSI_VACTL_EVENT_MM 614 560 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_START_EVENT_MM 615 561 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_END_EVENT_MM 616 562 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_START_EVENT_MM 617 563 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_END_EVENT_MM 618 564 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_VACT_TARGET_LINE_EVENT_MM 619 565 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_SAFE_BLANK_EVENT_MM 620 566 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_LINE_EVENT_MM 621 567 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_TRIGGER_LOOP_CLEAR_EVENT_MM 622 568 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_0_EVENT_MM 623 569 + #define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_1_EVENT_MM 624 570 + #define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_RESET_DONE_PULSE 625 571 + #define CMDQ_EVENT_VDO0_VPP_MERGE0_O_VPP_MERGE_EVENT 626 572 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_RESET_DONE_PULSE 627 573 + #define CMDQ_EVENT_VDO0_DISP_RDMA0_O_DISP_RDMA_TARGET_LINE_EVENT 628 574 + #define CMDQ_EVENT_VDO0_DISP_WDMA0_O_WDMA_TARGET_LINE_EVENT 629 575 + #define CMDQ_EVENT_VDO0_DISP_WDMA0_O_SW_RST_DONE 630 576 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_0 631 577 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_1 632 578 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_2 633 579 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_3 634 580 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_4 635 581 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_5 636 582 + #define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_6 637 583 + #define CMDQ_EVENT_VDO0_MDP_WROT0_O_SW_RST_DONE 638 584 + #define CMDQ_EVENT_VDO0_RESERVED 639 585 + #define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640 586 + #define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641 587 + #define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642 588 + #define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643 589 + #define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644 590 + #define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645 591 + #define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646 592 + #define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647 593 + #define CMDQ_EVENT_VDO1_DISP_PADDING0_SOF 648 594 + #define CMDQ_EVENT_VDO1_DISP_PADDING1_SOF 649 595 + #define CMDQ_EVENT_VDO1_DISP_PADDING2_SOF 650 596 + #define CMDQ_EVENT_VDO1_DISP_PADDING3_SOF 651 597 + #define CMDQ_EVENT_VDO1_DISP_PADDING4_SOF 652 598 + #define CMDQ_EVENT_VDO1_DISP_PADDING5_SOF 653 599 + #define CMDQ_EVENT_VDO1_DISP_PADDING6_SOF 654 600 + #define CMDQ_EVENT_VDO1_DISP_PADDING7_SOF 655 601 + #define CMDQ_EVENT_VDO1_DISP_RSZ0_SOF 656 602 + #define CMDQ_EVENT_VDO1_DISP_RSZ1_SOF 657 603 + #define CMDQ_EVENT_VDO1_DISP_RSZ2_SOF 658 604 + #define CMDQ_EVENT_VDO1_DISP_RSZ3_SOF 659 605 + #define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 660 606 + #define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 661 607 + #define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 662 608 + #define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 663 609 + #define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 664 610 + #define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 665 611 + #define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 666 612 + #define CMDQ_EVENT_VDO0_DSC_DL_ASYNC_SOF 667 613 + #define CMDQ_EVENT_VDO0_MERGE_DL_ASYNC_SOF 668 614 + #define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 669 615 + #define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 670 616 + #define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 671 617 + #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 672 618 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 673 619 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 674 620 + #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 675 621 + #define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 676 622 + #define CMDQ_EVENT_VDO1_DPI0_EXT_SOF 677 623 + #define CMDQ_EVENT_VDO1_DPI1_EXT_SOF 678 624 + #define CMDQ_EVENT_VDO1_DP_INTF_EXT_EXT_SOF 679 625 + #define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 680 626 + #define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 681 627 + #define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 682 628 + #define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 683 629 + #define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 684 630 + #define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 685 631 + #define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 686 632 + #define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 687 633 + #define CMDQ_EVENT_VDO1_DISP_PADDING0_FRAME_DONE 688 634 + #define CMDQ_EVENT_VDO1_DISP_PADDING1_FRAME_DONE 689 635 + #define CMDQ_EVENT_VDO1_DISP_PADDING2_FRAME_DONE 690 636 + #define CMDQ_EVENT_VDO1_DISP_PADDING3_FRAME_DONE 691 637 + #define CMDQ_EVENT_VDO1_DISP_PADDING4_FRAME_DONE 692 638 + #define CMDQ_EVENT_VDO1_DISP_PADDING5_FRAME_DONE 693 639 + #define CMDQ_EVENT_VDO1_DISP_PADDING6_FRAME_DONE 694 640 + #define CMDQ_EVENT_VDO1_DISP_PADDING7_FRAME_DONE 695 641 + #define CMDQ_EVENT_VDO1_DISP_RSZ0_FRAME_DONE 696 642 + #define CMDQ_EVENT_VDO1_DISP_RSZ1_FRAME_DONE 697 643 + #define CMDQ_EVENT_VDO1_DISP_RSZ2_FRAME_DONE 698 644 + #define CMDQ_EVENT_VDO1_DISP_RSZ3_FRAME_DONE 699 645 + #define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 700 646 + #define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 701 647 + #define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 702 648 + #define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 703 649 + #define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 704 650 + #define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 705 651 + #define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 706 652 + #define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 707 653 + #define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 708 654 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 709 655 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 710 656 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 711 657 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 712 658 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 713 659 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 714 660 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 715 661 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 716 662 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 717 663 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 718 664 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 719 665 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 720 666 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 721 667 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 722 668 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 723 669 + #define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 724 670 + #define CMDQ_EVENT_VDO1_DISP_RDMA_0_UNDERRUN 725 671 + #define CMDQ_EVENT_VDO1_DISP_RDMA_1_UNDERRUN 726 672 + #define CMDQ_EVENT_VDO1_U_MERGE4_UNDERRUN 727 673 + #define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_0_OVERFLOW 728 674 + #define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_1_OVERFLOW 729 675 + #define CMDQ_EVENT_VDO1_DSI_0_UNDERRUN 730 676 + #define CMDQ_EVENT_VDO1_DSI_1_UNDERRUN 731 677 + #define CMDQ_EVENT_VDO1_DP_INTF_0 732 678 + #define CMDQ_EVENT_VDO1_DP_INTF_1 733 679 + #define CMDQ_EVENT_VDO1_DPI_0 734 680 + #define CMDQ_EVENT_VDO1_DPI_1 735 681 + #define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 741 682 + #define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 742 683 + #define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 743 684 + #define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 744 685 + #define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 745 686 + #define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 746 687 + #define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 747 688 + #define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 748 689 + #define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 749 690 + #define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 750 691 + #define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 751 692 + #define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 752 693 + #define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 753 694 + #define CMDQ_EVENT_VDO1_VPP_MERGE0_EVENT 754 695 + #define CMDQ_EVENT_VDO1_VPP_MERGE1_EVENT 755 696 + #define CMDQ_EVENT_VDO1_VPP_MERGE2_EVENT 756 697 + #define CMDQ_EVENT_VDO1_VPP_MERGE3_EVENT 757 698 + #define CMDQ_EVENT_VDO1_VPP_MERGE4_EVENT 758 699 + #define CMDQ_EVENT_VDO1_HDMITX_EVENT 759 700 + #define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 760 701 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 761 702 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 762 703 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 763 704 + #define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 764 705 + #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 765 706 + #define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 766 707 + #define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_1_EVENT_MM 767 708 + #define CMDQ_EVENT_HANDSHAKE_0 768 709 + #define CMDQ_EVENT_HANDSHAKE_1 769 710 + #define CMDQ_EVENT_HANDSHAKE_2 770 711 + #define CMDQ_EVENT_HANDSHAKE_3 771 712 + #define CMDQ_EVENT_HANDSHAKE_4 772 713 + #define CMDQ_EVENT_HANDSHAKE_5 773 714 + #define CMDQ_EVENT_HANDSHAKE_6 774 715 + #define CMDQ_EVENT_HANDSHAKE_7 775 716 + #define CMDQ_EVENT_HANDSHAKE_8 776 717 + #define CMDQ_EVENT_HANDSHAKE_9 777 718 + #define CMDQ_EVENT_HANDSHAKE_10 778 719 + #define CMDQ_EVENT_HANDSHAKE_11 779 720 + #define CMDQ_EVENT_HANDSHAKE_12 780 721 + #define CMDQ_EVENT_HANDSHAKE_13 781 722 + #define CMDQ_EVENT_HANDSHAKE_14 782 723 + #define CMDQ_EVENT_HANDSHAKE_15 783 724 + #define CMDQ_EVENT_VDEC_SOC_EVENT_0 800 725 + #define CMDQ_EVENT_VDEC_SOC_EVENT_1 801 726 + #define CMDQ_EVENT_VDEC_SOC_EVENT_2 802 727 + #define CMDQ_EVENT_VDEC_SOC_EVENT_3 803 728 + #define CMDQ_EVENT_VDEC_SOC_EVENT_4 804 729 + #define CMDQ_EVENT_VDEC_SOC_EVENT_5 805 730 + #define CMDQ_EVENT_VDEC_SOC_EVENT_6 806 731 + #define CMDQ_EVENT_VDEC_SOC_EVENT_7 807 732 + #define CMDQ_EVENT_VDEC_SOC_EVENT_8 808 733 + #define CMDQ_EVENT_VDEC_SOC_EVENT_9 809 734 + #define CMDQ_EVENT_VDEC_SOC_EVENT_10 810 735 + #define CMDQ_EVENT_VDEC_SOC_EVENT_11 811 736 + #define CMDQ_EVENT_VDEC_SOC_EVENT_12 812 737 + #define CMDQ_EVENT_VDEC_SOC_EVENT_13 813 738 + #define CMDQ_EVENT_VDEC_SOC_EVENT_14 814 739 + #define CMDQ_EVENT_VDEC_SOC_EVENT_15 815 740 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_0 832 741 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_1 833 742 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_2 834 743 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_3 835 744 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_4 836 745 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_5 837 746 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_6 838 747 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_7 839 748 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_8 840 749 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_9 841 750 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_10 842 751 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_11 843 752 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_12 844 753 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_13 845 754 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_14 846 755 + #define CMDQ_EVENT_VDEC_CORE0_EVENT_15 847 756 + #define CMDQ_EVENT_VENC_TOP_VENC_FRAME_DONE 865 757 + #define CMDQ_EVENT_VENC_TOP_VENC_PAUSE_DONE 866 758 + #define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 867 759 + #define CMDQ_EVENT_VENC_TOP_VENC_MB_DONE 868 760 + #define CMDQ_EVENT_VENC_TOP_VENC_128BYTE_DONE 869 761 + #define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 870 762 + #define CMDQ_EVENT_VENC_TOP_VENC_SLICE_DONE 871 763 + #define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 872 764 + #define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 874 765 + #define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 875 766 + #define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 876 767 + #define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 877 768 + #define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 878 769 + #define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 882 770 + #define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 883 771 + #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_2 896 772 + #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_3 897 773 + #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_4 898 774 + #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_5 899 775 + #define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_6 900 776 + #define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_0_EVENT_MM 928 777 + #define CMDQ_EVENT_VDO1_DPI0_TRIGGER_LOOP_CLEAR_EVENT_MM 929 778 + #define CMDQ_EVENT_VDO1_DPI0_LAST_LINE_EVENT_MM 930 779 + #define CMDQ_EVENT_VDO1_DPI0_LAST_SAFE_BLANK_EVENT_MM 931 780 + #define CMDQ_EVENT_VDO1_DPI0_VSYNC_START_EVENT_MM 932 781 + #define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_1_EVENT_MM 933 782 + #define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_0_EVENT_MM 934 783 + #define CMDQ_EVENT_VDO1_DPI1_TRIGGER_LOOP_CLEAR_EVENT_MM 935 784 + #define CMDQ_EVENT_VDO1_DPI1_LAST_LINE_EVENT_MM 936 785 + #define CMDQ_EVENT_VDO1_DPI1_LAST_SAFE_BLANK_EVENT_MM 937 786 + #define CMDQ_EVENT_VDO1_DPI1_VSYNC_START_EVENT_MM 938 787 + #define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_1_EVENT_MM 939 788 + #define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_0_EVENT_MM 940 789 + #define CMDQ_EVENT_VDO1_DP_INTF_TRIGGER_LOOP_CLEAR_EVENT_MM 941 790 + #define CMDQ_EVENT_VDO1_DP_INTF_LAST_LINE_EVENT_MM 942 791 + #define CMDQ_EVENT_VDO1_DP_INTF_LAST_SAFE_BLANK_EVENT_MM 943 792 + #define CMDQ_EVENT_VBLANK_FALLING 946 793 + #define CMDQ_EVENT_VSC_FINISH 947 794 + #define CMDQ_EVENT_TPR_0 962 795 + #define CMDQ_EVENT_TPR_1 963 796 + #define CMDQ_EVENT_TPR_2 964 797 + #define CMDQ_EVENT_TPR_3 965 798 + #define CMDQ_EVENT_TPR_4 966 799 + #define CMDQ_EVENT_TPR_5 967 800 + #define CMDQ_EVENT_TPR_6 968 801 + #define CMDQ_EVENT_TPR_7 969 802 + #define CMDQ_EVENT_TPR_8 970 803 + #define CMDQ_EVENT_TPR_9 971 804 + #define CMDQ_EVENT_TPR_10 972 805 + #define CMDQ_EVENT_TPR_11 973 806 + #define CMDQ_EVENT_TPR_12 974 807 + #define CMDQ_EVENT_TPR_13 975 808 + #define CMDQ_EVENT_TPR_14 976 809 + #define CMDQ_EVENT_TPR_15 977 810 + #define CMDQ_EVENT_TPR_16 978 811 + #define CMDQ_EVENT_TPR_17 979 812 + #define CMDQ_EVENT_TPR_18 980 813 + #define CMDQ_EVENT_TPR_19 981 814 + #define CMDQ_EVENT_TPR_20 982 815 + #define CMDQ_EVENT_TPR_21 983 816 + #define CMDQ_EVENT_TPR_22 984 817 + #define CMDQ_EVENT_TPR_23 985 818 + #define CMDQ_EVENT_TPR_24 986 819 + #define CMDQ_EVENT_TPR_25 987 820 + #define CMDQ_EVENT_TPR_26 988 821 + #define CMDQ_EVENT_TPR_27 989 822 + #define CMDQ_EVENT_TPR_28 990 823 + #define CMDQ_EVENT_TPR_29 991 824 + #define CMDQ_EVENT_TPR_30 992 825 + #define CMDQ_EVENT_TPR_31 993 826 + #define CMDQ_EVENT_TPR_TIMEOUT_0 994 827 + #define CMDQ_EVENT_TPR_TIMEOUT_1 995 828 + #define CMDQ_EVENT_TPR_TIMEOUT_2 996 829 + #define CMDQ_EVENT_TPR_TIMEOUT_3 997 830 + #define CMDQ_EVENT_TPR_TIMEOUT_4 998 831 + #define CMDQ_EVENT_TPR_TIMEOUT_5 999 832 + #define CMDQ_EVENT_TPR_TIMEOUT_6 1000 833 + #define CMDQ_EVENT_TPR_TIMEOUT_7 1001 834 + #define CMDQ_EVENT_TPR_TIMEOUT_8 1002 835 + #define CMDQ_EVENT_TPR_TIMEOUT_9 1003 836 + #define CMDQ_EVENT_TPR_TIMEOUT_10 1004 837 + #define CMDQ_EVENT_TPR_TIMEOUT_11 1005 838 + #define CMDQ_EVENT_TPR_TIMEOUT_12 1006 839 + #define CMDQ_EVENT_TPR_TIMEOUT_13 1007 840 + #define CMDQ_EVENT_TPR_TIMEOUT_14 1008 841 + #define CMDQ_EVENT_TPR_TIMEOUT_15 1009 842 + #define CMDQ_EVENT_OUTPIN_0 1018 843 + #define CMDQ_EVENT_OUTPIN_1 1019 844 + 845 + #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 124 846 + #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 125 847 + #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 126 848 + #define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 127 849 + #define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 128 850 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_1 223 851 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_2 224 852 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_3 225 853 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_4 226 854 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_5 227 855 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_6 228 856 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_7 229 857 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_8 230 858 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_9 231 859 + #define CMDQ_SYNC_TOKEN_CAMSYS_POOL_10 232 860 + #define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 233 861 + #define CMDQ_SYNC_TOKEN_IMGSYS_DIP 234 862 + #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 235 863 + #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 236 864 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 237 865 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 238 866 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 239 867 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 240 868 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 241 869 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 242 870 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 243 871 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 244 872 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 245 873 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 246 874 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 247 875 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 248 876 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 249 877 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 250 878 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 251 879 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 252 880 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 253 881 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 254 882 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 255 883 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 276 884 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 277 885 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 278 886 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 279 887 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 280 888 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 281 889 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 282 890 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 283 891 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 284 892 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 285 893 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 286 894 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 287 895 + #define CMDQ_SYNC_TOKEN_IPESYS_ME 300 896 + #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 301 897 + #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 302 898 + #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 303 899 + #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 304 900 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 308 901 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 309 902 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 310 903 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 311 904 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 312 905 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 313 906 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 314 907 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 315 908 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 316 909 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 370 910 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 371 911 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 372 912 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 373 913 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 374 914 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 375 915 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 376 916 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 377 917 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 378 918 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 379 919 + #define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 380 920 + #define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 381 921 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 790 922 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 791 923 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 792 924 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 793 925 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 794 926 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 795 927 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 796 928 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 797 929 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 798 930 + #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 799 931 + #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_WAIT 816 932 + #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_SET 817 933 + #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 818 934 + #define CMDQ_SYNC_TOKEN_PREBUILT_MML_WAIT 819 935 + #define CMDQ_SYNC_TOKEN_PREBUILT_MML_SET 820 936 + #define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 821 937 + #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_WAIT 822 938 + #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_SET 823 939 + #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 824 940 + #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_WAIT 825 941 + #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_SET 826 942 + #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 827 943 + #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 848 944 + #define CMDQ_SYNC_TOKEN_STREAM_EOF 849 945 + #define CMDQ_SYNC_TOKEN_ESD_EOF 850 946 + #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 851 947 + #define CMDQ_SYNC_TOKEN_CABC_EOF 852 948 + #define CMDQ_SYNC_TOKEN_VENC_INPUT_READY 853 949 + #define CMDQ_SYNC_TOKEN_VENC_EOF 854 950 + #define CMDQ_SYNC_TOKEN_SECURE_THR_EOF 855 951 + #define CMDQ_SYNC_TOKEN_USER_0 856 952 + #define CMDQ_SYNC_TOKEN_USER_1 857 953 + #define CMDQ_SYNC_TOKEN_POLL_MONITOR 858 954 + #define CMDQ_TOKEN_TPR_LOCK 859 955 + #define CMDQ_SYNC_TOKEN_MSS 860 956 + #define CMDQ_SYNC_TOKEN_MSF 861 957 + #define CMDQ_SYNC_TOKEN_GPR_SET_0 884 958 + #define CMDQ_SYNC_TOKEN_GPR_SET_1 885 959 + #define CMDQ_SYNC_TOKEN_GPR_SET_2 886 960 + #define CMDQ_SYNC_TOKEN_GPR_SET_3 887 961 + #define CMDQ_SYNC_TOKEN_GPR_SET_4 888 962 + #define CMDQ_SYNC_RESOURCE_WROT0 889 963 + #define CMDQ_SYNC_RESOURCE_WROT1 890 964 + #define CMDQ_SYNC_TOKEN_DISP_VA_START 1012 965 + #define CMDQ_SYNC_TOKEN_DISP_VA_END 1013 966 + 967 + #endif