Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amdgpu: Update setting EEPROM table version

Use helper function instead of umc callback to set
EEPROM table version.

Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Candice Li and committed by
Alex Deucher
f26c4e3f 689898ca

+17 -13
+17 -5
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
··· 404 404 return res; 405 405 } 406 406 407 + static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) 408 + { 409 + struct amdgpu_device *adev = to_amdgpu_device(control); 410 + struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 411 + 412 + switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 413 + case IP_VERSION(8, 10, 0): 414 + case IP_VERSION(12, 0, 0): 415 + hdr->version = RAS_TABLE_VER_V2_1; 416 + return; 417 + default: 418 + hdr->version = RAS_TABLE_VER_V1; 419 + return; 420 + } 421 + } 422 + 407 423 /** 408 424 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 409 425 * @control: pointer to control structure ··· 439 423 mutex_lock(&control->ras_tbl_mutex); 440 424 441 425 hdr->header = RAS_TABLE_HDR_VAL; 442 - if (adev->umc.ras && 443 - adev->umc.ras->set_eeprom_table_version) 444 - adev->umc.ras->set_eeprom_table_version(hdr); 445 - else 446 - hdr->version = RAS_TABLE_VER_V1; 426 + amdgpu_ras_set_eeprom_table_version(control); 447 427 448 428 if (hdr->version == RAS_TABLE_VER_V2_1) { 449 429 hdr->first_rec_offset = RAS_RECORD_START_V2_1;
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
··· 66 66 void *ras_error_status); 67 67 bool (*check_ecc_err_status)(struct amdgpu_device *adev, 68 68 enum amdgpu_mca_error_type type, void *ras_error_status); 69 - /* support different eeprom table version for different asic */ 70 - void (*set_eeprom_table_version)(struct amdgpu_ras_eeprom_table_header *hdr); 71 69 }; 72 70 73 71 struct amdgpu_umc_funcs {
-6
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c
··· 442 442 umc_v8_10_ecc_info_query_error_address, ras_error_status); 443 443 } 444 444 445 - static void umc_v8_10_set_eeprom_table_version(struct amdgpu_ras_eeprom_table_header *hdr) 446 - { 447 - hdr->version = RAS_TABLE_VER_V2_1; 448 - } 449 - 450 445 const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = { 451 446 .query_ras_error_count = umc_v8_10_query_ras_error_count, 452 447 .query_ras_error_address = umc_v8_10_query_ras_error_address, ··· 455 460 .query_ras_poison_mode = umc_v8_10_query_ras_poison_mode, 456 461 .ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count, 457 462 .ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address, 458 - .set_eeprom_table_version = umc_v8_10_set_eeprom_table_version, 459 463 };