MIPS: BMIPS: Make whitespacely correct.

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

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MIPS: BMIPS: Make whitespacely correct.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Ralf Baechle 10 years ago f241265f 21b30c00

+133 -133

1 changed file

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arch

mips

kernel

bmips_5xxx_init.S

+133 -133

arch/mips/kernel/bmips_5xxx_init.S

··· 27 27 28 28 #define cacheop(kva, size, linesize, op) \ 29 29 .set noreorder ; \ 30 - addu t1, kva, size ; \ 31 - subu t2, linesize, 1 ; \ 32 - not t2 ; \ 33 - and t0, kva, t2 ; \ 34 - addiu t1, t1, -1 ; \ 35 - and t1, t2 ; \ 36 - 9: cache op, 0(t0) ; \ 37 - bne t0, t1, 9b ; \ 38 - addu t0, linesize ; \ 39 - .set reorder ; 30 + addu t1, kva, size ; \ 31 + subu t2, linesize, 1 ; \ 32 + not t2 ; \ 33 + and t0, kva, t2 ; \ 34 + addiu t1, t1, -1 ; \ 35 + and t1, t2 ; \ 36 + 9: cache op, 0(t0) ; \ 37 + bne t0, t1, 9b ; \ 38 + addu t0, linesize ; \ 39 + .set reorder ; 40 40 41 41 42 42 ··· 59 59 #define CP0_BRCM_MODE $22, 1 60 60 #define CP0_CONFIG_K0_MASK 7 61 61 62 - #define CP0_ICACHE_TAG_LO $28 63 - #define CP0_ICACHE_DATA_LO $28, 1 64 - #define CP0_DCACHE_TAG_LO $28, 2 62 + #define CP0_ICACHE_TAG_LO $28 63 + #define CP0_ICACHE_DATA_LO $28, 1 64 + #define CP0_DCACHE_TAG_LO $28, 2 65 65 #define CP0_D_SEC_CACHE_DATA_LO $28, 3 66 - #define CP0_ICACHE_TAG_HI $29 67 - #define CP0_ICACHE_DATA_HI $29, 1 68 - #define CP0_DCACHE_TAG_HI $29, 2 66 + #define CP0_ICACHE_TAG_HI $29 67 + #define CP0_ICACHE_DATA_HI $29, 1 68 + #define CP0_DCACHE_TAG_HI $29, 2 69 69 70 70 #define CP0_BRCM_MODE_Luc_MASK (1 << 11) 71 71 #define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20) ··· 78 78 #define CP0_BRCM_MODE_BrHIST_SHIFT 20 79 79 80 80 /* ZSC L2 Cache Register Access Register Definitions */ 81 - #define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24 81 + #define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24 82 82 83 83 #define BRCM_ZSC_CONFIG_REG 0 << 3 84 84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3 ··· 117 117 */ 118 118 119 119 LEAF(size_i_cache) 120 - .set noreorder 120 + .set noreorder 121 121 122 - mfc0 a0, CP0_CONFIG, 1 122 + mfc0 a0, CP0_CONFIG, 1 123 123 move t0, a0 124 124 125 125 /* ··· 131 131 * vi) 0x5 - 0x7: Reserved. 132 132 */ 133 133 134 - srl a0, a0, IS_SHIFT 135 - and a0, a0, IS_MASK 134 + srl a0, a0, IS_SHIFT 135 + and a0, a0, IS_MASK 136 136 137 137 /* sets per way = (64<<IS) */ 138 138 139 139 li v0, 0x40 140 - sllv v0, v0, a0 140 + sllv v0, v0, a0 141 141 142 142 /* 143 143 * Determine line size ··· 186 186 */ 187 187 188 188 multu v0, a0 /*multu is interlocked, so no need to insert nops */ 189 - mflo v0 189 + mflo v0 190 190 b 1f 191 191 nop 192 192 193 193 no_i_cache: 194 - move v0, zero 194 + move v0, zero 195 195 move v1, zero 196 196 1: 197 - jr ra 197 + jr ra 198 198 nop 199 - .set reorder 199 + .set reorder 200 200 201 201 END(size_i_cache) 202 202 ··· 210 210 */ 211 211 212 212 LEAF(size_d_cache) 213 - .set noreorder 213 + .set noreorder 214 214 215 - mfc0 a0, CP0_CONFIG, 1 215 + mfc0 a0, CP0_CONFIG, 1 216 216 move t0, a0 217 217 218 218 /* ··· 224 224 * vi) 0x5 - 0x7: Reserved. 225 225 */ 226 226 227 - srl a0, a0, DS_SHIFT 228 - and a0, a0, DS_MASK 227 + srl a0, a0, DS_SHIFT 228 + and a0, a0, DS_MASK 229 229 230 230 /* sets per way = (64<<IS) */ 231 231 232 232 li v0, 0x40 233 - sllv v0, v0, a0 233 + sllv v0, v0, a0 234 234 235 235 /* 236 236 * Determine line size ··· 277 277 */ 278 278 279 279 multu v0, a0 /*multu is interlocked, so no need to insert nops */ 280 - mflo v0 280 + mflo v0 281 281 282 282 b 1f 283 283 nop 284 284 285 285 no_d_cache: 286 - move v0, zero 286 + move v0, zero 287 287 move v1, zero 288 288 1: 289 289 jr ra 290 290 nop 291 - .set reorder 291 + .set reorder 292 292 293 293 END(size_d_cache) 294 294 ··· 298 298 * Arguments: None 299 299 * Returns: None 300 300 * Description: Enable I and D caches, initialize I and D-caches, also set 301 - * hardware delay for d-cache (TP0). 301 + * hardware delay for d-cache (TP0). 302 302 * Trashes: t0 303 303 * 304 304 */ 305 305 .global enable_ID 306 306 .ent enable_ID 307 - .set noreorder 307 + .set noreorder 308 308 enable_ID: 309 - mfc0 t0, CP0_BRCM_CONFIG0 309 + mfc0 t0, CP0_BRCM_CONFIG0 310 310 or t0, t0, (ICE_MASK | DCE_MASK) 311 - mtc0 t0, CP0_BRCM_CONFIG0 311 + mtc0 t0, CP0_BRCM_CONFIG0 312 312 jr ra 313 313 nop 314 314 315 315 .end enable_ID 316 - .set reorder 316 + .set reorder 317 317 318 318 319 319 /* ··· 326 326 */ 327 327 .globl l1_init 328 328 .ent l1_init 329 - .set noreorder 329 + .set noreorder 330 330 l1_init: 331 331 332 332 /* save return address */ 333 - move t8, ra 333 + move t8, ra 334 334 335 335 336 336 /* initialize I and D cache Data and Tag registers. */ 337 - mtc0 zero, CP0_ICACHE_TAG_LO 338 - mtc0 zero, CP0_ICACHE_TAG_HI 337 + mtc0 zero, CP0_ICACHE_TAG_LO 338 + mtc0 zero, CP0_ICACHE_TAG_HI 339 339 mtc0 zero, CP0_ICACHE_DATA_LO 340 340 mtc0 zero, CP0_ICACHE_DATA_HI 341 341 mtc0 zero, CP0_DCACHE_TAG_LO ··· 363 363 * set K0 cache mode 364 364 */ 365 365 366 - mfc0 t0, CP0_CONFIG 367 - and t0, t0, ~CP0_CONFIG_K0_MASK 368 - or t0, t0, 3 /* Write Back mode */ 369 - mtc0 t0, CP0_CONFIG 366 + mfc0 t0, CP0_CONFIG 367 + and t0, t0, ~CP0_CONFIG_K0_MASK 368 + or t0, t0, 3 /* Write Back mode */ 369 + mtc0 t0, CP0_CONFIG 370 370 371 371 /* 372 - * Initialize instruction cache. 372 + * Initialize instruction cache. 373 373 */ 374 374 375 375 li a0, KSEG0 ··· 386 386 nop 387 387 1: 388 388 /* 389 - * Initialize data cache. 389 + * Initialize data cache. 390 390 */ 391 391 392 392 jal size_d_cache /* v0 = d-cache size, v1 = d-cache line size */ 393 393 nop 394 394 395 395 396 - li a0, KSEG0 396 + li a0, KSEG0 397 397 cacheop(a0, v0, v1, Index_Store_Tag_D) 398 398 399 399 jr t8 400 400 nop 401 401 402 402 .end l1_init 403 - .set reorder 403 + .set reorder 404 404 405 405 406 406 /* ··· 416 416 LEAF(set_other_config) 417 417 .set noreorder 418 418 419 - /* enable Bus error for I-fetch */ 420 - mfc0 t0, CP0_CACHEERR, 0 421 - li t1, 0x4 422 - or t0, t1 419 + /* enable Bus error for I-fetch */ 420 + mfc0 t0, CP0_CACHEERR, 0 421 + li t1, 0x4 422 + or t0, t1 423 423 mtc0 t0, CP0_CACHEERR, 0 424 424 425 - /* enable Bus error for Load */ 426 - mfc0 t0, CP0_CACHEERR, 1 427 - li t1, 0x4 428 - or t0, t1 425 + /* enable Bus error for Load */ 426 + mfc0 t0, CP0_CACHEERR, 1 427 + li t1, 0x4 428 + or t0, t1 429 429 mtc0 t0, CP0_CACHEERR, 1 430 430 431 431 /* enable Bus Error for Store */ 432 - mfc0 t0, CP0_CACHEERR, 2 432 + mfc0 t0, CP0_CACHEERR, 2 433 433 li t1, 0x4 434 434 or t0, t1 435 - mtc0 t0, CP0_CACHEERR, 2 435 + mtc0 t0, CP0_CACHEERR, 2 436 436 437 437 jr ra 438 438 nop ··· 452 452 453 453 LEAF(set_branch_pred) 454 454 .set noreorder 455 - mfc0 t0, CP0_BRCM_MODE 455 + mfc0 t0, CP0_BRCM_MODE 456 456 li t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK ) 457 457 and t0, t0, t1 458 458 ··· 466 466 sll t1, CP0_BRCM_MODE_BrHIST_SHIFT 467 467 or t0, t0, t1 468 468 469 - mtc0 t0, CP0_BRCM_MODE 469 + mtc0 t0, CP0_BRCM_MODE 470 470 jr ra 471 471 nop 472 - .set reorder 472 + .set reorder 473 473 END(set_branch_pred) 474 474 475 475 ··· 483 483 */ 484 484 LEAF(set_luc) 485 485 .set noreorder 486 - mfc0 t0, CP0_BRCM_MODE 486 + mfc0 t0, CP0_BRCM_MODE 487 487 li t1, ~(CP0_BRCM_MODE_Luc_MASK) 488 488 and t0, t0, t1 489 489 490 490 /* set Luc */ 491 - ori t0, t0, CP0_BRCM_MODE_Luc_MASK 491 + ori t0, t0, CP0_BRCM_MODE_Luc_MASK 492 492 493 - mtc0 t0, CP0_BRCM_MODE 493 + mtc0 t0, CP0_BRCM_MODE 494 494 jr ra 495 495 nop 496 - .set reorder 496 + .set reorder 497 497 END(set_luc) 498 498 499 499 /* ··· 506 506 */ 507 507 LEAF(set_cwf_tse) 508 508 .set noreorder 509 - mfc0 t0, CP0_BRCM_CONFIG0 509 + mfc0 t0, CP0_BRCM_CONFIG0 510 510 li t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK) 511 511 or t0, t0, t1 512 512 513 - mtc0 t0, CP0_BRCM_CONFIG0 513 + mtc0 t0, CP0_BRCM_CONFIG0 514 514 jr ra 515 515 nop 516 - .set reorder 516 + .set reorder 517 517 END(set_cwf_tse) 518 518 519 519 /* 520 520 * Function: set_clock_ratio 521 - * Arguments: set clock ratio specified by a0 521 + * Arguments: set clock ratio specified by a0 522 522 * Returns: None 523 523 * Description: 524 524 * Trashes: v0, v1, a0, a1 ··· 529 529 LEAF(set_clock_ratio) 530 530 .set noreorder 531 531 532 - mfc0 t0, CP0_BRCM_MODE 532 + mfc0 t0, CP0_BRCM_MODE 533 533 li t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK) 534 534 and t0, t0, t1 535 535 li t1, CP0_BRCM_MODE_SET_MASK 536 536 or t0, t0, t1 537 537 or t0, t0, a0 538 - mtc0 t0, CP0_BRCM_MODE 538 + mtc0 t0, CP0_BRCM_MODE 539 539 jr ra 540 540 nop 541 - .set reorder 541 + .set reorder 542 542 END(set_clock_ratio) 543 543 /* 544 544 * Function: set_zephyr 545 - * Arguments: None 546 - * Returns: None 545 + * Arguments: None 546 + * Returns: None 547 547 * Description: Set any zephyr bits 548 - * Trashes: t0 & t1 548 + * Trashes: t0 & t1 549 549 * 550 550 */ 551 551 LEAF(set_zephyr) 552 - .set noreorder 552 + .set noreorder 553 553 554 - /* enable read/write of CP0 #22 sel. 8 */ 555 - li t0, 0x5a455048 556 - .word 0x4088b00f /* mtc0 t0, $22, 15 */ 554 + /* enable read/write of CP0 #22 sel. 8 */ 555 + li t0, 0x5a455048 556 + .word 0x4088b00f /* mtc0 t0, $22, 15 */ 557 557 558 - .word 0x4008b008 /* mfc0 t0, $22, 8 */ 559 - li t1, 0x09008000 /* turn off pref, jtb */ 560 - or t0, t0, t1 561 - .word 0x4088b008 /* mtc0 t0, $22, 8 */ 562 - sync 558 + .word 0x4008b008 /* mfc0 t0, $22, 8 */ 559 + li t1, 0x09008000 /* turn off pref, jtb */ 560 + or t0, t0, t1 561 + .word 0x4088b008 /* mtc0 t0, $22, 8 */ 562 + sync 563 563 564 564 /* disable read/write of CP0 #22 sel 8 */ 565 - li t0, 0x0 566 - .word 0x4088b00f /* mtc0 t0, $22, 15 */ 565 + li t0, 0x0 566 + .word 0x4088b00f /* mtc0 t0, $22, 15 */ 567 567 568 568 569 - jr ra 570 - nop 569 + jr ra 570 + nop 571 571 .set reorder 572 572 573 573 END(set_zephyr) 574 574 575 575 576 576 /* 577 - * Function: set_llmb 578 - * Arguments: a0=0 disable llmb, a0=1 enables llmb 579 - * Returns: None 577 + * Function: set_llmb 578 + * Arguments: a0=0 disable llmb, a0=1 enables llmb 579 + * Returns: None 580 580 * Description: 581 - * Trashes: t0, t1, t2 581 + * Trashes: t0, t1, t2 582 582 * 583 583 * pseudo code: 584 584 * ··· 607 607 cache 0xb, 0x0(t2) 608 608 sync 609 609 610 - jr ra 610 + jr ra 611 611 nop 612 612 .set reorder 613 613 ··· 623 623 * 624 624 */ 625 625 .globl core_init 626 - .ent core_init 626 + .ent core_init 627 627 .set noreorder 628 628 core_init: 629 629 move t8, ra ··· 639 639 #endif 640 640 641 641 /* set low latency memory bus */ 642 - li a0, 1 643 - bal set_llmb 642 + li a0, 1 643 + bal set_llmb 644 644 nop 645 645 646 646 /* set branch prediction (TP0 only) */ ··· 652 652 nop 653 653 654 654 /* set CWF and TSE */ 655 - bal set_cwf_tse 655 + bal set_cwf_tse 656 656 nop 657 657 658 658 /* ··· 676 676 677 677 /* 678 678 * Function: clear_jump_target_buffer 679 - * Arguments: None 680 - * Returns: None 679 + * Arguments: None 680 + * Returns: None 681 681 * Description: 682 - * Trashes: t0, t1, t2 682 + * Trashes: t0, t1, t2 683 683 * 684 684 */ 685 - #define RESET_CALL_RETURN_STACK_THIS_THREAD (0x06<<16) 686 - #define RESET_JUMP_TARGET_BUFFER_THIS_THREAD (0x04<<16) 685 + #define RESET_CALL_RETURN_STACK_THIS_THREAD (0x06<<16) 686 + #define RESET_JUMP_TARGET_BUFFER_THIS_THREAD (0x04<<16) 687 687 #define JTB_CS_CNTL_MASK (0xFF<<16) 688 688 689 - .globl clear_jump_target_buffer 690 - .ent clear_jump_target_buffer 691 - .set noreorder 689 + .globl clear_jump_target_buffer 690 + .ent clear_jump_target_buffer 691 + .set noreorder 692 692 clear_jump_target_buffer: 693 693 694 - mfc0 t0, $22, 2 695 - nop 696 - nop 694 + mfc0 t0, $22, 2 695 + nop 696 + nop 697 697 698 - li t1, ~JTB_CS_CNTL_MASK 699 - and t0, t0, t1 700 - li t2, RESET_CALL_RETURN_STACK_THIS_THREAD 701 - or t0, t0, t2 702 - mtc0 t0, $22, 2 703 - nop 704 - nop 698 + li t1, ~JTB_CS_CNTL_MASK 699 + and t0, t0, t1 700 + li t2, RESET_CALL_RETURN_STACK_THIS_THREAD 701 + or t0, t0, t2 702 + mtc0 t0, $22, 2 703 + nop 704 + nop 705 705 706 - and t0, t0, t1 707 - li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD 708 - or t0, t0, t2 709 - mtc0 t0, $22, 2 710 - nop 711 - nop 712 - jr ra 713 - nop 706 + and t0, t0, t1 707 + li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD 708 + or t0, t0, t2 709 + mtc0 t0, $22, 2 710 + nop 711 + nop 712 + jr ra 713 + nop 714 714 715 - .end clear_jump_target_buffer 716 - .set reorder 715 + .end clear_jump_target_buffer 716 + .set reorder 717 717 /* 718 718 * Function: bmips_cache_init 719 719 * Arguments: None ··· 724 724 */ 725 725 .globl bmips_5xxx_init 726 726 .ent bmips_5xxx_init 727 - .set noreorder 727 + .set noreorder 728 728 bmips_5xxx_init: 729 729 730 - /* save return address and A0 */ 731 - move t7, ra 730 + /* save return address and A0 */ 731 + move t7, ra 732 732 move t5, a0 733 733 734 734 jal l1_init ··· 740 740 jal clear_jump_target_buffer 741 741 nop 742 742 743 - mtc0 zero, CP0_CAUSE 743 + mtc0 zero, CP0_CAUSE 744 744 745 745 move a0, t5 746 746 jr t7 747 747 nop 748 748 749 749 .end bmips_5xxx_init 750 - .set reorder 750 + .set reorder 751 751 752 752 753 753 #endif