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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into next/dt
TI AM654 support for v4.20 merge window.
This branch adds changes for the Texas Instruments AM654 SoC. Included
changes are:
- Add uart nodes
- Change address cells and size-cells of interconnect tfrom 1 to 2
- Add secure proxy instance for main domain
- Add DMSC support
* tag 'am654-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux:
arm64: dts: ti: k3-am6: Add Device Management Security Controller support
arm64: dts: ti: am654: Add secure proxy instance for main domain
arm64: dts: ti: am654: Add uart nodes
arm64: dts: ti: k3-am65: Change #address-cells and #size-cells of interconnect to 2
Signed-off-by: Olof Johansson <olof@lixom.net>
+147
-27
+46
-5
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+46
-5
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
···
8
8
&cbass_main {
9
9
gic500: interrupt-controller@1800000 {
10
10
compatible = "arm,gic-v3";
11
-
#address-cells = <1>;
12
-
#size-cells = <1>;
11
+
#address-cells = <2>;
12
+
#size-cells = <2>;
13
13
ranges;
14
14
#interrupt-cells = <3>;
15
15
interrupt-controller;
16
-
reg = <0x01800000 0x10000>, /* GICD */
17
-
<0x01880000 0x90000>; /* GICR */
16
+
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
17
+
<0x00 0x01880000 0x00 0x90000>; /* GICR */
18
18
/*
19
19
* vcpumntirq:
20
20
* virtual CPU interface maintenance interrupt
···
23
23
24
24
gic_its: gic-its@18200000 {
25
25
compatible = "arm,gic-v3-its";
26
-
reg = <0x01820000 0x10000>;
26
+
reg = <0x00 0x01820000 0x00 0x10000>;
27
27
msi-controller;
28
28
#msi-cells = <1>;
29
29
};
30
+
};
31
+
32
+
secure_proxy_main: mailbox@32c00000 {
33
+
compatible = "ti,am654-secure-proxy";
34
+
#mbox-cells = <1>;
35
+
reg-names = "target_data", "rt", "scfg";
36
+
reg = <0x00 0x32c00000 0x00 0x100000>,
37
+
<0x00 0x32400000 0x00 0x100000>,
38
+
<0x00 0x32800000 0x00 0x100000>;
39
+
interrupt-names = "rx_011";
40
+
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
41
+
};
42
+
43
+
main_uart0: serial@2800000 {
44
+
compatible = "ti,am654-uart";
45
+
reg = <0x00 0x02800000 0x00 0x100>;
46
+
reg-shift = <2>;
47
+
reg-io-width = <4>;
48
+
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
49
+
clock-frequency = <48000000>;
50
+
current-speed = <115200>;
51
+
};
52
+
53
+
main_uart1: serial@2810000 {
54
+
compatible = "ti,am654-uart";
55
+
reg = <0x00 0x02810000 0x00 0x100>;
56
+
reg-shift = <2>;
57
+
reg-io-width = <4>;
58
+
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
59
+
clock-frequency = <48000000>;
60
+
current-speed = <115200>;
61
+
};
62
+
63
+
main_uart2: serial@2820000 {
64
+
compatible = "ti,am654-uart";
65
+
reg = <0x00 0x02820000 0x00 0x100>;
66
+
reg-shift = <2>;
67
+
reg-io-width = <4>;
68
+
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
69
+
clock-frequency = <48000000>;
70
+
current-speed = <115200>;
30
71
};
31
72
};
+18
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+18
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree Source for AM6 SoC Family MCU Domain peripherals
4
+
*
5
+
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6
+
*/
7
+
8
+
&cbass_mcu {
9
+
mcu_uart0: serial@40a00000 {
10
+
compatible = "ti,am654-uart";
11
+
reg = <0x00 0x40a00000 0x00 0x100>;
12
+
reg-shift = <2>;
13
+
reg-io-width = <4>;
14
+
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
15
+
clock-frequency = <96000000>;
16
+
current-speed = <115200>;
17
+
};
18
+
};
+46
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+46
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
4
+
*
5
+
* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6
+
*/
7
+
8
+
&cbass_wakeup {
9
+
dmsc: dmsc {
10
+
compatible = "ti,k2g-sci";
11
+
ti,host-id = <12>;
12
+
#address-cells = <1>;
13
+
#size-cells = <1>;
14
+
ranges;
15
+
16
+
mbox-names = "rx", "tx";
17
+
18
+
mboxes= <&secure_proxy_main 11>,
19
+
<&secure_proxy_main 13>;
20
+
21
+
k3_pds: power-controller {
22
+
compatible = "ti,sci-pm-domain";
23
+
#power-domain-cells = <1>;
24
+
};
25
+
26
+
k3_clks: clocks {
27
+
compatible = "ti,k2g-sci-clk";
28
+
#clock-cells = <2>;
29
+
};
30
+
31
+
k3_reset: reset-controller {
32
+
compatible = "ti,sci-reset";
33
+
#reset-cells = <2>;
34
+
};
35
+
};
36
+
37
+
wkup_uart0: serial@42300000 {
38
+
compatible = "ti,am654-uart";
39
+
reg = <0x00 0x42300000 0x00 0x100>;
40
+
reg-shift = <2>;
41
+
reg-io-width = <4>;
42
+
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
43
+
clock-frequency = <48000000>;
44
+
current-speed = <115200>;
45
+
};
46
+
};
+32
-22
arch/arm64/boot/dts/ti/k3-am65.dtsi
+32
-22
arch/arm64/boot/dts/ti/k3-am65.dtsi
···
16
16
#address-cells = <2>;
17
17
#size-cells = <2>;
18
18
19
+
aliases {
20
+
serial0 = &wkup_uart0;
21
+
serial1 = &mcu_uart0;
22
+
serial2 = &main_uart0;
23
+
serial3 = &main_uart1;
24
+
serial4 = &main_uart2;
25
+
};
26
+
19
27
chosen { };
20
28
21
29
firmware {
···
54
46
55
47
cbass_main: interconnect@100000 {
56
48
compatible = "simple-bus";
57
-
#address-cells = <1>;
58
-
#size-cells = <1>;
59
-
ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */
60
-
<0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */
61
-
<0x00900000 0x00 0x00900000 0x00012000>, /* serdes */
62
-
<0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */
63
-
<0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */
49
+
#address-cells = <2>;
50
+
#size-cells = <2>;
51
+
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
52
+
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
53
+
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
54
+
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
55
+
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
64
56
/* MCUSS Range */
65
-
<0x28380000 0x00 0x28380000 0x03880000>,
66
-
<0x40200000 0x00 0x40200000 0x00900100>,
67
-
<0x42040000 0x00 0x42040000 0x03ac2400>,
68
-
<0x45100000 0x00 0x45100000 0x00c24000>,
69
-
<0x46000000 0x00 0x46000000 0x00200000>,
70
-
<0x47000000 0x00 0x47000000 0x00068400>;
57
+
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
58
+
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
59
+
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
60
+
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
61
+
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
62
+
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>;
71
63
72
64
cbass_mcu: interconnect@28380000 {
73
65
compatible = "simple-bus";
74
-
#address-cells = <1>;
75
-
#size-cells = <1>;
76
-
ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/
77
-
<0x40200000 0x40200000 0x00900100>, /* First peripheral window */
78
-
<0x42040000 0x42040000 0x03ac2400>, /* WKUP */
79
-
<0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */
80
-
<0x46000000 0x46000000 0x00200000>, /* CPSW */
81
-
<0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */
66
+
#address-cells = <2>;
67
+
#size-cells = <2>;
68
+
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
69
+
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
70
+
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
71
+
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
72
+
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
73
+
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>; /* OSPI space 1 */
82
74
83
75
cbass_wakeup: interconnect@42040000 {
84
76
compatible = "simple-bus";
85
77
#address-cells = <1>;
86
78
#size-cells = <1>;
87
79
/* WKUP Basic peripherals */
88
-
ranges = <0x42040000 0x42040000 0x03ac2400>;
80
+
ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
89
81
};
90
82
};
91
83
};
···
93
85
94
86
/* Now include the peripherals for each bus segments */
95
87
#include "k3-am65-main.dtsi"
88
+
#include "k3-am65-mcu.dtsi"
89
+
#include "k3-am65-wakeup.dtsi"