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Merge tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson into v5.5/dt64-redo
First round of amlogic DT binding clock update target for v5.5
Add the audio clock and reset bindings for the sm1 SoC family
* tag 'clk-meson-dt-v5.5-1' of git://github.com/BayLibre/clk-meson:
dt-bindings: clock: meson: add sm1 resets to the axg-audio controller
dt-bindings: clk: axg-audio: add sm1 bindings
+27
-1
+2
-1
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+2
-1
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
···
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7
Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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-
"amlogic,g12a-audio-clkc" for G12A.
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+
"amlogic,g12a-audio-clkc" for G12A,
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"amlogic,sm1-audio-clkc" for S905X3.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
+10
include/dt-bindings/clock/axg-audio-clkc.h
+10
include/dt-bindings/clock/axg-audio-clkc.h
···
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#define AUD_CLKID_TDM_SCLK_PAD0 160
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#define AUD_CLKID_TDM_SCLK_PAD1 161
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#define AUD_CLKID_TDM_SCLK_PAD2 162
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+
#define AUD_CLKID_TOP 163
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+
#define AUD_CLKID_TORAM 164
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#define AUD_CLKID_EQDRC 165
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#define AUD_CLKID_RESAMPLE_B 166
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#define AUD_CLKID_TOVAD 167
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#define AUD_CLKID_LOCKER 168
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#define AUD_CLKID_SPDIFIN_LB 169
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#define AUD_CLKID_FRDDR_D 170
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+
#define AUD_CLKID_TODDR_D 171
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#define AUD_CLKID_LOOPBACK_B 172
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#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
+15
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
+15
include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
···
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#define AUD_RESET_TOHDMITX 24
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#define AUD_RESET_CLKTREE 25
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+
/* SM1 added resets */
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#define AUD_RESET_RESAMPLE_B 26
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#define AUD_RESET_TOVAD 27
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+
#define AUD_RESET_LOCKER 28
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+
#define AUD_RESET_SPDIFIN_LB 29
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#define AUD_RESET_FRATV 30
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#define AUD_RESET_FRHDMIRX 31
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+
#define AUD_RESET_FRDDR_D 32
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+
#define AUD_RESET_TODDR_D 33
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+
#define AUD_RESET_LOOPBACK_B 34
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#define AUD_RESET_EARCTX 35
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#define AUD_RESET_EARCRX 36
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#define AUD_RESET_FRDDR_E 37
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#define AUD_RESET_TODDR_E 38
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+
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#endif