Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband: (42 commits)
IB/qib: Fix refcount leak in lkey/rkey validation
IB/qib: Improve SERDES tunning on QMH boards
IB/qib: Unnecessary delayed completions on RC connection
IB/qib: Issue pre-emptive NAKs on eager buffer overflow
IB/qib: RDMA lkey/rkey validation is inefficient for large MRs
IB/qib: Change QPN increment
IB/qib: Add fix missing from earlier patch
IB/qib: Change receive queue/QPN selection
IB/qib: Fix interrupt mitigation
IB/qib: Avoid duplicate writes to the rcv head register
IB/qib: Add a few new SERDES tunings
IB/qib: Reset packet list after freeing
IB/qib: New SERDES init routine and improvements to SI quality
IB/qib: Clear WAIT_SEND flags when setting QP to error state
IB/qib: Fix context allocation with multiple HCAs
IB/qib: Fix multi-Florida HCA host panic on reboot
IB/qib: Handle transitions from ACTIVE_DEFERRED to ACTIVE better
IB/qib: UD send with immediate receive completion has wrong size
IB/qib: Set port physical state even if other fields are invalid
IB/qib: Generate completion callback on errors
...

+889 -622
+2
drivers/infiniband/hw/cxgb3/cxio_hal.c
··· 189 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); 190 } 191 192 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) 193 { 194 struct rdma_cq_setup setup; ··· 201 setup.ovfl_mode = 1; 202 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); 203 } 204 205 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx) 206 {
··· 189 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); 190 } 191 192 + #ifdef notyet 193 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq) 194 { 195 struct rdma_cq_setup setup; ··· 200 setup.ovfl_mode = 1; 201 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup)); 202 } 203 + #endif 204 205 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx) 206 {
-2
drivers/infiniband/hw/cxgb3/iwch_provider.h
··· 335 int iwch_post_zb_read(struct iwch_qp *qhp); 336 int iwch_register_device(struct iwch_dev *dev); 337 void iwch_unregister_device(struct iwch_dev *dev); 338 - int iwch_quiesce_qps(struct iwch_cq *chp); 339 - int iwch_resume_qps(struct iwch_cq *chp); 340 void stop_read_rep_timer(struct iwch_qp *qhp); 341 int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php, 342 struct iwch_mr *mhp, int shift);
··· 335 int iwch_post_zb_read(struct iwch_qp *qhp); 336 int iwch_register_device(struct iwch_dev *dev); 337 void iwch_unregister_device(struct iwch_dev *dev); 338 void stop_read_rep_timer(struct iwch_qp *qhp); 339 int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php, 340 struct iwch_mr *mhp, int shift);
-56
drivers/infiniband/hw/cxgb3/iwch_qp.c
··· 1149 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1150 return ret; 1151 } 1152 - 1153 - static int quiesce_qp(struct iwch_qp *qhp) 1154 - { 1155 - spin_lock_irq(&qhp->lock); 1156 - iwch_quiesce_tid(qhp->ep); 1157 - qhp->flags |= QP_QUIESCED; 1158 - spin_unlock_irq(&qhp->lock); 1159 - return 0; 1160 - } 1161 - 1162 - static int resume_qp(struct iwch_qp *qhp) 1163 - { 1164 - spin_lock_irq(&qhp->lock); 1165 - iwch_resume_tid(qhp->ep); 1166 - qhp->flags &= ~QP_QUIESCED; 1167 - spin_unlock_irq(&qhp->lock); 1168 - return 0; 1169 - } 1170 - 1171 - int iwch_quiesce_qps(struct iwch_cq *chp) 1172 - { 1173 - int i; 1174 - struct iwch_qp *qhp; 1175 - 1176 - for (i=0; i < T3_MAX_NUM_QP; i++) { 1177 - qhp = get_qhp(chp->rhp, i); 1178 - if (!qhp) 1179 - continue; 1180 - if ((qhp->attr.rcq == chp->cq.cqid) && !qp_quiesced(qhp)) { 1181 - quiesce_qp(qhp); 1182 - continue; 1183 - } 1184 - if ((qhp->attr.scq == chp->cq.cqid) && !qp_quiesced(qhp)) 1185 - quiesce_qp(qhp); 1186 - } 1187 - return 0; 1188 - } 1189 - 1190 - int iwch_resume_qps(struct iwch_cq *chp) 1191 - { 1192 - int i; 1193 - struct iwch_qp *qhp; 1194 - 1195 - for (i=0; i < T3_MAX_NUM_QP; i++) { 1196 - qhp = get_qhp(chp->rhp, i); 1197 - if (!qhp) 1198 - continue; 1199 - if ((qhp->attr.rcq == chp->cq.cqid) && qp_quiesced(qhp)) { 1200 - resume_qp(qhp); 1201 - continue; 1202 - } 1203 - if ((qhp->attr.scq == chp->cq.cqid) && qp_quiesced(qhp)) 1204 - resume_qp(qhp); 1205 - } 1206 - return 0; 1207 - }
··· 1149 PDBG("%s exit state %d\n", __func__, qhp->attr.state); 1150 return ret; 1151 }
-1
drivers/infiniband/hw/cxgb4/iw_cxgb4.h
··· 760 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count); 761 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 762 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 763 - int c4iw_post_zb_read(struct c4iw_qp *qhp); 764 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 765 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 766 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
··· 760 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count); 761 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); 762 u16 c4iw_rqes_posted(struct c4iw_qp *qhp); 763 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); 764 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); 765 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
-32
drivers/infiniband/hw/cxgb4/qp.c
··· 892 } 893 } 894 895 - int c4iw_post_zb_read(struct c4iw_qp *qhp) 896 - { 897 - union t4_wr *wqe; 898 - struct sk_buff *skb; 899 - u8 len16; 900 - 901 - PDBG("%s enter\n", __func__); 902 - skb = alloc_skb(40, GFP_KERNEL); 903 - if (!skb) { 904 - printk(KERN_ERR "%s cannot send zb_read!!\n", __func__); 905 - return -ENOMEM; 906 - } 907 - set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx); 908 - 909 - wqe = (union t4_wr *)skb_put(skb, sizeof wqe->read); 910 - memset(wqe, 0, sizeof wqe->read); 911 - wqe->read.r2 = cpu_to_be64(0); 912 - wqe->read.stag_sink = cpu_to_be32(1); 913 - wqe->read.to_sink_hi = cpu_to_be32(0); 914 - wqe->read.to_sink_lo = cpu_to_be32(1); 915 - wqe->read.stag_src = cpu_to_be32(1); 916 - wqe->read.plen = cpu_to_be32(0); 917 - wqe->read.to_src_hi = cpu_to_be32(0); 918 - wqe->read.to_src_lo = cpu_to_be32(1); 919 - len16 = DIV_ROUND_UP(sizeof wqe->read, 16); 920 - init_wr_hdr(wqe, 0, FW_RI_RDMA_READ_WR, FW_RI_COMPLETION_FLAG, len16); 921 - 922 - return c4iw_ofld_send(&qhp->rhp->rdev, skb); 923 - } 924 - 925 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 926 gfp_t gfp) 927 { ··· 999 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1000 1001 wqe->u.fini.type = FW_RI_TYPE_FINI; 1002 - c4iw_init_wr_wait(&ep->com.wr_wait); 1003 ret = c4iw_ofld_send(&rhp->rdev, skb); 1004 if (ret) 1005 goto out; ··· 1094 if (qhp->attr.mpa_attr.initiator) 1095 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1096 1097 - c4iw_init_wr_wait(&qhp->ep->com.wr_wait); 1098 ret = c4iw_ofld_send(&rhp->rdev, skb); 1099 if (ret) 1100 goto out;
··· 892 } 893 } 894 895 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, 896 gfp_t gfp) 897 { ··· 1029 wqe->cookie = (unsigned long) &ep->com.wr_wait; 1030 1031 wqe->u.fini.type = FW_RI_TYPE_FINI; 1032 ret = c4iw_ofld_send(&rhp->rdev, skb); 1033 if (ret) 1034 goto out; ··· 1125 if (qhp->attr.mpa_attr.initiator) 1126 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init); 1127 1128 ret = c4iw_ofld_send(&rhp->rdev, skb); 1129 if (ret) 1130 goto out;
+2 -3
drivers/infiniband/hw/ipath/ipath_driver.c
··· 530 for (j = 0; j < 6; j++) { 531 if (!pdev->resource[j].start) 532 continue; 533 - ipath_cdbg(VERBOSE, "BAR %d start %llx, end %llx, len %llx\n", 534 - j, (unsigned long long)pdev->resource[j].start, 535 - (unsigned long long)pdev->resource[j].end, 536 (unsigned long long)pci_resource_len(pdev, j)); 537 } 538
··· 530 for (j = 0; j < 6; j++) { 531 if (!pdev->resource[j].start) 532 continue; 533 + ipath_cdbg(VERBOSE, "BAR %d %pR, len %llx\n", 534 + j, &pdev->resource[j], 535 (unsigned long long)pci_resource_len(pdev, j)); 536 } 537
+8 -1
drivers/infiniband/hw/mlx4/cq.c
··· 397 cq->resize_buf = NULL; 398 cq->resize_umem = NULL; 399 } else { 400 spin_lock_irq(&cq->lock); 401 if (cq->resize_buf) { 402 mlx4_ib_cq_resize_copy_cqes(cq); 403 - mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); 404 cq->buf = cq->resize_buf->buf; 405 cq->ibcq.cqe = cq->resize_buf->cqe; 406 ··· 412 cq->resize_buf = NULL; 413 } 414 spin_unlock_irq(&cq->lock); 415 } 416 417 goto out;
··· 397 cq->resize_buf = NULL; 398 cq->resize_umem = NULL; 399 } else { 400 + struct mlx4_ib_cq_buf tmp_buf; 401 + int tmp_cqe = 0; 402 + 403 spin_lock_irq(&cq->lock); 404 if (cq->resize_buf) { 405 mlx4_ib_cq_resize_copy_cqes(cq); 406 + tmp_buf = cq->buf; 407 + tmp_cqe = cq->ibcq.cqe; 408 cq->buf = cq->resize_buf->buf; 409 cq->ibcq.cqe = cq->resize_buf->cqe; 410 ··· 408 cq->resize_buf = NULL; 409 } 410 spin_unlock_irq(&cq->lock); 411 + 412 + if (tmp_cqe) 413 + mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe); 414 } 415 416 goto out;
+2
drivers/infiniband/hw/mlx4/mad.c
··· 211 if (agent) { 212 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 213 IB_MGMT_MAD_DATA, GFP_ATOMIC); 214 /* 215 * We rely here on the fact that MLX QPs don't use the 216 * address handle after the send is posted (this is
··· 211 if (agent) { 212 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 213 IB_MGMT_MAD_DATA, GFP_ATOMIC); 214 + if (IS_ERR(send_buf)) 215 + return; 216 /* 217 * We rely here on the fact that MLX QPs don't use the 218 * address handle after the send is posted (this is
+2
drivers/infiniband/hw/mthca/mthca_mad.c
··· 171 if (agent) { 172 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 173 IB_MGMT_MAD_DATA, GFP_ATOMIC); 174 /* 175 * We rely here on the fact that MLX QPs don't use the 176 * address handle after the send is posted (this is
··· 171 if (agent) { 172 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 173 IB_MGMT_MAD_DATA, GFP_ATOMIC); 174 + if (IS_ERR(send_buf)) 175 + return; 176 /* 177 * We rely here on the fact that MLX QPs don't use the 178 * address handle after the send is posted (this is
+2 -2
drivers/infiniband/hw/nes/nes_nic.c
··· 908 nesvnic->nic_index && 909 mc_index < max_pft_entries_avaiable) { 910 nes_debug(NES_DBG_NIC_RX, 911 - "mc_index=%d skipping nic_index=%d,\ 912 - used for=%d \n", mc_index, 913 nesvnic->nic_index, 914 nesadapter->pft_mcast_map[mc_index]); 915 mc_index++;
··· 908 nesvnic->nic_index && 909 mc_index < max_pft_entries_avaiable) { 910 nes_debug(NES_DBG_NIC_RX, 911 + "mc_index=%d skipping nic_index=%d, " 912 + "used for=%d \n", mc_index, 913 nesvnic->nic_index, 914 nesadapter->pft_mcast_map[mc_index]); 915 mc_index++;
+1 -1
drivers/infiniband/hw/qib/qib.h
··· 766 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 767 void (*f_sdma_init_early)(struct qib_pportdata *); 768 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 769 - void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32); 770 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 771 u64 (*f_portcntr)(struct qib_pportdata *, u32); 772 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
··· 766 void (*f_sdma_hw_start_up)(struct qib_pportdata *); 767 void (*f_sdma_init_early)(struct qib_pportdata *); 768 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32); 769 + void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32); 770 u32 (*f_hdrqempty)(struct qib_ctxtdata *); 771 u64 (*f_portcntr)(struct qib_pportdata *, u32); 772 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
+2 -1
drivers/infiniband/hw/qib/qib_cq.c
··· 100 wc->head = next; 101 102 if (cq->notify == IB_CQ_NEXT_COMP || 103 - (cq->notify == IB_CQ_SOLICITED && solicited)) { 104 cq->notify = IB_CQ_NONE; 105 cq->triggered++; 106 /*
··· 100 wc->head = next; 101 102 if (cq->notify == IB_CQ_NEXT_COMP || 103 + (cq->notify == IB_CQ_SOLICITED && 104 + (solicited || entry->status != IB_WC_SUCCESS))) { 105 cq->notify = IB_CQ_NONE; 106 cq->triggered++; 107 /*
+148 -7
drivers/infiniband/hw/qib/qib_driver.c
··· 71 */ 72 #define QIB_PIO_MAXIBHDR 128 73 74 struct qlogic_ib_stats qib_stats; 75 76 const char *qib_get_unit_name(int unit) ··· 289 * Returns 1 if error was a CRC, else 0. 290 * Needed for some chip's synthesized error counters. 291 */ 292 - static u32 qib_rcv_hdrerr(struct qib_pportdata *ppd, u32 ctxt, 293 - u32 eflags, u32 l, u32 etail, __le32 *rhf_addr, 294 - struct qib_message_header *hdr) 295 { 296 u32 ret = 0; 297 298 if (eflags & (QLOGIC_IB_RHF_H_ICRCERR | QLOGIC_IB_RHF_H_VCRCERR)) 299 ret = 1; 300 return ret; 301 } 302 ··· 473 smp_rmb(); /* prevent speculative reads of dma'ed hdrq */ 474 } 475 476 - for (last = 0, i = 1; !last && i <= 64; i += !last) { 477 hdr = dd->f_get_msgheader(dd, rhf_addr); 478 eflags = qib_hdrget_err_flags(rhf_addr); 479 etype = qib_hdrget_rcv_type(rhf_addr); ··· 509 * packets; only qibhdrerr should be set. 510 */ 511 if (unlikely(eflags)) 512 - crcs += qib_rcv_hdrerr(ppd, rcd->ctxt, eflags, l, 513 etail, rhf_addr, hdr); 514 else if (etype == RCVHQ_RCV_TYPE_NON_KD) { 515 qib_ib_rcv(rcd, hdr, ebuf, tlen); ··· 522 l += rsize; 523 if (l >= maxcnt) 524 l = 0; 525 rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; 526 if (dd->flags & QIB_NODMA_RTAIL) { 527 u32 seq = qib_hdrget_seq(rhf_addr); ··· 543 */ 544 lval = l; 545 if (!last && !(i & 0xf)) { 546 - dd->f_update_usrhead(rcd, lval, updegr, etail); 547 updegr = 0; 548 } 549 } ··· 585 * if no packets were processed. 586 */ 587 lval = (u64)rcd->head | dd->rhdrhead_intr_off; 588 - dd->f_update_usrhead(rcd, lval, updegr, etail); 589 return crcs; 590 } 591
··· 71 */ 72 #define QIB_PIO_MAXIBHDR 128 73 74 + /* 75 + * QIB_MAX_PKT_RCV is the max # if packets processed per receive interrupt. 76 + */ 77 + #define QIB_MAX_PKT_RECV 64 78 + 79 struct qlogic_ib_stats qib_stats; 80 81 const char *qib_get_unit_name(int unit) ··· 284 * Returns 1 if error was a CRC, else 0. 285 * Needed for some chip's synthesized error counters. 286 */ 287 + static u32 qib_rcv_hdrerr(struct qib_ctxtdata *rcd, struct qib_pportdata *ppd, 288 + u32 ctxt, u32 eflags, u32 l, u32 etail, 289 + __le32 *rhf_addr, struct qib_message_header *rhdr) 290 { 291 u32 ret = 0; 292 293 if (eflags & (QLOGIC_IB_RHF_H_ICRCERR | QLOGIC_IB_RHF_H_VCRCERR)) 294 ret = 1; 295 + else if (eflags == QLOGIC_IB_RHF_H_TIDERR) { 296 + /* For TIDERR and RC QPs premptively schedule a NAK */ 297 + struct qib_ib_header *hdr = (struct qib_ib_header *) rhdr; 298 + struct qib_other_headers *ohdr = NULL; 299 + struct qib_ibport *ibp = &ppd->ibport_data; 300 + struct qib_qp *qp = NULL; 301 + u32 tlen = qib_hdrget_length_in_bytes(rhf_addr); 302 + u16 lid = be16_to_cpu(hdr->lrh[1]); 303 + int lnh = be16_to_cpu(hdr->lrh[0]) & 3; 304 + u32 qp_num; 305 + u32 opcode; 306 + u32 psn; 307 + int diff; 308 + unsigned long flags; 309 + 310 + /* Sanity check packet */ 311 + if (tlen < 24) 312 + goto drop; 313 + 314 + if (lid < QIB_MULTICAST_LID_BASE) { 315 + lid &= ~((1 << ppd->lmc) - 1); 316 + if (unlikely(lid != ppd->lid)) 317 + goto drop; 318 + } 319 + 320 + /* Check for GRH */ 321 + if (lnh == QIB_LRH_BTH) 322 + ohdr = &hdr->u.oth; 323 + else if (lnh == QIB_LRH_GRH) { 324 + u32 vtf; 325 + 326 + ohdr = &hdr->u.l.oth; 327 + if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR) 328 + goto drop; 329 + vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow); 330 + if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION) 331 + goto drop; 332 + } else 333 + goto drop; 334 + 335 + /* Get opcode and PSN from packet */ 336 + opcode = be32_to_cpu(ohdr->bth[0]); 337 + opcode >>= 24; 338 + psn = be32_to_cpu(ohdr->bth[2]); 339 + 340 + /* Get the destination QP number. */ 341 + qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK; 342 + if (qp_num != QIB_MULTICAST_QPN) { 343 + int ruc_res; 344 + qp = qib_lookup_qpn(ibp, qp_num); 345 + if (!qp) 346 + goto drop; 347 + 348 + /* 349 + * Handle only RC QPs - for other QP types drop error 350 + * packet. 351 + */ 352 + spin_lock(&qp->r_lock); 353 + 354 + /* Check for valid receive state. */ 355 + if (!(ib_qib_state_ops[qp->state] & 356 + QIB_PROCESS_RECV_OK)) { 357 + ibp->n_pkt_drops++; 358 + goto unlock; 359 + } 360 + 361 + switch (qp->ibqp.qp_type) { 362 + case IB_QPT_RC: 363 + spin_lock_irqsave(&qp->s_lock, flags); 364 + ruc_res = 365 + qib_ruc_check_hdr( 366 + ibp, hdr, 367 + lnh == QIB_LRH_GRH, 368 + qp, 369 + be32_to_cpu(ohdr->bth[0])); 370 + if (ruc_res) { 371 + spin_unlock_irqrestore(&qp->s_lock, 372 + flags); 373 + goto unlock; 374 + } 375 + spin_unlock_irqrestore(&qp->s_lock, flags); 376 + 377 + /* Only deal with RDMA Writes for now */ 378 + if (opcode < 379 + IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) { 380 + diff = qib_cmp24(psn, qp->r_psn); 381 + if (!qp->r_nak_state && diff >= 0) { 382 + ibp->n_rc_seqnak++; 383 + qp->r_nak_state = 384 + IB_NAK_PSN_ERROR; 385 + /* Use the expected PSN. */ 386 + qp->r_ack_psn = qp->r_psn; 387 + /* 388 + * Wait to send the sequence 389 + * NAK until all packets 390 + * in the receive queue have 391 + * been processed. 392 + * Otherwise, we end up 393 + * propagating congestion. 394 + */ 395 + if (list_empty(&qp->rspwait)) { 396 + qp->r_flags |= 397 + QIB_R_RSP_NAK; 398 + atomic_inc( 399 + &qp->refcount); 400 + list_add_tail( 401 + &qp->rspwait, 402 + &rcd->qp_wait_list); 403 + } 404 + } /* Out of sequence NAK */ 405 + } /* QP Request NAKs */ 406 + break; 407 + case IB_QPT_SMI: 408 + case IB_QPT_GSI: 409 + case IB_QPT_UD: 410 + case IB_QPT_UC: 411 + default: 412 + /* For now don't handle any other QP types */ 413 + break; 414 + } 415 + 416 + unlock: 417 + spin_unlock(&qp->r_lock); 418 + /* 419 + * Notify qib_destroy_qp() if it is waiting 420 + * for us to finish. 421 + */ 422 + if (atomic_dec_and_test(&qp->refcount)) 423 + wake_up(&qp->wait); 424 + } /* Unicast QP */ 425 + } /* Valid packet with TIDErr */ 426 + 427 + drop: 428 return ret; 429 } 430 ··· 335 smp_rmb(); /* prevent speculative reads of dma'ed hdrq */ 336 } 337 338 + for (last = 0, i = 1; !last; i += !last) { 339 hdr = dd->f_get_msgheader(dd, rhf_addr); 340 eflags = qib_hdrget_err_flags(rhf_addr); 341 etype = qib_hdrget_rcv_type(rhf_addr); ··· 371 * packets; only qibhdrerr should be set. 372 */ 373 if (unlikely(eflags)) 374 + crcs += qib_rcv_hdrerr(rcd, ppd, rcd->ctxt, eflags, l, 375 etail, rhf_addr, hdr); 376 else if (etype == RCVHQ_RCV_TYPE_NON_KD) { 377 qib_ib_rcv(rcd, hdr, ebuf, tlen); ··· 384 l += rsize; 385 if (l >= maxcnt) 386 l = 0; 387 + if (i == QIB_MAX_PKT_RECV) 388 + last = 1; 389 + 390 rhf_addr = (__le32 *) rcd->rcvhdrq + l + dd->rhf_offset; 391 if (dd->flags & QIB_NODMA_RTAIL) { 392 u32 seq = qib_hdrget_seq(rhf_addr); ··· 402 */ 403 lval = l; 404 if (!last && !(i & 0xf)) { 405 + dd->f_update_usrhead(rcd, lval, updegr, etail, i); 406 updegr = 0; 407 } 408 } ··· 444 * if no packets were processed. 445 */ 446 lval = (u64)rcd->head | dd->rhdrhead_intr_off; 447 + dd->f_update_usrhead(rcd, lval, updegr, etail, i); 448 return crcs; 449 } 450
+5 -5
drivers/infiniband/hw/qib/qib_file_ops.c
··· 1379 /* find device (with ACTIVE ports) with fewest ctxts in use */ 1380 for (ndev = 0; ndev < devmax; ndev++) { 1381 struct qib_devdata *dd = qib_lookup(ndev); 1382 - unsigned cused = 0, cfree = 0; 1383 if (!dd) 1384 continue; 1385 if (port && port <= dd->num_pports && 1386 usable(dd->pport + port - 1)) 1387 - dusable = 1; 1388 else 1389 for (i = 0; i < dd->num_pports; i++) 1390 if (usable(dd->pport + i)) 1391 - dusable++; 1392 - if (!dusable) 1393 continue; 1394 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; 1395 ctxt++) ··· 1397 cused++; 1398 else 1399 cfree++; 1400 - if (cfree && cused < inuse) { 1401 udd = dd; 1402 inuse = cused; 1403 }
··· 1379 /* find device (with ACTIVE ports) with fewest ctxts in use */ 1380 for (ndev = 0; ndev < devmax; ndev++) { 1381 struct qib_devdata *dd = qib_lookup(ndev); 1382 + unsigned cused = 0, cfree = 0, pusable = 0; 1383 if (!dd) 1384 continue; 1385 if (port && port <= dd->num_pports && 1386 usable(dd->pport + port - 1)) 1387 + pusable = 1; 1388 else 1389 for (i = 0; i < dd->num_pports; i++) 1390 if (usable(dd->pport + i)) 1391 + pusable++; 1392 + if (!pusable) 1393 continue; 1394 for (ctxt = dd->first_user_ctxt; ctxt < dd->cfgctxts; 1395 ctxt++) ··· 1397 cused++; 1398 else 1399 cfree++; 1400 + if (pusable && cfree && cused < inuse) { 1401 udd = dd; 1402 inuse = cused; 1403 }
+1 -1
drivers/infiniband/hw/qib/qib_iba6120.c
··· 2074 } 2075 2076 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd, 2077 - u32 updegr, u32 egrhd) 2078 { 2079 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 2080 if (updegr)
··· 2074 } 2075 2076 static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd, 2077 + u32 updegr, u32 egrhd, u32 npkts) 2078 { 2079 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 2080 if (updegr)
+2 -2
drivers/infiniband/hw/qib/qib_iba7220.c
··· 2297 nchipctxts = qib_read_kreg32(dd, kr_portcnt); 2298 dd->cspec->numctxts = nchipctxts; 2299 if (qib_n_krcv_queues > 1) { 2300 - dd->qpn_mask = 0x3f; 2301 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports; 2302 if (dd->first_user_ctxt > nchipctxts) 2303 dd->first_user_ctxt = nchipctxts; ··· 2703 } 2704 2705 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd, 2706 - u32 updegr, u32 egrhd) 2707 { 2708 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 2709 if (updegr)
··· 2297 nchipctxts = qib_read_kreg32(dd, kr_portcnt); 2298 dd->cspec->numctxts = nchipctxts; 2299 if (qib_n_krcv_queues > 1) { 2300 + dd->qpn_mask = 0x3e; 2301 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports; 2302 if (dd->first_user_ctxt > nchipctxts) 2303 dd->first_user_ctxt = nchipctxts; ··· 2703 } 2704 2705 static void qib_update_7220_usrhead(struct qib_ctxtdata *rcd, u64 hd, 2706 + u32 updegr, u32 egrhd, u32 npkts) 2707 { 2708 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 2709 if (updegr)
+339 -34
drivers/infiniband/hw/qib/qib_iba7322.c
··· 71 72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); 73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); 74 75 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) 76 ··· 113 static ushort qib_singleport; 114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO); 115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); 116 117 #define MAX_ATTEN_LEN 64 /* plenty for any real system */ 118 /* for read back, default index is ~5m copper cable */ ··· 562 563 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 564 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */ 565 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 566 567 #define H1_FORCE_VAL 8 ··· 623 u8 ibmalfusesnap; 624 struct qib_qsfp_data qsfp_data; 625 char epmsgbuf[192]; /* for port error interrupt msg buffer */ 626 }; 627 628 static struct { ··· 1697 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { 1698 force_h1(ppd); 1699 ppd->cpspec->qdr_reforce = 1; 1700 } else if (ppd->cpspec->qdr_reforce && 1701 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && 1702 (ibclt == IB_7322_LT_STATE_CFGENH || ··· 1714 ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) 1715 adj_tx_serdes(ppd); 1716 1717 - if (!ppd->cpspec->qdr_dfe_on && ibclt != IB_7322_LT_STATE_LINKUP && 1718 - ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { 1719 - ppd->cpspec->qdr_dfe_on = 1; 1720 - ppd->cpspec->qdr_dfe_time = 0; 1721 - /* On link down, reenable QDR adaptation */ 1722 - qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 1723 - ppd->dd->cspec->r1 ? 1724 - QDR_STATIC_ADAPT_DOWN_R1 : 1725 - QDR_STATIC_ADAPT_DOWN); 1726 } 1727 } 1728 1729 /* 1730 * This is per-pport error handling. ··· 1881 IB_PHYSPORTSTATE_DISABLED) 1882 qib_set_ib_7322_lstate(ppd, 0, 1883 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1884 - else 1885 /* 1886 * Since going into a recovery state causes the link 1887 * state to go down and since recovery is transitory, ··· 1911 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1912 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1913 qib_handle_e_ibstatuschanged(ppd, ibcs); 1914 } 1915 if (*msg && iserr) 1916 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); ··· 2843 ctxtrbits &= ~rmask; 2844 if (dd->rcd[i]) { 2845 qib_kreceive(dd->rcd[i], NULL, &npkts); 2846 - adjust_rcv_timeout(dd->rcd[i], npkts); 2847 } 2848 } 2849 rmask <<= 1; ··· 2892 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); 2893 2894 qib_kreceive(rcd, NULL, &npkts); 2895 - adjust_rcv_timeout(rcd, npkts); 2896 2897 return IRQ_HANDLED; 2898 } ··· 3213 case BOARD_QME7342: 3214 n = "InfiniPath_QME7342"; 3215 break; 3216 case 15: 3217 n = "InfiniPath_QLE7342_TEST"; 3218 dd->flags |= QIB_HAS_QSFP; ··· 3535 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); 3536 dd->cspec->numctxts = nchipctxts; 3537 if (qib_n_krcv_queues > 1 && dd->num_pports) { 3538 - /* 3539 - * Set the mask for which bits from the QPN are used 3540 - * to select a context number. 3541 - */ 3542 - dd->qpn_mask = 0x3f; 3543 dd->first_user_ctxt = NUM_IB_PORTS + 3544 (qib_n_krcv_queues - 1) * dd->num_pports; 3545 if (dd->first_user_ctxt > nchipctxts) ··· 3585 3586 /* kr_rcvegrcnt changes based on the number of contexts enabled */ 3587 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3588 - dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, 3589 - dd->num_pports > 1 ? 1024U : 2048U); 3590 } 3591 3592 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) ··· 4060 } 4061 4062 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, 4063 - u32 updegr, u32 egrhd) 4064 { 4065 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4066 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4067 if (updegr) ··· 5586 u64 now = get_jiffies_64(); 5587 if (time_after64(now, pwrup)) 5588 break; 5589 - msleep(1); 5590 } 5591 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 5592 /* ··· 5643 u32 pidx, unit, port, deflt, h1; 5644 unsigned long val; 5645 int any = 0, seth1; 5646 5647 str = txselect_list; 5648 ··· 5651 deflt = simple_strtoul(str, &nxt, 0); 5652 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5653 dd->pport[pidx].cpspec->no_eep = deflt; 5654 5655 while (*nxt && nxt[1]) { 5656 str = ++nxt; ··· 5678 ; 5679 continue; 5680 } 5681 - if (val >= TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ) 5682 continue; 5683 seth1 = 0; 5684 h1 = 0; /* gcc thinks it might be used uninitted */ ··· 5730 return -ENOSPC; 5731 } 5732 val = simple_strtoul(str, &n, 0); 5733 - if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { 5734 printk(KERN_INFO QIB_DRV_NAME 5735 "txselect_values must start with a number < %d\n", 5736 - TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); 5737 return -EINVAL; 5738 } 5739 strcpy(txselect_list, str); ··· 5880 unsigned n, regno; 5881 unsigned long flags; 5882 5883 - if (!dd->qpn_mask || !dd->pport[pidx].link_speed_supported) 5884 continue; 5885 5886 ppd = &dd->pport[pidx]; ··· 6168 ppd++; 6169 } 6170 6171 - dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE; 6172 - dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE; 6173 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); 6174 6175 /* we always allocate at least 2048 bytes for eager buffers */ ··· 6568 /* make sure we see an updated copy next time around */ 6569 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6570 sleeps++; 6571 - msleep(1); 6572 } 6573 6574 switch (which) { ··· 7066 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ 7067 }; 7068 7069 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 7070 unsigned atten) 7071 { ··· 7145 *sdr_dds = &txdds_extra_sdr[idx]; 7146 *ddr_dds = &txdds_extra_ddr[idx]; 7147 *qdr_dds = &txdds_extra_qdr[idx]; 7148 } else { 7149 /* this shouldn't happen, it's range checked */ 7150 *sdr_dds = txdds_sdr + qib_long_atten; ··· 7299 } 7300 } 7301 7302 static int serdes_7322_init(struct qib_pportdata *ppd) 7303 { 7304 - u64 data; 7305 u32 le_val; 7306 7307 /* ··· 7380 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7381 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7382 7383 - data = qib_read_kreg_port(ppd, krp_serdesctrl); 7384 - /* Turn off IB latency mode */ 7385 - data &= ~SYM_MASK(IBSerdesCtrl_0, IB_LAT_MODE); 7386 - qib_write_kreg_port(ppd, krp_serdesctrl, data | 7387 - SYM_MASK(IBSerdesCtrl_0, RXLOSEN)); 7388 7389 /* rxbistena; set 0 to avoid effects of it switch later */ 7390 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); ··· 7416 7417 /* Set the frequency loop bandwidth to 15 */ 7418 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); 7419 7420 return 0; 7421 }
··· 71 72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); 73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); 74 + static void serdes_7322_los_enable(struct qib_pportdata *, int); 75 + static int serdes_7322_init_old(struct qib_pportdata *); 76 + static int serdes_7322_init_new(struct qib_pportdata *); 77 78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb)) 79 ··· 110 static ushort qib_singleport; 111 module_param_named(singleport, qib_singleport, ushort, S_IRUGO); 112 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space"); 113 + 114 + /* 115 + * Receive header queue sizes 116 + */ 117 + static unsigned qib_rcvhdrcnt; 118 + module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); 119 + MODULE_PARM_DESC(rcvhdrcnt, "receive header count"); 120 + 121 + static unsigned qib_rcvhdrsize; 122 + module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); 123 + MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words"); 124 + 125 + static unsigned qib_rcvhdrentsize; 126 + module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); 127 + MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words"); 128 129 #define MAX_ATTEN_LEN 64 /* plenty for any real system */ 130 /* for read back, default index is ~5m copper cable */ ··· 544 545 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */ 546 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */ 547 + #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */ 548 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */ 549 550 #define H1_FORCE_VAL 8 ··· 604 u8 ibmalfusesnap; 605 struct qib_qsfp_data qsfp_data; 606 char epmsgbuf[192]; /* for port error interrupt msg buffer */ 607 + u8 bounced; 608 }; 609 610 static struct { ··· 1677 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) { 1678 force_h1(ppd); 1679 ppd->cpspec->qdr_reforce = 1; 1680 + if (!ppd->dd->cspec->r1) 1681 + serdes_7322_los_enable(ppd, 0); 1682 } else if (ppd->cpspec->qdr_reforce && 1683 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) && 1684 (ibclt == IB_7322_LT_STATE_CFGENH || ··· 1692 ibclt <= IB_7322_LT_STATE_SLEEPQUIET))) 1693 adj_tx_serdes(ppd); 1694 1695 + if (ibclt != IB_7322_LT_STATE_LINKUP) { 1696 + u8 ltstate = qib_7322_phys_portstate(ibcst); 1697 + u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, 1698 + LinkTrainingState); 1699 + if (!ppd->dd->cspec->r1 && 1700 + pibclt == IB_7322_LT_STATE_LINKUP && 1701 + ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER && 1702 + ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN && 1703 + ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1704 + ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1705 + /* If the link went down (but no into recovery, 1706 + * turn LOS back on */ 1707 + serdes_7322_los_enable(ppd, 1); 1708 + if (!ppd->cpspec->qdr_dfe_on && 1709 + ibclt <= IB_7322_LT_STATE_SLEEPQUIET) { 1710 + ppd->cpspec->qdr_dfe_on = 1; 1711 + ppd->cpspec->qdr_dfe_time = 0; 1712 + /* On link down, reenable QDR adaptation */ 1713 + qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 1714 + ppd->dd->cspec->r1 ? 1715 + QDR_STATIC_ADAPT_DOWN_R1 : 1716 + QDR_STATIC_ADAPT_DOWN); 1717 + printk(KERN_INFO QIB_DRV_NAME 1718 + " IB%u:%u re-enabled QDR adaptation " 1719 + "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt); 1720 + } 1721 } 1722 } 1723 + 1724 + static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); 1725 1726 /* 1727 * This is per-pport error handling. ··· 1840 IB_PHYSPORTSTATE_DISABLED) 1841 qib_set_ib_7322_lstate(ppd, 0, 1842 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); 1843 + else { 1844 + u32 lstate; 1845 + /* 1846 + * We need the current logical link state before 1847 + * lflags are set in handle_e_ibstatuschanged. 1848 + */ 1849 + lstate = qib_7322_iblink_state(ibcs); 1850 + 1851 + if (IS_QMH(dd) && !ppd->cpspec->bounced && 1852 + ltstate == IB_PHYSPORTSTATE_LINKUP && 1853 + (lstate >= IB_PORT_INIT && 1854 + lstate <= IB_PORT_ACTIVE)) { 1855 + ppd->cpspec->bounced = 1; 1856 + qib_7322_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE, 1857 + IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL); 1858 + } 1859 + 1860 /* 1861 * Since going into a recovery state causes the link 1862 * state to go down and since recovery is transitory, ··· 1854 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && 1855 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) 1856 qib_handle_e_ibstatuschanged(ppd, ibcs); 1857 + } 1858 } 1859 if (*msg && iserr) 1860 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); ··· 2785 ctxtrbits &= ~rmask; 2786 if (dd->rcd[i]) { 2787 qib_kreceive(dd->rcd[i], NULL, &npkts); 2788 } 2789 } 2790 rmask <<= 1; ··· 2835 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); 2836 2837 qib_kreceive(rcd, NULL, &npkts); 2838 2839 return IRQ_HANDLED; 2840 } ··· 3157 case BOARD_QME7342: 3158 n = "InfiniPath_QME7342"; 3159 break; 3160 + case 8: 3161 + n = "InfiniPath_QME7362"; 3162 + dd->flags |= QIB_HAS_QSFP; 3163 + break; 3164 case 15: 3165 n = "InfiniPath_QLE7342_TEST"; 3166 dd->flags |= QIB_HAS_QSFP; ··· 3475 nchipctxts = qib_read_kreg32(dd, kr_contextcnt); 3476 dd->cspec->numctxts = nchipctxts; 3477 if (qib_n_krcv_queues > 1 && dd->num_pports) { 3478 dd->first_user_ctxt = NUM_IB_PORTS + 3479 (qib_n_krcv_queues - 1) * dd->num_pports; 3480 if (dd->first_user_ctxt > nchipctxts) ··· 3530 3531 /* kr_rcvegrcnt changes based on the number of contexts enabled */ 3532 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); 3533 + if (qib_rcvhdrcnt) 3534 + dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); 3535 + else 3536 + dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, 3537 + dd->num_pports > 1 ? 1024U : 2048U); 3538 } 3539 3540 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) ··· 4002 } 4003 4004 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, 4005 + u32 updegr, u32 egrhd, u32 npkts) 4006 { 4007 + /* 4008 + * Need to write timeout register before updating rcvhdrhead to ensure 4009 + * that the timer is enabled on reception of a packet. 4010 + */ 4011 + if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT) 4012 + adjust_rcv_timeout(rcd, npkts); 4013 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4014 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); 4015 if (updegr) ··· 5522 u64 now = get_jiffies_64(); 5523 if (time_after64(now, pwrup)) 5524 break; 5525 + msleep(20); 5526 } 5527 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); 5528 /* ··· 5579 u32 pidx, unit, port, deflt, h1; 5580 unsigned long val; 5581 int any = 0, seth1; 5582 + int txdds_size; 5583 5584 str = txselect_list; 5585 ··· 5586 deflt = simple_strtoul(str, &nxt, 0); 5587 for (pidx = 0; pidx < dd->num_pports; ++pidx) 5588 dd->pport[pidx].cpspec->no_eep = deflt; 5589 + 5590 + txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ; 5591 + if (IS_QME(dd) || IS_QMH(dd)) 5592 + txdds_size += TXDDS_MFG_SZ; 5593 5594 while (*nxt && nxt[1]) { 5595 str = ++nxt; ··· 5609 ; 5610 continue; 5611 } 5612 + if (val >= txdds_size) 5613 continue; 5614 seth1 = 0; 5615 h1 = 0; /* gcc thinks it might be used uninitted */ ··· 5661 return -ENOSPC; 5662 } 5663 val = simple_strtoul(str, &n, 0); 5664 + if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 5665 + TXDDS_MFG_SZ)) { 5666 printk(KERN_INFO QIB_DRV_NAME 5667 "txselect_values must start with a number < %d\n", 5668 + TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ); 5669 return -EINVAL; 5670 } 5671 strcpy(txselect_list, str); ··· 5810 unsigned n, regno; 5811 unsigned long flags; 5812 5813 + if (dd->n_krcv_queues < 2 || 5814 + !dd->pport[pidx].link_speed_supported) 5815 continue; 5816 5817 ppd = &dd->pport[pidx]; ··· 6097 ppd++; 6098 } 6099 6100 + dd->rcvhdrentsize = qib_rcvhdrentsize ? 6101 + qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE; 6102 + dd->rcvhdrsize = qib_rcvhdrsize ? 6103 + qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE; 6104 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); 6105 6106 /* we always allocate at least 2048 bytes for eager buffers */ ··· 6495 /* make sure we see an updated copy next time around */ 6496 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); 6497 sleeps++; 6498 + msleep(20); 6499 } 6500 6501 switch (which) { ··· 6993 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */ 6994 }; 6995 6996 + static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = { 6997 + /* amp, pre, main, post */ 6998 + { 0, 0, 0, 0 }, /* QME7342 mfg settings */ 6999 + { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */ 7000 + }; 7001 + 7002 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, 7003 unsigned atten) 7004 { ··· 7066 *sdr_dds = &txdds_extra_sdr[idx]; 7067 *ddr_dds = &txdds_extra_ddr[idx]; 7068 *qdr_dds = &txdds_extra_qdr[idx]; 7069 + } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && 7070 + ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + 7071 + TXDDS_MFG_SZ)) { 7072 + idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); 7073 + printk(KERN_INFO QIB_DRV_NAME 7074 + " IB%u:%u use idx %u into txdds_mfg\n", 7075 + ppd->dd->unit, ppd->port, idx); 7076 + *sdr_dds = &txdds_extra_mfg[idx]; 7077 + *ddr_dds = &txdds_extra_mfg[idx]; 7078 + *qdr_dds = &txdds_extra_mfg[idx]; 7079 } else { 7080 /* this shouldn't happen, it's range checked */ 7081 *sdr_dds = txdds_sdr + qib_long_atten; ··· 7210 } 7211 } 7212 7213 + static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) 7214 + { 7215 + u64 data = qib_read_kreg_port(ppd, krp_serdesctrl); 7216 + printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS %s\n", 7217 + ppd->dd->unit, ppd->port, (enable ? "on" : "off")); 7218 + if (enable) 7219 + data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7220 + else 7221 + data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN); 7222 + qib_write_kreg_port(ppd, krp_serdesctrl, data); 7223 + } 7224 + 7225 static int serdes_7322_init(struct qib_pportdata *ppd) 7226 { 7227 + int ret = 0; 7228 + if (ppd->dd->cspec->r1) 7229 + ret = serdes_7322_init_old(ppd); 7230 + else 7231 + ret = serdes_7322_init_new(ppd); 7232 + return ret; 7233 + } 7234 + 7235 + static int serdes_7322_init_old(struct qib_pportdata *ppd) 7236 + { 7237 u32 le_val; 7238 7239 /* ··· 7270 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7271 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7272 7273 + serdes_7322_los_enable(ppd, 1); 7274 7275 /* rxbistena; set 0 to avoid effects of it switch later */ 7276 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15); ··· 7310 7311 /* Set the frequency loop bandwidth to 15 */ 7312 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5)); 7313 + 7314 + return 0; 7315 + } 7316 + 7317 + static int serdes_7322_init_new(struct qib_pportdata *ppd) 7318 + { 7319 + u64 tstart; 7320 + u32 le_val, rxcaldone; 7321 + int chan, chan_done = (1 << SERDES_CHANS) - 1; 7322 + 7323 + /* 7324 + * Initialize the Tx DDS tables. Also done every QSFP event, 7325 + * for adapters with QSFP 7326 + */ 7327 + init_txdds_table(ppd, 0); 7328 + 7329 + /* Clear cmode-override, may be set from older driver */ 7330 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); 7331 + 7332 + /* ensure no tx overrides from earlier driver loads */ 7333 + qib_write_kreg_port(ppd, krp_tx_deemph_override, 7334 + SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, 7335 + reset_tx_deemphasis_override)); 7336 + 7337 + /* START OF LSI SUGGESTED SERDES BRINGUP */ 7338 + /* Reset - Calibration Setup */ 7339 + /* Stop DFE adaptaion */ 7340 + ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1)); 7341 + /* Disable LE1 */ 7342 + ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5)); 7343 + /* Disable autoadapt for LE1 */ 7344 + ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15)); 7345 + /* Disable LE2 */ 7346 + ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6)); 7347 + /* Disable VGA */ 7348 + ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7349 + /* Disable AFE Offset Cancel */ 7350 + ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12)); 7351 + /* Disable Timing Loop */ 7352 + ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3)); 7353 + /* Disable Frequency Loop */ 7354 + ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4)); 7355 + /* Disable Baseline Wander Correction */ 7356 + ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13)); 7357 + /* Disable RX Calibration */ 7358 + ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7359 + /* Disable RX Offset Calibration */ 7360 + ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4)); 7361 + /* Select BB CDR */ 7362 + ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15)); 7363 + /* CDR Step Size */ 7364 + ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8)); 7365 + /* Enable phase Calibration */ 7366 + ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5)); 7367 + /* DFE Bandwidth [2:14-12] */ 7368 + ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12)); 7369 + /* DFE Config (4 taps only) */ 7370 + ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0)); 7371 + /* Gain Loop Bandwidth */ 7372 + if (!ppd->dd->cspec->r1) { 7373 + ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12)); 7374 + ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8)); 7375 + } else { 7376 + ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11)); 7377 + } 7378 + /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ 7379 + /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ 7380 + /* Data Rate Select [5:7-6] (leave as default) */ 7381 + /* RX Parralel Word Width [3:10-8] (leave as default) */ 7382 + 7383 + /* RX REST */ 7384 + /* Single- or Multi-channel reset */ 7385 + /* RX Analog reset */ 7386 + /* RX Digital reset */ 7387 + ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13)); 7388 + msleep(20); 7389 + /* RX Analog reset */ 7390 + ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14)); 7391 + msleep(20); 7392 + /* RX Digital reset */ 7393 + ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13)); 7394 + msleep(20); 7395 + 7396 + /* setup LoS params; these are subsystem, so chan == 5 */ 7397 + /* LoS filter threshold_count on, ch 0-3, set to 8 */ 7398 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); 7399 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); 7400 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); 7401 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); 7402 + 7403 + /* LoS filter threshold_count off, ch 0-3, set to 4 */ 7404 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); 7405 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); 7406 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); 7407 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); 7408 + 7409 + /* LoS filter select enabled */ 7410 + ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); 7411 + 7412 + /* LoS target data: SDR=4, DDR=2, QDR=1 */ 7413 + ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */ 7414 + ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */ 7415 + ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */ 7416 + 7417 + /* Turn on LOS on initial SERDES init */ 7418 + serdes_7322_los_enable(ppd, 1); 7419 + /* FLoop LOS gate: PPM filter enabled */ 7420 + ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10); 7421 + 7422 + /* RX LATCH CALIBRATION */ 7423 + /* Enable Eyefinder Phase Calibration latch */ 7424 + ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0)); 7425 + /* Enable RX Offset Calibration latch */ 7426 + ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4)); 7427 + msleep(20); 7428 + /* Start Calibration */ 7429 + ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10)); 7430 + tstart = get_jiffies_64(); 7431 + while (chan_done && 7432 + !time_after64(tstart, tstart + msecs_to_jiffies(500))) { 7433 + msleep(20); 7434 + for (chan = 0; chan < SERDES_CHANS; ++chan) { 7435 + rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7436 + (chan + (chan >> 1)), 7437 + 25, 0, 0); 7438 + if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 && 7439 + (~chan_done & (1 << chan)) == 0) 7440 + chan_done &= ~(1 << chan); 7441 + } 7442 + } 7443 + if (chan_done) { 7444 + printk(KERN_INFO QIB_DRV_NAME 7445 + " Serdes %d calibration not done after .5 sec: 0x%x\n", 7446 + IBSD(ppd->hw_pidx), chan_done); 7447 + } else { 7448 + for (chan = 0; chan < SERDES_CHANS; ++chan) { 7449 + rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 7450 + (chan + (chan >> 1)), 7451 + 25, 0, 0); 7452 + if ((~rxcaldone & (u32)BMASK(10, 10)) == 0) 7453 + printk(KERN_INFO QIB_DRV_NAME 7454 + " Serdes %d chan %d calibration " 7455 + "failed\n", IBSD(ppd->hw_pidx), chan); 7456 + } 7457 + } 7458 + 7459 + /* Turn off Calibration */ 7460 + ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10)); 7461 + msleep(20); 7462 + 7463 + /* BRING RX UP */ 7464 + /* Set LE2 value (May be overridden in qsfp_7322_event) */ 7465 + le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; 7466 + ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7)); 7467 + /* Set LE2 Loop bandwidth */ 7468 + ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5)); 7469 + /* Enable LE2 */ 7470 + ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6)); 7471 + msleep(20); 7472 + /* Enable H0 only */ 7473 + ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1)); 7474 + /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */ 7475 + le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; 7476 + ibsd_wr_allchans(ppd, 21, le_val, 0xfffe); 7477 + /* Enable VGA */ 7478 + ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0)); 7479 + msleep(20); 7480 + /* Set Frequency Loop Bandwidth */ 7481 + ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5)); 7482 + /* Enable Frequency Loop */ 7483 + ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4)); 7484 + /* Set Timing Loop Bandwidth */ 7485 + ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9)); 7486 + /* Enable Timing Loop */ 7487 + ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3)); 7488 + msleep(50); 7489 + /* Enable DFE 7490 + * Set receive adaptation mode. SDR and DDR adaptation are 7491 + * always on, and QDR is initially enabled; later disabled. 7492 + */ 7493 + qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL); 7494 + qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL); 7495 + qib_write_kreg_port(ppd, krp_static_adapt_dis(2), 7496 + ppd->dd->cspec->r1 ? 7497 + QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN); 7498 + ppd->cpspec->qdr_dfe_on = 1; 7499 + /* Disable LE1 */ 7500 + ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5)); 7501 + /* Disable auto adapt for LE1 */ 7502 + ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15)); 7503 + msleep(20); 7504 + /* Enable AFE Offset Cancel */ 7505 + ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12)); 7506 + /* Enable Baseline Wander Correction */ 7507 + ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13)); 7508 + /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */ 7509 + ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11)); 7510 + /* VGA output common mode */ 7511 + ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2)); 7512 7513 return 0; 7514 }
+4 -2
drivers/infiniband/hw/qib/qib_init.c
··· 92 /* set number of contexts we'll actually use */ 93 void qib_set_ctxtcnt(struct qib_devdata *dd) 94 { 95 - if (!qib_cfgctxts) 96 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus(); 97 - else if (qib_cfgctxts < dd->num_pports) 98 dd->cfgctxts = dd->ctxtcnt; 99 else if (qib_cfgctxts <= dd->ctxtcnt) 100 dd->cfgctxts = qib_cfgctxts;
··· 92 /* set number of contexts we'll actually use */ 93 void qib_set_ctxtcnt(struct qib_devdata *dd) 94 { 95 + if (!qib_cfgctxts) { 96 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus(); 97 + if (dd->cfgctxts > dd->ctxtcnt) 98 + dd->cfgctxts = dd->ctxtcnt; 99 + } else if (qib_cfgctxts < dd->num_pports) 100 dd->cfgctxts = dd->ctxtcnt; 101 else if (qib_cfgctxts <= dd->ctxtcnt) 102 dd->cfgctxts = qib_cfgctxts;
+2 -1
drivers/infiniband/hw/qib/qib_intr.c
··· 131 /* start a 75msec timer to clear symbol errors */ 132 mod_timer(&ppd->symerr_clear_timer, 133 msecs_to_jiffies(75)); 134 - } else if (ltstate == IB_PHYSPORTSTATE_LINKUP) { 135 /* active, but not active defered */ 136 qib_hol_up(ppd); /* useful only for 6120 now */ 137 *ppd->statusp |=
··· 131 /* start a 75msec timer to clear symbol errors */ 132 mod_timer(&ppd->symerr_clear_timer, 133 msecs_to_jiffies(75)); 134 + } else if (ltstate == IB_PHYSPORTSTATE_LINKUP && 135 + !(ppd->lflags & QIBL_LINKACTIVE)) { 136 /* active, but not active defered */ 137 qib_hol_up(ppd); /* useful only for 6120 now */ 138 *ppd->statusp |=
+56 -24
drivers/infiniband/hw/qib/qib_keys.c
··· 136 struct qib_mregion *mr; 137 unsigned n, m; 138 size_t off; 139 - int ret = 0; 140 unsigned long flags; 141 142 /* ··· 151 if (!dev->dma_mr) 152 goto bail; 153 atomic_inc(&dev->dma_mr->refcount); 154 isge->mr = dev->dma_mr; 155 isge->vaddr = (void *) sge->addr; 156 isge->length = sge->length; ··· 171 off + sge->length > mr->length || 172 (mr->access_flags & acc) != acc)) 173 goto bail; 174 175 off += mr->offset; 176 - m = 0; 177 - n = 0; 178 - while (off >= mr->map[m]->segs[n].length) { 179 - off -= mr->map[m]->segs[n].length; 180 - n++; 181 - if (n >= QIB_SEGSZ) { 182 - m++; 183 - n = 0; 184 } 185 } 186 - atomic_inc(&mr->refcount); 187 isge->mr = mr; 188 isge->vaddr = mr->map[m]->segs[n].vaddr + off; 189 isge->length = mr->map[m]->segs[n].length - off; ··· 206 isge->m = m; 207 isge->n = n; 208 ok: 209 - ret = 1; 210 bail: 211 spin_unlock_irqrestore(&rkt->lock, flags); 212 - return ret; 213 } 214 215 /** ··· 230 struct qib_mregion *mr; 231 unsigned n, m; 232 size_t off; 233 - int ret = 0; 234 unsigned long flags; 235 236 /* ··· 246 if (!dev->dma_mr) 247 goto bail; 248 atomic_inc(&dev->dma_mr->refcount); 249 sge->mr = dev->dma_mr; 250 sge->vaddr = (void *) vaddr; 251 sge->length = len; ··· 265 if (unlikely(vaddr < mr->iova || off + len > mr->length || 266 (mr->access_flags & acc) == 0)) 267 goto bail; 268 269 off += mr->offset; 270 - m = 0; 271 - n = 0; 272 - while (off >= mr->map[m]->segs[n].length) { 273 - off -= mr->map[m]->segs[n].length; 274 - n++; 275 - if (n >= QIB_SEGSZ) { 276 - m++; 277 - n = 0; 278 } 279 } 280 - atomic_inc(&mr->refcount); 281 sge->mr = mr; 282 sge->vaddr = mr->map[m]->segs[n].vaddr + off; 283 sge->length = mr->map[m]->segs[n].length - off; ··· 300 sge->m = m; 301 sge->n = n; 302 ok: 303 - ret = 1; 304 bail: 305 spin_unlock_irqrestore(&rkt->lock, flags); 306 - return ret; 307 } 308 309 /*
··· 136 struct qib_mregion *mr; 137 unsigned n, m; 138 size_t off; 139 unsigned long flags; 140 141 /* ··· 152 if (!dev->dma_mr) 153 goto bail; 154 atomic_inc(&dev->dma_mr->refcount); 155 + spin_unlock_irqrestore(&rkt->lock, flags); 156 + 157 isge->mr = dev->dma_mr; 158 isge->vaddr = (void *) sge->addr; 159 isge->length = sge->length; ··· 170 off + sge->length > mr->length || 171 (mr->access_flags & acc) != acc)) 172 goto bail; 173 + atomic_inc(&mr->refcount); 174 + spin_unlock_irqrestore(&rkt->lock, flags); 175 176 off += mr->offset; 177 + if (mr->page_shift) { 178 + /* 179 + page sizes are uniform power of 2 so no loop is necessary 180 + entries_spanned_by_off is the number of times the loop below 181 + would have executed. 182 + */ 183 + size_t entries_spanned_by_off; 184 + 185 + entries_spanned_by_off = off >> mr->page_shift; 186 + off -= (entries_spanned_by_off << mr->page_shift); 187 + m = entries_spanned_by_off/QIB_SEGSZ; 188 + n = entries_spanned_by_off%QIB_SEGSZ; 189 + } else { 190 + m = 0; 191 + n = 0; 192 + while (off >= mr->map[m]->segs[n].length) { 193 + off -= mr->map[m]->segs[n].length; 194 + n++; 195 + if (n >= QIB_SEGSZ) { 196 + m++; 197 + n = 0; 198 + } 199 } 200 } 201 isge->mr = mr; 202 isge->vaddr = mr->map[m]->segs[n].vaddr + off; 203 isge->length = mr->map[m]->segs[n].length - off; ··· 190 isge->m = m; 191 isge->n = n; 192 ok: 193 + return 1; 194 bail: 195 spin_unlock_irqrestore(&rkt->lock, flags); 196 + return 0; 197 } 198 199 /** ··· 214 struct qib_mregion *mr; 215 unsigned n, m; 216 size_t off; 217 unsigned long flags; 218 219 /* ··· 231 if (!dev->dma_mr) 232 goto bail; 233 atomic_inc(&dev->dma_mr->refcount); 234 + spin_unlock_irqrestore(&rkt->lock, flags); 235 + 236 sge->mr = dev->dma_mr; 237 sge->vaddr = (void *) vaddr; 238 sge->length = len; ··· 248 if (unlikely(vaddr < mr->iova || off + len > mr->length || 249 (mr->access_flags & acc) == 0)) 250 goto bail; 251 + atomic_inc(&mr->refcount); 252 + spin_unlock_irqrestore(&rkt->lock, flags); 253 254 off += mr->offset; 255 + if (mr->page_shift) { 256 + /* 257 + page sizes are uniform power of 2 so no loop is necessary 258 + entries_spanned_by_off is the number of times the loop below 259 + would have executed. 260 + */ 261 + size_t entries_spanned_by_off; 262 + 263 + entries_spanned_by_off = off >> mr->page_shift; 264 + off -= (entries_spanned_by_off << mr->page_shift); 265 + m = entries_spanned_by_off/QIB_SEGSZ; 266 + n = entries_spanned_by_off%QIB_SEGSZ; 267 + } else { 268 + m = 0; 269 + n = 0; 270 + while (off >= mr->map[m]->segs[n].length) { 271 + off -= mr->map[m]->segs[n].length; 272 + n++; 273 + if (n >= QIB_SEGSZ) { 274 + m++; 275 + n = 0; 276 + } 277 } 278 } 279 sge->mr = mr; 280 sge->vaddr = mr->map[m]->segs[n].vaddr + off; 281 sge->length = mr->map[m]->segs[n].length - off; ··· 268 sge->m = m; 269 sge->n = n; 270 ok: 271 + return 1; 272 bail: 273 spin_unlock_irqrestore(&rkt->lock, flags); 274 + return 0; 275 } 276 277 /*
+25 -20
drivers/infiniband/hw/qib/qib_mad.c
··· 668 lid = be16_to_cpu(pip->lid); 669 /* Must be a valid unicast LID address. */ 670 if (lid == 0 || lid >= QIB_MULTICAST_LID_BASE) 671 - goto err; 672 - if (ppd->lid != lid || ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) { 673 if (ppd->lid != lid) 674 qib_set_uevent_bits(ppd, _QIB_EVENT_LID_CHANGE_BIT); 675 if (ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) ··· 683 msl = pip->neighbormtu_mastersmsl & 0xF; 684 /* Must be a valid unicast LID address. */ 685 if (smlid == 0 || smlid >= QIB_MULTICAST_LID_BASE) 686 - goto err; 687 - if (smlid != ibp->sm_lid || msl != ibp->sm_sl) { 688 spin_lock_irqsave(&ibp->lock, flags); 689 if (ibp->sm_ah) { 690 if (smlid != ibp->sm_lid) ··· 707 if (lwe == 0xFF) 708 lwe = ppd->link_width_supported; 709 else if (lwe >= 16 || (lwe & ~ppd->link_width_supported)) 710 - goto err; 711 - set_link_width_enabled(ppd, lwe); 712 } 713 714 lse = pip->linkspeedactive_enabled & 0xF; ··· 722 if (lse == 15) 723 lse = ppd->link_speed_supported; 724 else if (lse >= 8 || (lse & ~ppd->link_speed_supported)) 725 - goto err; 726 - set_link_speed_enabled(ppd, lse); 727 } 728 729 /* Set link down default state. */ ··· 740 IB_LINKINITCMD_POLL); 741 break; 742 default: 743 - goto err; 744 } 745 746 ibp->mkeyprot = pip->mkeyprot_resv_lmc >> 6; ··· 750 751 mtu = ib_mtu_enum_to_int((pip->neighbormtu_mastersmsl >> 4) & 0xF); 752 if (mtu == -1) 753 - goto err; 754 - qib_set_mtu(ppd, mtu); 755 756 /* Set operational VLs */ 757 vls = (pip->operationalvl_pei_peo_fpi_fpo >> 4) & 0xF; 758 if (vls) { 759 if (vls > ppd->vls_supported) 760 - goto err; 761 - (void) dd->f_set_ib_cfg(ppd, QIB_IB_CFG_OP_VLS, vls); 762 } 763 764 if (pip->mkey_violations == 0) ··· 774 775 ore = pip->localphyerrors_overrunerrors; 776 if (set_phyerrthreshold(ppd, (ore >> 4) & 0xF)) 777 - goto err; 778 779 if (set_overrunthreshold(ppd, (ore & 0xF))) 780 - goto err; 781 782 ibp->subnet_timeout = pip->clientrereg_resv_subnetto & 0x1F; 783 ··· 796 state = pip->linkspeed_portstate & 0xF; 797 lstate = (pip->portphysstate_linkdown >> 4) & 0xF; 798 if (lstate && !(state == IB_PORT_DOWN || state == IB_PORT_NOP)) 799 - goto err; 800 801 /* 802 * Only state changes of DOWN, ARM, and ACTIVE are valid ··· 816 lstate = QIB_IB_LINKDOWN; 817 else if (lstate == 3) 818 lstate = QIB_IB_LINKDOWN_DISABLE; 819 - else 820 - goto err; 821 spin_lock_irqsave(&ppd->lflags_lock, flags); 822 ppd->lflags &= ~QIBL_LINKV; 823 spin_unlock_irqrestore(&ppd->lflags_lock, flags); ··· 841 qib_set_linkstate(ppd, QIB_IB_LINKACTIVE); 842 break; 843 default: 844 - /* XXX We have already partially updated our state! */ 845 - goto err; 846 } 847 848 ret = subn_get_portinfo(smp, ibdev, port);
··· 668 lid = be16_to_cpu(pip->lid); 669 /* Must be a valid unicast LID address. */ 670 if (lid == 0 || lid >= QIB_MULTICAST_LID_BASE) 671 + smp->status |= IB_SMP_INVALID_FIELD; 672 + else if (ppd->lid != lid || ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) { 673 if (ppd->lid != lid) 674 qib_set_uevent_bits(ppd, _QIB_EVENT_LID_CHANGE_BIT); 675 if (ppd->lmc != (pip->mkeyprot_resv_lmc & 7)) ··· 683 msl = pip->neighbormtu_mastersmsl & 0xF; 684 /* Must be a valid unicast LID address. */ 685 if (smlid == 0 || smlid >= QIB_MULTICAST_LID_BASE) 686 + smp->status |= IB_SMP_INVALID_FIELD; 687 + else if (smlid != ibp->sm_lid || msl != ibp->sm_sl) { 688 spin_lock_irqsave(&ibp->lock, flags); 689 if (ibp->sm_ah) { 690 if (smlid != ibp->sm_lid) ··· 707 if (lwe == 0xFF) 708 lwe = ppd->link_width_supported; 709 else if (lwe >= 16 || (lwe & ~ppd->link_width_supported)) 710 + smp->status |= IB_SMP_INVALID_FIELD; 711 + else if (lwe != ppd->link_width_enabled) 712 + set_link_width_enabled(ppd, lwe); 713 } 714 715 lse = pip->linkspeedactive_enabled & 0xF; ··· 721 if (lse == 15) 722 lse = ppd->link_speed_supported; 723 else if (lse >= 8 || (lse & ~ppd->link_speed_supported)) 724 + smp->status |= IB_SMP_INVALID_FIELD; 725 + else if (lse != ppd->link_speed_enabled) 726 + set_link_speed_enabled(ppd, lse); 727 } 728 729 /* Set link down default state. */ ··· 738 IB_LINKINITCMD_POLL); 739 break; 740 default: 741 + smp->status |= IB_SMP_INVALID_FIELD; 742 } 743 744 ibp->mkeyprot = pip->mkeyprot_resv_lmc >> 6; ··· 748 749 mtu = ib_mtu_enum_to_int((pip->neighbormtu_mastersmsl >> 4) & 0xF); 750 if (mtu == -1) 751 + smp->status |= IB_SMP_INVALID_FIELD; 752 + else 753 + qib_set_mtu(ppd, mtu); 754 755 /* Set operational VLs */ 756 vls = (pip->operationalvl_pei_peo_fpi_fpo >> 4) & 0xF; 757 if (vls) { 758 if (vls > ppd->vls_supported) 759 + smp->status |= IB_SMP_INVALID_FIELD; 760 + else 761 + (void) dd->f_set_ib_cfg(ppd, QIB_IB_CFG_OP_VLS, vls); 762 } 763 764 if (pip->mkey_violations == 0) ··· 770 771 ore = pip->localphyerrors_overrunerrors; 772 if (set_phyerrthreshold(ppd, (ore >> 4) & 0xF)) 773 + smp->status |= IB_SMP_INVALID_FIELD; 774 775 if (set_overrunthreshold(ppd, (ore & 0xF))) 776 + smp->status |= IB_SMP_INVALID_FIELD; 777 778 ibp->subnet_timeout = pip->clientrereg_resv_subnetto & 0x1F; 779 ··· 792 state = pip->linkspeed_portstate & 0xF; 793 lstate = (pip->portphysstate_linkdown >> 4) & 0xF; 794 if (lstate && !(state == IB_PORT_DOWN || state == IB_PORT_NOP)) 795 + smp->status |= IB_SMP_INVALID_FIELD; 796 797 /* 798 * Only state changes of DOWN, ARM, and ACTIVE are valid ··· 812 lstate = QIB_IB_LINKDOWN; 813 else if (lstate == 3) 814 lstate = QIB_IB_LINKDOWN_DISABLE; 815 + else { 816 + smp->status |= IB_SMP_INVALID_FIELD; 817 + break; 818 + } 819 spin_lock_irqsave(&ppd->lflags_lock, flags); 820 ppd->lflags &= ~QIBL_LINKV; 821 spin_unlock_irqrestore(&ppd->lflags_lock, flags); ··· 835 qib_set_linkstate(ppd, QIB_IB_LINKACTIVE); 836 break; 837 default: 838 + smp->status |= IB_SMP_INVALID_FIELD; 839 } 840 841 ret = subn_get_portinfo(smp, ibdev, port);
+5 -3
drivers/infiniband/hw/qib/qib_mr.c
··· 39 /* Fast memory region */ 40 struct qib_fmr { 41 struct ib_fmr ibfmr; 42 - u8 page_shift; 43 struct qib_mregion mr; /* must be last */ 44 }; 45 ··· 106 goto bail; 107 } 108 mr->mr.mapsz = m; 109 mr->mr.max_segs = count; 110 111 /* ··· 231 mr->mr.access_flags = mr_access_flags; 232 mr->umem = umem; 233 234 m = 0; 235 n = 0; 236 list_for_each_entry(chunk, &umem->chunk_list, list) { ··· 392 fmr->mr.offset = 0; 393 fmr->mr.access_flags = mr_access_flags; 394 fmr->mr.max_segs = fmr_attr->max_pages; 395 - fmr->page_shift = fmr_attr->page_shift; 396 397 atomic_set(&fmr->mr.refcount, 0); 398 ret = &fmr->ibfmr; ··· 439 spin_lock_irqsave(&rkt->lock, flags); 440 fmr->mr.user_base = iova; 441 fmr->mr.iova = iova; 442 - ps = 1 << fmr->page_shift; 443 fmr->mr.length = list_len * ps; 444 m = 0; 445 n = 0;
··· 39 /* Fast memory region */ 40 struct qib_fmr { 41 struct ib_fmr ibfmr; 42 struct qib_mregion mr; /* must be last */ 43 }; 44 ··· 107 goto bail; 108 } 109 mr->mr.mapsz = m; 110 + mr->mr.page_shift = 0; 111 mr->mr.max_segs = count; 112 113 /* ··· 231 mr->mr.access_flags = mr_access_flags; 232 mr->umem = umem; 233 234 + if (is_power_of_2(umem->page_size)) 235 + mr->mr.page_shift = ilog2(umem->page_size); 236 m = 0; 237 n = 0; 238 list_for_each_entry(chunk, &umem->chunk_list, list) { ··· 390 fmr->mr.offset = 0; 391 fmr->mr.access_flags = mr_access_flags; 392 fmr->mr.max_segs = fmr_attr->max_pages; 393 + fmr->mr.page_shift = fmr_attr->page_shift; 394 395 atomic_set(&fmr->mr.refcount, 0); 396 ret = &fmr->ibfmr; ··· 437 spin_lock_irqsave(&rkt->lock, flags); 438 fmr->mr.user_base = iova; 439 fmr->mr.iova = iova; 440 + ps = 1 << fmr->mr.page_shift; 441 fmr->mr.length = list_len * ps; 442 m = 0; 443 n = 0;
+15 -17
drivers/infiniband/hw/qib/qib_qp.c
··· 48 49 static inline unsigned find_next_offset(struct qib_qpn_table *qpt, 50 struct qpn_map *map, unsigned off, 51 - unsigned r) 52 { 53 if (qpt->mask) { 54 off++; 55 - if ((off & qpt->mask) >> 1 != r) 56 - off = ((off & qpt->mask) ? 57 - (off | qpt->mask) + 1 : off) | (r << 1); 58 } else 59 off = find_next_zero_bit(map->page, BITS_PER_PAGE, off); 60 return off; ··· 122 u32 i, offset, max_scan, qpn; 123 struct qpn_map *map; 124 u32 ret; 125 - int r; 126 127 if (type == IB_QPT_SMI || type == IB_QPT_GSI) { 128 unsigned n; ··· 137 goto bail; 138 } 139 140 - r = smp_processor_id(); 141 - if (r >= dd->n_krcv_queues) 142 - r %= dd->n_krcv_queues; 143 - qpn = qpt->last + 1; 144 if (qpn >= QPN_MAX) 145 qpn = 2; 146 - if (qpt->mask && ((qpn & qpt->mask) >> 1) != r) 147 - qpn = ((qpn & qpt->mask) ? (qpn | qpt->mask) + 1 : qpn) | 148 - (r << 1); 149 offset = qpn & BITS_PER_PAGE_MASK; 150 map = &qpt->map[qpn / BITS_PER_PAGE]; 151 max_scan = qpt->nmaps - !offset; ··· 157 ret = qpn; 158 goto bail; 159 } 160 - offset = find_next_offset(qpt, map, offset, r); 161 qpn = mk_qpn(qpt, map, offset); 162 /* 163 * This test differs from alloc_pidmap(). ··· 178 if (qpt->nmaps == QPNMAP_ENTRIES) 179 break; 180 map = &qpt->map[qpt->nmaps++]; 181 - offset = qpt->mask ? (r << 1) : 0; 182 } else if (map < &qpt->map[qpt->nmaps]) { 183 ++map; 184 - offset = qpt->mask ? (r << 1) : 0; 185 } else { 186 map = &qpt->map[0]; 187 - offset = qpt->mask ? (r << 1) : 2; 188 } 189 qpn = mk_qpn(qpt, map, offset); 190 } ··· 463 qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR); 464 del_timer(&qp->s_timer); 465 } 466 spin_lock(&dev->pending_lock); 467 if (!list_empty(&qp->iowait) && !(qp->s_flags & QIB_S_BUSY)) { 468 qp->s_flags &= ~QIB_S_ANY_WAIT_IO; ··· 1060 } 1061 qp->ibqp.qp_num = err; 1062 qp->port_num = init_attr->port_num; 1063 - qp->processor_id = smp_processor_id(); 1064 qib_reset_qp(qp, init_attr->qp_type); 1065 break; 1066
··· 48 49 static inline unsigned find_next_offset(struct qib_qpn_table *qpt, 50 struct qpn_map *map, unsigned off, 51 + unsigned n) 52 { 53 if (qpt->mask) { 54 off++; 55 + if (((off & qpt->mask) >> 1) >= n) 56 + off = (off | qpt->mask) + 2; 57 } else 58 off = find_next_zero_bit(map->page, BITS_PER_PAGE, off); 59 return off; ··· 123 u32 i, offset, max_scan, qpn; 124 struct qpn_map *map; 125 u32 ret; 126 127 if (type == IB_QPT_SMI || type == IB_QPT_GSI) { 128 unsigned n; ··· 139 goto bail; 140 } 141 142 + qpn = qpt->last + 2; 143 if (qpn >= QPN_MAX) 144 qpn = 2; 145 + if (qpt->mask && ((qpn & qpt->mask) >> 1) >= dd->n_krcv_queues) 146 + qpn = (qpn | qpt->mask) + 2; 147 offset = qpn & BITS_PER_PAGE_MASK; 148 map = &qpt->map[qpn / BITS_PER_PAGE]; 149 max_scan = qpt->nmaps - !offset; ··· 163 ret = qpn; 164 goto bail; 165 } 166 + offset = find_next_offset(qpt, map, offset, 167 + dd->n_krcv_queues); 168 qpn = mk_qpn(qpt, map, offset); 169 /* 170 * This test differs from alloc_pidmap(). ··· 183 if (qpt->nmaps == QPNMAP_ENTRIES) 184 break; 185 map = &qpt->map[qpt->nmaps++]; 186 + offset = 0; 187 } else if (map < &qpt->map[qpt->nmaps]) { 188 ++map; 189 + offset = 0; 190 } else { 191 map = &qpt->map[0]; 192 + offset = 2; 193 } 194 qpn = mk_qpn(qpt, map, offset); 195 } ··· 468 qp->s_flags &= ~(QIB_S_TIMER | QIB_S_WAIT_RNR); 469 del_timer(&qp->s_timer); 470 } 471 + 472 + if (qp->s_flags & QIB_S_ANY_WAIT_SEND) 473 + qp->s_flags &= ~QIB_S_ANY_WAIT_SEND; 474 + 475 spin_lock(&dev->pending_lock); 476 if (!list_empty(&qp->iowait) && !(qp->s_flags & QIB_S_BUSY)) { 477 qp->s_flags &= ~QIB_S_ANY_WAIT_IO; ··· 1061 } 1062 qp->ibqp.qp_num = err; 1063 qp->port_num = init_attr->port_num; 1064 qib_reset_qp(qp, init_attr->qp_type); 1065 break; 1066
+24
drivers/infiniband/hw/qib/qib_rc.c
··· 1407 struct qib_ctxtdata *rcd) 1408 { 1409 struct qib_swqe *wqe; 1410 enum ib_wc_status status; 1411 unsigned long flags; 1412 int diff; 1413 u32 pad; 1414 u32 aeth; 1415 u64 val; 1416 1417 spin_lock_irqsave(&qp->s_lock, flags); 1418
··· 1407 struct qib_ctxtdata *rcd) 1408 { 1409 struct qib_swqe *wqe; 1410 + struct qib_pportdata *ppd = ppd_from_ibp(ibp); 1411 enum ib_wc_status status; 1412 unsigned long flags; 1413 int diff; 1414 u32 pad; 1415 u32 aeth; 1416 u64 val; 1417 + 1418 + if (opcode != OP(RDMA_READ_RESPONSE_MIDDLE)) { 1419 + /* 1420 + * If ACK'd PSN on SDMA busy list try to make progress to 1421 + * reclaim SDMA credits. 1422 + */ 1423 + if ((qib_cmp24(psn, qp->s_sending_psn) >= 0) && 1424 + (qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)) { 1425 + 1426 + /* 1427 + * If send tasklet not running attempt to progress 1428 + * SDMA queue. 1429 + */ 1430 + if (!(qp->s_flags & QIB_S_BUSY)) { 1431 + /* Acquire SDMA Lock */ 1432 + spin_lock_irqsave(&ppd->sdma_lock, flags); 1433 + /* Invoke sdma make progress */ 1434 + qib_sdma_make_progress(ppd); 1435 + /* Release SDMA Lock */ 1436 + spin_unlock_irqrestore(&ppd->sdma_lock, flags); 1437 + } 1438 + } 1439 + } 1440 1441 spin_lock_irqsave(&qp->s_lock, flags); 1442
+25 -32
drivers/infiniband/hw/qib/qib_ud.c
··· 445 qkey = be32_to_cpu(ohdr->u.ud.deth[0]); 446 src_qp = be32_to_cpu(ohdr->u.ud.deth[1]) & QIB_QPN_MASK; 447 448 - /* Get the number of bytes the message was padded by. */ 449 pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3; 450 - if (unlikely(tlen < (hdrsize + pad + 4))) { 451 - /* Drop incomplete packets. */ 452 - ibp->n_pkt_drops++; 453 - goto bail; 454 - } 455 tlen -= hdrsize + pad + 4; 456 457 /* ··· 461 */ 462 if (qp->ibqp.qp_num) { 463 if (unlikely(hdr->lrh[1] == IB_LID_PERMISSIVE || 464 - hdr->lrh[3] == IB_LID_PERMISSIVE)) { 465 - ibp->n_pkt_drops++; 466 - goto bail; 467 - } 468 if (qp->ibqp.qp_num > 1) { 469 u16 pkey1, pkey2; 470 ··· 475 0xF, 476 src_qp, qp->ibqp.qp_num, 477 hdr->lrh[3], hdr->lrh[1]); 478 - goto bail; 479 } 480 } 481 if (unlikely(qkey != qp->qkey)) { ··· 483 (be16_to_cpu(hdr->lrh[0]) >> 4) & 0xF, 484 src_qp, qp->ibqp.qp_num, 485 hdr->lrh[3], hdr->lrh[1]); 486 - goto bail; 487 } 488 /* Drop invalid MAD packets (see 13.5.3.1). */ 489 if (unlikely(qp->ibqp.qp_num == 1 && 490 (tlen != 256 || 491 - (be16_to_cpu(hdr->lrh[0]) >> 12) == 15))) { 492 - ibp->n_pkt_drops++; 493 - goto bail; 494 - } 495 } else { 496 struct ib_smp *smp; 497 498 /* Drop invalid MAD packets (see 13.5.3.1). */ 499 - if (tlen != 256 || (be16_to_cpu(hdr->lrh[0]) >> 12) != 15) { 500 - ibp->n_pkt_drops++; 501 - goto bail; 502 - } 503 smp = (struct ib_smp *) data; 504 if ((hdr->lrh[1] == IB_LID_PERMISSIVE || 505 hdr->lrh[3] == IB_LID_PERMISSIVE) && 506 - smp->mgmt_class != IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) { 507 - ibp->n_pkt_drops++; 508 - goto bail; 509 - } 510 } 511 512 /* ··· 512 opcode == IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE) { 513 wc.ex.imm_data = ohdr->u.ud.imm_data; 514 wc.wc_flags = IB_WC_WITH_IMM; 515 - hdrsize += sizeof(u32); 516 } else if (opcode == IB_OPCODE_UD_SEND_ONLY) { 517 wc.ex.imm_data = 0; 518 wc.wc_flags = 0; 519 - } else { 520 - ibp->n_pkt_drops++; 521 - goto bail; 522 - } 523 524 /* 525 * A GRH is expected to preceed the data even if not ··· 547 /* Silently drop packets which are too big. */ 548 if (unlikely(wc.byte_len > qp->r_len)) { 549 qp->r_flags |= QIB_R_REUSE_SGE; 550 - ibp->n_pkt_drops++; 551 - return; 552 } 553 if (has_grh) { 554 qib_copy_sge(&qp->r_sge, &hdr->u.l.grh, ··· 584 qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc, 585 (ohdr->bth[0] & 586 cpu_to_be32(IB_BTH_SOLICITED)) != 0); 587 - bail:; 588 }
··· 445 qkey = be32_to_cpu(ohdr->u.ud.deth[0]); 446 src_qp = be32_to_cpu(ohdr->u.ud.deth[1]) & QIB_QPN_MASK; 447 448 + /* 449 + * Get the number of bytes the message was padded by 450 + * and drop incomplete packets. 451 + */ 452 pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3; 453 + if (unlikely(tlen < (hdrsize + pad + 4))) 454 + goto drop; 455 + 456 tlen -= hdrsize + pad + 4; 457 458 /* ··· 460 */ 461 if (qp->ibqp.qp_num) { 462 if (unlikely(hdr->lrh[1] == IB_LID_PERMISSIVE || 463 + hdr->lrh[3] == IB_LID_PERMISSIVE)) 464 + goto drop; 465 if (qp->ibqp.qp_num > 1) { 466 u16 pkey1, pkey2; 467 ··· 476 0xF, 477 src_qp, qp->ibqp.qp_num, 478 hdr->lrh[3], hdr->lrh[1]); 479 + return; 480 } 481 } 482 if (unlikely(qkey != qp->qkey)) { ··· 484 (be16_to_cpu(hdr->lrh[0]) >> 4) & 0xF, 485 src_qp, qp->ibqp.qp_num, 486 hdr->lrh[3], hdr->lrh[1]); 487 + return; 488 } 489 /* Drop invalid MAD packets (see 13.5.3.1). */ 490 if (unlikely(qp->ibqp.qp_num == 1 && 491 (tlen != 256 || 492 + (be16_to_cpu(hdr->lrh[0]) >> 12) == 15))) 493 + goto drop; 494 } else { 495 struct ib_smp *smp; 496 497 /* Drop invalid MAD packets (see 13.5.3.1). */ 498 + if (tlen != 256 || (be16_to_cpu(hdr->lrh[0]) >> 12) != 15) 499 + goto drop; 500 smp = (struct ib_smp *) data; 501 if ((hdr->lrh[1] == IB_LID_PERMISSIVE || 502 hdr->lrh[3] == IB_LID_PERMISSIVE) && 503 + smp->mgmt_class != IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) 504 + goto drop; 505 } 506 507 /* ··· 519 opcode == IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE) { 520 wc.ex.imm_data = ohdr->u.ud.imm_data; 521 wc.wc_flags = IB_WC_WITH_IMM; 522 + tlen -= sizeof(u32); 523 } else if (opcode == IB_OPCODE_UD_SEND_ONLY) { 524 wc.ex.imm_data = 0; 525 wc.wc_flags = 0; 526 + } else 527 + goto drop; 528 529 /* 530 * A GRH is expected to preceed the data even if not ··· 556 /* Silently drop packets which are too big. */ 557 if (unlikely(wc.byte_len > qp->r_len)) { 558 qp->r_flags |= QIB_R_REUSE_SGE; 559 + goto drop; 560 } 561 if (has_grh) { 562 qib_copy_sge(&qp->r_sge, &hdr->u.l.grh, ··· 594 qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc, 595 (ohdr->bth[0] & 596 cpu_to_be32(IB_BTH_SOLICITED)) != 0); 597 + return; 598 + 599 + drop: 600 + ibp->n_pkt_drops++; 601 }
+1
drivers/infiniband/hw/qib/qib_user_sdma.c
··· 382 383 kmem_cache_free(pq->pkt_slab, pkt); 384 } 385 } 386 387 /*
··· 382 383 kmem_cache_free(pq->pkt_slab, pkt); 384 } 385 + INIT_LIST_HEAD(list); 386 } 387 388 /*
+3 -8
drivers/infiniband/hw/qib/qib_verbs.h
··· 301 int access_flags; 302 u32 max_segs; /* number of qib_segs in all the arrays */ 303 u32 mapsz; /* size of the map array */ 304 atomic_t refcount; 305 struct qib_segarray *map[0]; /* the segments */ 306 }; ··· 436 spinlock_t r_lock; /* used for APM */ 437 spinlock_t s_lock; 438 atomic_t s_dma_busy; 439 - unsigned processor_id; /* Processor ID QP is bound to */ 440 u32 s_flags; 441 u32 s_cur_size; /* size of send packet in bytes */ 442 u32 s_len; /* total length of s_sge */ ··· 813 */ 814 static inline void qib_schedule_send(struct qib_qp *qp) 815 { 816 - if (qib_send_ok(qp)) { 817 - if (qp->processor_id == smp_processor_id()) 818 - queue_work(qib_wq, &qp->s_work); 819 - else 820 - queue_work_on(qp->processor_id, 821 - qib_wq, &qp->s_work); 822 - } 823 } 824 825 static inline int qib_pkey_ok(u16 pkey1, u16 pkey2)
··· 301 int access_flags; 302 u32 max_segs; /* number of qib_segs in all the arrays */ 303 u32 mapsz; /* size of the map array */ 304 + u8 page_shift; /* 0 - non unform/non powerof2 sizes */ 305 atomic_t refcount; 306 struct qib_segarray *map[0]; /* the segments */ 307 }; ··· 435 spinlock_t r_lock; /* used for APM */ 436 spinlock_t s_lock; 437 atomic_t s_dma_busy; 438 u32 s_flags; 439 u32 s_cur_size; /* size of send packet in bytes */ 440 u32 s_len; /* total length of s_sge */ ··· 813 */ 814 static inline void qib_schedule_send(struct qib_qp *qp) 815 { 816 + if (qib_send_ok(qp)) 817 + queue_work(qib_wq, &qp->s_work); 818 } 819 820 static inline int qib_pkey_ok(u16 pkey1, u16 pkey2)
-1
drivers/infiniband/ulp/ipoib/Kconfig
··· 1 config INFINIBAND_IPOIB 2 tristate "IP-over-InfiniBand" 3 depends on NETDEVICES && INET && (IPV6 || IPV6=n) 4 - select INET_LRO 5 ---help--- 6 Support for the IP-over-InfiniBand protocol (IPoIB). This 7 transports IP packets over InfiniBand so you can use your IB
··· 1 config INFINIBAND_IPOIB 2 tristate "IP-over-InfiniBand" 3 depends on NETDEVICES && INET && (IPV6 || IPV6=n) 4 ---help--- 5 Support for the IP-over-InfiniBand protocol (IPoIB). This 6 transports IP packets over InfiniBand so you can use your IB
+1 -11
drivers/infiniband/ulp/ipoib/ipoib.h
··· 50 #include <rdma/ib_verbs.h> 51 #include <rdma/ib_pack.h> 52 #include <rdma/ib_sa.h> 53 - #include <linux/inet_lro.h> 54 55 /* constants */ 56 ··· 99 IPOIB_MCAST_FLAG_SENDONLY = 1, 100 IPOIB_MCAST_FLAG_BUSY = 2, /* joining or already joined */ 101 IPOIB_MCAST_FLAG_ATTACHED = 3, 102 - 103 - IPOIB_MAX_LRO_DESCRIPTORS = 8, 104 - IPOIB_LRO_MAX_AGGR = 64, 105 106 MAX_SEND_CQE = 16, 107 IPOIB_CM_COPYBREAK = 256, ··· 259 u16 max_coalesced_frames; 260 }; 261 262 - struct ipoib_lro { 263 - struct net_lro_mgr lro_mgr; 264 - struct net_lro_desc lro_desc[IPOIB_MAX_LRO_DESCRIPTORS]; 265 - }; 266 - 267 /* 268 * Device private locking: network stack tx_lock protects members used 269 * in TX fast path, lock protects everything else. lock nests inside ··· 344 int hca_caps; 345 struct ipoib_ethtool_st ethtool; 346 struct timer_list poll_timer; 347 - 348 - struct ipoib_lro lro; 349 }; 350 351 struct ipoib_ah {
··· 50 #include <rdma/ib_verbs.h> 51 #include <rdma/ib_pack.h> 52 #include <rdma/ib_sa.h> 53 + #include <linux/sched.h> 54 55 /* constants */ 56 ··· 99 IPOIB_MCAST_FLAG_SENDONLY = 1, 100 IPOIB_MCAST_FLAG_BUSY = 2, /* joining or already joined */ 101 IPOIB_MCAST_FLAG_ATTACHED = 3, 102 103 MAX_SEND_CQE = 16, 104 IPOIB_CM_COPYBREAK = 256, ··· 262 u16 max_coalesced_frames; 263 }; 264 265 /* 266 * Device private locking: network stack tx_lock protects members used 267 * in TX fast path, lock protects everything else. lock nests inside ··· 352 int hca_caps; 353 struct ipoib_ethtool_st ethtool; 354 struct timer_list poll_timer; 355 }; 356 357 struct ipoib_ah {
+1
drivers/infiniband/ulp/ipoib/ipoib_cm.c
··· 1480 1481 if (test_bit(IPOIB_FLAG_CSUM, &priv->flags)) { 1482 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 1483 if (priv->hca_caps & IB_DEVICE_UD_TSO) 1484 dev->features |= NETIF_F_TSO; 1485 }
··· 1480 1481 if (test_bit(IPOIB_FLAG_CSUM, &priv->flags)) { 1482 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 1483 + priv->dev->features |= NETIF_F_GRO; 1484 if (priv->hca_caps & IB_DEVICE_UD_TSO) 1485 dev->features |= NETIF_F_TSO; 1486 }
-51
drivers/infiniband/ulp/ipoib/ipoib_ethtool.c
··· 106 return 0; 107 } 108 109 - static const char ipoib_stats_keys[][ETH_GSTRING_LEN] = { 110 - "LRO aggregated", "LRO flushed", 111 - "LRO avg aggr", "LRO no desc" 112 - }; 113 - 114 - static void ipoib_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 115 - { 116 - switch (stringset) { 117 - case ETH_SS_STATS: 118 - memcpy(data, *ipoib_stats_keys, sizeof(ipoib_stats_keys)); 119 - break; 120 - } 121 - } 122 - 123 - static int ipoib_get_sset_count(struct net_device *dev, int sset) 124 - { 125 - switch (sset) { 126 - case ETH_SS_STATS: 127 - return ARRAY_SIZE(ipoib_stats_keys); 128 - default: 129 - return -EOPNOTSUPP; 130 - } 131 - } 132 - 133 - static void ipoib_get_ethtool_stats(struct net_device *dev, 134 - struct ethtool_stats *stats, uint64_t *data) 135 - { 136 - struct ipoib_dev_priv *priv = netdev_priv(dev); 137 - int index = 0; 138 - 139 - /* Get LRO statistics */ 140 - data[index++] = priv->lro.lro_mgr.stats.aggregated; 141 - data[index++] = priv->lro.lro_mgr.stats.flushed; 142 - if (priv->lro.lro_mgr.stats.flushed) 143 - data[index++] = priv->lro.lro_mgr.stats.aggregated / 144 - priv->lro.lro_mgr.stats.flushed; 145 - else 146 - data[index++] = 0; 147 - data[index++] = priv->lro.lro_mgr.stats.no_desc; 148 - } 149 - 150 - static int ipoib_set_flags(struct net_device *dev, u32 flags) 151 - { 152 - return ethtool_op_set_flags(dev, flags, ETH_FLAG_LRO); 153 - } 154 - 155 static const struct ethtool_ops ipoib_ethtool_ops = { 156 .get_drvinfo = ipoib_get_drvinfo, 157 .get_rx_csum = ipoib_get_rx_csum, 158 .set_tso = ipoib_set_tso, 159 .get_coalesce = ipoib_get_coalesce, 160 .set_coalesce = ipoib_set_coalesce, 161 - .get_flags = ethtool_op_get_flags, 162 - .set_flags = ipoib_set_flags, 163 - .get_strings = ipoib_get_strings, 164 - .get_sset_count = ipoib_get_sset_count, 165 - .get_ethtool_stats = ipoib_get_ethtool_stats, 166 }; 167 168 void ipoib_set_ethtool_ops(struct net_device *dev)
··· 106 return 0; 107 } 108 109 static const struct ethtool_ops ipoib_ethtool_ops = { 110 .get_drvinfo = ipoib_get_drvinfo, 111 .get_rx_csum = ipoib_get_rx_csum, 112 .set_tso = ipoib_set_tso, 113 .get_coalesce = ipoib_get_coalesce, 114 .set_coalesce = ipoib_set_coalesce, 115 }; 116 117 void ipoib_set_ethtool_ops(struct net_device *dev)
+1 -7
drivers/infiniband/ulp/ipoib/ipoib_ib.c
··· 295 if (test_bit(IPOIB_FLAG_CSUM, &priv->flags) && likely(wc->csum_ok)) 296 skb->ip_summed = CHECKSUM_UNNECESSARY; 297 298 - if (dev->features & NETIF_F_LRO) 299 - lro_receive_skb(&priv->lro.lro_mgr, skb, NULL); 300 - else 301 - netif_receive_skb(skb); 302 303 repost: 304 if (unlikely(ipoib_ib_post_receive(dev, wr_id))) ··· 447 } 448 449 if (done < budget) { 450 - if (dev->features & NETIF_F_LRO) 451 - lro_flush_all(&priv->lro.lro_mgr); 452 - 453 napi_complete(napi); 454 if (unlikely(ib_req_notify_cq(priv->recv_cq, 455 IB_CQ_NEXT_COMP |
··· 295 if (test_bit(IPOIB_FLAG_CSUM, &priv->flags) && likely(wc->csum_ok)) 296 skb->ip_summed = CHECKSUM_UNNECESSARY; 297 298 + napi_gro_receive(&priv->napi, skb); 299 300 repost: 301 if (unlikely(ipoib_ib_post_receive(dev, wr_id))) ··· 450 } 451 452 if (done < budget) { 453 napi_complete(napi); 454 if (unlikely(ib_req_notify_cq(priv->recv_cq, 455 IB_CQ_NEXT_COMP |
+1 -61
drivers/infiniband/ulp/ipoib/ipoib_main.c
··· 60 module_param_named(recv_queue_size, ipoib_recvq_size, int, 0444); 61 MODULE_PARM_DESC(recv_queue_size, "Number of descriptors in receive queue"); 62 63 - static int lro; 64 - module_param(lro, bool, 0444); 65 - MODULE_PARM_DESC(lro, "Enable LRO (Large Receive Offload)"); 66 - 67 - static int lro_max_aggr = IPOIB_LRO_MAX_AGGR; 68 - module_param(lro_max_aggr, int, 0644); 69 - MODULE_PARM_DESC(lro_max_aggr, "LRO: Max packets to be aggregated " 70 - "(default = 64)"); 71 - 72 #ifdef CONFIG_INFINIBAND_IPOIB_DEBUG 73 int ipoib_debug_level; 74 ··· 967 .create = ipoib_hard_header, 968 }; 969 970 - static int get_skb_hdr(struct sk_buff *skb, void **iphdr, 971 - void **tcph, u64 *hdr_flags, void *priv) 972 - { 973 - unsigned int ip_len; 974 - struct iphdr *iph; 975 - 976 - if (unlikely(skb->protocol != htons(ETH_P_IP))) 977 - return -1; 978 - 979 - /* 980 - * In the future we may add an else clause that verifies the 981 - * checksum and allows devices which do not calculate checksum 982 - * to use LRO. 983 - */ 984 - if (unlikely(skb->ip_summed != CHECKSUM_UNNECESSARY)) 985 - return -1; 986 - 987 - /* Check for non-TCP packet */ 988 - skb_reset_network_header(skb); 989 - iph = ip_hdr(skb); 990 - if (iph->protocol != IPPROTO_TCP) 991 - return -1; 992 - 993 - ip_len = ip_hdrlen(skb); 994 - skb_set_transport_header(skb, ip_len); 995 - *tcph = tcp_hdr(skb); 996 - 997 - /* check if IP header and TCP header are complete */ 998 - if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb)) 999 - return -1; 1000 - 1001 - *hdr_flags = LRO_IPV4 | LRO_TCP; 1002 - *iphdr = iph; 1003 - 1004 - return 0; 1005 - } 1006 - 1007 - static void ipoib_lro_setup(struct ipoib_dev_priv *priv) 1008 - { 1009 - priv->lro.lro_mgr.max_aggr = lro_max_aggr; 1010 - priv->lro.lro_mgr.max_desc = IPOIB_MAX_LRO_DESCRIPTORS; 1011 - priv->lro.lro_mgr.lro_arr = priv->lro.lro_desc; 1012 - priv->lro.lro_mgr.get_skb_header = get_skb_hdr; 1013 - priv->lro.lro_mgr.features = LRO_F_NAPI; 1014 - priv->lro.lro_mgr.dev = priv->dev; 1015 - priv->lro.lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; 1016 - } 1017 - 1018 static const struct net_device_ops ipoib_netdev_ops = { 1019 .ndo_open = ipoib_open, 1020 .ndo_stop = ipoib_stop, ··· 1009 netif_carrier_off(dev); 1010 1011 priv->dev = dev; 1012 - 1013 - ipoib_lro_setup(priv); 1014 1015 spin_lock_init(&priv->lock); 1016 ··· 1159 priv->dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 1160 } 1161 1162 - if (lro) 1163 - priv->dev->features |= NETIF_F_LRO; 1164 1165 if (priv->dev->features & NETIF_F_SG && priv->hca_caps & IB_DEVICE_UD_TSO) 1166 priv->dev->features |= NETIF_F_TSO;
··· 60 module_param_named(recv_queue_size, ipoib_recvq_size, int, 0444); 61 MODULE_PARM_DESC(recv_queue_size, "Number of descriptors in receive queue"); 62 63 #ifdef CONFIG_INFINIBAND_IPOIB_DEBUG 64 int ipoib_debug_level; 65 ··· 976 .create = ipoib_hard_header, 977 }; 978 979 static const struct net_device_ops ipoib_netdev_ops = { 980 .ndo_open = ipoib_open, 981 .ndo_stop = ipoib_stop, ··· 1066 netif_carrier_off(dev); 1067 1068 priv->dev = dev; 1069 1070 spin_lock_init(&priv->lock); 1071 ··· 1218 priv->dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 1219 } 1220 1221 + priv->dev->features |= NETIF_F_GRO; 1222 1223 if (priv->dev->features & NETIF_F_SG && priv->hca_caps & IB_DEVICE_UD_TSO) 1224 priv->dev->features |= NETIF_F_TSO;
+181 -211
drivers/infiniband/ulp/srp/ib_srp.c
··· 441 wait_for_completion(&target->done); 442 } 443 444 static void srp_remove_work(struct work_struct *work) 445 { 446 struct srp_target_port *target = 447 container_of(work, struct srp_target_port, work); 448 449 - spin_lock_irq(target->scsi_host->host_lock); 450 - if (target->state != SRP_TARGET_DEAD) { 451 - spin_unlock_irq(target->scsi_host->host_lock); 452 return; 453 - } 454 - target->state = SRP_TARGET_REMOVED; 455 - spin_unlock_irq(target->scsi_host->host_lock); 456 457 spin_lock(&target->srp_host->target_lock); 458 list_del(&target->list); ··· 549 scsi_sg_count(scmnd), scmnd->sc_data_direction); 550 } 551 552 - static void srp_remove_req(struct srp_target_port *target, struct srp_request *req) 553 { 554 srp_unmap_data(req->scmnd, target, req); 555 - list_move_tail(&req->list, &target->free_reqs); 556 } 557 558 static void srp_reset_req(struct srp_target_port *target, struct srp_request *req) 559 { 560 req->scmnd->result = DID_RESET << 16; 561 req->scmnd->scsi_done(req->scmnd); 562 - srp_remove_req(target, req); 563 } 564 565 static int srp_reconnect_target(struct srp_target_port *target) 566 { 567 struct ib_qp_attr qp_attr; 568 - struct srp_request *req, *tmp; 569 struct ib_wc wc; 570 - int ret; 571 572 - spin_lock_irq(target->scsi_host->host_lock); 573 - if (target->state != SRP_TARGET_LIVE) { 574 - spin_unlock_irq(target->scsi_host->host_lock); 575 return -EAGAIN; 576 - } 577 - target->state = SRP_TARGET_CONNECTING; 578 - spin_unlock_irq(target->scsi_host->host_lock); 579 580 srp_disconnect_target(target); 581 /* ··· 601 while (ib_poll_cq(target->send_cq, 1, &wc) > 0) 602 ; /* nothing */ 603 604 - spin_lock_irq(target->scsi_host->host_lock); 605 - list_for_each_entry_safe(req, tmp, &target->req_queue, list) 606 - srp_reset_req(target, req); 607 - spin_unlock_irq(target->scsi_host->host_lock); 608 609 - target->rx_head = 0; 610 - target->tx_head = 0; 611 - target->tx_tail = 0; 612 613 target->qp_in_error = 0; 614 ret = srp_connect_target(target); 615 if (ret) 616 goto err; 617 618 - spin_lock_irq(target->scsi_host->host_lock); 619 - if (target->state == SRP_TARGET_CONNECTING) { 620 - ret = 0; 621 - target->state = SRP_TARGET_LIVE; 622 - } else 623 ret = -EAGAIN; 624 - spin_unlock_irq(target->scsi_host->host_lock); 625 626 return ret; 627 ··· 627 628 /* 629 * We couldn't reconnect, so kill our target port off. 630 - * However, we have to defer the real removal because we might 631 - * be in the context of the SCSI error handler now, which 632 - * would deadlock if we call scsi_remove_host(). 633 */ 634 - spin_lock_irq(target->scsi_host->host_lock); 635 if (target->state == SRP_TARGET_CONNECTING) { 636 target->state = SRP_TARGET_DEAD; 637 INIT_WORK(&target->work, srp_remove_work); 638 schedule_work(&target->work); 639 } 640 - spin_unlock_irq(target->scsi_host->host_lock); 641 642 return ret; 643 } ··· 768 struct srp_direct_buf *buf = (void *) cmd->add_data; 769 770 buf->va = cpu_to_be64(ib_sg_dma_address(ibdev, scat)); 771 - buf->key = cpu_to_be32(dev->mr->rkey); 772 buf->len = cpu_to_be32(ib_sg_dma_len(ibdev, scat)); 773 } else if (srp_map_fmr(target, scat, count, req, 774 (void *) cmd->add_data)) { ··· 793 buf->desc_list[i].va = 794 cpu_to_be64(ib_sg_dma_address(ibdev, sg)); 795 buf->desc_list[i].key = 796 - cpu_to_be32(dev->mr->rkey); 797 buf->desc_list[i].len = cpu_to_be32(dma_len); 798 datalen += dma_len; 799 } ··· 806 buf->table_desc.va = 807 cpu_to_be64(req->cmd->dma + sizeof *cmd + sizeof *buf); 808 buf->table_desc.key = 809 - cpu_to_be32(target->srp_host->srp_dev->mr->rkey); 810 buf->table_desc.len = 811 cpu_to_be32(count * sizeof (struct srp_direct_buf)); 812 ··· 822 } 823 824 /* 825 - * Must be called with target->scsi_host->host_lock held to protect 826 - * req_lim and tx_head. Lock cannot be dropped between call here and 827 - * call to __srp_post_send(). 828 * 829 * Note: 830 * An upper limit for the number of allocated information units for each ··· 857 858 srp_send_completion(target->send_cq, target); 859 860 - if (target->tx_head - target->tx_tail >= SRP_SQ_SIZE) 861 return NULL; 862 863 /* Initiator responses to target requests do not consume credits */ 864 - if (target->req_lim <= rsv && iu_type != SRP_IU_RSP) { 865 - ++target->zero_req_lim; 866 - return NULL; 867 } 868 869 - iu = target->tx_ring[target->tx_head & SRP_SQ_MASK]; 870 - iu->type = iu_type; 871 return iu; 872 } 873 874 - /* 875 - * Must be called with target->scsi_host->host_lock held to protect 876 - * req_lim and tx_head. 877 - */ 878 - static int __srp_post_send(struct srp_target_port *target, 879 - struct srp_iu *iu, int len) 880 { 881 struct ib_sge list; 882 struct ib_send_wr wr, *bad_wr; 883 - int ret = 0; 884 885 list.addr = iu->dma; 886 list.length = len; 887 - list.lkey = target->srp_host->srp_dev->mr->lkey; 888 889 wr.next = NULL; 890 - wr.wr_id = target->tx_head & SRP_SQ_MASK; 891 wr.sg_list = &list; 892 wr.num_sge = 1; 893 wr.opcode = IB_WR_SEND; 894 wr.send_flags = IB_SEND_SIGNALED; 895 896 - ret = ib_post_send(target->qp, &wr, &bad_wr); 897 - 898 - if (!ret) { 899 - ++target->tx_head; 900 - if (iu->type != SRP_IU_RSP) 901 - --target->req_lim; 902 - } 903 - 904 - return ret; 905 } 906 907 - static int srp_post_recv(struct srp_target_port *target) 908 { 909 - unsigned long flags; 910 - struct srp_iu *iu; 911 - struct ib_sge list; 912 struct ib_recv_wr wr, *bad_wr; 913 - unsigned int next; 914 - int ret; 915 - 916 - spin_lock_irqsave(target->scsi_host->host_lock, flags); 917 - 918 - next = target->rx_head & SRP_RQ_MASK; 919 - wr.wr_id = next; 920 - iu = target->rx_ring[next]; 921 922 list.addr = iu->dma; 923 list.length = iu->size; 924 - list.lkey = target->srp_host->srp_dev->mr->lkey; 925 926 wr.next = NULL; 927 wr.sg_list = &list; 928 wr.num_sge = 1; 929 930 - ret = ib_post_recv(target->qp, &wr, &bad_wr); 931 - if (!ret) 932 - ++target->rx_head; 933 - 934 - spin_unlock_irqrestore(target->scsi_host->host_lock, flags); 935 - 936 - return ret; 937 } 938 939 static void srp_process_rsp(struct srp_target_port *target, struct srp_rsp *rsp) ··· 917 struct srp_request *req; 918 struct scsi_cmnd *scmnd; 919 unsigned long flags; 920 - s32 delta; 921 - 922 - delta = (s32) be32_to_cpu(rsp->req_lim_delta); 923 - 924 - spin_lock_irqsave(target->scsi_host->host_lock, flags); 925 - 926 - target->req_lim += delta; 927 - 928 - req = &target->req_ring[rsp->tag & ~SRP_TAG_TSK_MGMT]; 929 930 if (unlikely(rsp->tag & SRP_TAG_TSK_MGMT)) { 931 - if (be32_to_cpu(rsp->resp_data_len) < 4) 932 - req->tsk_status = -1; 933 - else 934 - req->tsk_status = rsp->data[3]; 935 - complete(&req->done); 936 } else { 937 scmnd = req->scmnd; 938 if (!scmnd) 939 shost_printk(KERN_ERR, target->scsi_host, ··· 948 else if (rsp->flags & (SRP_RSP_FLAG_DIOVER | SRP_RSP_FLAG_DIUNDER)) 949 scsi_set_resid(scmnd, be32_to_cpu(rsp->data_in_res_cnt)); 950 951 - if (!req->tsk_mgmt) { 952 - scmnd->host_scribble = (void *) -1L; 953 - scmnd->scsi_done(scmnd); 954 - 955 - srp_remove_req(target, req); 956 - } else 957 - req->cmd_done = 1; 958 } 959 - 960 - spin_unlock_irqrestore(target->scsi_host->host_lock, flags); 961 } 962 963 static int srp_response_common(struct srp_target_port *target, s32 req_delta, 964 void *rsp, int len) 965 { 966 - struct ib_device *dev; 967 unsigned long flags; 968 struct srp_iu *iu; 969 - int err = 1; 970 971 - dev = target->srp_host->srp_dev->dev; 972 - 973 - spin_lock_irqsave(target->scsi_host->host_lock, flags); 974 target->req_lim += req_delta; 975 - 976 iu = __srp_get_tx_iu(target, SRP_IU_RSP); 977 if (!iu) { 978 shost_printk(KERN_ERR, target->scsi_host, PFX 979 "no IU available to send response\n"); 980 - goto out; 981 } 982 983 ib_dma_sync_single_for_cpu(dev, iu->dma, len, DMA_TO_DEVICE); 984 memcpy(iu->buf, rsp, len); 985 ib_dma_sync_single_for_device(dev, iu->dma, len, DMA_TO_DEVICE); 986 987 - err = __srp_post_send(target, iu, len); 988 - if (err) 989 shost_printk(KERN_ERR, target->scsi_host, PFX 990 "unable to post response: %d\n", err); 991 992 - out: 993 - spin_unlock_irqrestore(target->scsi_host->host_lock, flags); 994 return err; 995 } 996 ··· 1020 1021 static void srp_handle_recv(struct srp_target_port *target, struct ib_wc *wc) 1022 { 1023 - struct ib_device *dev; 1024 - struct srp_iu *iu; 1025 int res; 1026 u8 opcode; 1027 1028 - iu = target->rx_ring[wc->wr_id]; 1029 - 1030 - dev = target->srp_host->srp_dev->dev; 1031 ib_dma_sync_single_for_cpu(dev, iu->dma, target->max_ti_iu_len, 1032 DMA_FROM_DEVICE); 1033 ··· 1065 ib_dma_sync_single_for_device(dev, iu->dma, target->max_ti_iu_len, 1066 DMA_FROM_DEVICE); 1067 1068 - res = srp_post_recv(target); 1069 if (res != 0) 1070 shost_printk(KERN_ERR, target->scsi_host, 1071 PFX "Recv failed with error code %d\n", res); ··· 1094 { 1095 struct srp_target_port *target = target_ptr; 1096 struct ib_wc wc; 1097 1098 while (ib_poll_cq(cq, 1, &wc) > 0) { 1099 if (wc.status) { ··· 1105 break; 1106 } 1107 1108 - ++target->tx_tail; 1109 } 1110 } 1111 1112 - static int srp_queuecommand_lck(struct scsi_cmnd *scmnd, 1113 - void (*done)(struct scsi_cmnd *)) 1114 { 1115 - struct srp_target_port *target = host_to_target(scmnd->device->host); 1116 struct srp_request *req; 1117 struct srp_iu *iu; 1118 struct srp_cmd *cmd; 1119 struct ib_device *dev; 1120 int len; 1121 1122 if (target->state == SRP_TARGET_CONNECTING) ··· 1126 if (target->state == SRP_TARGET_DEAD || 1127 target->state == SRP_TARGET_REMOVED) { 1128 scmnd->result = DID_BAD_TARGET << 16; 1129 - done(scmnd); 1130 return 0; 1131 } 1132 1133 iu = __srp_get_tx_iu(target, SRP_IU_CMD); 1134 if (!iu) 1135 goto err; 1136 ··· 1146 ib_dma_sync_single_for_cpu(dev, iu->dma, srp_max_iu_len, 1147 DMA_TO_DEVICE); 1148 1149 - req = list_first_entry(&target->free_reqs, struct srp_request, list); 1150 - 1151 - scmnd->scsi_done = done; 1152 scmnd->result = 0; 1153 - scmnd->host_scribble = (void *) (long) req->index; 1154 1155 cmd = iu->buf; 1156 memset(cmd, 0, sizeof *cmd); ··· 1159 1160 req->scmnd = scmnd; 1161 req->cmd = iu; 1162 - req->cmd_done = 0; 1163 - req->tsk_mgmt = NULL; 1164 1165 len = srp_map_data(scmnd, target, req); 1166 if (len < 0) { 1167 shost_printk(KERN_ERR, target->scsi_host, 1168 PFX "Failed to map data\n"); 1169 - goto err; 1170 } 1171 1172 ib_dma_sync_single_for_device(dev, iu->dma, srp_max_iu_len, 1173 DMA_TO_DEVICE); 1174 1175 - if (__srp_post_send(target, iu, len)) { 1176 shost_printk(KERN_ERR, target->scsi_host, PFX "Send failed\n"); 1177 goto err_unmap; 1178 } 1179 - 1180 - list_move_tail(&req->list, &target->req_queue); 1181 1182 return 0; 1183 1184 err_unmap: 1185 srp_unmap_data(scmnd, target, req); 1186 1187 err: 1188 return SCSI_MLQUEUE_HOST_BUSY; 1189 } 1190 - 1191 - static DEF_SCSI_QCMD(srp_queuecommand) 1192 1193 static int srp_alloc_iu_bufs(struct srp_target_port *target) 1194 { ··· 1209 GFP_KERNEL, DMA_TO_DEVICE); 1210 if (!target->tx_ring[i]) 1211 goto err; 1212 } 1213 1214 return 0; ··· 1372 break; 1373 1374 for (i = 0; i < SRP_RQ_SIZE; i++) { 1375 - target->status = srp_post_recv(target); 1376 if (target->status) 1377 break; 1378 } ··· 1438 } 1439 1440 static int srp_send_tsk_mgmt(struct srp_target_port *target, 1441 - struct srp_request *req, u8 func) 1442 { 1443 struct ib_device *dev = target->srp_host->srp_dev->dev; 1444 struct srp_iu *iu; 1445 struct srp_tsk_mgmt *tsk_mgmt; 1446 1447 - spin_lock_irq(target->scsi_host->host_lock); 1448 - 1449 if (target->state == SRP_TARGET_DEAD || 1450 - target->state == SRP_TARGET_REMOVED) { 1451 - req->scmnd->result = DID_BAD_TARGET << 16; 1452 - goto out; 1453 - } 1454 1455 - init_completion(&req->done); 1456 1457 iu = __srp_get_tx_iu(target, SRP_IU_TSK_MGMT); 1458 if (!iu) 1459 - goto out; 1460 1461 ib_dma_sync_single_for_cpu(dev, iu->dma, sizeof *tsk_mgmt, 1462 DMA_TO_DEVICE); ··· 1463 memset(tsk_mgmt, 0, sizeof *tsk_mgmt); 1464 1465 tsk_mgmt->opcode = SRP_TSK_MGMT; 1466 - tsk_mgmt->lun = cpu_to_be64((u64) req->scmnd->device->lun << 48); 1467 - tsk_mgmt->tag = req->index | SRP_TAG_TSK_MGMT; 1468 tsk_mgmt->tsk_mgmt_func = func; 1469 - tsk_mgmt->task_tag = req->index; 1470 1471 ib_dma_sync_single_for_device(dev, iu->dma, sizeof *tsk_mgmt, 1472 DMA_TO_DEVICE); 1473 - if (__srp_post_send(target, iu, sizeof *tsk_mgmt)) 1474 - goto out; 1475 1476 - req->tsk_mgmt = iu; 1477 - 1478 - spin_unlock_irq(target->scsi_host->host_lock); 1479 - 1480 - if (!wait_for_completion_timeout(&req->done, 1481 msecs_to_jiffies(SRP_ABORT_TIMEOUT_MS))) 1482 return -1; 1483 - 1484 - return 0; 1485 - 1486 - out: 1487 - spin_unlock_irq(target->scsi_host->host_lock); 1488 - return -1; 1489 - } 1490 - 1491 - static int srp_find_req(struct srp_target_port *target, 1492 - struct scsi_cmnd *scmnd, 1493 - struct srp_request **req) 1494 - { 1495 - if (scmnd->host_scribble == (void *) -1L) 1496 - return -1; 1497 - 1498 - *req = &target->req_ring[(long) scmnd->host_scribble]; 1499 1500 return 0; 1501 } ··· 1485 static int srp_abort(struct scsi_cmnd *scmnd) 1486 { 1487 struct srp_target_port *target = host_to_target(scmnd->device->host); 1488 - struct srp_request *req; 1489 int ret = SUCCESS; 1490 1491 shost_printk(KERN_ERR, target->scsi_host, "SRP abort called\n"); 1492 1493 - if (target->qp_in_error) 1494 return FAILED; 1495 - if (srp_find_req(target, scmnd, &req)) 1496 - return FAILED; 1497 - if (srp_send_tsk_mgmt(target, req, SRP_TSK_ABORT_TASK)) 1498 return FAILED; 1499 1500 - spin_lock_irq(target->scsi_host->host_lock); 1501 - 1502 - if (req->cmd_done) { 1503 - srp_remove_req(target, req); 1504 - scmnd->scsi_done(scmnd); 1505 - } else if (!req->tsk_status) { 1506 - srp_remove_req(target, req); 1507 - scmnd->result = DID_ABORT << 16; 1508 - } else 1509 - ret = FAILED; 1510 - 1511 - spin_unlock_irq(target->scsi_host->host_lock); 1512 1513 return ret; 1514 } ··· 1510 static int srp_reset_device(struct scsi_cmnd *scmnd) 1511 { 1512 struct srp_target_port *target = host_to_target(scmnd->device->host); 1513 - struct srp_request *req, *tmp; 1514 1515 shost_printk(KERN_ERR, target->scsi_host, "SRP reset_device called\n"); 1516 1517 if (target->qp_in_error) 1518 return FAILED; 1519 - if (srp_find_req(target, scmnd, &req)) 1520 return FAILED; 1521 - if (srp_send_tsk_mgmt(target, req, SRP_TSK_LUN_RESET)) 1522 - return FAILED; 1523 - if (req->tsk_status) 1524 return FAILED; 1525 1526 - spin_lock_irq(target->scsi_host->host_lock); 1527 - 1528 - list_for_each_entry_safe(req, tmp, &target->req_queue, list) 1529 - if (req->scmnd->device == scmnd->device) 1530 srp_reset_req(target, req); 1531 - 1532 - spin_unlock_irq(target->scsi_host->host_lock); 1533 1534 return SUCCESS; 1535 } ··· 1955 target->io_class = SRP_REV16A_IB_IO_CLASS; 1956 target->scsi_host = target_host; 1957 target->srp_host = host; 1958 1959 INIT_LIST_HEAD(&target->free_reqs); 1960 - INIT_LIST_HEAD(&target->req_queue); 1961 for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) { 1962 target->req_ring[i].index = i; 1963 list_add_tail(&target->req_ring[i].list, &target->free_reqs); ··· 2188 */ 2189 spin_lock(&host->target_lock); 2190 list_for_each_entry(target, &host->target_list, list) { 2191 - spin_lock_irq(target->scsi_host->host_lock); 2192 target->state = SRP_TARGET_REMOVED; 2193 - spin_unlock_irq(target->scsi_host->host_lock); 2194 } 2195 spin_unlock(&host->target_lock); 2196 ··· 2229 { 2230 int ret; 2231 2232 - BUILD_BUG_ON_NOT_POWER_OF_2(SRP_SQ_SIZE); 2233 - BUILD_BUG_ON_NOT_POWER_OF_2(SRP_RQ_SIZE); 2234 2235 if (srp_sg_tablesize > 255) { 2236 printk(KERN_WARNING PFX "Clamping srp_sg_tablesize to 255\n");
··· 441 wait_for_completion(&target->done); 442 } 443 444 + static bool srp_change_state(struct srp_target_port *target, 445 + enum srp_target_state old, 446 + enum srp_target_state new) 447 + { 448 + bool changed = false; 449 + 450 + spin_lock_irq(&target->lock); 451 + if (target->state == old) { 452 + target->state = new; 453 + changed = true; 454 + } 455 + spin_unlock_irq(&target->lock); 456 + return changed; 457 + } 458 + 459 static void srp_remove_work(struct work_struct *work) 460 { 461 struct srp_target_port *target = 462 container_of(work, struct srp_target_port, work); 463 464 + if (!srp_change_state(target, SRP_TARGET_DEAD, SRP_TARGET_REMOVED)) 465 return; 466 467 spin_lock(&target->srp_host->target_lock); 468 list_del(&target->list); ··· 539 scsi_sg_count(scmnd), scmnd->sc_data_direction); 540 } 541 542 + static void srp_remove_req(struct srp_target_port *target, 543 + struct srp_request *req, s32 req_lim_delta) 544 { 545 + unsigned long flags; 546 + 547 srp_unmap_data(req->scmnd, target, req); 548 + spin_lock_irqsave(&target->lock, flags); 549 + target->req_lim += req_lim_delta; 550 + req->scmnd = NULL; 551 + list_add_tail(&req->list, &target->free_reqs); 552 + spin_unlock_irqrestore(&target->lock, flags); 553 } 554 555 static void srp_reset_req(struct srp_target_port *target, struct srp_request *req) 556 { 557 req->scmnd->result = DID_RESET << 16; 558 req->scmnd->scsi_done(req->scmnd); 559 + srp_remove_req(target, req, 0); 560 } 561 562 static int srp_reconnect_target(struct srp_target_port *target) 563 { 564 struct ib_qp_attr qp_attr; 565 struct ib_wc wc; 566 + int i, ret; 567 568 + if (!srp_change_state(target, SRP_TARGET_LIVE, SRP_TARGET_CONNECTING)) 569 return -EAGAIN; 570 571 srp_disconnect_target(target); 572 /* ··· 590 while (ib_poll_cq(target->send_cq, 1, &wc) > 0) 591 ; /* nothing */ 592 593 + for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) { 594 + struct srp_request *req = &target->req_ring[i]; 595 + if (req->scmnd) 596 + srp_reset_req(target, req); 597 + } 598 599 + INIT_LIST_HEAD(&target->free_tx); 600 + for (i = 0; i < SRP_SQ_SIZE; ++i) 601 + list_add(&target->tx_ring[i]->list, &target->free_tx); 602 603 target->qp_in_error = 0; 604 ret = srp_connect_target(target); 605 if (ret) 606 goto err; 607 608 + if (!srp_change_state(target, SRP_TARGET_CONNECTING, SRP_TARGET_LIVE)) 609 ret = -EAGAIN; 610 611 return ret; 612 ··· 620 621 /* 622 * We couldn't reconnect, so kill our target port off. 623 + * However, we have to defer the real removal because we 624 + * are in the context of the SCSI error handler now, which 625 + * will deadlock if we call scsi_remove_host(). 626 + * 627 + * Schedule our work inside the lock to avoid a race with 628 + * the flush_scheduled_work() in srp_remove_one(). 629 */ 630 + spin_lock_irq(&target->lock); 631 if (target->state == SRP_TARGET_CONNECTING) { 632 target->state = SRP_TARGET_DEAD; 633 INIT_WORK(&target->work, srp_remove_work); 634 schedule_work(&target->work); 635 } 636 + spin_unlock_irq(&target->lock); 637 638 return ret; 639 } ··· 758 struct srp_direct_buf *buf = (void *) cmd->add_data; 759 760 buf->va = cpu_to_be64(ib_sg_dma_address(ibdev, scat)); 761 + buf->key = cpu_to_be32(target->rkey); 762 buf->len = cpu_to_be32(ib_sg_dma_len(ibdev, scat)); 763 } else if (srp_map_fmr(target, scat, count, req, 764 (void *) cmd->add_data)) { ··· 783 buf->desc_list[i].va = 784 cpu_to_be64(ib_sg_dma_address(ibdev, sg)); 785 buf->desc_list[i].key = 786 + cpu_to_be32(target->rkey); 787 buf->desc_list[i].len = cpu_to_be32(dma_len); 788 datalen += dma_len; 789 } ··· 796 buf->table_desc.va = 797 cpu_to_be64(req->cmd->dma + sizeof *cmd + sizeof *buf); 798 buf->table_desc.key = 799 + cpu_to_be32(target->rkey); 800 buf->table_desc.len = 801 cpu_to_be32(count * sizeof (struct srp_direct_buf)); 802 ··· 812 } 813 814 /* 815 + * Return an IU and possible credit to the free pool 816 + */ 817 + static void srp_put_tx_iu(struct srp_target_port *target, struct srp_iu *iu, 818 + enum srp_iu_type iu_type) 819 + { 820 + unsigned long flags; 821 + 822 + spin_lock_irqsave(&target->lock, flags); 823 + list_add(&iu->list, &target->free_tx); 824 + if (iu_type != SRP_IU_RSP) 825 + ++target->req_lim; 826 + spin_unlock_irqrestore(&target->lock, flags); 827 + } 828 + 829 + /* 830 + * Must be called with target->lock held to protect req_lim and free_tx. 831 + * If IU is not sent, it must be returned using srp_put_tx_iu(). 832 * 833 * Note: 834 * An upper limit for the number of allocated information units for each ··· 833 834 srp_send_completion(target->send_cq, target); 835 836 + if (list_empty(&target->free_tx)) 837 return NULL; 838 839 /* Initiator responses to target requests do not consume credits */ 840 + if (iu_type != SRP_IU_RSP) { 841 + if (target->req_lim <= rsv) { 842 + ++target->zero_req_lim; 843 + return NULL; 844 + } 845 + 846 + --target->req_lim; 847 } 848 849 + iu = list_first_entry(&target->free_tx, struct srp_iu, list); 850 + list_del(&iu->list); 851 return iu; 852 } 853 854 + static int srp_post_send(struct srp_target_port *target, 855 + struct srp_iu *iu, int len) 856 { 857 struct ib_sge list; 858 struct ib_send_wr wr, *bad_wr; 859 860 list.addr = iu->dma; 861 list.length = len; 862 + list.lkey = target->lkey; 863 864 wr.next = NULL; 865 + wr.wr_id = (uintptr_t) iu; 866 wr.sg_list = &list; 867 wr.num_sge = 1; 868 wr.opcode = IB_WR_SEND; 869 wr.send_flags = IB_SEND_SIGNALED; 870 871 + return ib_post_send(target->qp, &wr, &bad_wr); 872 } 873 874 + static int srp_post_recv(struct srp_target_port *target, struct srp_iu *iu) 875 { 876 struct ib_recv_wr wr, *bad_wr; 877 + struct ib_sge list; 878 879 list.addr = iu->dma; 880 list.length = iu->size; 881 + list.lkey = target->lkey; 882 883 wr.next = NULL; 884 + wr.wr_id = (uintptr_t) iu; 885 wr.sg_list = &list; 886 wr.num_sge = 1; 887 888 + return ib_post_recv(target->qp, &wr, &bad_wr); 889 } 890 891 static void srp_process_rsp(struct srp_target_port *target, struct srp_rsp *rsp) ··· 917 struct srp_request *req; 918 struct scsi_cmnd *scmnd; 919 unsigned long flags; 920 921 if (unlikely(rsp->tag & SRP_TAG_TSK_MGMT)) { 922 + spin_lock_irqsave(&target->lock, flags); 923 + target->req_lim += be32_to_cpu(rsp->req_lim_delta); 924 + spin_unlock_irqrestore(&target->lock, flags); 925 + 926 + target->tsk_mgmt_status = -1; 927 + if (be32_to_cpu(rsp->resp_data_len) >= 4) 928 + target->tsk_mgmt_status = rsp->data[3]; 929 + complete(&target->tsk_mgmt_done); 930 } else { 931 + req = &target->req_ring[rsp->tag]; 932 scmnd = req->scmnd; 933 if (!scmnd) 934 shost_printk(KERN_ERR, target->scsi_host, ··· 953 else if (rsp->flags & (SRP_RSP_FLAG_DIOVER | SRP_RSP_FLAG_DIUNDER)) 954 scsi_set_resid(scmnd, be32_to_cpu(rsp->data_in_res_cnt)); 955 956 + srp_remove_req(target, req, be32_to_cpu(rsp->req_lim_delta)); 957 + scmnd->host_scribble = NULL; 958 + scmnd->scsi_done(scmnd); 959 } 960 } 961 962 static int srp_response_common(struct srp_target_port *target, s32 req_delta, 963 void *rsp, int len) 964 { 965 + struct ib_device *dev = target->srp_host->srp_dev->dev; 966 unsigned long flags; 967 struct srp_iu *iu; 968 + int err; 969 970 + spin_lock_irqsave(&target->lock, flags); 971 target->req_lim += req_delta; 972 iu = __srp_get_tx_iu(target, SRP_IU_RSP); 973 + spin_unlock_irqrestore(&target->lock, flags); 974 + 975 if (!iu) { 976 shost_printk(KERN_ERR, target->scsi_host, PFX 977 "no IU available to send response\n"); 978 + return 1; 979 } 980 981 ib_dma_sync_single_for_cpu(dev, iu->dma, len, DMA_TO_DEVICE); 982 memcpy(iu->buf, rsp, len); 983 ib_dma_sync_single_for_device(dev, iu->dma, len, DMA_TO_DEVICE); 984 985 + err = srp_post_send(target, iu, len); 986 + if (err) { 987 shost_printk(KERN_ERR, target->scsi_host, PFX 988 "unable to post response: %d\n", err); 989 + srp_put_tx_iu(target, iu, SRP_IU_RSP); 990 + } 991 992 return err; 993 } 994 ··· 1032 1033 static void srp_handle_recv(struct srp_target_port *target, struct ib_wc *wc) 1034 { 1035 + struct ib_device *dev = target->srp_host->srp_dev->dev; 1036 + struct srp_iu *iu = (struct srp_iu *) wc->wr_id; 1037 int res; 1038 u8 opcode; 1039 1040 ib_dma_sync_single_for_cpu(dev, iu->dma, target->max_ti_iu_len, 1041 DMA_FROM_DEVICE); 1042 ··· 1080 ib_dma_sync_single_for_device(dev, iu->dma, target->max_ti_iu_len, 1081 DMA_FROM_DEVICE); 1082 1083 + res = srp_post_recv(target, iu); 1084 if (res != 0) 1085 shost_printk(KERN_ERR, target->scsi_host, 1086 PFX "Recv failed with error code %d\n", res); ··· 1109 { 1110 struct srp_target_port *target = target_ptr; 1111 struct ib_wc wc; 1112 + struct srp_iu *iu; 1113 1114 while (ib_poll_cq(cq, 1, &wc) > 0) { 1115 if (wc.status) { ··· 1119 break; 1120 } 1121 1122 + iu = (struct srp_iu *) wc.wr_id; 1123 + list_add(&iu->list, &target->free_tx); 1124 } 1125 } 1126 1127 + static int srp_queuecommand(struct Scsi_Host *shost, struct scsi_cmnd *scmnd) 1128 { 1129 + struct srp_target_port *target = host_to_target(shost); 1130 struct srp_request *req; 1131 struct srp_iu *iu; 1132 struct srp_cmd *cmd; 1133 struct ib_device *dev; 1134 + unsigned long flags; 1135 int len; 1136 1137 if (target->state == SRP_TARGET_CONNECTING) ··· 1139 if (target->state == SRP_TARGET_DEAD || 1140 target->state == SRP_TARGET_REMOVED) { 1141 scmnd->result = DID_BAD_TARGET << 16; 1142 + scmnd->scsi_done(scmnd); 1143 return 0; 1144 } 1145 1146 + spin_lock_irqsave(&target->lock, flags); 1147 iu = __srp_get_tx_iu(target, SRP_IU_CMD); 1148 + if (iu) { 1149 + req = list_first_entry(&target->free_reqs, struct srp_request, 1150 + list); 1151 + list_del(&req->list); 1152 + } 1153 + spin_unlock_irqrestore(&target->lock, flags); 1154 + 1155 if (!iu) 1156 goto err; 1157 ··· 1151 ib_dma_sync_single_for_cpu(dev, iu->dma, srp_max_iu_len, 1152 DMA_TO_DEVICE); 1153 1154 scmnd->result = 0; 1155 + scmnd->host_scribble = (void *) req; 1156 1157 cmd = iu->buf; 1158 memset(cmd, 0, sizeof *cmd); ··· 1167 1168 req->scmnd = scmnd; 1169 req->cmd = iu; 1170 1171 len = srp_map_data(scmnd, target, req); 1172 if (len < 0) { 1173 shost_printk(KERN_ERR, target->scsi_host, 1174 PFX "Failed to map data\n"); 1175 + goto err_iu; 1176 } 1177 1178 ib_dma_sync_single_for_device(dev, iu->dma, srp_max_iu_len, 1179 DMA_TO_DEVICE); 1180 1181 + if (srp_post_send(target, iu, len)) { 1182 shost_printk(KERN_ERR, target->scsi_host, PFX "Send failed\n"); 1183 goto err_unmap; 1184 } 1185 1186 return 0; 1187 1188 err_unmap: 1189 srp_unmap_data(scmnd, target, req); 1190 1191 + err_iu: 1192 + srp_put_tx_iu(target, iu, SRP_IU_CMD); 1193 + 1194 + spin_lock_irqsave(&target->lock, flags); 1195 + list_add(&req->list, &target->free_reqs); 1196 + spin_unlock_irqrestore(&target->lock, flags); 1197 + 1198 err: 1199 return SCSI_MLQUEUE_HOST_BUSY; 1200 } 1201 1202 static int srp_alloc_iu_bufs(struct srp_target_port *target) 1203 { ··· 1216 GFP_KERNEL, DMA_TO_DEVICE); 1217 if (!target->tx_ring[i]) 1218 goto err; 1219 + 1220 + list_add(&target->tx_ring[i]->list, &target->free_tx); 1221 } 1222 1223 return 0; ··· 1377 break; 1378 1379 for (i = 0; i < SRP_RQ_SIZE; i++) { 1380 + struct srp_iu *iu = target->rx_ring[i]; 1381 + target->status = srp_post_recv(target, iu); 1382 if (target->status) 1383 break; 1384 } ··· 1442 } 1443 1444 static int srp_send_tsk_mgmt(struct srp_target_port *target, 1445 + u64 req_tag, unsigned int lun, u8 func) 1446 { 1447 struct ib_device *dev = target->srp_host->srp_dev->dev; 1448 struct srp_iu *iu; 1449 struct srp_tsk_mgmt *tsk_mgmt; 1450 1451 if (target->state == SRP_TARGET_DEAD || 1452 + target->state == SRP_TARGET_REMOVED) 1453 + return -1; 1454 1455 + init_completion(&target->tsk_mgmt_done); 1456 1457 + spin_lock_irq(&target->lock); 1458 iu = __srp_get_tx_iu(target, SRP_IU_TSK_MGMT); 1459 + spin_unlock_irq(&target->lock); 1460 + 1461 if (!iu) 1462 + return -1; 1463 1464 ib_dma_sync_single_for_cpu(dev, iu->dma, sizeof *tsk_mgmt, 1465 DMA_TO_DEVICE); ··· 1468 memset(tsk_mgmt, 0, sizeof *tsk_mgmt); 1469 1470 tsk_mgmt->opcode = SRP_TSK_MGMT; 1471 + tsk_mgmt->lun = cpu_to_be64((u64) lun << 48); 1472 + tsk_mgmt->tag = req_tag | SRP_TAG_TSK_MGMT; 1473 tsk_mgmt->tsk_mgmt_func = func; 1474 + tsk_mgmt->task_tag = req_tag; 1475 1476 ib_dma_sync_single_for_device(dev, iu->dma, sizeof *tsk_mgmt, 1477 DMA_TO_DEVICE); 1478 + if (srp_post_send(target, iu, sizeof *tsk_mgmt)) { 1479 + srp_put_tx_iu(target, iu, SRP_IU_TSK_MGMT); 1480 + return -1; 1481 + } 1482 1483 + if (!wait_for_completion_timeout(&target->tsk_mgmt_done, 1484 msecs_to_jiffies(SRP_ABORT_TIMEOUT_MS))) 1485 return -1; 1486 1487 return 0; 1488 } ··· 1508 static int srp_abort(struct scsi_cmnd *scmnd) 1509 { 1510 struct srp_target_port *target = host_to_target(scmnd->device->host); 1511 + struct srp_request *req = (struct srp_request *) scmnd->host_scribble; 1512 int ret = SUCCESS; 1513 1514 shost_printk(KERN_ERR, target->scsi_host, "SRP abort called\n"); 1515 1516 + if (!req || target->qp_in_error) 1517 return FAILED; 1518 + if (srp_send_tsk_mgmt(target, req->index, scmnd->device->lun, 1519 + SRP_TSK_ABORT_TASK)) 1520 return FAILED; 1521 1522 + if (req->scmnd) { 1523 + if (!target->tsk_mgmt_status) { 1524 + srp_remove_req(target, req, 0); 1525 + scmnd->result = DID_ABORT << 16; 1526 + } else 1527 + ret = FAILED; 1528 + } 1529 1530 return ret; 1531 } ··· 1539 static int srp_reset_device(struct scsi_cmnd *scmnd) 1540 { 1541 struct srp_target_port *target = host_to_target(scmnd->device->host); 1542 + int i; 1543 1544 shost_printk(KERN_ERR, target->scsi_host, "SRP reset_device called\n"); 1545 1546 if (target->qp_in_error) 1547 return FAILED; 1548 + if (srp_send_tsk_mgmt(target, SRP_TAG_NO_REQ, scmnd->device->lun, 1549 + SRP_TSK_LUN_RESET)) 1550 return FAILED; 1551 + if (target->tsk_mgmt_status) 1552 return FAILED; 1553 1554 + for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) { 1555 + struct srp_request *req = &target->req_ring[i]; 1556 + if (req->scmnd && req->scmnd->device == scmnd->device) 1557 srp_reset_req(target, req); 1558 + } 1559 1560 return SUCCESS; 1561 } ··· 1987 target->io_class = SRP_REV16A_IB_IO_CLASS; 1988 target->scsi_host = target_host; 1989 target->srp_host = host; 1990 + target->lkey = host->srp_dev->mr->lkey; 1991 + target->rkey = host->srp_dev->mr->rkey; 1992 1993 + spin_lock_init(&target->lock); 1994 + INIT_LIST_HEAD(&target->free_tx); 1995 INIT_LIST_HEAD(&target->free_reqs); 1996 for (i = 0; i < SRP_CMD_SQ_SIZE; ++i) { 1997 target->req_ring[i].index = i; 1998 list_add_tail(&target->req_ring[i].list, &target->free_reqs); ··· 2217 */ 2218 spin_lock(&host->target_lock); 2219 list_for_each_entry(target, &host->target_list, list) { 2220 + spin_lock_irq(&target->lock); 2221 target->state = SRP_TARGET_REMOVED; 2222 + spin_unlock_irq(&target->lock); 2223 } 2224 spin_unlock(&host->target_lock); 2225 ··· 2258 { 2259 int ret; 2260 2261 + BUILD_BUG_ON(FIELD_SIZEOF(struct ib_wc, wr_id) < sizeof(void *)); 2262 2263 if (srp_sg_tablesize > 255) { 2264 printk(KERN_WARNING PFX "Clamping srp_sg_tablesize to 255\n");
+25 -21
drivers/infiniband/ulp/srp/ib_srp.h
··· 59 60 SRP_RQ_SHIFT = 6, 61 SRP_RQ_SIZE = 1 << SRP_RQ_SHIFT, 62 - SRP_RQ_MASK = SRP_RQ_SIZE - 1, 63 64 SRP_SQ_SIZE = SRP_RQ_SIZE, 65 - SRP_SQ_MASK = SRP_SQ_SIZE - 1, 66 SRP_RSP_SQ_SIZE = 1, 67 SRP_REQ_SQ_SIZE = SRP_SQ_SIZE - SRP_RSP_SQ_SIZE, 68 SRP_TSK_MGMT_SQ_SIZE = 1, 69 SRP_CMD_SQ_SIZE = SRP_REQ_SQ_SIZE - SRP_TSK_MGMT_SQ_SIZE, 70 71 - SRP_TAG_TSK_MGMT = 1 << (SRP_RQ_SHIFT + 1), 72 73 SRP_FMR_SIZE = 256, 74 SRP_FMR_POOL_SIZE = 1024, ··· 112 struct list_head list; 113 struct scsi_cmnd *scmnd; 114 struct srp_iu *cmd; 115 - struct srp_iu *tsk_mgmt; 116 struct ib_pool_fmr *fmr; 117 - struct completion done; 118 short index; 119 - u8 cmd_done; 120 - u8 tsk_status; 121 }; 122 123 struct srp_target_port { 124 __be64 id_ext; 125 __be64 ioc_guid; 126 __be64 service_id; ··· 151 int path_query_id; 152 153 struct ib_cm_id *cm_id; 154 - struct ib_cq *recv_cq; 155 - struct ib_cq *send_cq; 156 - struct ib_qp *qp; 157 158 int max_ti_iu_len; 159 - s32 req_lim; 160 161 int zero_req_lim; 162 163 - unsigned rx_head; 164 - struct srp_iu *rx_ring[SRP_RQ_SIZE]; 165 - 166 - unsigned tx_head; 167 - unsigned tx_tail; 168 struct srp_iu *tx_ring[SRP_SQ_SIZE]; 169 - 170 - struct list_head free_reqs; 171 - struct list_head req_queue; 172 struct srp_request req_ring[SRP_CMD_SQ_SIZE]; 173 174 struct work_struct work; ··· 165 struct list_head list; 166 struct completion done; 167 int status; 168 - enum srp_target_state state; 169 int qp_in_error; 170 }; 171 172 struct srp_iu { 173 u64 dma; 174 void *buf; 175 size_t size; 176 enum dma_data_direction direction; 177 - enum srp_iu_type type; 178 }; 179 180 #endif /* IB_SRP_H */
··· 59 60 SRP_RQ_SHIFT = 6, 61 SRP_RQ_SIZE = 1 << SRP_RQ_SHIFT, 62 63 SRP_SQ_SIZE = SRP_RQ_SIZE, 64 SRP_RSP_SQ_SIZE = 1, 65 SRP_REQ_SQ_SIZE = SRP_SQ_SIZE - SRP_RSP_SQ_SIZE, 66 SRP_TSK_MGMT_SQ_SIZE = 1, 67 SRP_CMD_SQ_SIZE = SRP_REQ_SQ_SIZE - SRP_TSK_MGMT_SQ_SIZE, 68 69 + SRP_TAG_NO_REQ = ~0U, 70 + SRP_TAG_TSK_MGMT = 1U << 31, 71 72 SRP_FMR_SIZE = 256, 73 SRP_FMR_POOL_SIZE = 1024, ··· 113 struct list_head list; 114 struct scsi_cmnd *scmnd; 115 struct srp_iu *cmd; 116 struct ib_pool_fmr *fmr; 117 short index; 118 }; 119 120 struct srp_target_port { 121 + /* These are RW in the hot path, and commonly used together */ 122 + struct list_head free_tx; 123 + struct list_head free_reqs; 124 + spinlock_t lock; 125 + s32 req_lim; 126 + 127 + /* These are read-only in the hot path */ 128 + struct ib_cq *send_cq ____cacheline_aligned_in_smp; 129 + struct ib_cq *recv_cq; 130 + struct ib_qp *qp; 131 + u32 lkey; 132 + u32 rkey; 133 + enum srp_target_state state; 134 + 135 + /* Everything above this point is used in the hot path of 136 + * command processing. Try to keep them packed into cachelines. 137 + */ 138 + 139 __be64 id_ext; 140 __be64 ioc_guid; 141 __be64 service_id; ··· 138 int path_query_id; 139 140 struct ib_cm_id *cm_id; 141 142 int max_ti_iu_len; 143 144 int zero_req_lim; 145 146 struct srp_iu *tx_ring[SRP_SQ_SIZE]; 147 + struct srp_iu *rx_ring[SRP_RQ_SIZE]; 148 struct srp_request req_ring[SRP_CMD_SQ_SIZE]; 149 150 struct work_struct work; ··· 163 struct list_head list; 164 struct completion done; 165 int status; 166 int qp_in_error; 167 + 168 + struct completion tsk_mgmt_done; 169 + u8 tsk_mgmt_status; 170 }; 171 172 struct srp_iu { 173 + struct list_head list; 174 u64 dma; 175 void *buf; 176 size_t size; 177 enum dma_data_direction direction; 178 }; 179 180 #endif /* IB_SRP_H */
+2 -1
drivers/net/mlx4/alloc.c
··· 178 } else { 179 int i; 180 181 buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE; 182 buf->npages = buf->nbufs; 183 buf->page_shift = PAGE_SHIFT; ··· 230 dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf, 231 buf->direct.map); 232 else { 233 - if (BITS_PER_LONG == 64) 234 vunmap(buf->direct.buf); 235 236 for (i = 0; i < buf->nbufs; ++i)
··· 178 } else { 179 int i; 180 181 + buf->direct.buf = NULL; 182 buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE; 183 buf->npages = buf->nbufs; 184 buf->page_shift = PAGE_SHIFT; ··· 229 dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf, 230 buf->direct.map); 231 else { 232 + if (BITS_PER_LONG == 64 && buf->direct.buf) 233 vunmap(buf->direct.buf); 234 235 for (i = 0; i < buf->nbufs; ++i)
+1 -3
drivers/net/mlx4/fw.c
··· 289 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 290 dev_cap->bf_reg_size = 1 << (field & 0x1f); 291 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 292 - if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) { 293 - mlx4_warn(dev, "firmware bug: log2 # of blue flame regs is invalid (%d), forcing 3\n", field & 0x1f); 294 field = 3; 295 - } 296 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 297 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 298 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
··· 289 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 290 dev_cap->bf_reg_size = 1 << (field & 0x1f); 291 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 292 + if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 293 field = 3; 294 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 295 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 296 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);