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linux
Staging: iio: Prefer using the BIT macro
This patch replaces bit shifting on 1 with the BIT(x) macro
as it's extensively used by other function in this driver.
This was done with coccinelle:
@@ int g; @@
-(1 << g)
+BIT(g)
Signed-off-by: Cristina Opriceana <cristina.opriceana@gmail.com>
Reviewed-by: Daniel Baluta <daniel.baluta@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Cristina Opriceana
and committed by
Greg Kroah-Hartman
f1d05b5f
6970791f
+27
-27
+1
-1
drivers/staging/iio/frequency/ad9832.c
+1
-1
drivers/staging/iio/frequency/ad9832.c
···
59
59
static int ad9832_write_phase(struct ad9832_state *st,
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unsigned long addr, unsigned long phase)
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{
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-
if (phase > (1 << AD9832_PHASE_BITS))
62
+
if (phase > BIT(AD9832_PHASE_BITS))
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return -EINVAL;
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st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
+6
-6
drivers/staging/iio/frequency/ad9832.h
+6
-6
drivers/staging/iio/frequency/ad9832.h
···
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42
#define AD9832_CMD_SYNCSELSRC 0x8
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#define AD9832_CMD_SLEEPRESCLR 0xC
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-
#define AD9832_FREQ (1 << 11)
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+
#define AD9832_FREQ BIT(11)
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#define AD9832_PHASE(x) (((x) & 3) << 9)
47
-
#define AD9832_SYNC (1 << 13)
48
-
#define AD9832_SELSRC (1 << 12)
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-
#define AD9832_SLEEP (1 << 13)
50
-
#define AD9832_RESET (1 << 12)
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-
#define AD9832_CLR (1 << 11)
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+
#define AD9832_SYNC BIT(13)
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+
#define AD9832_SELSRC BIT(12)
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+
#define AD9832_SLEEP BIT(13)
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+
#define AD9832_RESET BIT(12)
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+
#define AD9832_CLR BIT(11)
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#define CMD_SHIFT 12
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#define ADD_SHIFT 8
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#define AD9832_FREQ_BITS 32
+2
-2
drivers/staging/iio/frequency/ad9834.c
+2
-2
drivers/staging/iio/frequency/ad9834.c
···
27
27
28
28
static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
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{
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-
unsigned long long freqreg = (u64)fout * (u64)(1 << AD9834_FREQ_BITS);
30
+
unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
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do_div(freqreg, mclk);
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return freqreg;
···
55
55
static int ad9834_write_phase(struct ad9834_state *st,
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unsigned long addr, unsigned long phase)
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{
58
-
if (phase > (1 << AD9834_PHASE_BITS))
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+
if (phase > BIT(AD9834_PHASE_BITS))
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return -EINVAL;
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st->data = cpu_to_be16(addr | phase);
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61
+18
-18
drivers/staging/iio/frequency/ad9834.h
+18
-18
drivers/staging/iio/frequency/ad9834.h
···
10
10
11
11
/* Registers */
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12
13
-
#define AD9834_REG_CMD (0 << 14)
14
-
#define AD9834_REG_FREQ0 (1 << 14)
15
-
#define AD9834_REG_FREQ1 (2 << 14)
16
-
#define AD9834_REG_PHASE0 (6 << 13)
17
-
#define AD9834_REG_PHASE1 (7 << 13)
13
+
#define AD9834_REG_CMD 0
14
+
#define AD9834_REG_FREQ0 BIT(14)
15
+
#define AD9834_REG_FREQ1 BIT(15)
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+
#define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
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+
#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
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/* Command Control Bits */
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-
#define AD9834_B28 (1 << 13)
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-
#define AD9834_HLB (1 << 12)
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-
#define AD9834_FSEL (1 << 11)
24
-
#define AD9834_PSEL (1 << 10)
25
-
#define AD9834_PIN_SW (1 << 9)
26
-
#define AD9834_RESET (1 << 8)
27
-
#define AD9834_SLEEP1 (1 << 7)
28
-
#define AD9834_SLEEP12 (1 << 6)
29
-
#define AD9834_OPBITEN (1 << 5)
30
-
#define AD9834_SIGN_PIB (1 << 4)
31
-
#define AD9834_DIV2 (1 << 3)
32
-
#define AD9834_MODE (1 << 1)
21
+
#define AD9834_B28 BIT(13)
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+
#define AD9834_HLB BIT(12)
23
+
#define AD9834_FSEL BIT(11)
24
+
#define AD9834_PSEL BIT(10)
25
+
#define AD9834_PIN_SW BIT(9)
26
+
#define AD9834_RESET BIT(8)
27
+
#define AD9834_SLEEP1 BIT(7)
28
+
#define AD9834_SLEEP12 BIT(6)
29
+
#define AD9834_OPBITEN BIT(5)
30
+
#define AD9834_SIGN_PIB BIT(4)
31
+
#define AD9834_DIV2 BIT(3)
32
+
#define AD9834_MODE BIT(1)
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34
#define AD9834_FREQ_BITS 28
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#define AD9834_PHASE_BITS 12
36
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37
-
#define RES_MASK(bits) ((1 << (bits)) - 1)
37
+
#define RES_MASK(bits) (BIT(bits) - 1)
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/**
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* struct ad9834_state - driver instance specific data