Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: rts5208: Remove unused driver

Wei Wang from Realsil contributed this driver in 2011.

The following reasons lead to the removal:
- This driver generates maintenance workload
- Did not find minimal documentation on the web.
- No blog entries about anyone using the rts5208 and rts5288 during the
last years.
- Did not find any device that may has it in and is still available on
the market.

Link: https://lore.kernel.org/linux-staging/2024100943-shank-washed-a765@gregkh/T/#t
Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/20241009193250.6211-1-philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Philipp Hortmann and committed by
Greg Kroah-Hartman
f11192a2 31d2ad61

-23686
-2
drivers/staging/Kconfig
··· 30 30 31 31 source "drivers/staging/rtl8712/Kconfig" 32 32 33 - source "drivers/staging/rts5208/Kconfig" 34 - 35 33 source "drivers/staging/octeon/Kconfig" 36 34 37 35 source "drivers/staging/vt6655/Kconfig"
-1
drivers/staging/Makefile
··· 5 5 obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/ 6 6 obj-$(CONFIG_RTL8723BS) += rtl8723bs/ 7 7 obj-$(CONFIG_R8712U) += rtl8712/ 8 - obj-$(CONFIG_RTS5208) += rts5208/ 9 8 obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ 10 9 obj-$(CONFIG_VT6655) += vt6655/ 11 10 obj-$(CONFIG_VT6656) += vt6656/
-9
drivers/staging/rts5208/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - config RTS5208 3 - tristate "Realtek PCI-E Card Reader RTS5208/5288 support" 4 - depends on PCI && SCSI 5 - help 6 - Say Y here to include driver code to support the Realtek 7 - PCI-E card reader rts5208/rts5288. 8 - 9 - If this driver is compiled as a module, it will be named rts5208.
-5
drivers/staging/rts5208/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - obj-$(CONFIG_RTS5208) := rts5208.o 3 - 4 - rts5208-y := rtsx.o rtsx_chip.o rtsx_transport.o rtsx_scsi.o \ 5 - rtsx_card.o general.o sd.o xd.o ms.o spi.o
-7
drivers/staging/rts5208/TODO
··· 1 - TODO: 2 - - use kernel coding style 3 - - checkpatch.pl fixes 4 - - We will use the stack in drivers/mmc to implement 5 - rts5208/5288 in the future 6 - 7 - Micky Ching <micky_ching@realsil.com.cn>
-25
drivers/staging/rts5208/general.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include "general.h" 13 - 14 - int bit1cnt_long(u32 data) 15 - { 16 - int i, cnt = 0; 17 - 18 - for (i = 0; i < 32; i++) { 19 - if (data & 0x01) 20 - cnt++; 21 - data >>= 1; 22 - } 23 - return cnt; 24 - } 25 -
-19
drivers/staging/rts5208/general.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __RTSX_GENERAL_H 13 - #define __RTSX_GENERAL_H 14 - 15 - #include "rtsx.h" 16 - 17 - int bit1cnt_long(u32 data); 18 - 19 - #endif /* __RTSX_GENERAL_H */
-4311
drivers/staging/rts5208/ms.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/vmalloc.h> 16 - 17 - #include "rtsx.h" 18 - #include "ms.h" 19 - 20 - static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 21 - { 22 - struct ms_info *ms_card = &chip->ms_card; 23 - 24 - ms_card->err_code = err_code; 25 - } 26 - 27 - static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 28 - { 29 - struct ms_info *ms_card = &chip->ms_card; 30 - 31 - return (ms_card->err_code == err_code); 32 - } 33 - 34 - static int ms_parse_err_code(struct rtsx_chip *chip) 35 - { 36 - return STATUS_FAIL; 37 - } 38 - 39 - static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 40 - u8 tpc, u8 cnt, u8 cfg) 41 - { 42 - struct ms_info *ms_card = &chip->ms_card; 43 - int retval; 44 - u8 *ptr; 45 - 46 - dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 47 - 48 - rtsx_init_cmd(chip); 49 - 50 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 51 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 52 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 53 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 54 - 0x01, PINGPONG_BUFFER); 55 - 56 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 57 - 0xFF, MS_TRANSFER_START | trans_mode); 58 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 59 - MS_TRANSFER_END, MS_TRANSFER_END); 60 - 61 - rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 62 - 63 - retval = rtsx_send_cmd(chip, MS_CARD, 5000); 64 - if (retval < 0) { 65 - rtsx_clear_ms_error(chip); 66 - ms_set_err_code(chip, MS_TO_ERROR); 67 - return ms_parse_err_code(chip); 68 - } 69 - 70 - ptr = rtsx_get_cmd_data(chip) + 1; 71 - 72 - if (!(tpc & 0x08)) { /* Read Packet */ 73 - if (*ptr & MS_CRC16_ERR) { 74 - ms_set_err_code(chip, MS_CRC16_ERROR); 75 - return ms_parse_err_code(chip); 76 - } 77 - } else { /* Write Packet */ 78 - if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 79 - if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 80 - ms_set_err_code(chip, MS_CMD_NK); 81 - return ms_parse_err_code(chip); 82 - } 83 - } 84 - } 85 - 86 - if (*ptr & MS_RDY_TIMEOUT) { 87 - rtsx_clear_ms_error(chip); 88 - ms_set_err_code(chip, MS_TO_ERROR); 89 - return ms_parse_err_code(chip); 90 - } 91 - 92 - return STATUS_SUCCESS; 93 - } 94 - 95 - static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 96 - u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 97 - int use_sg, void *buf, int buf_len) 98 - { 99 - int retval; 100 - u8 val, err_code = 0; 101 - enum dma_data_direction dir; 102 - 103 - if (!buf || !buf_len) 104 - return STATUS_FAIL; 105 - 106 - if (trans_mode == MS_TM_AUTO_READ) { 107 - dir = DMA_FROM_DEVICE; 108 - err_code = MS_FLASH_READ_ERROR; 109 - } else if (trans_mode == MS_TM_AUTO_WRITE) { 110 - dir = DMA_TO_DEVICE; 111 - err_code = MS_FLASH_WRITE_ERROR; 112 - } else { 113 - return STATUS_FAIL; 114 - } 115 - 116 - rtsx_init_cmd(chip); 117 - 118 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 119 - rtsx_add_cmd(chip, WRITE_REG_CMD, 120 - MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 121 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 122 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 123 - 124 - if (mode_2k) { 125 - rtsx_add_cmd(chip, WRITE_REG_CMD, 126 - MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 127 - } else { 128 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 129 - } 130 - 131 - trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 132 - 133 - rtsx_add_cmd(chip, WRITE_REG_CMD, 134 - MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 135 - rtsx_add_cmd(chip, CHECK_REG_CMD, 136 - MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 137 - 138 - rtsx_send_cmd_no_wait(chip); 139 - 140 - retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 141 - use_sg, dir, chip->mspro_timeout); 142 - if (retval < 0) { 143 - ms_set_err_code(chip, err_code); 144 - if (retval == -ETIMEDOUT) 145 - retval = STATUS_TIMEDOUT; 146 - else 147 - retval = STATUS_FAIL; 148 - 149 - return retval; 150 - } 151 - 152 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 153 - if (retval) 154 - return retval; 155 - 156 - if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) 157 - return STATUS_FAIL; 158 - 159 - return STATUS_SUCCESS; 160 - } 161 - 162 - static int ms_write_bytes(struct rtsx_chip *chip, 163 - u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 164 - { 165 - struct ms_info *ms_card = &chip->ms_card; 166 - int retval, i; 167 - 168 - if (!data || data_len < cnt) 169 - return STATUS_ERROR; 170 - 171 - rtsx_init_cmd(chip); 172 - 173 - for (i = 0; i < cnt; i++) { 174 - rtsx_add_cmd(chip, WRITE_REG_CMD, 175 - PPBUF_BASE2 + i, 0xFF, data[i]); 176 - } 177 - if (cnt % 2) 178 - rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 179 - 180 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 181 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 182 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 183 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 184 - 0x01, PINGPONG_BUFFER); 185 - 186 - rtsx_add_cmd(chip, WRITE_REG_CMD, 187 - MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 188 - rtsx_add_cmd(chip, CHECK_REG_CMD, 189 - MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 190 - 191 - retval = rtsx_send_cmd(chip, MS_CARD, 5000); 192 - if (retval < 0) { 193 - u8 val = 0; 194 - 195 - rtsx_read_register(chip, MS_TRANS_CFG, &val); 196 - dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 197 - 198 - rtsx_clear_ms_error(chip); 199 - 200 - if (!(tpc & 0x08)) { 201 - if (val & MS_CRC16_ERR) { 202 - ms_set_err_code(chip, MS_CRC16_ERROR); 203 - return ms_parse_err_code(chip); 204 - } 205 - } else { 206 - if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 207 - if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 208 - ms_set_err_code(chip, MS_CMD_NK); 209 - return ms_parse_err_code(chip); 210 - } 211 - } 212 - } 213 - 214 - if (val & MS_RDY_TIMEOUT) { 215 - ms_set_err_code(chip, MS_TO_ERROR); 216 - return ms_parse_err_code(chip); 217 - } 218 - 219 - ms_set_err_code(chip, MS_TO_ERROR); 220 - return ms_parse_err_code(chip); 221 - } 222 - 223 - return STATUS_SUCCESS; 224 - } 225 - 226 - static int ms_read_bytes(struct rtsx_chip *chip, 227 - u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 228 - { 229 - struct ms_info *ms_card = &chip->ms_card; 230 - int retval, i; 231 - u8 *ptr; 232 - 233 - if (!data) 234 - return STATUS_ERROR; 235 - 236 - rtsx_init_cmd(chip); 237 - 238 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 239 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 240 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 241 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 242 - 0x01, PINGPONG_BUFFER); 243 - 244 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 245 - MS_TRANSFER_START | MS_TM_READ_BYTES); 246 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 247 - MS_TRANSFER_END, MS_TRANSFER_END); 248 - 249 - for (i = 0; i < data_len - 1; i++) 250 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 251 - 252 - if (data_len % 2) 253 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 254 - else 255 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 256 - 0, 0); 257 - 258 - retval = rtsx_send_cmd(chip, MS_CARD, 5000); 259 - if (retval < 0) { 260 - u8 val = 0; 261 - 262 - rtsx_read_register(chip, MS_TRANS_CFG, &val); 263 - rtsx_clear_ms_error(chip); 264 - 265 - if (!(tpc & 0x08)) { 266 - if (val & MS_CRC16_ERR) { 267 - ms_set_err_code(chip, MS_CRC16_ERROR); 268 - return ms_parse_err_code(chip); 269 - } 270 - } else { 271 - if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 272 - if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 273 - ms_set_err_code(chip, MS_CMD_NK); 274 - return ms_parse_err_code(chip); 275 - } 276 - } 277 - } 278 - 279 - if (val & MS_RDY_TIMEOUT) { 280 - ms_set_err_code(chip, MS_TO_ERROR); 281 - return ms_parse_err_code(chip); 282 - } 283 - 284 - ms_set_err_code(chip, MS_TO_ERROR); 285 - return ms_parse_err_code(chip); 286 - } 287 - 288 - ptr = rtsx_get_cmd_data(chip) + 1; 289 - 290 - for (i = 0; i < data_len; i++) 291 - data[i] = ptr[i]; 292 - 293 - if (tpc == PRO_READ_SHORT_DATA && data_len == 8) { 294 - dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 295 - print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 296 - cnt); 297 - } 298 - 299 - return STATUS_SUCCESS; 300 - } 301 - 302 - static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start, 303 - u8 read_cnt, u8 write_start, u8 write_cnt) 304 - { 305 - int retval, i; 306 - u8 data[4]; 307 - 308 - data[0] = read_start; 309 - data[1] = read_cnt; 310 - data[2] = write_start; 311 - data[3] = write_cnt; 312 - 313 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 314 - retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 315 - NO_WAIT_INT, data, 4); 316 - if (retval == STATUS_SUCCESS) 317 - return STATUS_SUCCESS; 318 - rtsx_clear_ms_error(chip); 319 - } 320 - 321 - return STATUS_FAIL; 322 - } 323 - 324 - static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 325 - { 326 - u8 data[2]; 327 - 328 - data[0] = cmd; 329 - data[1] = 0; 330 - 331 - return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 332 - } 333 - 334 - static int ms_set_init_para(struct rtsx_chip *chip) 335 - { 336 - struct ms_info *ms_card = &chip->ms_card; 337 - int retval; 338 - 339 - if (CHK_HG8BIT(ms_card)) { 340 - if (chip->asic_code) 341 - ms_card->ms_clock = chip->asic_ms_hg_clk; 342 - else 343 - ms_card->ms_clock = chip->fpga_ms_hg_clk; 344 - 345 - } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 346 - if (chip->asic_code) 347 - ms_card->ms_clock = chip->asic_ms_4bit_clk; 348 - else 349 - ms_card->ms_clock = chip->fpga_ms_4bit_clk; 350 - 351 - } else { 352 - if (chip->asic_code) 353 - ms_card->ms_clock = chip->asic_ms_1bit_clk; 354 - else 355 - ms_card->ms_clock = chip->fpga_ms_1bit_clk; 356 - } 357 - 358 - retval = switch_clock(chip, ms_card->ms_clock); 359 - if (retval != STATUS_SUCCESS) 360 - return STATUS_FAIL; 361 - 362 - retval = select_card(chip, MS_CARD); 363 - if (retval != STATUS_SUCCESS) 364 - return STATUS_FAIL; 365 - 366 - return STATUS_SUCCESS; 367 - } 368 - 369 - static int ms_switch_clock(struct rtsx_chip *chip) 370 - { 371 - struct ms_info *ms_card = &chip->ms_card; 372 - int retval; 373 - 374 - retval = select_card(chip, MS_CARD); 375 - if (retval != STATUS_SUCCESS) 376 - return STATUS_FAIL; 377 - 378 - retval = switch_clock(chip, ms_card->ms_clock); 379 - if (retval != STATUS_SUCCESS) 380 - return STATUS_FAIL; 381 - 382 - return STATUS_SUCCESS; 383 - } 384 - 385 - static int ms_pull_ctl_disable(struct rtsx_chip *chip) 386 - { 387 - int retval; 388 - 389 - if (CHECK_PID(chip, 0x5208)) { 390 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 391 - MS_D1_PD | MS_D2_PD | MS_CLK_PD | 392 - MS_D6_PD); 393 - if (retval) 394 - return retval; 395 - 396 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 397 - MS_D3_PD | MS_D0_PD | MS_BS_PD | 398 - XD_D4_PD); 399 - if (retval) 400 - return retval; 401 - 402 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 403 - MS_D7_PD | XD_CE_PD | XD_CLE_PD | 404 - XD_CD_PU); 405 - if (retval) 406 - return retval; 407 - 408 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 409 - XD_RDY_PD | SD_D3_PD | SD_D2_PD | 410 - XD_ALE_PD); 411 - if (retval) 412 - return retval; 413 - 414 - retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 415 - MS_INS_PU | SD_WP_PD | SD_CD_PU | 416 - SD_CMD_PD); 417 - if (retval) 418 - return retval; 419 - 420 - retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 421 - MS_D5_PD | MS_D4_PD); 422 - if (retval) 423 - return retval; 424 - 425 - } else if (CHECK_PID(chip, 0x5288)) { 426 - if (CHECK_BARO_PKG(chip, QFN)) { 427 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 428 - 0xFF, 0x55); 429 - if (retval) 430 - return retval; 431 - 432 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 433 - 0xFF, 0x55); 434 - if (retval) 435 - return retval; 436 - 437 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 438 - 0xFF, 0x4B); 439 - if (retval) 440 - return retval; 441 - 442 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 443 - 0xFF, 0x69); 444 - if (retval) 445 - return retval; 446 - } 447 - } 448 - 449 - return STATUS_SUCCESS; 450 - } 451 - 452 - static int ms_pull_ctl_enable(struct rtsx_chip *chip) 453 - { 454 - int retval; 455 - 456 - rtsx_init_cmd(chip); 457 - 458 - if (CHECK_PID(chip, 0x5208)) { 459 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 460 - MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 461 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 462 - MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 463 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 464 - MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 465 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 466 - XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 467 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 468 - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 469 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 470 - MS_D5_PD | MS_D4_PD); 471 - } else if (CHECK_PID(chip, 0x5288)) { 472 - if (CHECK_BARO_PKG(chip, QFN)) { 473 - rtsx_add_cmd(chip, WRITE_REG_CMD, 474 - CARD_PULL_CTL1, 0xFF, 0x55); 475 - rtsx_add_cmd(chip, WRITE_REG_CMD, 476 - CARD_PULL_CTL2, 0xFF, 0x45); 477 - rtsx_add_cmd(chip, WRITE_REG_CMD, 478 - CARD_PULL_CTL3, 0xFF, 0x4B); 479 - rtsx_add_cmd(chip, WRITE_REG_CMD, 480 - CARD_PULL_CTL4, 0xFF, 0x29); 481 - } 482 - } 483 - 484 - retval = rtsx_send_cmd(chip, MS_CARD, 100); 485 - if (retval < 0) 486 - return STATUS_FAIL; 487 - 488 - return STATUS_SUCCESS; 489 - } 490 - 491 - static int ms_prepare_reset(struct rtsx_chip *chip) 492 - { 493 - struct ms_info *ms_card = &chip->ms_card; 494 - int retval; 495 - u8 oc_mask = 0; 496 - 497 - ms_card->ms_type = 0; 498 - ms_card->check_ms_flow = 0; 499 - ms_card->switch_8bit_fail = 0; 500 - ms_card->delay_write.delay_write_flag = 0; 501 - 502 - ms_card->pro_under_formatting = 0; 503 - 504 - retval = ms_power_off_card3v3(chip); 505 - if (retval != STATUS_SUCCESS) 506 - return STATUS_FAIL; 507 - 508 - if (!chip->ft2_fast_mode) 509 - wait_timeout(250); 510 - 511 - retval = enable_card_clock(chip, MS_CARD); 512 - if (retval != STATUS_SUCCESS) 513 - return STATUS_FAIL; 514 - 515 - if (chip->asic_code) { 516 - retval = ms_pull_ctl_enable(chip); 517 - if (retval != STATUS_SUCCESS) 518 - return STATUS_FAIL; 519 - } else { 520 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 521 - FPGA_MS_PULL_CTL_BIT | 0x20, 0); 522 - if (retval) 523 - return retval; 524 - } 525 - 526 - if (!chip->ft2_fast_mode) { 527 - retval = card_power_on(chip, MS_CARD); 528 - if (retval != STATUS_SUCCESS) 529 - return STATUS_FAIL; 530 - 531 - wait_timeout(150); 532 - 533 - #ifdef SUPPORT_OCP 534 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 535 - oc_mask = MS_OC_NOW | MS_OC_EVER; 536 - else 537 - oc_mask = SD_OC_NOW | SD_OC_EVER; 538 - 539 - if (chip->ocp_stat & oc_mask) { 540 - dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 541 - chip->ocp_stat); 542 - return STATUS_FAIL; 543 - } 544 - #endif 545 - } 546 - 547 - retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 548 - MS_OUTPUT_EN); 549 - if (retval) 550 - return retval; 551 - 552 - if (chip->asic_code) { 553 - retval = rtsx_write_register(chip, MS_CFG, 0xFF, 554 - SAMPLE_TIME_RISING | 555 - PUSH_TIME_DEFAULT | 556 - NO_EXTEND_TOGGLE | 557 - MS_BUS_WIDTH_1); 558 - if (retval) 559 - return retval; 560 - 561 - } else { 562 - retval = rtsx_write_register(chip, MS_CFG, 0xFF, 563 - SAMPLE_TIME_FALLING | 564 - PUSH_TIME_DEFAULT | 565 - NO_EXTEND_TOGGLE | 566 - MS_BUS_WIDTH_1); 567 - if (retval) 568 - return retval; 569 - } 570 - retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 571 - NO_WAIT_INT | NO_AUTO_READ_INT_REG); 572 - if (retval) 573 - return retval; 574 - 575 - retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 576 - MS_STOP | MS_CLR_ERR); 577 - if (retval) 578 - return retval; 579 - 580 - retval = ms_set_init_para(chip); 581 - if (retval != STATUS_SUCCESS) 582 - return STATUS_FAIL; 583 - 584 - return STATUS_SUCCESS; 585 - } 586 - 587 - static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 588 - { 589 - struct ms_info *ms_card = &chip->ms_card; 590 - int retval, i; 591 - u8 val; 592 - 593 - retval = ms_set_rw_reg_addr(chip, PRO_STATUS_REG, 6, SYSTEM_PARAM, 1); 594 - if (retval != STATUS_SUCCESS) 595 - return STATUS_FAIL; 596 - 597 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 598 - retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 599 - 6, NO_WAIT_INT); 600 - if (retval == STATUS_SUCCESS) 601 - break; 602 - } 603 - if (i == MS_MAX_RETRY_COUNT) 604 - return STATUS_FAIL; 605 - 606 - retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 607 - if (retval) 608 - return retval; 609 - 610 - dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 611 - if (val != 0x01) { 612 - if (val != 0x02) 613 - ms_card->check_ms_flow = 1; 614 - 615 - return STATUS_FAIL; 616 - } 617 - 618 - retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 619 - if (retval) 620 - return retval; 621 - 622 - dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 623 - if (val != 0) { 624 - ms_card->check_ms_flow = 1; 625 - return STATUS_FAIL; 626 - } 627 - 628 - retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 629 - if (retval) 630 - return retval; 631 - 632 - dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 633 - if (val == 0) { 634 - retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 635 - if (retval) 636 - return retval; 637 - 638 - if (val & WRT_PRTCT) 639 - chip->card_wp |= MS_CARD; 640 - else 641 - chip->card_wp &= ~MS_CARD; 642 - 643 - } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 644 - chip->card_wp |= MS_CARD; 645 - } else { 646 - ms_card->check_ms_flow = 1; 647 - return STATUS_FAIL; 648 - } 649 - 650 - ms_card->ms_type |= TYPE_MSPRO; 651 - 652 - retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 653 - if (retval) 654 - return retval; 655 - 656 - dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 657 - if (val == 0) { 658 - ms_card->ms_type &= 0x0F; 659 - } else if (val == 7) { 660 - if (switch_8bit_bus) 661 - ms_card->ms_type |= MS_HG; 662 - else 663 - ms_card->ms_type &= 0x0F; 664 - 665 - } else { 666 - return STATUS_FAIL; 667 - } 668 - 669 - return STATUS_SUCCESS; 670 - } 671 - 672 - static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 673 - { 674 - int retval, i, k; 675 - u8 val; 676 - 677 - /* Confirm CPU StartUp */ 678 - k = 0; 679 - do { 680 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 681 - ms_set_err_code(chip, MS_NO_CARD); 682 - return STATUS_FAIL; 683 - } 684 - 685 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 686 - retval = ms_read_bytes(chip, GET_INT, 1, 687 - NO_WAIT_INT, &val, 1); 688 - if (retval == STATUS_SUCCESS) 689 - break; 690 - } 691 - if (i == MS_MAX_RETRY_COUNT) 692 - return STATUS_FAIL; 693 - 694 - if (k > 100) 695 - return STATUS_FAIL; 696 - 697 - k++; 698 - wait_timeout(100); 699 - } while (!(val & INT_REG_CED)); 700 - 701 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 702 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 703 - if (retval == STATUS_SUCCESS) 704 - break; 705 - } 706 - if (i == MS_MAX_RETRY_COUNT) 707 - return STATUS_FAIL; 708 - 709 - if (val & INT_REG_ERR) { 710 - if (val & INT_REG_CMDNK) 711 - chip->card_wp |= (MS_CARD); 712 - else 713 - return STATUS_FAIL; 714 - } 715 - /* -- end confirm CPU startup */ 716 - 717 - return STATUS_SUCCESS; 718 - } 719 - 720 - static int ms_switch_parallel_bus(struct rtsx_chip *chip) 721 - { 722 - int retval, i; 723 - u8 data[2]; 724 - 725 - data[0] = PARALLEL_4BIT_IF; 726 - data[1] = 0; 727 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 728 - retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 729 - data, 2); 730 - if (retval == STATUS_SUCCESS) 731 - break; 732 - } 733 - if (retval != STATUS_SUCCESS) 734 - return STATUS_FAIL; 735 - 736 - return STATUS_SUCCESS; 737 - } 738 - 739 - static int ms_switch_8bit_bus(struct rtsx_chip *chip) 740 - { 741 - struct ms_info *ms_card = &chip->ms_card; 742 - int retval, i; 743 - u8 data[2]; 744 - 745 - data[0] = PARALLEL_8BIT_IF; 746 - data[1] = 0; 747 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 748 - retval = ms_write_bytes(chip, WRITE_REG, 1, 749 - NO_WAIT_INT, data, 2); 750 - if (retval == STATUS_SUCCESS) 751 - break; 752 - } 753 - if (retval != STATUS_SUCCESS) 754 - return STATUS_FAIL; 755 - 756 - retval = rtsx_write_register(chip, MS_CFG, 0x98, 757 - MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 758 - if (retval) 759 - return retval; 760 - 761 - ms_card->ms_type |= MS_8BIT; 762 - retval = ms_set_init_para(chip); 763 - if (retval != STATUS_SUCCESS) 764 - return STATUS_FAIL; 765 - 766 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 767 - retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 768 - 1, NO_WAIT_INT); 769 - if (retval != STATUS_SUCCESS) 770 - return STATUS_FAIL; 771 - } 772 - 773 - return STATUS_SUCCESS; 774 - } 775 - 776 - static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 777 - { 778 - struct ms_info *ms_card = &chip->ms_card; 779 - int retval, i; 780 - 781 - for (i = 0; i < 3; i++) { 782 - retval = ms_prepare_reset(chip); 783 - if (retval != STATUS_SUCCESS) 784 - return STATUS_FAIL; 785 - 786 - retval = ms_identify_media_type(chip, switch_8bit_bus); 787 - if (retval != STATUS_SUCCESS) 788 - return STATUS_FAIL; 789 - 790 - retval = ms_confirm_cpu_startup(chip); 791 - if (retval != STATUS_SUCCESS) 792 - return STATUS_FAIL; 793 - 794 - retval = ms_switch_parallel_bus(chip); 795 - if (retval != STATUS_SUCCESS) { 796 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 797 - ms_set_err_code(chip, MS_NO_CARD); 798 - return STATUS_FAIL; 799 - } 800 - continue; 801 - } else { 802 - break; 803 - } 804 - } 805 - 806 - if (retval != STATUS_SUCCESS) 807 - return STATUS_FAIL; 808 - 809 - /* Switch MS-PRO into Parallel mode */ 810 - retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 811 - if (retval) 812 - return retval; 813 - 814 - retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 815 - PUSH_TIME_ODD); 816 - if (retval) 817 - return retval; 818 - 819 - retval = ms_set_init_para(chip); 820 - if (retval != STATUS_SUCCESS) 821 - return STATUS_FAIL; 822 - 823 - /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 824 - if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 825 - retval = ms_switch_8bit_bus(chip); 826 - if (retval != STATUS_SUCCESS) { 827 - ms_card->switch_8bit_fail = 1; 828 - return STATUS_FAIL; 829 - } 830 - } 831 - 832 - return STATUS_SUCCESS; 833 - } 834 - 835 - #ifdef XC_POWERCLASS 836 - static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 837 - { 838 - int retval; 839 - u8 buf[6]; 840 - 841 - ms_cleanup_work(chip); 842 - 843 - retval = ms_set_rw_reg_addr(chip, 0, 0, PRO_DATA_COUNT1, 6); 844 - if (retval != STATUS_SUCCESS) 845 - return STATUS_FAIL; 846 - 847 - buf[0] = 0; 848 - buf[1] = mode; 849 - buf[2] = 0; 850 - buf[3] = 0; 851 - buf[4] = 0; 852 - buf[5] = 0; 853 - 854 - retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 855 - if (retval != STATUS_SUCCESS) 856 - return STATUS_FAIL; 857 - 858 - retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 859 - if (retval != STATUS_SUCCESS) 860 - return STATUS_FAIL; 861 - 862 - retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 863 - if (retval) 864 - return retval; 865 - 866 - if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) 867 - return STATUS_FAIL; 868 - 869 - return STATUS_SUCCESS; 870 - } 871 - #endif 872 - 873 - static int ms_read_attribute_info(struct rtsx_chip *chip) 874 - { 875 - struct ms_info *ms_card = &chip->ms_card; 876 - int retval, i; 877 - u8 val, *buf, class_code, device_type, sub_class, data[16]; 878 - u16 total_blk = 0, blk_size = 0; 879 - #ifdef SUPPORT_MSXC 880 - u32 xc_total_blk = 0, xc_blk_size = 0; 881 - #endif 882 - u32 sys_info_addr = 0, sys_info_size; 883 - #ifdef SUPPORT_PCGL_1P18 884 - u32 model_name_addr = 0, model_name_size; 885 - int found_sys_info = 0, found_model_name = 0; 886 - #endif 887 - 888 - retval = ms_set_rw_reg_addr(chip, PRO_INT_REG, 2, PRO_SYSTEM_PARAM, 7); 889 - if (retval != STATUS_SUCCESS) 890 - return STATUS_FAIL; 891 - 892 - if (CHK_MS8BIT(ms_card)) 893 - data[0] = PARALLEL_8BIT_IF; 894 - else 895 - data[0] = PARALLEL_4BIT_IF; 896 - 897 - data[1] = 0; 898 - 899 - data[2] = 0x40; 900 - data[3] = 0; 901 - data[4] = 0; 902 - data[5] = 0; 903 - data[6] = 0; 904 - data[7] = 0; 905 - 906 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 907 - retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 908 - data, 8); 909 - if (retval == STATUS_SUCCESS) 910 - break; 911 - } 912 - if (retval != STATUS_SUCCESS) 913 - return STATUS_FAIL; 914 - 915 - buf = kmalloc(64 * 512, GFP_KERNEL); 916 - if (!buf) 917 - return STATUS_ERROR; 918 - 919 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 920 - retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 921 - if (retval != STATUS_SUCCESS) 922 - continue; 923 - 924 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 925 - if (retval != STATUS_SUCCESS) { 926 - kfree(buf); 927 - return STATUS_FAIL; 928 - } 929 - if (!(val & MS_INT_BREQ)) { 930 - kfree(buf); 931 - return STATUS_FAIL; 932 - } 933 - retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 934 - PRO_READ_LONG_DATA, 0x40, WAIT_INT, 935 - 0, 0, buf, 64 * 512); 936 - if (retval == STATUS_SUCCESS) 937 - break; 938 - 939 - rtsx_clear_ms_error(chip); 940 - } 941 - if (retval != STATUS_SUCCESS) { 942 - kfree(buf); 943 - return STATUS_FAIL; 944 - } 945 - 946 - i = 0; 947 - do { 948 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 949 - if (retval != STATUS_SUCCESS) { 950 - kfree(buf); 951 - return STATUS_FAIL; 952 - } 953 - 954 - if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 955 - break; 956 - 957 - retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 958 - PRO_READ_LONG_DATA, 0, WAIT_INT); 959 - if (retval != STATUS_SUCCESS) { 960 - kfree(buf); 961 - return STATUS_FAIL; 962 - } 963 - 964 - i++; 965 - } while (i < 1024); 966 - 967 - if (buf[0] != 0xa5 && buf[1] != 0xc3) { 968 - /* Signature code is wrong */ 969 - kfree(buf); 970 - return STATUS_FAIL; 971 - } 972 - 973 - if (buf[4] < 1 || buf[4] > 12) { 974 - kfree(buf); 975 - return STATUS_FAIL; 976 - } 977 - 978 - for (i = 0; i < buf[4]; i++) { 979 - int cur_addr_off = 16 + i * 12; 980 - 981 - #ifdef SUPPORT_MSXC 982 - if (buf[cur_addr_off + 8] == 0x10 || 983 - buf[cur_addr_off + 8] == 0x13) { 984 - #else 985 - if (buf[cur_addr_off + 8] == 0x10) { 986 - #endif 987 - sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 988 - ((u32)buf[cur_addr_off + 1] << 16) | 989 - ((u32)buf[cur_addr_off + 2] << 8) | 990 - buf[cur_addr_off + 3]; 991 - sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 992 - ((u32)buf[cur_addr_off + 5] << 16) | 993 - ((u32)buf[cur_addr_off + 6] << 8) | 994 - buf[cur_addr_off + 7]; 995 - dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 996 - sys_info_addr, sys_info_size); 997 - if (sys_info_size != 96) { 998 - kfree(buf); 999 - return STATUS_FAIL; 1000 - } 1001 - if (sys_info_addr < 0x1A0) { 1002 - kfree(buf); 1003 - return STATUS_FAIL; 1004 - } 1005 - if ((sys_info_size + sys_info_addr) > 0x8000) { 1006 - kfree(buf); 1007 - return STATUS_FAIL; 1008 - } 1009 - 1010 - #ifdef SUPPORT_MSXC 1011 - if (buf[cur_addr_off + 8] == 0x13) 1012 - ms_card->ms_type |= MS_XC; 1013 - #endif 1014 - #ifdef SUPPORT_PCGL_1P18 1015 - found_sys_info = 1; 1016 - #else 1017 - break; 1018 - #endif 1019 - } 1020 - #ifdef SUPPORT_PCGL_1P18 1021 - if (buf[cur_addr_off + 8] == 0x15) { 1022 - model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1023 - ((u32)buf[cur_addr_off + 1] << 16) | 1024 - ((u32)buf[cur_addr_off + 2] << 8) | 1025 - buf[cur_addr_off + 3]; 1026 - model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1027 - ((u32)buf[cur_addr_off + 5] << 16) | 1028 - ((u32)buf[cur_addr_off + 6] << 8) | 1029 - buf[cur_addr_off + 7]; 1030 - dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1031 - model_name_addr, model_name_size); 1032 - if (model_name_size != 48) { 1033 - kfree(buf); 1034 - return STATUS_FAIL; 1035 - } 1036 - if (model_name_addr < 0x1A0) { 1037 - kfree(buf); 1038 - return STATUS_FAIL; 1039 - } 1040 - if ((model_name_size + model_name_addr) > 0x8000) { 1041 - kfree(buf); 1042 - return STATUS_FAIL; 1043 - } 1044 - 1045 - found_model_name = 1; 1046 - } 1047 - 1048 - if (found_sys_info && found_model_name) 1049 - break; 1050 - #endif 1051 - } 1052 - 1053 - if (i == buf[4]) { 1054 - kfree(buf); 1055 - return STATUS_FAIL; 1056 - } 1057 - 1058 - class_code = buf[sys_info_addr + 0]; 1059 - device_type = buf[sys_info_addr + 56]; 1060 - sub_class = buf[sys_info_addr + 46]; 1061 - #ifdef SUPPORT_MSXC 1062 - if (CHK_MSXC(ms_card)) { 1063 - xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1064 - ((u32)buf[sys_info_addr + 7] << 16) | 1065 - ((u32)buf[sys_info_addr + 8] << 8) | 1066 - buf[sys_info_addr + 9]; 1067 - xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1068 - ((u32)buf[sys_info_addr + 33] << 16) | 1069 - ((u32)buf[sys_info_addr + 34] << 8) | 1070 - buf[sys_info_addr + 35]; 1071 - dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1072 - xc_total_blk, xc_blk_size); 1073 - } else { 1074 - total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1075 - buf[sys_info_addr + 7]; 1076 - blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1077 - buf[sys_info_addr + 3]; 1078 - dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1079 - total_blk, blk_size); 1080 - } 1081 - #else 1082 - total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1083 - blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1084 - dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1085 - total_blk, blk_size); 1086 - #endif 1087 - 1088 - dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1089 - class_code, device_type, sub_class); 1090 - 1091 - memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1092 - #ifdef SUPPORT_PCGL_1P18 1093 - memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1094 - #endif 1095 - 1096 - kfree(buf); 1097 - 1098 - #ifdef SUPPORT_MSXC 1099 - if (CHK_MSXC(ms_card)) { 1100 - if (class_code != 0x03) 1101 - return STATUS_FAIL; 1102 - } else { 1103 - if (class_code != 0x02) 1104 - return STATUS_FAIL; 1105 - } 1106 - #else 1107 - if (class_code != 0x02) 1108 - return STATUS_FAIL; 1109 - #endif 1110 - 1111 - if (device_type != 0x00) { 1112 - if (device_type == 0x01 || device_type == 0x02 || 1113 - device_type == 0x03) { 1114 - chip->card_wp |= MS_CARD; 1115 - } else { 1116 - return STATUS_FAIL; 1117 - } 1118 - } 1119 - 1120 - if (sub_class & 0xC0) 1121 - return STATUS_FAIL; 1122 - 1123 - dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1124 - class_code, device_type, sub_class); 1125 - 1126 - #ifdef SUPPORT_MSXC 1127 - if (CHK_MSXC(ms_card)) { 1128 - chip->capacity[chip->card2lun[MS_CARD]] = 1129 - ms_card->capacity = xc_total_blk * xc_blk_size; 1130 - } else { 1131 - chip->capacity[chip->card2lun[MS_CARD]] = 1132 - ms_card->capacity = total_blk * blk_size; 1133 - } 1134 - #else 1135 - ms_card->capacity = total_blk * blk_size; 1136 - chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1137 - #endif 1138 - 1139 - return STATUS_SUCCESS; 1140 - } 1141 - 1142 - #ifdef SUPPORT_MAGIC_GATE 1143 - static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1144 - int type, u8 mg_entry_num); 1145 - #endif 1146 - 1147 - static int reset_ms_pro(struct rtsx_chip *chip) 1148 - { 1149 - struct ms_info *ms_card = &chip->ms_card; 1150 - int retval; 1151 - #ifdef XC_POWERCLASS 1152 - u8 change_power_class; 1153 - 1154 - if (chip->ms_power_class_en & 0x02) 1155 - change_power_class = 2; 1156 - else if (chip->ms_power_class_en & 0x01) 1157 - change_power_class = 1; 1158 - else 1159 - change_power_class = 0; 1160 - #endif 1161 - 1162 - #ifdef XC_POWERCLASS 1163 - retry: 1164 - #endif 1165 - retval = ms_pro_reset_flow(chip, 1); 1166 - if (retval != STATUS_SUCCESS) { 1167 - if (ms_card->switch_8bit_fail) { 1168 - retval = ms_pro_reset_flow(chip, 0); 1169 - if (retval != STATUS_SUCCESS) 1170 - return STATUS_FAIL; 1171 - } else { 1172 - return STATUS_FAIL; 1173 - } 1174 - } 1175 - 1176 - retval = ms_read_attribute_info(chip); 1177 - if (retval != STATUS_SUCCESS) 1178 - return STATUS_FAIL; 1179 - 1180 - #ifdef XC_POWERCLASS 1181 - if (CHK_HG8BIT(ms_card)) 1182 - change_power_class = 0; 1183 - 1184 - if (change_power_class && CHK_MSXC(ms_card)) { 1185 - u8 power_class_en = chip->ms_power_class_en; 1186 - 1187 - dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1188 - power_class_en); 1189 - dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1190 - change_power_class); 1191 - 1192 - if (change_power_class) 1193 - power_class_en &= (1 << (change_power_class - 1)); 1194 - else 1195 - power_class_en = 0; 1196 - 1197 - if (power_class_en) { 1198 - u8 power_class_mode = 1199 - (ms_card->raw_sys_info[46] & 0x18) >> 3; 1200 - dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1201 - power_class_mode); 1202 - if (change_power_class > power_class_mode) 1203 - change_power_class = power_class_mode; 1204 - if (change_power_class) { 1205 - retval = msxc_change_power(chip, 1206 - change_power_class); 1207 - if (retval != STATUS_SUCCESS) { 1208 - change_power_class--; 1209 - goto retry; 1210 - } 1211 - } 1212 - } 1213 - } 1214 - #endif 1215 - 1216 - #ifdef SUPPORT_MAGIC_GATE 1217 - retval = mg_set_tpc_para_sub(chip, 0, 0); 1218 - if (retval != STATUS_SUCCESS) 1219 - return STATUS_FAIL; 1220 - #endif 1221 - 1222 - if (CHK_HG8BIT(ms_card)) 1223 - chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1224 - else 1225 - chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1226 - 1227 - return STATUS_SUCCESS; 1228 - } 1229 - 1230 - static int ms_read_status_reg(struct rtsx_chip *chip) 1231 - { 1232 - int retval; 1233 - u8 val[2]; 1234 - 1235 - retval = ms_set_rw_reg_addr(chip, STATUS_REG0, 2, 0, 0); 1236 - if (retval != STATUS_SUCCESS) 1237 - return STATUS_FAIL; 1238 - 1239 - retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1240 - if (retval != STATUS_SUCCESS) 1241 - return STATUS_FAIL; 1242 - 1243 - if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1244 - ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1245 - return STATUS_FAIL; 1246 - } 1247 - 1248 - return STATUS_SUCCESS; 1249 - } 1250 - 1251 - static int ms_read_extra_data(struct rtsx_chip *chip, 1252 - u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1253 - { 1254 - struct ms_info *ms_card = &chip->ms_card; 1255 - int retval, i; 1256 - u8 val, data[10]; 1257 - 1258 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1259 - SYSTEM_PARAM, 6); 1260 - if (retval != STATUS_SUCCESS) 1261 - return STATUS_FAIL; 1262 - 1263 - if (CHK_MS4BIT(ms_card)) { 1264 - /* Parallel interface */ 1265 - data[0] = 0x88; 1266 - } else { 1267 - /* Serial interface */ 1268 - data[0] = 0x80; 1269 - } 1270 - data[1] = 0; 1271 - data[2] = (u8)(block_addr >> 8); 1272 - data[3] = (u8)block_addr; 1273 - data[4] = 0x40; 1274 - data[5] = page_num; 1275 - 1276 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1277 - retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1278 - data, 6); 1279 - if (retval == STATUS_SUCCESS) 1280 - break; 1281 - } 1282 - if (i == MS_MAX_RETRY_COUNT) 1283 - return STATUS_FAIL; 1284 - 1285 - ms_set_err_code(chip, MS_NO_ERROR); 1286 - 1287 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1288 - retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1289 - if (retval == STATUS_SUCCESS) 1290 - break; 1291 - } 1292 - if (i == MS_MAX_RETRY_COUNT) 1293 - return STATUS_FAIL; 1294 - 1295 - ms_set_err_code(chip, MS_NO_ERROR); 1296 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1297 - if (retval != STATUS_SUCCESS) 1298 - return STATUS_FAIL; 1299 - 1300 - if (val & INT_REG_CMDNK) { 1301 - ms_set_err_code(chip, MS_CMD_NK); 1302 - return STATUS_FAIL; 1303 - } 1304 - if (val & INT_REG_CED) { 1305 - if (val & INT_REG_ERR) { 1306 - retval = ms_read_status_reg(chip); 1307 - if (retval != STATUS_SUCCESS) 1308 - return STATUS_FAIL; 1309 - 1310 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, 1311 - MS_EXTRA_SIZE, SYSTEM_PARAM, 1312 - 6); 1313 - if (retval != STATUS_SUCCESS) 1314 - return STATUS_FAIL; 1315 - } 1316 - } 1317 - 1318 - retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1319 - data, MS_EXTRA_SIZE); 1320 - if (retval != STATUS_SUCCESS) 1321 - return STATUS_FAIL; 1322 - 1323 - if (buf && buf_len) { 1324 - if (buf_len > MS_EXTRA_SIZE) 1325 - buf_len = MS_EXTRA_SIZE; 1326 - memcpy(buf, data, buf_len); 1327 - } 1328 - 1329 - return STATUS_SUCCESS; 1330 - } 1331 - 1332 - static int ms_write_extra_data(struct rtsx_chip *chip, u16 block_addr, 1333 - u8 page_num, u8 *buf, int buf_len) 1334 - { 1335 - struct ms_info *ms_card = &chip->ms_card; 1336 - int retval, i; 1337 - u8 val, data[16]; 1338 - 1339 - if (!buf || buf_len < MS_EXTRA_SIZE) 1340 - return STATUS_FAIL; 1341 - 1342 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1343 - SYSTEM_PARAM, 6 + MS_EXTRA_SIZE); 1344 - if (retval != STATUS_SUCCESS) 1345 - return STATUS_FAIL; 1346 - 1347 - if (CHK_MS4BIT(ms_card)) 1348 - data[0] = 0x88; 1349 - else 1350 - data[0] = 0x80; 1351 - 1352 - data[1] = 0; 1353 - data[2] = (u8)(block_addr >> 8); 1354 - data[3] = (u8)block_addr; 1355 - data[4] = 0x40; 1356 - data[5] = page_num; 1357 - 1358 - for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1359 - data[i] = buf[i - 6]; 1360 - 1361 - retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1362 - NO_WAIT_INT, data, 16); 1363 - if (retval != STATUS_SUCCESS) 1364 - return STATUS_FAIL; 1365 - 1366 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1367 - if (retval != STATUS_SUCCESS) 1368 - return STATUS_FAIL; 1369 - 1370 - ms_set_err_code(chip, MS_NO_ERROR); 1371 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1372 - if (retval != STATUS_SUCCESS) 1373 - return STATUS_FAIL; 1374 - 1375 - if (val & INT_REG_CMDNK) { 1376 - ms_set_err_code(chip, MS_CMD_NK); 1377 - return STATUS_FAIL; 1378 - } 1379 - if (val & INT_REG_CED) { 1380 - if (val & INT_REG_ERR) { 1381 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1382 - return STATUS_FAIL; 1383 - } 1384 - } 1385 - 1386 - return STATUS_SUCCESS; 1387 - } 1388 - 1389 - static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1390 - { 1391 - struct ms_info *ms_card = &chip->ms_card; 1392 - int retval; 1393 - u8 val, data[6]; 1394 - 1395 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1396 - SYSTEM_PARAM, 6); 1397 - if (retval != STATUS_SUCCESS) 1398 - return STATUS_FAIL; 1399 - 1400 - if (CHK_MS4BIT(ms_card)) 1401 - data[0] = 0x88; 1402 - else 1403 - data[0] = 0x80; 1404 - 1405 - data[1] = 0; 1406 - data[2] = (u8)(block_addr >> 8); 1407 - data[3] = (u8)block_addr; 1408 - data[4] = 0x20; 1409 - data[5] = page_num; 1410 - 1411 - retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1412 - if (retval != STATUS_SUCCESS) 1413 - return STATUS_FAIL; 1414 - 1415 - retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1416 - if (retval != STATUS_SUCCESS) 1417 - return STATUS_FAIL; 1418 - 1419 - ms_set_err_code(chip, MS_NO_ERROR); 1420 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1421 - if (retval != STATUS_SUCCESS) 1422 - return STATUS_FAIL; 1423 - 1424 - if (val & INT_REG_CMDNK) { 1425 - ms_set_err_code(chip, MS_CMD_NK); 1426 - return STATUS_FAIL; 1427 - } 1428 - 1429 - if (val & INT_REG_CED) { 1430 - if (val & INT_REG_ERR) { 1431 - if (!(val & INT_REG_BREQ)) { 1432 - ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1433 - return STATUS_FAIL; 1434 - } 1435 - retval = ms_read_status_reg(chip); 1436 - if (retval != STATUS_SUCCESS) 1437 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1438 - 1439 - } else { 1440 - if (!(val & INT_REG_BREQ)) { 1441 - ms_set_err_code(chip, MS_BREQ_ERROR); 1442 - return STATUS_FAIL; 1443 - } 1444 - } 1445 - } 1446 - 1447 - retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1448 - 0, NO_WAIT_INT); 1449 - if (retval != STATUS_SUCCESS) 1450 - return STATUS_FAIL; 1451 - 1452 - if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) 1453 - return STATUS_FAIL; 1454 - 1455 - return STATUS_SUCCESS; 1456 - } 1457 - 1458 - static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1459 - { 1460 - struct ms_info *ms_card = &chip->ms_card; 1461 - int retval; 1462 - u8 val, data[8], extra[MS_EXTRA_SIZE]; 1463 - 1464 - retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1465 - if (retval != STATUS_SUCCESS) 1466 - return STATUS_FAIL; 1467 - 1468 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1469 - SYSTEM_PARAM, 7); 1470 - if (retval != STATUS_SUCCESS) 1471 - return STATUS_FAIL; 1472 - 1473 - ms_set_err_code(chip, MS_NO_ERROR); 1474 - 1475 - if (CHK_MS4BIT(ms_card)) 1476 - data[0] = 0x88; 1477 - else 1478 - data[0] = 0x80; 1479 - 1480 - data[1] = 0; 1481 - data[2] = (u8)(phy_blk >> 8); 1482 - data[3] = (u8)phy_blk; 1483 - data[4] = 0x80; 1484 - data[5] = 0; 1485 - data[6] = extra[0] & 0x7F; 1486 - data[7] = 0xFF; 1487 - 1488 - retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1489 - if (retval != STATUS_SUCCESS) 1490 - return STATUS_FAIL; 1491 - 1492 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1493 - if (retval != STATUS_SUCCESS) 1494 - return STATUS_FAIL; 1495 - 1496 - ms_set_err_code(chip, MS_NO_ERROR); 1497 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1498 - if (retval != STATUS_SUCCESS) 1499 - return STATUS_FAIL; 1500 - 1501 - if (val & INT_REG_CMDNK) { 1502 - ms_set_err_code(chip, MS_CMD_NK); 1503 - return STATUS_FAIL; 1504 - } 1505 - 1506 - if (val & INT_REG_CED) { 1507 - if (val & INT_REG_ERR) { 1508 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1509 - return STATUS_FAIL; 1510 - } 1511 - } 1512 - 1513 - return STATUS_SUCCESS; 1514 - } 1515 - 1516 - static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1517 - { 1518 - struct ms_info *ms_card = &chip->ms_card; 1519 - int retval, i = 0; 1520 - u8 val, data[6]; 1521 - 1522 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1523 - SYSTEM_PARAM, 6); 1524 - if (retval != STATUS_SUCCESS) 1525 - return STATUS_FAIL; 1526 - 1527 - ms_set_err_code(chip, MS_NO_ERROR); 1528 - 1529 - if (CHK_MS4BIT(ms_card)) 1530 - data[0] = 0x88; 1531 - else 1532 - data[0] = 0x80; 1533 - 1534 - data[1] = 0; 1535 - data[2] = (u8)(phy_blk >> 8); 1536 - data[3] = (u8)phy_blk; 1537 - data[4] = 0; 1538 - data[5] = 0; 1539 - 1540 - retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1541 - if (retval != STATUS_SUCCESS) 1542 - return STATUS_FAIL; 1543 - 1544 - ERASE_RTY: 1545 - retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1546 - if (retval != STATUS_SUCCESS) 1547 - return STATUS_FAIL; 1548 - 1549 - ms_set_err_code(chip, MS_NO_ERROR); 1550 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1551 - if (retval != STATUS_SUCCESS) 1552 - return STATUS_FAIL; 1553 - 1554 - if (val & INT_REG_CMDNK) { 1555 - if (i < 3) { 1556 - i++; 1557 - goto ERASE_RTY; 1558 - } 1559 - 1560 - ms_set_err_code(chip, MS_CMD_NK); 1561 - ms_set_bad_block(chip, phy_blk); 1562 - return STATUS_FAIL; 1563 - } 1564 - 1565 - if (val & INT_REG_CED) { 1566 - if (val & INT_REG_ERR) { 1567 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1568 - return STATUS_FAIL; 1569 - } 1570 - } 1571 - 1572 - return STATUS_SUCCESS; 1573 - } 1574 - 1575 - static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1576 - { 1577 - if (!extra || extra_len < MS_EXTRA_SIZE) 1578 - return; 1579 - 1580 - memset(extra, 0xFF, MS_EXTRA_SIZE); 1581 - 1582 - if (type == set_PS_NG) { 1583 - /* set page status as 1:NG,and block status keep 1:OK */ 1584 - extra[0] = 0xB8; 1585 - } else { 1586 - /* set page status as 0:Data Error,and block status keep 1:OK */ 1587 - extra[0] = 0x98; 1588 - } 1589 - 1590 - extra[2] = (u8)(log_blk >> 8); 1591 - extra[3] = (u8)log_blk; 1592 - } 1593 - 1594 - static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1595 - u8 start_page, u8 end_page) 1596 - { 1597 - int retval; 1598 - u8 extra[MS_EXTRA_SIZE], i; 1599 - 1600 - memset(extra, 0xff, MS_EXTRA_SIZE); 1601 - 1602 - extra[0] = 0xf8; /* Block, page OK, data erased */ 1603 - extra[1] = 0xff; 1604 - extra[2] = (u8)(log_blk >> 8); 1605 - extra[3] = (u8)log_blk; 1606 - 1607 - for (i = start_page; i < end_page; i++) { 1608 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1609 - ms_set_err_code(chip, MS_NO_CARD); 1610 - return STATUS_FAIL; 1611 - } 1612 - 1613 - retval = ms_write_extra_data(chip, phy_blk, i, 1614 - extra, MS_EXTRA_SIZE); 1615 - if (retval != STATUS_SUCCESS) 1616 - return STATUS_FAIL; 1617 - } 1618 - 1619 - return STATUS_SUCCESS; 1620 - } 1621 - 1622 - static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1623 - u16 log_blk, u8 start_page, u8 end_page) 1624 - { 1625 - struct ms_info *ms_card = &chip->ms_card; 1626 - bool uncorrect_flag = false; 1627 - int retval, rty_cnt; 1628 - u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1629 - 1630 - dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1631 - old_blk, new_blk, log_blk); 1632 - dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1633 - start_page, end_page); 1634 - 1635 - retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1636 - if (retval != STATUS_SUCCESS) 1637 - return STATUS_FAIL; 1638 - 1639 - retval = ms_read_status_reg(chip); 1640 - if (retval != STATUS_SUCCESS) 1641 - return STATUS_FAIL; 1642 - 1643 - retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1644 - if (retval) 1645 - return retval; 1646 - 1647 - if (val & BUF_FULL) { 1648 - retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1649 - if (retval != STATUS_SUCCESS) 1650 - return STATUS_FAIL; 1651 - 1652 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1653 - if (retval != STATUS_SUCCESS) 1654 - return STATUS_FAIL; 1655 - 1656 - if (!(val & INT_REG_CED)) { 1657 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1658 - return STATUS_FAIL; 1659 - } 1660 - } 1661 - 1662 - for (i = start_page; i < end_page; i++) { 1663 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1664 - ms_set_err_code(chip, MS_NO_CARD); 1665 - return STATUS_FAIL; 1666 - } 1667 - 1668 - retval = ms_read_extra_data(chip, old_blk, i, extra, 1669 - MS_EXTRA_SIZE); 1670 - if (retval != STATUS_SUCCESS) 1671 - return STATUS_FAIL; 1672 - 1673 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, 1674 - MS_EXTRA_SIZE, SYSTEM_PARAM, 6); 1675 - if (retval != STATUS_SUCCESS) 1676 - return STATUS_FAIL; 1677 - 1678 - ms_set_err_code(chip, MS_NO_ERROR); 1679 - 1680 - if (CHK_MS4BIT(ms_card)) 1681 - data[0] = 0x88; 1682 - else 1683 - data[0] = 0x80; 1684 - 1685 - data[1] = 0; 1686 - data[2] = (u8)(old_blk >> 8); 1687 - data[3] = (u8)old_blk; 1688 - data[4] = 0x20; 1689 - data[5] = i; 1690 - 1691 - retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1692 - data, 6); 1693 - if (retval != STATUS_SUCCESS) 1694 - return STATUS_FAIL; 1695 - 1696 - retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1697 - if (retval != STATUS_SUCCESS) 1698 - return STATUS_FAIL; 1699 - 1700 - ms_set_err_code(chip, MS_NO_ERROR); 1701 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1702 - if (retval != STATUS_SUCCESS) 1703 - return STATUS_FAIL; 1704 - 1705 - if (val & INT_REG_CMDNK) { 1706 - ms_set_err_code(chip, MS_CMD_NK); 1707 - return STATUS_FAIL; 1708 - } 1709 - 1710 - if (val & INT_REG_CED) { 1711 - if (val & INT_REG_ERR) { 1712 - retval = ms_read_status_reg(chip); 1713 - if (retval != STATUS_SUCCESS) { 1714 - uncorrect_flag = true; 1715 - dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1716 - } else { 1717 - uncorrect_flag = false; 1718 - } 1719 - 1720 - retval = ms_transfer_tpc(chip, 1721 - MS_TM_NORMAL_READ, 1722 - READ_PAGE_DATA, 1723 - 0, NO_WAIT_INT); 1724 - if (retval != STATUS_SUCCESS) 1725 - return STATUS_FAIL; 1726 - 1727 - if (uncorrect_flag) { 1728 - ms_set_page_status(log_blk, set_PS_NG, 1729 - extra, 1730 - MS_EXTRA_SIZE); 1731 - if (i == 0) 1732 - extra[0] &= 0xEF; 1733 - 1734 - ms_write_extra_data(chip, old_blk, i, 1735 - extra, 1736 - MS_EXTRA_SIZE); 1737 - dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1738 - i, extra[0]); 1739 - MS_SET_BAD_BLOCK_FLG(ms_card); 1740 - 1741 - ms_set_page_status(log_blk, 1742 - set_PS_error, extra, 1743 - MS_EXTRA_SIZE); 1744 - ms_write_extra_data(chip, new_blk, i, 1745 - extra, 1746 - MS_EXTRA_SIZE); 1747 - continue; 1748 - } 1749 - 1750 - for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 1751 - rty_cnt++) { 1752 - retval = ms_transfer_tpc(chip, 1753 - MS_TM_NORMAL_WRITE, 1754 - WRITE_PAGE_DATA, 1755 - 0, NO_WAIT_INT); 1756 - if (retval == STATUS_SUCCESS) 1757 - break; 1758 - } 1759 - if (rty_cnt == MS_MAX_RETRY_COUNT) 1760 - return STATUS_FAIL; 1761 - } 1762 - 1763 - if (!(val & INT_REG_BREQ)) { 1764 - ms_set_err_code(chip, MS_BREQ_ERROR); 1765 - return STATUS_FAIL; 1766 - } 1767 - } 1768 - 1769 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 1770 - SYSTEM_PARAM, (6 + MS_EXTRA_SIZE)); 1771 - if (retval != STATUS_SUCCESS) 1772 - return STATUS_FAIL; 1773 - 1774 - ms_set_err_code(chip, MS_NO_ERROR); 1775 - 1776 - if (CHK_MS4BIT(ms_card)) 1777 - data[0] = 0x88; 1778 - else 1779 - data[0] = 0x80; 1780 - 1781 - data[1] = 0; 1782 - data[2] = (u8)(new_blk >> 8); 1783 - data[3] = (u8)new_blk; 1784 - data[4] = 0x20; 1785 - data[5] = i; 1786 - 1787 - if ((extra[0] & 0x60) != 0x60) 1788 - data[6] = extra[0]; 1789 - else 1790 - data[6] = 0xF8; 1791 - 1792 - data[6 + 1] = 0xFF; 1793 - data[6 + 2] = (u8)(log_blk >> 8); 1794 - data[6 + 3] = (u8)log_blk; 1795 - 1796 - for (j = 4; j <= MS_EXTRA_SIZE; j++) 1797 - data[6 + j] = 0xFF; 1798 - 1799 - retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1800 - NO_WAIT_INT, data, 16); 1801 - if (retval != STATUS_SUCCESS) 1802 - return STATUS_FAIL; 1803 - 1804 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1805 - if (retval != STATUS_SUCCESS) 1806 - return STATUS_FAIL; 1807 - 1808 - ms_set_err_code(chip, MS_NO_ERROR); 1809 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1810 - if (retval != STATUS_SUCCESS) 1811 - return STATUS_FAIL; 1812 - 1813 - if (val & INT_REG_CMDNK) { 1814 - ms_set_err_code(chip, MS_CMD_NK); 1815 - return STATUS_FAIL; 1816 - } 1817 - 1818 - if (val & INT_REG_CED) { 1819 - if (val & INT_REG_ERR) { 1820 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1821 - return STATUS_FAIL; 1822 - } 1823 - } 1824 - 1825 - if (i == 0) { 1826 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, 1827 - MS_EXTRA_SIZE, SYSTEM_PARAM, 1828 - 7); 1829 - if (retval != STATUS_SUCCESS) 1830 - return STATUS_FAIL; 1831 - 1832 - ms_set_err_code(chip, MS_NO_ERROR); 1833 - 1834 - if (CHK_MS4BIT(ms_card)) 1835 - data[0] = 0x88; 1836 - else 1837 - data[0] = 0x80; 1838 - 1839 - data[1] = 0; 1840 - data[2] = (u8)(old_blk >> 8); 1841 - data[3] = (u8)old_blk; 1842 - data[4] = 0x80; 1843 - data[5] = 0; 1844 - data[6] = 0xEF; 1845 - data[7] = 0xFF; 1846 - 1847 - retval = ms_write_bytes(chip, WRITE_REG, 7, 1848 - NO_WAIT_INT, data, 8); 1849 - if (retval != STATUS_SUCCESS) 1850 - return STATUS_FAIL; 1851 - 1852 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1853 - if (retval != STATUS_SUCCESS) 1854 - return STATUS_FAIL; 1855 - 1856 - ms_set_err_code(chip, MS_NO_ERROR); 1857 - retval = ms_read_bytes(chip, GET_INT, 1, 1858 - NO_WAIT_INT, &val, 1); 1859 - if (retval != STATUS_SUCCESS) 1860 - return STATUS_FAIL; 1861 - 1862 - if (val & INT_REG_CMDNK) { 1863 - ms_set_err_code(chip, MS_CMD_NK); 1864 - return STATUS_FAIL; 1865 - } 1866 - 1867 - if (val & INT_REG_CED) { 1868 - if (val & INT_REG_ERR) { 1869 - ms_set_err_code(chip, 1870 - MS_FLASH_WRITE_ERROR); 1871 - return STATUS_FAIL; 1872 - } 1873 - } 1874 - } 1875 - } 1876 - 1877 - return STATUS_SUCCESS; 1878 - } 1879 - 1880 - static int reset_ms(struct rtsx_chip *chip) 1881 - { 1882 - struct ms_info *ms_card = &chip->ms_card; 1883 - int retval; 1884 - u16 i, reg_addr, block_size; 1885 - u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 1886 - #ifndef SUPPORT_MAGIC_GATE 1887 - u16 eblock_cnt; 1888 - #endif 1889 - 1890 - retval = ms_prepare_reset(chip); 1891 - if (retval != STATUS_SUCCESS) 1892 - return STATUS_FAIL; 1893 - 1894 - ms_card->ms_type |= TYPE_MS; 1895 - 1896 - retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 1897 - if (retval != STATUS_SUCCESS) 1898 - return STATUS_FAIL; 1899 - 1900 - retval = ms_read_status_reg(chip); 1901 - if (retval != STATUS_SUCCESS) 1902 - return STATUS_FAIL; 1903 - 1904 - retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1905 - if (retval) 1906 - return retval; 1907 - 1908 - if (val & WRT_PRTCT) 1909 - chip->card_wp |= MS_CARD; 1910 - else 1911 - chip->card_wp &= ~MS_CARD; 1912 - 1913 - i = 0; 1914 - 1915 - RE_SEARCH: 1916 - /* Search Boot Block */ 1917 - while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 1918 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1919 - ms_set_err_code(chip, MS_NO_CARD); 1920 - return STATUS_FAIL; 1921 - } 1922 - 1923 - retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 1924 - if (retval != STATUS_SUCCESS) { 1925 - i++; 1926 - continue; 1927 - } 1928 - 1929 - if (extra[0] & BLOCK_OK) { 1930 - if (!(extra[1] & NOT_BOOT_BLOCK)) { 1931 - ms_card->boot_block = i; 1932 - break; 1933 - } 1934 - } 1935 - i++; 1936 - } 1937 - 1938 - if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 1939 - dev_dbg(rtsx_dev(chip), "No boot block found!"); 1940 - return STATUS_FAIL; 1941 - } 1942 - 1943 - for (j = 0; j < 3; j++) { 1944 - retval = ms_read_page(chip, ms_card->boot_block, j); 1945 - if (retval != STATUS_SUCCESS) { 1946 - if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1947 - i = ms_card->boot_block + 1; 1948 - ms_set_err_code(chip, MS_NO_ERROR); 1949 - goto RE_SEARCH; 1950 - } 1951 - } 1952 - } 1953 - 1954 - retval = ms_read_page(chip, ms_card->boot_block, 0); 1955 - if (retval != STATUS_SUCCESS) 1956 - return STATUS_FAIL; 1957 - 1958 - /* Read MS system information as sys_info */ 1959 - rtsx_init_cmd(chip); 1960 - 1961 - for (i = 0; i < 96; i++) 1962 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 1963 - 1964 - retval = rtsx_send_cmd(chip, MS_CARD, 100); 1965 - if (retval < 0) 1966 - return STATUS_FAIL; 1967 - 1968 - ptr = rtsx_get_cmd_data(chip); 1969 - memcpy(ms_card->raw_sys_info, ptr, 96); 1970 - 1971 - /* Read useful block contents */ 1972 - rtsx_init_cmd(chip); 1973 - 1974 - rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 1975 - rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 1976 - 1977 - for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 1978 - reg_addr++) 1979 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 1980 - 1981 - for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 1982 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 1983 - 1984 - rtsx_add_cmd(chip, READ_REG_CMD, MS_device_type, 0, 0); 1985 - rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_support, 0, 0); 1986 - 1987 - retval = rtsx_send_cmd(chip, MS_CARD, 100); 1988 - if (retval < 0) 1989 - return STATUS_FAIL; 1990 - 1991 - ptr = rtsx_get_cmd_data(chip); 1992 - 1993 - dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 1994 - dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 1995 - 1996 - /* Block ID error 1997 - * HEADER_ID0, HEADER_ID1 1998 - */ 1999 - if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2000 - i = ms_card->boot_block + 1; 2001 - goto RE_SEARCH; 2002 - } 2003 - 2004 - /* Page size error 2005 - * PAGE_SIZE_0, PAGE_SIZE_1 2006 - */ 2007 - if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2008 - i = ms_card->boot_block + 1; 2009 - goto RE_SEARCH; 2010 - } 2011 - 2012 - if (ptr[14] == 1 || ptr[14] == 3) 2013 - chip->card_wp |= MS_CARD; 2014 - 2015 - /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2016 - block_size = ((u16)ptr[6] << 8) | ptr[7]; 2017 - if (block_size == 0x0010) { 2018 - /* Block size 16KB */ 2019 - ms_card->block_shift = 5; 2020 - ms_card->page_off = 0x1F; 2021 - } else if (block_size == 0x0008) { 2022 - /* Block size 8KB */ 2023 - ms_card->block_shift = 4; 2024 - ms_card->page_off = 0x0F; 2025 - } 2026 - 2027 - /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2028 - ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2029 - 2030 - #ifdef SUPPORT_MAGIC_GATE 2031 - j = ptr[10]; 2032 - 2033 - if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2034 - if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2035 - ms_card->capacity = 0x1EE0; 2036 - } else { /* Effective block for 8MB: 0x3E0 */ 2037 - ms_card->capacity = 0x3DE0; 2038 - } 2039 - } else { /* 16MB, 32MB, 64MB or 128MB */ 2040 - if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2041 - ms_card->capacity = 0x7BC0; 2042 - } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2043 - ms_card->capacity = 0xF7C0; 2044 - } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2045 - ms_card->capacity = 0x1EF80; 2046 - } else { /* Effective block for 128MB: 0x1F00 */ 2047 - ms_card->capacity = 0x3DF00; 2048 - } 2049 - } 2050 - #else 2051 - /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2052 - eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2053 - 2054 - ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2055 - #endif 2056 - 2057 - chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2058 - 2059 - /* Switch I/F Mode */ 2060 - if (ptr[15]) { 2061 - retval = ms_set_rw_reg_addr(chip, 0, 0, SYSTEM_PARAM, 1); 2062 - if (retval != STATUS_SUCCESS) 2063 - return STATUS_FAIL; 2064 - 2065 - retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2066 - if (retval) 2067 - return retval; 2068 - 2069 - retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2070 - if (retval) 2071 - return retval; 2072 - 2073 - retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2074 - NO_WAIT_INT); 2075 - if (retval != STATUS_SUCCESS) 2076 - return STATUS_FAIL; 2077 - 2078 - retval = rtsx_write_register(chip, MS_CFG, 2079 - 0x58 | MS_NO_CHECK_INT, 2080 - MS_BUS_WIDTH_4 | 2081 - PUSH_TIME_ODD | 2082 - MS_NO_CHECK_INT); 2083 - if (retval) 2084 - return retval; 2085 - 2086 - ms_card->ms_type |= MS_4BIT; 2087 - } 2088 - 2089 - if (CHK_MS4BIT(ms_card)) 2090 - chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2091 - else 2092 - chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2093 - 2094 - return STATUS_SUCCESS; 2095 - } 2096 - 2097 - static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2098 - { 2099 - struct ms_info *ms_card = &chip->ms_card; 2100 - int size, i, seg_no, retval; 2101 - u16 defect_block, reg_addr; 2102 - u8 val1, val2; 2103 - 2104 - ms_card->segment_cnt = ms_card->total_block >> 9; 2105 - dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2106 - ms_card->segment_cnt); 2107 - 2108 - size = ms_card->segment_cnt * sizeof(struct zone_entry); 2109 - ms_card->segment = vzalloc(size); 2110 - if (!ms_card->segment) 2111 - return STATUS_FAIL; 2112 - 2113 - retval = ms_read_page(chip, ms_card->boot_block, 1); 2114 - if (retval != STATUS_SUCCESS) 2115 - goto INIT_FAIL; 2116 - 2117 - reg_addr = PPBUF_BASE2; 2118 - for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2119 - int block_no; 2120 - 2121 - retval = rtsx_read_register(chip, reg_addr++, &val1); 2122 - if (retval != STATUS_SUCCESS) 2123 - goto INIT_FAIL; 2124 - 2125 - retval = rtsx_read_register(chip, reg_addr++, &val2); 2126 - if (retval != STATUS_SUCCESS) 2127 - goto INIT_FAIL; 2128 - 2129 - defect_block = ((u16)val1 << 8) | val2; 2130 - if (defect_block == 0xFFFF) 2131 - break; 2132 - 2133 - seg_no = defect_block / 512; 2134 - 2135 - block_no = ms_card->segment[seg_no].disable_count++; 2136 - ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2137 - } 2138 - 2139 - for (i = 0; i < ms_card->segment_cnt; i++) { 2140 - ms_card->segment[i].build_flag = 0; 2141 - ms_card->segment[i].l2p_table = NULL; 2142 - ms_card->segment[i].free_table = NULL; 2143 - ms_card->segment[i].get_index = 0; 2144 - ms_card->segment[i].set_index = 0; 2145 - ms_card->segment[i].unused_blk_cnt = 0; 2146 - 2147 - dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2148 - i, ms_card->segment[i].disable_count); 2149 - } 2150 - 2151 - return STATUS_SUCCESS; 2152 - 2153 - INIT_FAIL: 2154 - vfree(ms_card->segment); 2155 - ms_card->segment = NULL; 2156 - 2157 - return STATUS_FAIL; 2158 - } 2159 - 2160 - static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2161 - { 2162 - struct ms_info *ms_card = &chip->ms_card; 2163 - struct zone_entry *segment; 2164 - 2165 - if (!ms_card->segment) 2166 - return 0xFFFF; 2167 - 2168 - segment = &ms_card->segment[seg_no]; 2169 - 2170 - if (segment->l2p_table) 2171 - return segment->l2p_table[log_off]; 2172 - 2173 - return 0xFFFF; 2174 - } 2175 - 2176 - static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2177 - int seg_no, u16 log_off, u16 phy_blk) 2178 - { 2179 - struct ms_info *ms_card = &chip->ms_card; 2180 - struct zone_entry *segment; 2181 - 2182 - if (!ms_card->segment) 2183 - return; 2184 - 2185 - segment = &ms_card->segment[seg_no]; 2186 - if (segment->l2p_table) 2187 - segment->l2p_table[log_off] = phy_blk; 2188 - } 2189 - 2190 - static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2191 - { 2192 - struct ms_info *ms_card = &chip->ms_card; 2193 - struct zone_entry *segment; 2194 - int seg_no; 2195 - 2196 - seg_no = (int)phy_blk >> 9; 2197 - segment = &ms_card->segment[seg_no]; 2198 - 2199 - segment->free_table[segment->set_index++] = phy_blk; 2200 - if (segment->set_index >= MS_FREE_TABLE_CNT) 2201 - segment->set_index = 0; 2202 - 2203 - segment->unused_blk_cnt++; 2204 - } 2205 - 2206 - static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2207 - { 2208 - struct ms_info *ms_card = &chip->ms_card; 2209 - struct zone_entry *segment; 2210 - u16 phy_blk; 2211 - 2212 - segment = &ms_card->segment[seg_no]; 2213 - 2214 - if (segment->unused_blk_cnt <= 0) 2215 - return 0xFFFF; 2216 - 2217 - phy_blk = segment->free_table[segment->get_index]; 2218 - segment->free_table[segment->get_index++] = 0xFFFF; 2219 - if (segment->get_index >= MS_FREE_TABLE_CNT) 2220 - segment->get_index = 0; 2221 - 2222 - segment->unused_blk_cnt--; 2223 - 2224 - return phy_blk; 2225 - } 2226 - 2227 - static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2228 - 2974, 3470, 3966, 4462, 4958, 2229 - 5454, 5950, 6446, 6942, 7438, 2230 - 7934}; 2231 - 2232 - static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2233 - u16 log_off, u8 us1, u8 us2) 2234 - { 2235 - struct ms_info *ms_card = &chip->ms_card; 2236 - struct zone_entry *segment; 2237 - int seg_no; 2238 - u16 tmp_blk; 2239 - 2240 - seg_no = (int)phy_blk >> 9; 2241 - segment = &ms_card->segment[seg_no]; 2242 - tmp_blk = segment->l2p_table[log_off]; 2243 - 2244 - if (us1 != us2) { 2245 - if (us1 == 0) { 2246 - if (!(chip->card_wp & MS_CARD)) 2247 - ms_erase_block(chip, tmp_blk); 2248 - 2249 - ms_set_unused_block(chip, tmp_blk); 2250 - segment->l2p_table[log_off] = phy_blk; 2251 - } else { 2252 - if (!(chip->card_wp & MS_CARD)) 2253 - ms_erase_block(chip, phy_blk); 2254 - 2255 - ms_set_unused_block(chip, phy_blk); 2256 - } 2257 - } else { 2258 - if (phy_blk < tmp_blk) { 2259 - if (!(chip->card_wp & MS_CARD)) 2260 - ms_erase_block(chip, phy_blk); 2261 - 2262 - ms_set_unused_block(chip, phy_blk); 2263 - } else { 2264 - if (!(chip->card_wp & MS_CARD)) 2265 - ms_erase_block(chip, tmp_blk); 2266 - 2267 - ms_set_unused_block(chip, tmp_blk); 2268 - segment->l2p_table[log_off] = phy_blk; 2269 - } 2270 - } 2271 - 2272 - return STATUS_SUCCESS; 2273 - } 2274 - 2275 - static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2276 - { 2277 - struct ms_info *ms_card = &chip->ms_card; 2278 - struct zone_entry *segment; 2279 - bool defect_flag; 2280 - int retval, table_size, disable_cnt, i; 2281 - u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2282 - u8 extra[MS_EXTRA_SIZE], us1, us2; 2283 - 2284 - dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, seg_no); 2285 - 2286 - if (!ms_card->segment) { 2287 - retval = ms_init_l2p_tbl(chip); 2288 - if (retval != STATUS_SUCCESS) 2289 - return retval; 2290 - } 2291 - 2292 - if (ms_card->segment[seg_no].build_flag) { 2293 - dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2294 - seg_no); 2295 - return STATUS_SUCCESS; 2296 - } 2297 - 2298 - if (seg_no == 0) 2299 - table_size = 494; 2300 - else 2301 - table_size = 496; 2302 - 2303 - segment = &ms_card->segment[seg_no]; 2304 - 2305 - if (!segment->l2p_table) { 2306 - segment->l2p_table = vmalloc(array_size(table_size, 2)); 2307 - if (!segment->l2p_table) 2308 - goto BUILD_FAIL; 2309 - } 2310 - memset((u8 *)(segment->l2p_table), 0xff, array_size(table_size, 2)); 2311 - 2312 - if (!segment->free_table) { 2313 - segment->free_table = vmalloc(array_size(MS_FREE_TABLE_CNT, 2)); 2314 - if (!segment->free_table) 2315 - goto BUILD_FAIL; 2316 - } 2317 - memset((u8 *)(segment->free_table), 0xff, array_size(MS_FREE_TABLE_CNT, 2)); 2318 - 2319 - start = (u16)seg_no << 9; 2320 - end = (u16)(seg_no + 1) << 9; 2321 - 2322 - disable_cnt = segment->disable_count; 2323 - 2324 - segment->get_index = 0; 2325 - segment->set_index = 0; 2326 - segment->unused_blk_cnt = 0; 2327 - 2328 - for (phy_blk = start; phy_blk < end; phy_blk++) { 2329 - if (disable_cnt) { 2330 - defect_flag = false; 2331 - for (i = 0; i < segment->disable_count; i++) { 2332 - if (phy_blk == segment->defect_list[i]) { 2333 - defect_flag = true; 2334 - break; 2335 - } 2336 - } 2337 - if (defect_flag) { 2338 - disable_cnt--; 2339 - continue; 2340 - } 2341 - } 2342 - 2343 - retval = ms_read_extra_data(chip, phy_blk, 0, 2344 - extra, MS_EXTRA_SIZE); 2345 - if (retval != STATUS_SUCCESS) { 2346 - dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2347 - ms_set_bad_block(chip, phy_blk); 2348 - continue; 2349 - } 2350 - 2351 - if (seg_no == ms_card->segment_cnt - 1) { 2352 - if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2353 - if (!(chip->card_wp & MS_CARD)) { 2354 - retval = ms_erase_block(chip, phy_blk); 2355 - if (retval != STATUS_SUCCESS) 2356 - continue; 2357 - extra[2] = 0xff; 2358 - extra[3] = 0xff; 2359 - } 2360 - } 2361 - } 2362 - 2363 - if (!(extra[0] & BLOCK_OK)) 2364 - continue; 2365 - if (!(extra[1] & NOT_BOOT_BLOCK)) 2366 - continue; 2367 - if ((extra[0] & PAGE_OK) != PAGE_OK) 2368 - continue; 2369 - 2370 - log_blk = ((u16)extra[2] << 8) | extra[3]; 2371 - 2372 - if (log_blk == 0xFFFF) { 2373 - if (!(chip->card_wp & MS_CARD)) { 2374 - retval = ms_erase_block(chip, phy_blk); 2375 - if (retval != STATUS_SUCCESS) 2376 - continue; 2377 - } 2378 - ms_set_unused_block(chip, phy_blk); 2379 - continue; 2380 - } 2381 - 2382 - if (log_blk < ms_start_idx[seg_no] || 2383 - log_blk >= ms_start_idx[seg_no + 1]) { 2384 - if (!(chip->card_wp & MS_CARD)) { 2385 - retval = ms_erase_block(chip, phy_blk); 2386 - if (retval != STATUS_SUCCESS) 2387 - continue; 2388 - } 2389 - ms_set_unused_block(chip, phy_blk); 2390 - continue; 2391 - } 2392 - 2393 - idx = log_blk - ms_start_idx[seg_no]; 2394 - 2395 - if (segment->l2p_table[idx] == 0xFFFF) { 2396 - segment->l2p_table[idx] = phy_blk; 2397 - continue; 2398 - } 2399 - 2400 - us1 = extra[0] & 0x10; 2401 - tmp_blk = segment->l2p_table[idx]; 2402 - retval = ms_read_extra_data(chip, tmp_blk, 0, 2403 - extra, MS_EXTRA_SIZE); 2404 - if (retval != STATUS_SUCCESS) 2405 - continue; 2406 - us2 = extra[0] & 0x10; 2407 - 2408 - (void)ms_arbitrate_l2p(chip, phy_blk, 2409 - log_blk - ms_start_idx[seg_no], us1, us2); 2410 - } 2411 - 2412 - segment->build_flag = 1; 2413 - 2414 - dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2415 - segment->unused_blk_cnt); 2416 - 2417 - /* Logical Address Confirmation Process */ 2418 - if (seg_no == ms_card->segment_cnt - 1) { 2419 - if (segment->unused_blk_cnt < 2) 2420 - chip->card_wp |= MS_CARD; 2421 - } else { 2422 - if (segment->unused_blk_cnt < 1) 2423 - chip->card_wp |= MS_CARD; 2424 - } 2425 - 2426 - if (chip->card_wp & MS_CARD) 2427 - return STATUS_SUCCESS; 2428 - 2429 - for (log_blk = ms_start_idx[seg_no]; 2430 - log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2431 - idx = log_blk - ms_start_idx[seg_no]; 2432 - if (segment->l2p_table[idx] == 0xFFFF) { 2433 - phy_blk = ms_get_unused_block(chip, seg_no); 2434 - if (phy_blk == 0xFFFF) { 2435 - chip->card_wp |= MS_CARD; 2436 - return STATUS_SUCCESS; 2437 - } 2438 - retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2439 - if (retval != STATUS_SUCCESS) 2440 - goto BUILD_FAIL; 2441 - 2442 - segment->l2p_table[idx] = phy_blk; 2443 - if (seg_no == ms_card->segment_cnt - 1) { 2444 - if (segment->unused_blk_cnt < 2) { 2445 - chip->card_wp |= MS_CARD; 2446 - return STATUS_SUCCESS; 2447 - } 2448 - } else { 2449 - if (segment->unused_blk_cnt < 1) { 2450 - chip->card_wp |= MS_CARD; 2451 - return STATUS_SUCCESS; 2452 - } 2453 - } 2454 - } 2455 - } 2456 - 2457 - /* Make boot block be the first normal block */ 2458 - if (seg_no == 0) { 2459 - for (log_blk = 0; log_blk < 494; log_blk++) { 2460 - tmp_blk = segment->l2p_table[log_blk]; 2461 - if (tmp_blk < ms_card->boot_block) { 2462 - dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2463 - 2464 - if (chip->card_wp & MS_CARD) 2465 - break; 2466 - 2467 - phy_blk = ms_get_unused_block(chip, 0); 2468 - retval = ms_copy_page(chip, tmp_blk, phy_blk, 2469 - log_blk, 0, 2470 - ms_card->page_off + 1); 2471 - if (retval != STATUS_SUCCESS) 2472 - return STATUS_FAIL; 2473 - 2474 - segment->l2p_table[log_blk] = phy_blk; 2475 - 2476 - retval = ms_set_bad_block(chip, tmp_blk); 2477 - if (retval != STATUS_SUCCESS) 2478 - return STATUS_FAIL; 2479 - } 2480 - } 2481 - } 2482 - 2483 - return STATUS_SUCCESS; 2484 - 2485 - BUILD_FAIL: 2486 - segment->build_flag = 0; 2487 - vfree(segment->l2p_table); 2488 - segment->l2p_table = NULL; 2489 - vfree(segment->free_table); 2490 - segment->free_table = NULL; 2491 - 2492 - return STATUS_FAIL; 2493 - } 2494 - 2495 - int reset_ms_card(struct rtsx_chip *chip) 2496 - { 2497 - struct ms_info *ms_card = &chip->ms_card; 2498 - int seg_no = ms_card->total_block / 512 - 1; 2499 - int retval; 2500 - 2501 - memset(ms_card, 0, sizeof(struct ms_info)); 2502 - 2503 - retval = enable_card_clock(chip, MS_CARD); 2504 - if (retval != STATUS_SUCCESS) 2505 - return STATUS_FAIL; 2506 - 2507 - retval = select_card(chip, MS_CARD); 2508 - if (retval != STATUS_SUCCESS) 2509 - return STATUS_FAIL; 2510 - 2511 - ms_card->ms_type = 0; 2512 - 2513 - retval = reset_ms_pro(chip); 2514 - if (retval != STATUS_SUCCESS) { 2515 - if (ms_card->check_ms_flow) { 2516 - retval = reset_ms(chip); 2517 - if (retval != STATUS_SUCCESS) 2518 - return STATUS_FAIL; 2519 - } else { 2520 - return STATUS_FAIL; 2521 - } 2522 - } 2523 - 2524 - retval = ms_set_init_para(chip); 2525 - if (retval != STATUS_SUCCESS) 2526 - return STATUS_FAIL; 2527 - 2528 - if (!CHK_MSPRO(ms_card)) { 2529 - /* Build table for the last segment, 2530 - * to check if L2P table block exists, erasing it 2531 - */ 2532 - retval = ms_build_l2p_tbl(chip, seg_no); 2533 - if (retval != STATUS_SUCCESS) 2534 - return STATUS_FAIL; 2535 - } 2536 - 2537 - dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2538 - 2539 - return STATUS_SUCCESS; 2540 - } 2541 - 2542 - static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2543 - u32 start_sec, u16 sec_cnt, u8 cmd) 2544 - { 2545 - int retval, i; 2546 - u8 data[8]; 2547 - 2548 - data[0] = cmd; 2549 - data[1] = (u8)(sec_cnt >> 8); 2550 - data[2] = (u8)sec_cnt; 2551 - data[3] = (u8)(start_sec >> 24); 2552 - data[4] = (u8)(start_sec >> 16); 2553 - data[5] = (u8)(start_sec >> 8); 2554 - data[6] = (u8)start_sec; 2555 - data[7] = 0; 2556 - 2557 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2558 - retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2559 - WAIT_INT, data, 8); 2560 - if (retval == STATUS_SUCCESS) 2561 - break; 2562 - } 2563 - if (i == MS_MAX_RETRY_COUNT) 2564 - return STATUS_FAIL; 2565 - 2566 - return STATUS_SUCCESS; 2567 - } 2568 - 2569 - void mspro_stop_seq_mode(struct rtsx_chip *chip) 2570 - { 2571 - struct ms_info *ms_card = &chip->ms_card; 2572 - int retval; 2573 - 2574 - if (ms_card->seq_mode) { 2575 - retval = ms_switch_clock(chip); 2576 - if (retval != STATUS_SUCCESS) 2577 - return; 2578 - 2579 - ms_card->seq_mode = 0; 2580 - ms_card->total_sec_cnt = 0; 2581 - ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2582 - 2583 - rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2584 - } 2585 - } 2586 - 2587 - static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2588 - { 2589 - struct ms_info *ms_card = &chip->ms_card; 2590 - int retval; 2591 - 2592 - if (chip->asic_code) { 2593 - if (ms_card->ms_clock > 30) 2594 - ms_card->ms_clock -= 20; 2595 - } else { 2596 - if (ms_card->ms_clock == CLK_80) 2597 - ms_card->ms_clock = CLK_60; 2598 - else if (ms_card->ms_clock == CLK_60) 2599 - ms_card->ms_clock = CLK_40; 2600 - } 2601 - 2602 - retval = ms_switch_clock(chip); 2603 - if (retval != STATUS_SUCCESS) 2604 - return STATUS_FAIL; 2605 - 2606 - return STATUS_SUCCESS; 2607 - } 2608 - 2609 - static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2610 - struct rtsx_chip *chip, u32 start_sector, 2611 - u16 sector_cnt) 2612 - { 2613 - struct ms_info *ms_card = &chip->ms_card; 2614 - bool mode_2k = false; 2615 - int retval; 2616 - u16 count; 2617 - u8 val, trans_mode, rw_tpc, rw_cmd; 2618 - 2619 - ms_set_err_code(chip, MS_NO_ERROR); 2620 - 2621 - ms_card->cleanup_counter = 0; 2622 - 2623 - if (CHK_MSHG(ms_card)) { 2624 - if ((start_sector % 4) || (sector_cnt % 4)) { 2625 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2626 - rw_tpc = PRO_READ_LONG_DATA; 2627 - rw_cmd = PRO_READ_DATA; 2628 - } else { 2629 - rw_tpc = PRO_WRITE_LONG_DATA; 2630 - rw_cmd = PRO_WRITE_DATA; 2631 - } 2632 - } else { 2633 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2634 - rw_tpc = PRO_READ_QUAD_DATA; 2635 - rw_cmd = PRO_READ_2K_DATA; 2636 - } else { 2637 - rw_tpc = PRO_WRITE_QUAD_DATA; 2638 - rw_cmd = PRO_WRITE_2K_DATA; 2639 - } 2640 - mode_2k = true; 2641 - } 2642 - } else { 2643 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2644 - rw_tpc = PRO_READ_LONG_DATA; 2645 - rw_cmd = PRO_READ_DATA; 2646 - } else { 2647 - rw_tpc = PRO_WRITE_LONG_DATA; 2648 - rw_cmd = PRO_WRITE_DATA; 2649 - } 2650 - } 2651 - 2652 - retval = ms_switch_clock(chip); 2653 - if (retval != STATUS_SUCCESS) 2654 - return STATUS_FAIL; 2655 - 2656 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 2657 - trans_mode = MS_TM_AUTO_READ; 2658 - else 2659 - trans_mode = MS_TM_AUTO_WRITE; 2660 - 2661 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 2662 - if (retval) 2663 - return retval; 2664 - 2665 - if (ms_card->seq_mode) { 2666 - if (ms_card->pre_dir != srb->sc_data_direction || 2667 - ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != 2668 - start_sector) || 2669 - (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) || 2670 - (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) || 2671 - !(val & MS_INT_BREQ) || 2672 - ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 2673 - ms_card->seq_mode = 0; 2674 - ms_card->total_sec_cnt = 0; 2675 - if (val & MS_INT_BREQ) { 2676 - retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2677 - if (retval != STATUS_SUCCESS) 2678 - return STATUS_FAIL; 2679 - 2680 - rtsx_write_register(chip, RBCTL, RB_FLUSH, 2681 - RB_FLUSH); 2682 - } 2683 - } 2684 - } 2685 - 2686 - if (!ms_card->seq_mode) { 2687 - ms_card->total_sec_cnt = 0; 2688 - if (sector_cnt >= SEQ_START_CRITERIA) { 2689 - if ((ms_card->capacity - start_sector) > 0xFE00) 2690 - count = 0xFE00; 2691 - else 2692 - count = (u16)(ms_card->capacity - start_sector); 2693 - 2694 - if (count > sector_cnt) { 2695 - if (mode_2k) 2696 - ms_card->seq_mode = MODE_2K_SEQ; 2697 - else 2698 - ms_card->seq_mode = MODE_512_SEQ; 2699 - } 2700 - } else { 2701 - count = sector_cnt; 2702 - } 2703 - retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 2704 - if (retval != STATUS_SUCCESS) { 2705 - ms_card->seq_mode = 0; 2706 - return STATUS_FAIL; 2707 - } 2708 - } 2709 - 2710 - retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 2711 - WAIT_INT, mode_2k, scsi_sg_count(srb), 2712 - scsi_sglist(srb), scsi_bufflen(srb)); 2713 - if (retval != STATUS_SUCCESS) { 2714 - ms_card->seq_mode = 0; 2715 - rtsx_read_register(chip, MS_TRANS_CFG, &val); 2716 - rtsx_clear_ms_error(chip); 2717 - 2718 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2719 - chip->rw_need_retry = 0; 2720 - dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", 2721 - __func__); 2722 - return STATUS_FAIL; 2723 - } 2724 - 2725 - if (val & MS_INT_BREQ) 2726 - ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2727 - 2728 - if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 2729 - dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 2730 - chip->rw_need_retry = 1; 2731 - ms_auto_tune_clock(chip); 2732 - } 2733 - 2734 - return retval; 2735 - } 2736 - 2737 - if (ms_card->seq_mode) { 2738 - ms_card->pre_sec_addr = start_sector; 2739 - ms_card->pre_sec_cnt = sector_cnt; 2740 - ms_card->pre_dir = srb->sc_data_direction; 2741 - ms_card->total_sec_cnt += sector_cnt; 2742 - } 2743 - 2744 - return STATUS_SUCCESS; 2745 - } 2746 - 2747 - static int mspro_read_format_progress(struct rtsx_chip *chip, 2748 - const int short_data_len) 2749 - { 2750 - struct ms_info *ms_card = &chip->ms_card; 2751 - int retval, i; 2752 - u32 total_progress, cur_progress; 2753 - u8 cnt, tmp; 2754 - u8 data[8]; 2755 - 2756 - dev_dbg(rtsx_dev(chip), "%s, short_data_len = %d\n", __func__, 2757 - short_data_len); 2758 - 2759 - retval = ms_switch_clock(chip); 2760 - if (retval != STATUS_SUCCESS) { 2761 - ms_card->format_status = FORMAT_FAIL; 2762 - return STATUS_FAIL; 2763 - } 2764 - 2765 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2766 - if (retval != STATUS_SUCCESS) { 2767 - ms_card->format_status = FORMAT_FAIL; 2768 - return STATUS_FAIL; 2769 - } 2770 - 2771 - if (!(tmp & MS_INT_BREQ)) { 2772 - if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | 2773 - MS_INT_ERR)) == MS_INT_CED) { 2774 - ms_card->format_status = FORMAT_SUCCESS; 2775 - return STATUS_SUCCESS; 2776 - } 2777 - ms_card->format_status = FORMAT_FAIL; 2778 - return STATUS_FAIL; 2779 - } 2780 - 2781 - if (short_data_len >= 256) 2782 - cnt = 0; 2783 - else 2784 - cnt = (u8)short_data_len; 2785 - 2786 - retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 2787 - MS_NO_CHECK_INT); 2788 - if (retval != STATUS_SUCCESS) { 2789 - ms_card->format_status = FORMAT_FAIL; 2790 - return STATUS_FAIL; 2791 - } 2792 - 2793 - retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 2794 - data, 8); 2795 - if (retval != STATUS_SUCCESS) { 2796 - ms_card->format_status = FORMAT_FAIL; 2797 - return STATUS_FAIL; 2798 - } 2799 - 2800 - total_progress = (data[0] << 24) | (data[1] << 16) | 2801 - (data[2] << 8) | data[3]; 2802 - cur_progress = (data[4] << 24) | (data[5] << 16) | 2803 - (data[6] << 8) | data[7]; 2804 - 2805 - dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 2806 - total_progress, cur_progress); 2807 - 2808 - if (total_progress == 0) { 2809 - ms_card->progress = 0; 2810 - } else { 2811 - u64 ulltmp = (u64)cur_progress * (u64)65535; 2812 - 2813 - do_div(ulltmp, total_progress); 2814 - ms_card->progress = (u16)ulltmp; 2815 - } 2816 - dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 2817 - 2818 - for (i = 0; i < 5000; i++) { 2819 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2820 - if (retval != STATUS_SUCCESS) { 2821 - ms_card->format_status = FORMAT_FAIL; 2822 - return STATUS_FAIL; 2823 - } 2824 - if (tmp & (MS_INT_CED | MS_INT_CMDNK | 2825 - MS_INT_BREQ | MS_INT_ERR)) 2826 - break; 2827 - 2828 - wait_timeout(1); 2829 - } 2830 - 2831 - retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 2832 - if (retval != STATUS_SUCCESS) { 2833 - ms_card->format_status = FORMAT_FAIL; 2834 - return STATUS_FAIL; 2835 - } 2836 - 2837 - if (i == 5000) { 2838 - ms_card->format_status = FORMAT_FAIL; 2839 - return STATUS_FAIL; 2840 - } 2841 - 2842 - if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 2843 - ms_card->format_status = FORMAT_FAIL; 2844 - return STATUS_FAIL; 2845 - } 2846 - 2847 - if (tmp & MS_INT_CED) { 2848 - ms_card->format_status = FORMAT_SUCCESS; 2849 - ms_card->pro_under_formatting = 0; 2850 - } else if (tmp & MS_INT_BREQ) { 2851 - ms_card->format_status = FORMAT_IN_PROGRESS; 2852 - } else { 2853 - ms_card->format_status = FORMAT_FAIL; 2854 - ms_card->pro_under_formatting = 0; 2855 - return STATUS_FAIL; 2856 - } 2857 - 2858 - return STATUS_SUCCESS; 2859 - } 2860 - 2861 - void mspro_polling_format_status(struct rtsx_chip *chip) 2862 - { 2863 - struct ms_info *ms_card = &chip->ms_card; 2864 - int i; 2865 - 2866 - if (ms_card->pro_under_formatting && 2867 - (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 2868 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2869 - 2870 - for (i = 0; i < 65535; i++) { 2871 - mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 2872 - if (ms_card->format_status != FORMAT_IN_PROGRESS) 2873 - break; 2874 - } 2875 - } 2876 - } 2877 - 2878 - int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 2879 - int short_data_len, bool quick_format) 2880 - { 2881 - struct ms_info *ms_card = &chip->ms_card; 2882 - int retval, i; 2883 - u8 buf[8], tmp; 2884 - u16 para; 2885 - 2886 - retval = ms_switch_clock(chip); 2887 - if (retval != STATUS_SUCCESS) 2888 - return STATUS_FAIL; 2889 - 2890 - retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, PRO_TPC_PARM, 0x01); 2891 - if (retval != STATUS_SUCCESS) 2892 - return STATUS_FAIL; 2893 - 2894 - memset(buf, 0, 2); 2895 - switch (short_data_len) { 2896 - case 32: 2897 - buf[0] = 0; 2898 - break; 2899 - case 64: 2900 - buf[0] = 1; 2901 - break; 2902 - case 128: 2903 - buf[0] = 2; 2904 - break; 2905 - case 256: 2906 - default: 2907 - buf[0] = 3; 2908 - break; 2909 - } 2910 - 2911 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2912 - retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 2913 - NO_WAIT_INT, buf, 2); 2914 - if (retval == STATUS_SUCCESS) 2915 - break; 2916 - } 2917 - if (i == MS_MAX_RETRY_COUNT) 2918 - return STATUS_FAIL; 2919 - 2920 - if (quick_format) 2921 - para = 0x0000; 2922 - else 2923 - para = 0x0001; 2924 - 2925 - retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 2926 - if (retval != STATUS_SUCCESS) 2927 - return STATUS_FAIL; 2928 - 2929 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2930 - if (retval) 2931 - return retval; 2932 - 2933 - if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) 2934 - return STATUS_FAIL; 2935 - 2936 - if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 2937 - ms_card->pro_under_formatting = 1; 2938 - ms_card->progress = 0; 2939 - ms_card->format_status = FORMAT_IN_PROGRESS; 2940 - return STATUS_SUCCESS; 2941 - } 2942 - 2943 - if (tmp & MS_INT_CED) { 2944 - ms_card->pro_under_formatting = 0; 2945 - ms_card->progress = 0; 2946 - ms_card->format_status = FORMAT_SUCCESS; 2947 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 2948 - return STATUS_SUCCESS; 2949 - } 2950 - 2951 - return STATUS_FAIL; 2952 - } 2953 - 2954 - static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 2955 - u16 log_blk, u8 start_page, u8 end_page, 2956 - u8 *buf, unsigned int *index, 2957 - unsigned int *offset) 2958 - { 2959 - struct ms_info *ms_card = &chip->ms_card; 2960 - int retval, i; 2961 - u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 2962 - u8 *ptr; 2963 - 2964 - retval = ms_read_extra_data(chip, phy_blk, start_page, 2965 - extra, MS_EXTRA_SIZE); 2966 - if (retval == STATUS_SUCCESS) { 2967 - if ((extra[1] & 0x30) != 0x30) { 2968 - ms_set_err_code(chip, MS_FLASH_READ_ERROR); 2969 - return STATUS_FAIL; 2970 - } 2971 - } 2972 - 2973 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 2974 - SYSTEM_PARAM, 6); 2975 - if (retval != STATUS_SUCCESS) 2976 - return STATUS_FAIL; 2977 - 2978 - if (CHK_MS4BIT(ms_card)) 2979 - data[0] = 0x88; 2980 - else 2981 - data[0] = 0x80; 2982 - 2983 - data[1] = 0; 2984 - data[2] = (u8)(phy_blk >> 8); 2985 - data[3] = (u8)phy_blk; 2986 - data[4] = 0; 2987 - data[5] = start_page; 2988 - 2989 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2990 - retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 2991 - data, 6); 2992 - if (retval == STATUS_SUCCESS) 2993 - break; 2994 - } 2995 - if (i == MS_MAX_RETRY_COUNT) 2996 - return STATUS_FAIL; 2997 - 2998 - ms_set_err_code(chip, MS_NO_ERROR); 2999 - 3000 - retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3001 - if (retval != STATUS_SUCCESS) 3002 - return STATUS_FAIL; 3003 - 3004 - ptr = buf; 3005 - 3006 - for (page_addr = start_page; page_addr < end_page; page_addr++) { 3007 - ms_set_err_code(chip, MS_NO_ERROR); 3008 - 3009 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3010 - ms_set_err_code(chip, MS_NO_CARD); 3011 - return STATUS_FAIL; 3012 - } 3013 - 3014 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3015 - if (retval != STATUS_SUCCESS) 3016 - return STATUS_FAIL; 3017 - 3018 - if (val & INT_REG_CMDNK) { 3019 - ms_set_err_code(chip, MS_CMD_NK); 3020 - return STATUS_FAIL; 3021 - } 3022 - if (val & INT_REG_ERR) { 3023 - if (val & INT_REG_BREQ) { 3024 - retval = ms_read_status_reg(chip); 3025 - if (retval != STATUS_SUCCESS) { 3026 - if (!(chip->card_wp & MS_CARD)) { 3027 - reset_ms(chip); 3028 - ms_set_page_status 3029 - (log_blk, set_PS_NG, 3030 - extra, 3031 - MS_EXTRA_SIZE); 3032 - ms_write_extra_data 3033 - (chip, phy_blk, 3034 - page_addr, extra, 3035 - MS_EXTRA_SIZE); 3036 - } 3037 - ms_set_err_code(chip, 3038 - MS_FLASH_READ_ERROR); 3039 - return STATUS_FAIL; 3040 - } 3041 - } else { 3042 - ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3043 - return STATUS_FAIL; 3044 - } 3045 - } else { 3046 - if (!(val & INT_REG_BREQ)) { 3047 - ms_set_err_code(chip, MS_BREQ_ERROR); 3048 - return STATUS_FAIL; 3049 - } 3050 - } 3051 - 3052 - if (page_addr == (end_page - 1)) { 3053 - if (!(val & INT_REG_CED)) { 3054 - retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3055 - if (retval != STATUS_SUCCESS) 3056 - return STATUS_FAIL; 3057 - } 3058 - 3059 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3060 - &val, 1); 3061 - if (retval != STATUS_SUCCESS) 3062 - return STATUS_FAIL; 3063 - 3064 - if (!(val & INT_REG_CED)) { 3065 - ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3066 - return STATUS_FAIL; 3067 - } 3068 - 3069 - trans_cfg = NO_WAIT_INT; 3070 - } else { 3071 - trans_cfg = WAIT_INT; 3072 - } 3073 - 3074 - rtsx_init_cmd(chip); 3075 - 3076 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3077 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3078 - 0xFF, trans_cfg); 3079 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3080 - 0x01, RING_BUFFER); 3081 - 3082 - trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3083 - 3084 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3085 - MS_TRANSFER_START | MS_TM_NORMAL_READ); 3086 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3087 - MS_TRANSFER_END, MS_TRANSFER_END); 3088 - 3089 - rtsx_send_cmd_no_wait(chip); 3090 - 3091 - retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3092 - scsi_sg_count(chip->srb), 3093 - index, offset, 3094 - DMA_FROM_DEVICE, 3095 - chip->ms_timeout); 3096 - if (retval < 0) { 3097 - if (retval == -ETIMEDOUT) { 3098 - ms_set_err_code(chip, MS_TO_ERROR); 3099 - rtsx_clear_ms_error(chip); 3100 - return STATUS_TIMEDOUT; 3101 - } 3102 - 3103 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3104 - if (retval != STATUS_SUCCESS) { 3105 - ms_set_err_code(chip, MS_TO_ERROR); 3106 - rtsx_clear_ms_error(chip); 3107 - return STATUS_TIMEDOUT; 3108 - } 3109 - if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3110 - ms_set_err_code(chip, MS_CRC16_ERROR); 3111 - rtsx_clear_ms_error(chip); 3112 - return STATUS_FAIL; 3113 - } 3114 - } 3115 - 3116 - if (scsi_sg_count(chip->srb) == 0) 3117 - ptr += 512; 3118 - } 3119 - 3120 - return STATUS_SUCCESS; 3121 - } 3122 - 3123 - static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3124 - u16 new_blk, u16 log_blk, u8 start_page, 3125 - u8 end_page, u8 *buf, unsigned int *index, 3126 - unsigned int *offset) 3127 - { 3128 - struct ms_info *ms_card = &chip->ms_card; 3129 - int retval, i; 3130 - u8 page_addr, val, data[16]; 3131 - u8 *ptr; 3132 - 3133 - if (!start_page) { 3134 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 3135 - SYSTEM_PARAM, 7); 3136 - if (retval != STATUS_SUCCESS) 3137 - return STATUS_FAIL; 3138 - 3139 - if (CHK_MS4BIT(ms_card)) 3140 - data[0] = 0x88; 3141 - else 3142 - data[0] = 0x80; 3143 - 3144 - data[1] = 0; 3145 - data[2] = (u8)(old_blk >> 8); 3146 - data[3] = (u8)old_blk; 3147 - data[4] = 0x80; 3148 - data[5] = 0; 3149 - data[6] = 0xEF; 3150 - data[7] = 0xFF; 3151 - 3152 - retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3153 - data, 8); 3154 - if (retval != STATUS_SUCCESS) 3155 - return STATUS_FAIL; 3156 - 3157 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3158 - if (retval != STATUS_SUCCESS) 3159 - return STATUS_FAIL; 3160 - 3161 - ms_set_err_code(chip, MS_NO_ERROR); 3162 - retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3163 - NO_WAIT_INT); 3164 - if (retval != STATUS_SUCCESS) 3165 - return STATUS_FAIL; 3166 - } 3167 - 3168 - retval = ms_set_rw_reg_addr(chip, OVERWRITE_FLAG, MS_EXTRA_SIZE, 3169 - SYSTEM_PARAM, (6 + MS_EXTRA_SIZE)); 3170 - if (retval != STATUS_SUCCESS) 3171 - return STATUS_FAIL; 3172 - 3173 - ms_set_err_code(chip, MS_NO_ERROR); 3174 - 3175 - if (CHK_MS4BIT(ms_card)) 3176 - data[0] = 0x88; 3177 - else 3178 - data[0] = 0x80; 3179 - 3180 - data[1] = 0; 3181 - data[2] = (u8)(new_blk >> 8); 3182 - data[3] = (u8)new_blk; 3183 - if ((end_page - start_page) == 1) 3184 - data[4] = 0x20; 3185 - else 3186 - data[4] = 0; 3187 - 3188 - data[5] = start_page; 3189 - data[6] = 0xF8; 3190 - data[7] = 0xFF; 3191 - data[8] = (u8)(log_blk >> 8); 3192 - data[9] = (u8)log_blk; 3193 - 3194 - for (i = 0x0A; i < 0x10; i++) 3195 - data[i] = 0xFF; 3196 - 3197 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3198 - retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3199 - NO_WAIT_INT, data, 16); 3200 - if (retval == STATUS_SUCCESS) 3201 - break; 3202 - } 3203 - if (i == MS_MAX_RETRY_COUNT) 3204 - return STATUS_FAIL; 3205 - 3206 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3207 - retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3208 - if (retval == STATUS_SUCCESS) 3209 - break; 3210 - } 3211 - if (i == MS_MAX_RETRY_COUNT) 3212 - return STATUS_FAIL; 3213 - 3214 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3215 - if (retval != STATUS_SUCCESS) 3216 - return STATUS_FAIL; 3217 - 3218 - ptr = buf; 3219 - for (page_addr = start_page; page_addr < end_page; page_addr++) { 3220 - ms_set_err_code(chip, MS_NO_ERROR); 3221 - 3222 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3223 - ms_set_err_code(chip, MS_NO_CARD); 3224 - return STATUS_FAIL; 3225 - } 3226 - 3227 - if (val & INT_REG_CMDNK) { 3228 - ms_set_err_code(chip, MS_CMD_NK); 3229 - return STATUS_FAIL; 3230 - } 3231 - if (val & INT_REG_ERR) { 3232 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3233 - return STATUS_FAIL; 3234 - } 3235 - if (!(val & INT_REG_BREQ)) { 3236 - ms_set_err_code(chip, MS_BREQ_ERROR); 3237 - return STATUS_FAIL; 3238 - } 3239 - 3240 - udelay(30); 3241 - 3242 - rtsx_init_cmd(chip); 3243 - 3244 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3245 - 0xFF, WRITE_PAGE_DATA); 3246 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3247 - 0xFF, WAIT_INT); 3248 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3249 - 0x01, RING_BUFFER); 3250 - 3251 - trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3252 - 3253 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3254 - MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3255 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3256 - MS_TRANSFER_END, MS_TRANSFER_END); 3257 - 3258 - rtsx_send_cmd_no_wait(chip); 3259 - 3260 - retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3261 - scsi_sg_count(chip->srb), 3262 - index, offset, 3263 - DMA_TO_DEVICE, 3264 - chip->ms_timeout); 3265 - if (retval < 0) { 3266 - ms_set_err_code(chip, MS_TO_ERROR); 3267 - rtsx_clear_ms_error(chip); 3268 - 3269 - if (retval == -ETIMEDOUT) 3270 - return STATUS_TIMEDOUT; 3271 - return STATUS_FAIL; 3272 - } 3273 - 3274 - retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3275 - if (retval != STATUS_SUCCESS) 3276 - return STATUS_FAIL; 3277 - 3278 - if ((end_page - start_page) == 1) { 3279 - if (!(val & INT_REG_CED)) { 3280 - ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3281 - return STATUS_FAIL; 3282 - } 3283 - } else { 3284 - if (page_addr == (end_page - 1)) { 3285 - if (!(val & INT_REG_CED)) { 3286 - retval = ms_send_cmd(chip, BLOCK_END, 3287 - WAIT_INT); 3288 - if (retval != STATUS_SUCCESS) 3289 - return STATUS_FAIL; 3290 - } 3291 - 3292 - retval = ms_read_bytes(chip, GET_INT, 1, 3293 - NO_WAIT_INT, &val, 1); 3294 - if (retval != STATUS_SUCCESS) 3295 - return STATUS_FAIL; 3296 - } 3297 - 3298 - if (page_addr == (end_page - 1) || 3299 - page_addr == ms_card->page_off) { 3300 - if (!(val & INT_REG_CED)) { 3301 - ms_set_err_code(chip, 3302 - MS_FLASH_WRITE_ERROR); 3303 - return STATUS_FAIL; 3304 - } 3305 - } 3306 - } 3307 - 3308 - if (scsi_sg_count(chip->srb) == 0) 3309 - ptr += 512; 3310 - } 3311 - 3312 - return STATUS_SUCCESS; 3313 - } 3314 - 3315 - static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3316 - u16 log_blk, u8 page_off) 3317 - { 3318 - struct ms_info *ms_card = &chip->ms_card; 3319 - int retval, seg_no; 3320 - 3321 - retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3322 - page_off, ms_card->page_off + 1); 3323 - if (retval != STATUS_SUCCESS) 3324 - return STATUS_FAIL; 3325 - 3326 - seg_no = old_blk >> 9; 3327 - 3328 - if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3329 - MS_CLR_BAD_BLOCK_FLG(ms_card); 3330 - ms_set_bad_block(chip, old_blk); 3331 - } else { 3332 - retval = ms_erase_block(chip, old_blk); 3333 - if (retval == STATUS_SUCCESS) 3334 - ms_set_unused_block(chip, old_blk); 3335 - } 3336 - 3337 - ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3338 - 3339 - return STATUS_SUCCESS; 3340 - } 3341 - 3342 - static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3343 - u16 log_blk, u8 start_page) 3344 - { 3345 - int retval; 3346 - 3347 - if (start_page) { 3348 - retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3349 - 0, start_page); 3350 - if (retval != STATUS_SUCCESS) 3351 - return STATUS_FAIL; 3352 - } 3353 - 3354 - return STATUS_SUCCESS; 3355 - } 3356 - 3357 - #ifdef MS_DELAY_WRITE 3358 - int ms_delay_write(struct rtsx_chip *chip) 3359 - { 3360 - struct ms_info *ms_card = &chip->ms_card; 3361 - struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3362 - int retval; 3363 - 3364 - if (delay_write->delay_write_flag) { 3365 - retval = ms_set_init_para(chip); 3366 - if (retval != STATUS_SUCCESS) 3367 - return STATUS_FAIL; 3368 - 3369 - delay_write->delay_write_flag = 0; 3370 - retval = ms_finish_write(chip, 3371 - delay_write->old_phyblock, 3372 - delay_write->new_phyblock, 3373 - delay_write->logblock, 3374 - delay_write->pageoff); 3375 - if (retval != STATUS_SUCCESS) 3376 - return STATUS_FAIL; 3377 - } 3378 - 3379 - return STATUS_SUCCESS; 3380 - } 3381 - #endif 3382 - 3383 - static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3384 - { 3385 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 3386 - set_sense_type(chip, SCSI_LUN(srb), 3387 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3388 - else 3389 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3390 - } 3391 - 3392 - static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3393 - u32 start_sector, u16 sector_cnt) 3394 - { 3395 - struct ms_info *ms_card = &chip->ms_card; 3396 - unsigned int lun = SCSI_LUN(srb); 3397 - int retval, seg_no; 3398 - unsigned int index = 0, offset = 0; 3399 - u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3400 - u8 start_page, end_page = 0, page_cnt; 3401 - u8 *ptr; 3402 - #ifdef MS_DELAY_WRITE 3403 - struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3404 - #endif 3405 - 3406 - ms_set_err_code(chip, MS_NO_ERROR); 3407 - 3408 - ms_card->cleanup_counter = 0; 3409 - 3410 - ptr = (u8 *)scsi_sglist(srb); 3411 - 3412 - retval = ms_switch_clock(chip); 3413 - if (retval != STATUS_SUCCESS) { 3414 - ms_rw_fail(srb, chip); 3415 - return STATUS_FAIL; 3416 - } 3417 - 3418 - log_blk = (u16)(start_sector >> ms_card->block_shift); 3419 - start_page = (u8)(start_sector & ms_card->page_off); 3420 - 3421 - for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3422 - if (log_blk < ms_start_idx[seg_no + 1]) 3423 - break; 3424 - } 3425 - 3426 - if (ms_card->segment[seg_no].build_flag == 0) { 3427 - retval = ms_build_l2p_tbl(chip, seg_no); 3428 - if (retval != STATUS_SUCCESS) { 3429 - chip->card_fail |= MS_CARD; 3430 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3431 - return STATUS_FAIL; 3432 - } 3433 - } 3434 - 3435 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 3436 - #ifdef MS_DELAY_WRITE 3437 - if (delay_write->delay_write_flag && 3438 - delay_write->logblock == log_blk && 3439 - start_page > delay_write->pageoff) { 3440 - delay_write->delay_write_flag = 0; 3441 - retval = ms_copy_page(chip, 3442 - delay_write->old_phyblock, 3443 - delay_write->new_phyblock, 3444 - log_blk, 3445 - delay_write->pageoff, start_page); 3446 - if (retval != STATUS_SUCCESS) { 3447 - set_sense_type(chip, lun, 3448 - SENSE_TYPE_MEDIA_WRITE_ERR); 3449 - return STATUS_FAIL; 3450 - } 3451 - old_blk = delay_write->old_phyblock; 3452 - new_blk = delay_write->new_phyblock; 3453 - } else if (delay_write->delay_write_flag && 3454 - (delay_write->logblock == log_blk) && 3455 - (start_page == delay_write->pageoff)) { 3456 - delay_write->delay_write_flag = 0; 3457 - old_blk = delay_write->old_phyblock; 3458 - new_blk = delay_write->new_phyblock; 3459 - } else { 3460 - retval = ms_delay_write(chip); 3461 - if (retval != STATUS_SUCCESS) { 3462 - set_sense_type(chip, lun, 3463 - SENSE_TYPE_MEDIA_WRITE_ERR); 3464 - return STATUS_FAIL; 3465 - } 3466 - #endif 3467 - old_blk = ms_get_l2p_tbl 3468 - (chip, seg_no, 3469 - log_blk - ms_start_idx[seg_no]); 3470 - new_blk = ms_get_unused_block(chip, seg_no); 3471 - if (old_blk == 0xFFFF || new_blk == 0xFFFF) { 3472 - set_sense_type(chip, lun, 3473 - SENSE_TYPE_MEDIA_WRITE_ERR); 3474 - return STATUS_FAIL; 3475 - } 3476 - 3477 - retval = ms_prepare_write(chip, old_blk, new_blk, 3478 - log_blk, start_page); 3479 - if (retval != STATUS_SUCCESS) { 3480 - if (detect_card_cd(chip, MS_CARD) != 3481 - STATUS_SUCCESS) { 3482 - set_sense_type 3483 - (chip, lun, 3484 - SENSE_TYPE_MEDIA_NOT_PRESENT); 3485 - return STATUS_FAIL; 3486 - } 3487 - set_sense_type(chip, lun, 3488 - SENSE_TYPE_MEDIA_WRITE_ERR); 3489 - return STATUS_FAIL; 3490 - } 3491 - #ifdef MS_DELAY_WRITE 3492 - } 3493 - #endif 3494 - } else { 3495 - #ifdef MS_DELAY_WRITE 3496 - retval = ms_delay_write(chip); 3497 - if (retval != STATUS_SUCCESS) { 3498 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3499 - set_sense_type(chip, lun, 3500 - SENSE_TYPE_MEDIA_NOT_PRESENT); 3501 - return STATUS_FAIL; 3502 - } 3503 - set_sense_type(chip, lun, 3504 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3505 - return STATUS_FAIL; 3506 - } 3507 - #endif 3508 - old_blk = ms_get_l2p_tbl(chip, seg_no, 3509 - log_blk - ms_start_idx[seg_no]); 3510 - if (old_blk == 0xFFFF) { 3511 - set_sense_type(chip, lun, 3512 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3513 - return STATUS_FAIL; 3514 - } 3515 - } 3516 - 3517 - dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3518 - seg_no, old_blk, new_blk); 3519 - 3520 - while (total_sec_cnt) { 3521 - if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3522 - end_page = ms_card->page_off + 1; 3523 - else 3524 - end_page = start_page + (u8)total_sec_cnt; 3525 - 3526 - page_cnt = end_page - start_page; 3527 - 3528 - dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3529 - start_page, end_page, page_cnt); 3530 - 3531 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3532 - retval = ms_read_multiple_pages(chip, 3533 - old_blk, log_blk, 3534 - start_page, end_page, 3535 - ptr, &index, &offset); 3536 - } else { 3537 - retval = ms_write_multiple_pages(chip, old_blk, new_blk, 3538 - log_blk, start_page, 3539 - end_page, ptr, &index, 3540 - &offset); 3541 - } 3542 - 3543 - if (retval != STATUS_SUCCESS) { 3544 - toggle_gpio(chip, 1); 3545 - if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3546 - set_sense_type(chip, lun, 3547 - SENSE_TYPE_MEDIA_NOT_PRESENT); 3548 - return STATUS_FAIL; 3549 - } 3550 - ms_rw_fail(srb, chip); 3551 - return STATUS_FAIL; 3552 - } 3553 - 3554 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 3555 - if (end_page == (ms_card->page_off + 1)) { 3556 - retval = ms_erase_block(chip, old_blk); 3557 - if (retval == STATUS_SUCCESS) 3558 - ms_set_unused_block(chip, old_blk); 3559 - 3560 - ms_set_l2p_tbl(chip, seg_no, 3561 - log_blk - ms_start_idx[seg_no], 3562 - new_blk); 3563 - } 3564 - } 3565 - 3566 - total_sec_cnt -= page_cnt; 3567 - if (scsi_sg_count(srb) == 0) 3568 - ptr += page_cnt * 512; 3569 - 3570 - if (total_sec_cnt == 0) 3571 - break; 3572 - 3573 - log_blk++; 3574 - 3575 - for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 3576 - seg_no++) { 3577 - if (log_blk < ms_start_idx[seg_no + 1]) 3578 - break; 3579 - } 3580 - 3581 - if (ms_card->segment[seg_no].build_flag == 0) { 3582 - retval = ms_build_l2p_tbl(chip, seg_no); 3583 - if (retval != STATUS_SUCCESS) { 3584 - chip->card_fail |= MS_CARD; 3585 - set_sense_type(chip, lun, 3586 - SENSE_TYPE_MEDIA_NOT_PRESENT); 3587 - return STATUS_FAIL; 3588 - } 3589 - } 3590 - 3591 - old_blk = ms_get_l2p_tbl(chip, seg_no, 3592 - log_blk - ms_start_idx[seg_no]); 3593 - if (old_blk == 0xFFFF) { 3594 - ms_rw_fail(srb, chip); 3595 - return STATUS_FAIL; 3596 - } 3597 - 3598 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 3599 - new_blk = ms_get_unused_block(chip, seg_no); 3600 - if (new_blk == 0xFFFF) { 3601 - ms_rw_fail(srb, chip); 3602 - return STATUS_FAIL; 3603 - } 3604 - } 3605 - 3606 - dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3607 - seg_no, old_blk, new_blk); 3608 - 3609 - start_page = 0; 3610 - } 3611 - 3612 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 3613 - if (end_page < (ms_card->page_off + 1)) { 3614 - #ifdef MS_DELAY_WRITE 3615 - delay_write->delay_write_flag = 1; 3616 - delay_write->old_phyblock = old_blk; 3617 - delay_write->new_phyblock = new_blk; 3618 - delay_write->logblock = log_blk; 3619 - delay_write->pageoff = end_page; 3620 - #else 3621 - retval = ms_finish_write(chip, old_blk, new_blk, 3622 - log_blk, end_page); 3623 - if (retval != STATUS_SUCCESS) { 3624 - if (detect_card_cd(chip, MS_CARD) != 3625 - STATUS_SUCCESS) { 3626 - set_sense_type 3627 - (chip, lun, 3628 - SENSE_TYPE_MEDIA_NOT_PRESENT); 3629 - return STATUS_FAIL; 3630 - } 3631 - 3632 - ms_rw_fail(srb, chip); 3633 - return STATUS_FAIL; 3634 - } 3635 - #endif 3636 - } 3637 - } 3638 - 3639 - scsi_set_resid(srb, 0); 3640 - 3641 - return STATUS_SUCCESS; 3642 - } 3643 - 3644 - int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3645 - u32 start_sector, u16 sector_cnt) 3646 - { 3647 - struct ms_info *ms_card = &chip->ms_card; 3648 - int retval; 3649 - 3650 - if (CHK_MSPRO(ms_card)) 3651 - retval = mspro_rw_multi_sector(srb, chip, start_sector, 3652 - sector_cnt); 3653 - else 3654 - retval = ms_rw_multi_sector(srb, chip, start_sector, 3655 - sector_cnt); 3656 - 3657 - return retval; 3658 - } 3659 - 3660 - void ms_free_l2p_tbl(struct rtsx_chip *chip) 3661 - { 3662 - struct ms_info *ms_card = &chip->ms_card; 3663 - int i = 0; 3664 - 3665 - if (ms_card->segment) { 3666 - for (i = 0; i < ms_card->segment_cnt; i++) { 3667 - vfree(ms_card->segment[i].l2p_table); 3668 - ms_card->segment[i].l2p_table = NULL; 3669 - vfree(ms_card->segment[i].free_table); 3670 - ms_card->segment[i].free_table = NULL; 3671 - } 3672 - vfree(ms_card->segment); 3673 - ms_card->segment = NULL; 3674 - } 3675 - } 3676 - 3677 - #ifdef SUPPORT_MAGIC_GATE 3678 - 3679 - #ifdef READ_BYTES_WAIT_INT 3680 - static int ms_poll_int(struct rtsx_chip *chip) 3681 - { 3682 - int retval; 3683 - u8 val; 3684 - 3685 - rtsx_init_cmd(chip); 3686 - 3687 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 3688 - 3689 - retval = rtsx_send_cmd(chip, MS_CARD, 5000); 3690 - if (retval != STATUS_SUCCESS) 3691 - return STATUS_FAIL; 3692 - 3693 - val = *rtsx_get_cmd_data(chip); 3694 - if (val & MS_INT_ERR) 3695 - return STATUS_FAIL; 3696 - 3697 - return STATUS_SUCCESS; 3698 - } 3699 - #endif 3700 - 3701 - #ifdef MS_SAMPLE_INT_ERR 3702 - static int check_ms_err(struct rtsx_chip *chip) 3703 - { 3704 - int retval; 3705 - u8 val; 3706 - 3707 - retval = rtsx_read_register(chip, MS_TRANSFER, &val); 3708 - if (retval != STATUS_SUCCESS) 3709 - return 1; 3710 - if (val & MS_TRANSFER_ERR) 3711 - return 1; 3712 - 3713 - retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3714 - if (retval != STATUS_SUCCESS) 3715 - return 1; 3716 - 3717 - if (val & (MS_INT_ERR | MS_INT_CMDNK)) 3718 - return 1; 3719 - 3720 - return 0; 3721 - } 3722 - #else 3723 - static int check_ms_err(struct rtsx_chip *chip) 3724 - { 3725 - int retval; 3726 - u8 val; 3727 - 3728 - retval = rtsx_read_register(chip, MS_TRANSFER, &val); 3729 - if (retval != STATUS_SUCCESS) 3730 - return 1; 3731 - if (val & MS_TRANSFER_ERR) 3732 - return 1; 3733 - 3734 - return 0; 3735 - } 3736 - #endif 3737 - 3738 - static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 3739 - { 3740 - int retval, i; 3741 - u8 data[8]; 3742 - 3743 - data[0] = cmd; 3744 - data[1] = 0; 3745 - data[2] = 0; 3746 - data[3] = 0; 3747 - data[4] = 0; 3748 - data[5] = 0; 3749 - data[6] = entry_num; 3750 - data[7] = 0; 3751 - 3752 - for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3753 - retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 3754 - data, 8); 3755 - if (retval == STATUS_SUCCESS) 3756 - break; 3757 - } 3758 - if (i == MS_MAX_RETRY_COUNT) 3759 - return STATUS_FAIL; 3760 - 3761 - if (check_ms_err(chip)) { 3762 - rtsx_clear_ms_error(chip); 3763 - return STATUS_FAIL; 3764 - } 3765 - 3766 - return STATUS_SUCCESS; 3767 - } 3768 - 3769 - static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 3770 - u8 mg_entry_num) 3771 - { 3772 - int retval; 3773 - u8 buf[6]; 3774 - 3775 - if (type == 0) 3776 - retval = ms_set_rw_reg_addr(chip, 0, 0, PRO_TPC_PARM, 1); 3777 - else 3778 - retval = ms_set_rw_reg_addr(chip, 0, 0, PRO_DATA_COUNT1, 6); 3779 - 3780 - if (retval != STATUS_SUCCESS) 3781 - return STATUS_FAIL; 3782 - 3783 - buf[0] = 0; 3784 - buf[1] = 0; 3785 - if (type == 1) { 3786 - buf[2] = 0; 3787 - buf[3] = 0; 3788 - buf[4] = 0; 3789 - buf[5] = mg_entry_num; 3790 - } 3791 - retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 3792 - NO_WAIT_INT, buf, 6); 3793 - if (retval != STATUS_SUCCESS) 3794 - return STATUS_FAIL; 3795 - 3796 - return STATUS_SUCCESS; 3797 - } 3798 - 3799 - int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3800 - { 3801 - int retval; 3802 - int i; 3803 - unsigned int lun = SCSI_LUN(srb); 3804 - u8 buf1[32], buf2[12]; 3805 - 3806 - if (scsi_bufflen(srb) < 12) { 3807 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3808 - return STATUS_FAIL; 3809 - } 3810 - 3811 - ms_cleanup_work(chip); 3812 - 3813 - retval = ms_switch_clock(chip); 3814 - if (retval != STATUS_SUCCESS) 3815 - return STATUS_FAIL; 3816 - 3817 - retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 3818 - if (retval != STATUS_SUCCESS) { 3819 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3820 - return STATUS_FAIL; 3821 - } 3822 - 3823 - memset(buf1, 0, 32); 3824 - rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 3825 - for (i = 0; i < 8; i++) 3826 - buf1[8 + i] = buf2[4 + i]; 3827 - 3828 - retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 3829 - buf1, 32); 3830 - if (retval != STATUS_SUCCESS) { 3831 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3832 - return STATUS_FAIL; 3833 - } 3834 - if (check_ms_err(chip)) { 3835 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3836 - rtsx_clear_ms_error(chip); 3837 - return STATUS_FAIL; 3838 - } 3839 - 3840 - return STATUS_SUCCESS; 3841 - } 3842 - 3843 - int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3844 - { 3845 - int retval; 3846 - int bufflen; 3847 - unsigned int lun = SCSI_LUN(srb); 3848 - u8 *buf = NULL; 3849 - 3850 - ms_cleanup_work(chip); 3851 - 3852 - retval = ms_switch_clock(chip); 3853 - if (retval != STATUS_SUCCESS) 3854 - return STATUS_FAIL; 3855 - 3856 - buf = kmalloc(1540, GFP_KERNEL); 3857 - if (!buf) 3858 - return STATUS_ERROR; 3859 - 3860 - buf[0] = 0x04; 3861 - buf[1] = 0x1A; 3862 - buf[2] = 0x00; 3863 - buf[3] = 0x00; 3864 - 3865 - retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 3866 - if (retval != STATUS_SUCCESS) { 3867 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3868 - goto free_buffer; 3869 - } 3870 - 3871 - retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 3872 - 3, WAIT_INT, 0, 0, buf + 4, 1536); 3873 - if (retval != STATUS_SUCCESS) { 3874 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3875 - rtsx_clear_ms_error(chip); 3876 - goto free_buffer; 3877 - } 3878 - if (check_ms_err(chip)) { 3879 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3880 - rtsx_clear_ms_error(chip); 3881 - retval = STATUS_FAIL; 3882 - goto free_buffer; 3883 - } 3884 - 3885 - bufflen = min_t(int, 1052, scsi_bufflen(srb)); 3886 - rtsx_stor_set_xfer_buf(buf, bufflen, srb); 3887 - 3888 - free_buffer: 3889 - kfree(buf); 3890 - return retval; 3891 - } 3892 - 3893 - int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3894 - { 3895 - struct ms_info *ms_card = &chip->ms_card; 3896 - int retval; 3897 - int bufflen; 3898 - int i; 3899 - unsigned int lun = SCSI_LUN(srb); 3900 - u8 buf[32]; 3901 - 3902 - ms_cleanup_work(chip); 3903 - 3904 - retval = ms_switch_clock(chip); 3905 - if (retval != STATUS_SUCCESS) 3906 - return STATUS_FAIL; 3907 - 3908 - retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 3909 - if (retval != STATUS_SUCCESS) { 3910 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3911 - return STATUS_FAIL; 3912 - } 3913 - 3914 - retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 3915 - buf, 32); 3916 - if (retval != STATUS_SUCCESS) { 3917 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3918 - return STATUS_FAIL; 3919 - } 3920 - if (check_ms_err(chip)) { 3921 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3922 - rtsx_clear_ms_error(chip); 3923 - return STATUS_FAIL; 3924 - } 3925 - 3926 - memcpy(ms_card->magic_gate_id, buf, 16); 3927 - 3928 - #ifdef READ_BYTES_WAIT_INT 3929 - retval = ms_poll_int(chip); 3930 - if (retval != STATUS_SUCCESS) { 3931 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3932 - return STATUS_FAIL; 3933 - } 3934 - #endif 3935 - 3936 - retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 3937 - if (retval != STATUS_SUCCESS) { 3938 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3939 - return STATUS_FAIL; 3940 - } 3941 - 3942 - bufflen = min_t(int, 12, scsi_bufflen(srb)); 3943 - rtsx_stor_get_xfer_buf(buf, bufflen, srb); 3944 - 3945 - for (i = 0; i < 8; i++) 3946 - buf[i] = buf[4 + i]; 3947 - 3948 - for (i = 0; i < 24; i++) 3949 - buf[8 + i] = 0; 3950 - 3951 - retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 3952 - 32, WAIT_INT, buf, 32); 3953 - if (retval != STATUS_SUCCESS) { 3954 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3955 - return STATUS_FAIL; 3956 - } 3957 - if (check_ms_err(chip)) { 3958 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3959 - rtsx_clear_ms_error(chip); 3960 - return STATUS_FAIL; 3961 - } 3962 - 3963 - ms_card->mg_auth = 0; 3964 - 3965 - return STATUS_SUCCESS; 3966 - } 3967 - 3968 - int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3969 - { 3970 - struct ms_info *ms_card = &chip->ms_card; 3971 - int retval; 3972 - int bufflen; 3973 - unsigned int lun = SCSI_LUN(srb); 3974 - u8 buf1[32], buf2[36]; 3975 - 3976 - ms_cleanup_work(chip); 3977 - 3978 - retval = ms_switch_clock(chip); 3979 - if (retval != STATUS_SUCCESS) 3980 - return STATUS_FAIL; 3981 - 3982 - retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 3983 - if (retval != STATUS_SUCCESS) { 3984 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3985 - return STATUS_FAIL; 3986 - } 3987 - 3988 - retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 3989 - buf1, 32); 3990 - if (retval != STATUS_SUCCESS) { 3991 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3992 - return STATUS_FAIL; 3993 - } 3994 - if (check_ms_err(chip)) { 3995 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3996 - rtsx_clear_ms_error(chip); 3997 - return STATUS_FAIL; 3998 - } 3999 - 4000 - buf2[0] = 0x00; 4001 - buf2[1] = 0x22; 4002 - buf2[2] = 0x00; 4003 - buf2[3] = 0x00; 4004 - 4005 - memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4006 - memcpy(buf2 + 20, buf1, 16); 4007 - 4008 - bufflen = min_t(int, 36, scsi_bufflen(srb)); 4009 - rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4010 - 4011 - #ifdef READ_BYTES_WAIT_INT 4012 - retval = ms_poll_int(chip); 4013 - if (retval != STATUS_SUCCESS) { 4014 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4015 - return STATUS_FAIL; 4016 - } 4017 - #endif 4018 - 4019 - return STATUS_SUCCESS; 4020 - } 4021 - 4022 - int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4023 - { 4024 - struct ms_info *ms_card = &chip->ms_card; 4025 - int retval; 4026 - int i; 4027 - int bufflen; 4028 - unsigned int lun = SCSI_LUN(srb); 4029 - u8 buf[32]; 4030 - 4031 - ms_cleanup_work(chip); 4032 - 4033 - retval = ms_switch_clock(chip); 4034 - if (retval != STATUS_SUCCESS) 4035 - return STATUS_FAIL; 4036 - 4037 - retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4038 - if (retval != STATUS_SUCCESS) { 4039 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4040 - return STATUS_FAIL; 4041 - } 4042 - 4043 - bufflen = min_t(int, 12, scsi_bufflen(srb)); 4044 - rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4045 - 4046 - for (i = 0; i < 8; i++) 4047 - buf[i] = buf[4 + i]; 4048 - 4049 - for (i = 0; i < 24; i++) 4050 - buf[8 + i] = 0; 4051 - 4052 - retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4053 - buf, 32); 4054 - if (retval != STATUS_SUCCESS) { 4055 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4056 - return STATUS_FAIL; 4057 - } 4058 - if (check_ms_err(chip)) { 4059 - set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4060 - rtsx_clear_ms_error(chip); 4061 - return STATUS_FAIL; 4062 - } 4063 - 4064 - ms_card->mg_auth = 1; 4065 - 4066 - return STATUS_SUCCESS; 4067 - } 4068 - 4069 - int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4070 - { 4071 - struct ms_info *ms_card = &chip->ms_card; 4072 - int retval; 4073 - int bufflen; 4074 - unsigned int lun = SCSI_LUN(srb); 4075 - u8 *buf = NULL; 4076 - 4077 - ms_cleanup_work(chip); 4078 - 4079 - retval = ms_switch_clock(chip); 4080 - if (retval != STATUS_SUCCESS) 4081 - return STATUS_FAIL; 4082 - 4083 - buf = kmalloc(1028, GFP_KERNEL); 4084 - if (!buf) 4085 - return STATUS_ERROR; 4086 - 4087 - buf[0] = 0x04; 4088 - buf[1] = 0x02; 4089 - buf[2] = 0x00; 4090 - buf[3] = 0x00; 4091 - 4092 - retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4093 - if (retval != STATUS_SUCCESS) { 4094 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4095 - goto free_buffer; 4096 - } 4097 - 4098 - retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4099 - 2, WAIT_INT, 0, 0, buf + 4, 1024); 4100 - if (retval != STATUS_SUCCESS) { 4101 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4102 - rtsx_clear_ms_error(chip); 4103 - goto free_buffer; 4104 - } 4105 - if (check_ms_err(chip)) { 4106 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4107 - rtsx_clear_ms_error(chip); 4108 - retval = STATUS_FAIL; 4109 - goto free_buffer; 4110 - } 4111 - 4112 - bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4113 - rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4114 - 4115 - free_buffer: 4116 - kfree(buf); 4117 - return retval; 4118 - } 4119 - 4120 - int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4121 - { 4122 - struct ms_info *ms_card = &chip->ms_card; 4123 - int retval; 4124 - int bufflen; 4125 - #ifdef MG_SET_ICV_SLOW 4126 - int i; 4127 - #endif 4128 - unsigned int lun = SCSI_LUN(srb); 4129 - u8 *buf = NULL; 4130 - 4131 - ms_cleanup_work(chip); 4132 - 4133 - retval = ms_switch_clock(chip); 4134 - if (retval != STATUS_SUCCESS) 4135 - return STATUS_FAIL; 4136 - 4137 - buf = kmalloc(1028, GFP_KERNEL); 4138 - if (!buf) 4139 - return STATUS_ERROR; 4140 - 4141 - bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4142 - rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4143 - 4144 - retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4145 - if (retval != STATUS_SUCCESS) { 4146 - if (ms_card->mg_auth == 0) { 4147 - if ((buf[5] & 0xC0) != 0) 4148 - set_sense_type 4149 - (chip, lun, 4150 - SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4151 - else 4152 - set_sense_type(chip, lun, 4153 - SENSE_TYPE_MG_WRITE_ERR); 4154 - } else { 4155 - set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4156 - } 4157 - goto set_ICV_finish; 4158 - } 4159 - 4160 - #ifdef MG_SET_ICV_SLOW 4161 - for (i = 0; i < 2; i++) { 4162 - udelay(50); 4163 - 4164 - rtsx_init_cmd(chip); 4165 - 4166 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4167 - 0xFF, PRO_WRITE_LONG_DATA); 4168 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4169 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4170 - 0x01, RING_BUFFER); 4171 - 4172 - trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4173 - 4174 - rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4175 - MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4176 - rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4177 - MS_TRANSFER_END, MS_TRANSFER_END); 4178 - 4179 - rtsx_send_cmd_no_wait(chip); 4180 - 4181 - retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512, 4182 - 512, 0, DMA_TO_DEVICE, 3000); 4183 - if (retval < 0 || check_ms_err(chip)) { 4184 - rtsx_clear_ms_error(chip); 4185 - if (ms_card->mg_auth == 0) { 4186 - if ((buf[5] & 0xC0) != 0) 4187 - set_sense_type 4188 - (chip, lun, 4189 - SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4190 - else 4191 - set_sense_type(chip, lun, 4192 - SENSE_TYPE_MG_WRITE_ERR); 4193 - } else { 4194 - set_sense_type(chip, lun, 4195 - SENSE_TYPE_MG_WRITE_ERR); 4196 - } 4197 - retval = STATUS_FAIL; 4198 - goto set_ICV_finish; 4199 - } 4200 - } 4201 - #else 4202 - retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4203 - 2, WAIT_INT, 0, 0, buf + 4, 1024); 4204 - if (retval != STATUS_SUCCESS || check_ms_err(chip)) { 4205 - rtsx_clear_ms_error(chip); 4206 - if (ms_card->mg_auth == 0) { 4207 - if ((buf[5] & 0xC0) != 0) 4208 - set_sense_type 4209 - (chip, lun, 4210 - SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4211 - else 4212 - set_sense_type(chip, lun, 4213 - SENSE_TYPE_MG_WRITE_ERR); 4214 - } else { 4215 - set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4216 - } 4217 - goto set_ICV_finish; 4218 - } 4219 - #endif 4220 - 4221 - set_ICV_finish: 4222 - kfree(buf); 4223 - return retval; 4224 - } 4225 - 4226 - #endif /* SUPPORT_MAGIC_GATE */ 4227 - 4228 - void ms_cleanup_work(struct rtsx_chip *chip) 4229 - { 4230 - struct ms_info *ms_card = &chip->ms_card; 4231 - 4232 - if (CHK_MSPRO(ms_card)) { 4233 - if (ms_card->seq_mode) { 4234 - dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4235 - mspro_stop_seq_mode(chip); 4236 - ms_card->cleanup_counter = 0; 4237 - } 4238 - if (CHK_MSHG(ms_card)) { 4239 - rtsx_write_register(chip, MS_CFG, 4240 - MS_2K_SECTOR_MODE, 0x00); 4241 - } 4242 - } 4243 - #ifdef MS_DELAY_WRITE 4244 - else if ((!CHK_MSPRO(ms_card)) && 4245 - ms_card->delay_write.delay_write_flag) { 4246 - dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4247 - ms_delay_write(chip); 4248 - ms_card->cleanup_counter = 0; 4249 - } 4250 - #endif 4251 - } 4252 - 4253 - int ms_power_off_card3v3(struct rtsx_chip *chip) 4254 - { 4255 - int retval; 4256 - 4257 - retval = disable_card_clock(chip, MS_CARD); 4258 - if (retval != STATUS_SUCCESS) 4259 - return STATUS_FAIL; 4260 - 4261 - if (chip->asic_code) { 4262 - retval = ms_pull_ctl_disable(chip); 4263 - if (retval != STATUS_SUCCESS) 4264 - return STATUS_FAIL; 4265 - } else { 4266 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4267 - FPGA_MS_PULL_CTL_BIT | 0x20, 4268 - FPGA_MS_PULL_CTL_BIT); 4269 - if (retval) 4270 - return retval; 4271 - } 4272 - retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4273 - if (retval) 4274 - return retval; 4275 - 4276 - if (!chip->ft2_fast_mode) { 4277 - retval = card_power_off(chip, MS_CARD); 4278 - if (retval != STATUS_SUCCESS) 4279 - return STATUS_FAIL; 4280 - } 4281 - 4282 - return STATUS_SUCCESS; 4283 - } 4284 - 4285 - int release_ms_card(struct rtsx_chip *chip) 4286 - { 4287 - struct ms_info *ms_card = &chip->ms_card; 4288 - int retval; 4289 - 4290 - #ifdef MS_DELAY_WRITE 4291 - ms_card->delay_write.delay_write_flag = 0; 4292 - #endif 4293 - ms_card->pro_under_formatting = 0; 4294 - 4295 - chip->card_ready &= ~MS_CARD; 4296 - chip->card_fail &= ~MS_CARD; 4297 - chip->card_wp &= ~MS_CARD; 4298 - 4299 - ms_free_l2p_tbl(chip); 4300 - 4301 - memset(ms_card->raw_sys_info, 0, 96); 4302 - #ifdef SUPPORT_PCGL_1P18 4303 - memset(ms_card->raw_model_name, 0, 48); 4304 - #endif 4305 - 4306 - retval = ms_power_off_card3v3(chip); 4307 - if (retval != STATUS_SUCCESS) 4308 - return STATUS_FAIL; 4309 - 4310 - return STATUS_SUCCESS; 4311 - }
-214
drivers/staging/rts5208/ms.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_MS_H 13 - #define __REALTEK_RTSX_MS_H 14 - 15 - #define MS_DELAY_WRITE 16 - 17 - #define MS_MAX_RETRY_COUNT 3 18 - 19 - #define MS_EXTRA_SIZE 0x9 20 - 21 - #define WRT_PRTCT 0x01 22 - 23 - /* Error Code */ 24 - #define MS_NO_ERROR 0x00 25 - #define MS_CRC16_ERROR 0x80 26 - #define MS_TO_ERROR 0x40 27 - #define MS_NO_CARD 0x20 28 - #define MS_NO_MEMORY 0x10 29 - #define MS_CMD_NK 0x08 30 - #define MS_FLASH_READ_ERROR 0x04 31 - #define MS_FLASH_WRITE_ERROR 0x02 32 - #define MS_BREQ_ERROR 0x01 33 - #define MS_NOT_FOUND 0x03 34 - 35 - /* Transfer Protocol Command */ 36 - #define READ_PAGE_DATA 0x02 37 - #define READ_REG 0x04 38 - #define GET_INT 0x07 39 - #define WRITE_PAGE_DATA 0x0D 40 - #define WRITE_REG 0x0B 41 - #define SET_RW_REG_ADRS 0x08 42 - #define SET_CMD 0x0E 43 - 44 - #define PRO_READ_LONG_DATA 0x02 45 - #define PRO_READ_SHORT_DATA 0x03 46 - #define PRO_READ_REG 0x04 47 - #define PRO_READ_QUAD_DATA 0x05 48 - #define PRO_GET_INT 0x07 49 - #define PRO_WRITE_LONG_DATA 0x0D 50 - #define PRO_WRITE_SHORT_DATA 0x0C 51 - #define PRO_WRITE_QUAD_DATA 0x0A 52 - #define PRO_WRITE_REG 0x0B 53 - #define PRO_SET_RW_REG_ADRS 0x08 54 - #define PRO_SET_CMD 0x0E 55 - #define PRO_EX_SET_CMD 0x09 56 - 57 - #ifdef SUPPORT_MAGIC_GATE 58 - 59 - #define MG_GET_ID 0x40 60 - #define MG_SET_LID 0x41 61 - #define MG_GET_LEKB 0x42 62 - #define MG_SET_RD 0x43 63 - #define MG_MAKE_RMS 0x44 64 - #define MG_MAKE_KSE 0x45 65 - #define MG_SET_IBD 0x46 66 - #define MG_GET_IBD 0x47 67 - 68 - #endif 69 - 70 - #ifdef XC_POWERCLASS 71 - #define XC_CHG_POWER 0x16 72 - #endif 73 - 74 - #define BLOCK_READ 0xAA 75 - #define BLOCK_WRITE 0x55 76 - #define BLOCK_END 0x33 77 - #define BLOCK_ERASE 0x99 78 - #define FLASH_STOP 0xCC 79 - 80 - #define SLEEP 0x5A 81 - #define CLEAR_BUF 0xC3 82 - #define MS_RESET 0x3C 83 - 84 - #define PRO_READ_DATA 0x20 85 - #define PRO_WRITE_DATA 0x21 86 - #define PRO_READ_ATRB 0x24 87 - #define PRO_STOP 0x25 88 - #define PRO_ERASE 0x26 89 - #define PRO_READ_2K_DATA 0x27 90 - #define PRO_WRITE_2K_DATA 0x28 91 - 92 - #define PRO_FORMAT 0x10 93 - #define PRO_SLEEP 0x11 94 - 95 - #define INT_REG 0x01 96 - #define STATUS_REG0 0x02 97 - #define STATUS_REG1 0x03 98 - 99 - #define SYSTEM_PARAM 0x10 100 - #define BLOCK_ADRS 0x11 101 - #define CMD_PARM 0x14 102 - #define PAGE_ADRS 0x15 103 - 104 - #define OVERWRITE_FLAG 0x16 105 - #define MANAGEMEN_FLAG 0x17 106 - #define LOGICAL_ADRS 0x18 107 - #define RESERVE_AREA 0x1A 108 - 109 - #define PRO_INT_REG 0x01 110 - #define PRO_STATUS_REG 0x02 111 - #define PRO_TYPE_REG 0x04 112 - #define PRO_IF_mode_REG 0x05 113 - #define PRO_CATEGORY_REG 0x06 114 - #define PRO_CLASS_REG 0x07 115 - 116 - #define PRO_SYSTEM_PARAM 0x10 117 - #define PRO_DATA_COUNT1 0x11 118 - #define PRO_DATA_COUNT0 0x12 119 - #define PRO_DATA_ADDR3 0x13 120 - #define PRO_DATA_ADDR2 0x14 121 - #define PRO_DATA_ADDR1 0x15 122 - #define PRO_DATA_ADDR0 0x16 123 - 124 - #define PRO_TPC_PARM 0x17 125 - #define PRO_CMD_PARM 0x18 126 - 127 - #define INT_REG_CED 0x80 128 - #define INT_REG_ERR 0x40 129 - #define INT_REG_BREQ 0x20 130 - #define INT_REG_CMDNK 0x01 131 - 132 - #define BLOCK_BOOT 0xC0 133 - #define BLOCK_OK 0x80 134 - #define PAGE_OK 0x60 135 - #define DATA_COMPL 0x10 136 - 137 - #define NOT_BOOT_BLOCK 0x4 138 - #define NOT_TRANSLATION_TABLE 0x8 139 - 140 - #define HEADER_ID0 PPBUF_BASE2 141 - #define HEADER_ID1 (PPBUF_BASE2 + 1) 142 - #define DISABLED_BLOCK0 (PPBUF_BASE2 + 0x170 + 4) 143 - #define DISABLED_BLOCK1 (PPBUF_BASE2 + 0x170 + 5) 144 - #define DISABLED_BLOCK2 (PPBUF_BASE2 + 0x170 + 6) 145 - #define DISABLED_BLOCK3 (PPBUF_BASE2 + 0x170 + 7) 146 - #define BLOCK_SIZE_0 (PPBUF_BASE2 + 0x1a0 + 2) 147 - #define BLOCK_SIZE_1 (PPBUF_BASE2 + 0x1a0 + 3) 148 - #define BLOCK_COUNT_0 (PPBUF_BASE2 + 0x1a0 + 4) 149 - #define BLOCK_COUNT_1 (PPBUF_BASE2 + 0x1a0 + 5) 150 - #define EBLOCK_COUNT_0 (PPBUF_BASE2 + 0x1a0 + 6) 151 - #define EBLOCK_COUNT_1 (PPBUF_BASE2 + 0x1a0 + 7) 152 - #define PAGE_SIZE_0 (PPBUF_BASE2 + 0x1a0 + 8) 153 - #define PAGE_SIZE_1 (PPBUF_BASE2 + 0x1a0 + 9) 154 - 155 - #define MS_device_type (PPBUF_BASE2 + 0x1D8) 156 - 157 - #define MS_4bit_support (PPBUF_BASE2 + 0x1D3) 158 - 159 - #define set_PS_NG 1 160 - #define set_PS_error 0 161 - 162 - #define PARALLEL_8BIT_IF 0x40 163 - #define PARALLEL_4BIT_IF 0x00 164 - #define SERIAL_IF 0x80 165 - 166 - #define BUF_FULL 0x10 167 - #define BUF_EMPTY 0x20 168 - 169 - #define MEDIA_BUSY 0x80 170 - #define FLASH_BUSY 0x40 171 - #define DATA_ERROR 0x20 172 - #define STS_UCDT 0x10 173 - #define EXTRA_ERROR 0x08 174 - #define STS_UCEX 0x04 175 - #define FLAG_ERROR 0x02 176 - #define STS_UCFG 0x01 177 - 178 - #define MS_SHORT_DATA_LEN 32 179 - 180 - #define FORMAT_SUCCESS 0 181 - #define FORMAT_FAIL 1 182 - #define FORMAT_IN_PROGRESS 2 183 - 184 - #define MS_SET_BAD_BLOCK_FLG(ms_card) ((ms_card)->multi_flag |= 0x80) 185 - #define MS_CLR_BAD_BLOCK_FLG(ms_card) ((ms_card)->multi_flag &= 0x7F) 186 - #define MS_TST_BAD_BLOCK_FLG(ms_card) ((ms_card)->multi_flag & 0x80) 187 - 188 - void mspro_polling_format_status(struct rtsx_chip *chip); 189 - 190 - void mspro_stop_seq_mode(struct rtsx_chip *chip); 191 - int reset_ms_card(struct rtsx_chip *chip); 192 - int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 193 - u32 start_sector, u16 sector_cnt); 194 - int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 195 - int short_data_len, bool quick_format); 196 - void ms_free_l2p_tbl(struct rtsx_chip *chip); 197 - void ms_cleanup_work(struct rtsx_chip *chip); 198 - int ms_power_off_card3v3(struct rtsx_chip *chip); 199 - int release_ms_card(struct rtsx_chip *chip); 200 - #ifdef MS_DELAY_WRITE 201 - int ms_delay_write(struct rtsx_chip *chip); 202 - #endif 203 - 204 - #ifdef SUPPORT_MAGIC_GATE 205 - int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip); 206 - int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip); 207 - int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip); 208 - int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip); 209 - int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); 210 - int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip); 211 - int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip); 212 - #endif 213 - 214 - #endif /* __REALTEK_RTSX_MS_H */
-987
drivers/staging/rts5208/rtsx.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/workqueue.h> 16 - 17 - #include "rtsx.h" 18 - #include "ms.h" 19 - #include "sd.h" 20 - #include "xd.h" 21 - 22 - MODULE_DESCRIPTION("Realtek PCI-Express card reader rts5208/rts5288 driver"); 23 - MODULE_LICENSE("GPL"); 24 - 25 - static unsigned int delay_use = 1; 26 - module_param(delay_use, uint, 0644); 27 - MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device"); 28 - 29 - static int ss_en; 30 - module_param(ss_en, int, 0644); 31 - MODULE_PARM_DESC(ss_en, "enable selective suspend"); 32 - 33 - static int ss_interval = 50; 34 - module_param(ss_interval, int, 0644); 35 - MODULE_PARM_DESC(ss_interval, "Interval to enter ss state in seconds"); 36 - 37 - static int auto_delink_en; 38 - module_param(auto_delink_en, int, 0644); 39 - MODULE_PARM_DESC(auto_delink_en, "enable auto delink"); 40 - 41 - static unsigned char aspm_l0s_l1_en; 42 - module_param(aspm_l0s_l1_en, byte, 0644); 43 - MODULE_PARM_DESC(aspm_l0s_l1_en, "enable device aspm"); 44 - 45 - static int msi_en; 46 - module_param(msi_en, int, 0644); 47 - MODULE_PARM_DESC(msi_en, "enable msi"); 48 - 49 - static irqreturn_t rtsx_interrupt(int irq, void *dev_id); 50 - 51 - /*********************************************************************** 52 - * Host functions 53 - ***********************************************************************/ 54 - 55 - static const char *host_info(struct Scsi_Host *host) 56 - { 57 - return "SCSI emulation for PCI-Express Mass Storage devices"; 58 - } 59 - 60 - static int slave_alloc(struct scsi_device *sdev) 61 - { 62 - /* 63 - * Set the INQUIRY transfer length to 36. We don't use any of 64 - * the extra data and many devices choke if asked for more or 65 - * less than 36 bytes. 66 - */ 67 - sdev->inquiry_len = 36; 68 - return 0; 69 - } 70 - 71 - static int slave_configure(struct scsi_device *sdev) 72 - { 73 - /* Set the SCSI level to at least 2. We'll leave it at 3 if that's 74 - * what is originally reported. We need this to avoid confusing 75 - * the SCSI layer with devices that report 0 or 1, but need 10-byte 76 - * commands (ala ATAPI devices behind certain bridges, or devices 77 - * which simply have broken INQUIRY data). 78 - * 79 - * NOTE: This means /dev/sg programs (ala cdrecord) will get the 80 - * actual information. This seems to be the preference for 81 - * programs like that. 82 - * 83 - * NOTE: This also means that /proc/scsi/scsi and sysfs may report 84 - * the actual value or the modified one, depending on where the 85 - * data comes from. 86 - */ 87 - if (sdev->scsi_level < SCSI_2) { 88 - sdev->scsi_level = SCSI_2; 89 - sdev->sdev_target->scsi_level = SCSI_2; 90 - } 91 - 92 - return 0; 93 - } 94 - 95 - /*********************************************************************** 96 - * /proc/scsi/ functions 97 - ***********************************************************************/ 98 - 99 - /* we use this macro to help us write into the buffer */ 100 - #undef SPRINTF 101 - #define SPRINTF(args...) \ 102 - do { \ 103 - if (pos < buffer + length) \ 104 - pos += sprintf(pos, ## args); \ 105 - } while (0) 106 - 107 - /* queue a command */ 108 - /* This is always called with spin_lock_irq(host->host_lock) held */ 109 - static int queuecommand_lck(struct scsi_cmnd *srb) 110 - { 111 - void (*done)(struct scsi_cmnd *) = scsi_done; 112 - struct rtsx_dev *dev = host_to_rtsx(srb->device->host); 113 - struct rtsx_chip *chip = dev->chip; 114 - 115 - /* check for state-transition errors */ 116 - if (chip->srb) { 117 - dev_err(&dev->pci->dev, "Error: chip->srb = %p\n", 118 - chip->srb); 119 - return SCSI_MLQUEUE_HOST_BUSY; 120 - } 121 - 122 - /* fail the command if we are disconnecting */ 123 - if (rtsx_chk_stat(chip, RTSX_STAT_DISCONNECT)) { 124 - dev_info(&dev->pci->dev, "Fail command during disconnect\n"); 125 - srb->result = DID_NO_CONNECT << 16; 126 - done(srb); 127 - return 0; 128 - } 129 - 130 - /* enqueue the command and wake up the control thread */ 131 - chip->srb = srb; 132 - complete(&dev->cmnd_ready); 133 - 134 - return 0; 135 - } 136 - 137 - static DEF_SCSI_QCMD(queuecommand) 138 - 139 - /*********************************************************************** 140 - * Error handling functions 141 - ***********************************************************************/ 142 - 143 - /* Command timeout and abort */ 144 - static int command_abort(struct scsi_cmnd *srb) 145 - { 146 - struct Scsi_Host *host = srb->device->host; 147 - struct rtsx_dev *dev = host_to_rtsx(host); 148 - struct rtsx_chip *chip = dev->chip; 149 - 150 - spin_lock_irq(host->host_lock); 151 - 152 - /* Is this command still active? */ 153 - if (chip->srb != srb) { 154 - spin_unlock_irq(host->host_lock); 155 - dev_info(&dev->pci->dev, "-- nothing to abort\n"); 156 - return FAILED; 157 - } 158 - 159 - rtsx_set_stat(chip, RTSX_STAT_ABORT); 160 - 161 - spin_unlock_irq(host->host_lock); 162 - 163 - /* Wait for the aborted command to finish */ 164 - wait_for_completion(&dev->notify); 165 - 166 - return SUCCESS; 167 - } 168 - 169 - /* 170 - * This invokes the transport reset mechanism to reset the state of the 171 - * device 172 - */ 173 - static int device_reset(struct scsi_cmnd *srb) 174 - { 175 - return SUCCESS; 176 - } 177 - 178 - /* 179 - * this defines our host template, with which we'll allocate hosts 180 - */ 181 - 182 - static const struct scsi_host_template rtsx_host_template = { 183 - /* basic userland interface stuff */ 184 - .name = CR_DRIVER_NAME, 185 - .proc_name = CR_DRIVER_NAME, 186 - .info = host_info, 187 - 188 - /* command interface -- queued only */ 189 - .queuecommand = queuecommand, 190 - 191 - /* error and abort handlers */ 192 - .eh_abort_handler = command_abort, 193 - .eh_device_reset_handler = device_reset, 194 - 195 - /* queue commands only, only one command per LUN */ 196 - .can_queue = 1, 197 - 198 - /* unknown initiator id */ 199 - .this_id = -1, 200 - 201 - .slave_alloc = slave_alloc, 202 - .slave_configure = slave_configure, 203 - 204 - /* lots of sg segments can be handled */ 205 - .sg_tablesize = SG_ALL, 206 - 207 - /* limit the total size of a transfer to 120 KB */ 208 - .max_sectors = 240, 209 - 210 - /* 211 - * Scatter-gather buffers (all but the last) must have a length 212 - * divisible by the bulk maxpacket size. Otherwise a data packet 213 - * would end up being short, causing a premature end to the data 214 - * transfer. Since high-speed bulk pipes have a maxpacket size 215 - * of 512, we'll use that as the scsi device queue's DMA alignment 216 - * mask. Guaranteeing proper alignment of the first buffer will 217 - * have the desired effect because, except at the beginning and 218 - * the end, scatter-gather buffers follow page boundaries. 219 - */ 220 - .dma_alignment = 511, 221 - 222 - /* emulated HBA */ 223 - .emulated = 1, 224 - 225 - /* we do our own delay after a device or bus reset */ 226 - .skip_settle_delay = 1, 227 - 228 - /* module management */ 229 - .module = THIS_MODULE 230 - }; 231 - 232 - static int rtsx_acquire_irq(struct rtsx_dev *dev) 233 - { 234 - struct rtsx_chip *chip = dev->chip; 235 - 236 - dev_info(&dev->pci->dev, "%s: chip->msi_en = %d, pci->irq = %d\n", 237 - __func__, chip->msi_en, dev->pci->irq); 238 - 239 - if (request_irq(dev->pci->irq, rtsx_interrupt, 240 - chip->msi_en ? 0 : IRQF_SHARED, 241 - CR_DRIVER_NAME, dev)) { 242 - dev_err(&dev->pci->dev, 243 - "rtsx: unable to grab IRQ %d, disabling device\n", 244 - dev->pci->irq); 245 - return -1; 246 - } 247 - 248 - dev->irq = dev->pci->irq; 249 - pci_intx(dev->pci, !chip->msi_en); 250 - 251 - return 0; 252 - } 253 - 254 - /* 255 - * power management 256 - */ 257 - static int __maybe_unused rtsx_suspend(struct device *dev_d) 258 - { 259 - struct pci_dev *pci = to_pci_dev(dev_d); 260 - struct rtsx_dev *dev = pci_get_drvdata(pci); 261 - struct rtsx_chip *chip; 262 - 263 - if (!dev) 264 - return 0; 265 - 266 - /* lock the device pointers */ 267 - mutex_lock(&dev->dev_mutex); 268 - 269 - chip = dev->chip; 270 - 271 - rtsx_do_before_power_down(chip, PM_S3); 272 - 273 - if (dev->irq >= 0) { 274 - free_irq(dev->irq, (void *)dev); 275 - dev->irq = -1; 276 - } 277 - 278 - if (chip->msi_en) 279 - pci_free_irq_vectors(pci); 280 - 281 - device_wakeup_enable(dev_d); 282 - 283 - /* unlock the device pointers */ 284 - mutex_unlock(&dev->dev_mutex); 285 - 286 - return 0; 287 - } 288 - 289 - static int __maybe_unused rtsx_resume(struct device *dev_d) 290 - { 291 - struct pci_dev *pci = to_pci_dev(dev_d); 292 - struct rtsx_dev *dev = pci_get_drvdata(pci); 293 - struct rtsx_chip *chip; 294 - 295 - if (!dev) 296 - return 0; 297 - 298 - chip = dev->chip; 299 - 300 - /* lock the device pointers */ 301 - mutex_lock(&dev->dev_mutex); 302 - 303 - pci_set_master(pci); 304 - 305 - if (chip->msi_en) { 306 - if (pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) < 0) 307 - chip->msi_en = 0; 308 - } 309 - 310 - if (rtsx_acquire_irq(dev) < 0) { 311 - /* unlock the device pointers */ 312 - mutex_unlock(&dev->dev_mutex); 313 - return -EIO; 314 - } 315 - 316 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); 317 - rtsx_init_chip(chip); 318 - 319 - /* unlock the device pointers */ 320 - mutex_unlock(&dev->dev_mutex); 321 - 322 - return 0; 323 - } 324 - 325 - static void rtsx_shutdown(struct pci_dev *pci) 326 - { 327 - struct rtsx_dev *dev = pci_get_drvdata(pci); 328 - struct rtsx_chip *chip; 329 - 330 - if (!dev) 331 - return; 332 - 333 - chip = dev->chip; 334 - 335 - rtsx_do_before_power_down(chip, PM_S1); 336 - 337 - if (dev->irq >= 0) { 338 - free_irq(dev->irq, (void *)dev); 339 - dev->irq = -1; 340 - } 341 - 342 - if (chip->msi_en) 343 - pci_free_irq_vectors(pci); 344 - 345 - pci_disable_device(pci); 346 - } 347 - 348 - static int rtsx_control_thread(void *__dev) 349 - { 350 - struct rtsx_dev *dev = __dev; 351 - struct rtsx_chip *chip = dev->chip; 352 - struct Scsi_Host *host = rtsx_to_host(dev); 353 - 354 - for (;;) { 355 - if (wait_for_completion_interruptible(&dev->cmnd_ready)) 356 - break; 357 - 358 - /* lock the device pointers */ 359 - mutex_lock(&dev->dev_mutex); 360 - 361 - /* if the device has disconnected, we are free to exit */ 362 - if (rtsx_chk_stat(chip, RTSX_STAT_DISCONNECT)) { 363 - dev_info(&dev->pci->dev, "-- rtsx-control exiting\n"); 364 - mutex_unlock(&dev->dev_mutex); 365 - break; 366 - } 367 - 368 - /* lock access to the state */ 369 - spin_lock_irq(host->host_lock); 370 - 371 - /* has the command aborted ? */ 372 - if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) { 373 - chip->srb->result = DID_ABORT << 16; 374 - goto skip_for_abort; 375 - } 376 - 377 - spin_unlock_irq(host->host_lock); 378 - 379 - /* reject the command if the direction indicator 380 - * is UNKNOWN 381 - */ 382 - if (chip->srb->sc_data_direction == DMA_BIDIRECTIONAL) { 383 - dev_err(&dev->pci->dev, "UNKNOWN data direction\n"); 384 - chip->srb->result = DID_ERROR << 16; 385 - } else if (chip->srb->device->id) { 386 - /* reject if target != 0 or if LUN is higher than 387 - * the maximum known LUN 388 - */ 389 - dev_err(&dev->pci->dev, "Bad target number (%d:%d)\n", 390 - chip->srb->device->id, 391 - (u8)chip->srb->device->lun); 392 - chip->srb->result = DID_BAD_TARGET << 16; 393 - } else if (chip->srb->device->lun > chip->max_lun) { 394 - dev_err(&dev->pci->dev, "Bad LUN (%d:%d)\n", 395 - chip->srb->device->id, 396 - (u8)chip->srb->device->lun); 397 - chip->srb->result = DID_BAD_TARGET << 16; 398 - } else { 399 - /* we've got a command, let's do it! */ 400 - scsi_show_command(chip); 401 - rtsx_invoke_transport(chip->srb, chip); 402 - } 403 - 404 - /* lock access to the state */ 405 - spin_lock_irq(host->host_lock); 406 - 407 - /* did the command already complete because of a disconnect? */ 408 - if (!chip->srb) 409 - ; /* nothing to do */ 410 - 411 - /* indicate that the command is done */ 412 - else if (chip->srb->result != DID_ABORT << 16) { 413 - scsi_done(chip->srb); 414 - } else { 415 - skip_for_abort: 416 - dev_err(&dev->pci->dev, "scsi command aborted\n"); 417 - } 418 - 419 - if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) { 420 - complete(&dev->notify); 421 - 422 - rtsx_set_stat(chip, RTSX_STAT_IDLE); 423 - } 424 - 425 - /* finished working on this command */ 426 - chip->srb = NULL; 427 - spin_unlock_irq(host->host_lock); 428 - 429 - /* unlock the device pointers */ 430 - mutex_unlock(&dev->dev_mutex); 431 - } /* for (;;) */ 432 - 433 - /* notify the exit routine that we're actually exiting now 434 - * 435 - * complete()/wait_for_completion() is similar to up()/down(), 436 - * except that complete() is safe in the case where the structure 437 - * is getting deleted in a parallel mode of execution (i.e. just 438 - * after the down() -- that's necessary for the thread-shutdown 439 - * case. 440 - * 441 - * kthread_complete_and_exit() goes even further than this -- 442 - * it is safe in the case that the thread of the caller is going away 443 - * (not just the structure) -- this is necessary for the module-remove 444 - * case. This is important in preemption kernels, which transfer the 445 - * flow of execution immediately upon a complete(). 446 - */ 447 - kthread_complete_and_exit(&dev->control_exit, 0); 448 - } 449 - 450 - static int rtsx_polling_thread(void *__dev) 451 - { 452 - struct rtsx_dev *dev = __dev; 453 - struct rtsx_chip *chip = dev->chip; 454 - struct sd_info *sd_card = &chip->sd_card; 455 - struct xd_info *xd_card = &chip->xd_card; 456 - struct ms_info *ms_card = &chip->ms_card; 457 - 458 - sd_card->cleanup_counter = 0; 459 - xd_card->cleanup_counter = 0; 460 - ms_card->cleanup_counter = 0; 461 - 462 - /* Wait until SCSI scan finished */ 463 - wait_timeout((delay_use + 5) * 1000); 464 - 465 - for (;;) { 466 - set_current_state(TASK_INTERRUPTIBLE); 467 - schedule_timeout(msecs_to_jiffies(POLLING_INTERVAL)); 468 - 469 - /* lock the device pointers */ 470 - mutex_lock(&dev->dev_mutex); 471 - 472 - /* if the device has disconnected, we are free to exit */ 473 - if (rtsx_chk_stat(chip, RTSX_STAT_DISCONNECT)) { 474 - dev_info(&dev->pci->dev, "-- rtsx-polling exiting\n"); 475 - mutex_unlock(&dev->dev_mutex); 476 - break; 477 - } 478 - 479 - mutex_unlock(&dev->dev_mutex); 480 - 481 - mspro_polling_format_status(chip); 482 - 483 - /* lock the device pointers */ 484 - mutex_lock(&dev->dev_mutex); 485 - 486 - rtsx_polling_func(chip); 487 - 488 - /* unlock the device pointers */ 489 - mutex_unlock(&dev->dev_mutex); 490 - } 491 - 492 - kthread_complete_and_exit(&dev->polling_exit, 0); 493 - } 494 - 495 - /* 496 - * interrupt handler 497 - */ 498 - static irqreturn_t rtsx_interrupt(int irq, void *dev_id) 499 - { 500 - struct rtsx_dev *dev = dev_id; 501 - struct rtsx_chip *chip; 502 - int retval; 503 - u32 status; 504 - 505 - if (dev) 506 - chip = dev->chip; 507 - else 508 - return IRQ_NONE; 509 - 510 - if (!chip) 511 - return IRQ_NONE; 512 - 513 - spin_lock(&dev->reg_lock); 514 - 515 - retval = rtsx_pre_handle_interrupt(chip); 516 - if (retval == STATUS_FAIL) { 517 - spin_unlock(&dev->reg_lock); 518 - if (chip->int_reg == 0xFFFFFFFF) 519 - return IRQ_HANDLED; 520 - return IRQ_NONE; 521 - } 522 - 523 - status = chip->int_reg; 524 - 525 - if (dev->check_card_cd) { 526 - if (!(dev->check_card_cd & status)) { 527 - /* card not exist, return TRANS_RESULT_FAIL */ 528 - dev->trans_result = TRANS_RESULT_FAIL; 529 - if (dev->done) 530 - complete(dev->done); 531 - goto exit; 532 - } 533 - } 534 - 535 - if (status & (NEED_COMPLETE_INT | DELINK_INT)) { 536 - if (status & (TRANS_FAIL_INT | DELINK_INT)) { 537 - if (status & DELINK_INT) 538 - RTSX_SET_DELINK(chip); 539 - dev->trans_result = TRANS_RESULT_FAIL; 540 - if (dev->done) 541 - complete(dev->done); 542 - } else if (status & TRANS_OK_INT) { 543 - dev->trans_result = TRANS_RESULT_OK; 544 - if (dev->done) 545 - complete(dev->done); 546 - } else if (status & DATA_DONE_INT) { 547 - dev->trans_result = TRANS_NOT_READY; 548 - if (dev->done && dev->trans_state == STATE_TRANS_SG) 549 - complete(dev->done); 550 - } 551 - } 552 - 553 - exit: 554 - spin_unlock(&dev->reg_lock); 555 - return IRQ_HANDLED; 556 - } 557 - 558 - /* Release all our dynamic resources */ 559 - static void rtsx_release_resources(struct rtsx_dev *dev) 560 - { 561 - dev_info(&dev->pci->dev, "-- %s\n", __func__); 562 - 563 - /* Tell the control thread to exit. The SCSI host must 564 - * already have been removed so it won't try to queue 565 - * any more commands. 566 - */ 567 - dev_info(&dev->pci->dev, "-- sending exit command to thread\n"); 568 - complete(&dev->cmnd_ready); 569 - if (dev->ctl_thread) 570 - wait_for_completion(&dev->control_exit); 571 - if (dev->polling_thread) 572 - wait_for_completion(&dev->polling_exit); 573 - 574 - wait_timeout(200); 575 - 576 - if (dev->rtsx_resv_buf) { 577 - dev->chip->host_cmds_ptr = NULL; 578 - dev->chip->host_sg_tbl_ptr = NULL; 579 - } 580 - 581 - if (dev->irq > 0) 582 - free_irq(dev->irq, (void *)dev); 583 - if (dev->chip->msi_en) 584 - pci_free_irq_vectors(dev->pci); 585 - if (dev->remap_addr) 586 - iounmap(dev->remap_addr); 587 - 588 - rtsx_release_chip(dev->chip); 589 - kfree(dev->chip); 590 - } 591 - 592 - /* 593 - * First stage of disconnect processing: stop all commands and remove 594 - * the host 595 - */ 596 - static void quiesce_and_remove_host(struct rtsx_dev *dev) 597 - { 598 - struct Scsi_Host *host = rtsx_to_host(dev); 599 - struct rtsx_chip *chip = dev->chip; 600 - 601 - /* 602 - * Prevent new transfers, stop the current command, and 603 - * interrupt a SCSI-scan or device-reset delay 604 - */ 605 - mutex_lock(&dev->dev_mutex); 606 - spin_lock_irq(host->host_lock); 607 - rtsx_set_stat(chip, RTSX_STAT_DISCONNECT); 608 - spin_unlock_irq(host->host_lock); 609 - mutex_unlock(&dev->dev_mutex); 610 - wake_up(&dev->delay_wait); 611 - wait_for_completion(&dev->scanning_done); 612 - 613 - /* Wait some time to let other threads exist */ 614 - wait_timeout(100); 615 - 616 - /* 617 - * queuecommand won't accept any new commands and the control 618 - * thread won't execute a previously-queued command. If there 619 - * is such a command pending, complete it with an error. 620 - */ 621 - mutex_lock(&dev->dev_mutex); 622 - if (chip->srb) { 623 - chip->srb->result = DID_NO_CONNECT << 16; 624 - spin_lock_irq(host->host_lock); 625 - scsi_done(dev->chip->srb); 626 - chip->srb = NULL; 627 - spin_unlock_irq(host->host_lock); 628 - } 629 - mutex_unlock(&dev->dev_mutex); 630 - 631 - /* Now we own no commands so it's safe to remove the SCSI host */ 632 - scsi_remove_host(host); 633 - } 634 - 635 - /* Second stage of disconnect processing: deallocate all resources */ 636 - static void release_everything(struct rtsx_dev *dev) 637 - { 638 - rtsx_release_resources(dev); 639 - 640 - /* 641 - * Drop our reference to the host; the SCSI core will free it 642 - * when the refcount becomes 0. 643 - */ 644 - scsi_host_put(rtsx_to_host(dev)); 645 - } 646 - 647 - /* Thread to carry out delayed SCSI-device scanning */ 648 - static int rtsx_scan_thread(void *__dev) 649 - { 650 - struct rtsx_dev *dev = __dev; 651 - struct rtsx_chip *chip = dev->chip; 652 - 653 - /* Wait for the timeout to expire or for a disconnect */ 654 - if (delay_use > 0) { 655 - dev_info(&dev->pci->dev, 656 - "%s: waiting for device to settle before scanning\n", 657 - CR_DRIVER_NAME); 658 - wait_event_interruptible_timeout 659 - (dev->delay_wait, 660 - rtsx_chk_stat(chip, RTSX_STAT_DISCONNECT), 661 - delay_use * HZ); 662 - } 663 - 664 - /* If the device is still connected, perform the scanning */ 665 - if (!rtsx_chk_stat(chip, RTSX_STAT_DISCONNECT)) { 666 - scsi_scan_host(rtsx_to_host(dev)); 667 - dev_info(&dev->pci->dev, "%s: device scan complete\n", 668 - CR_DRIVER_NAME); 669 - 670 - /* Should we unbind if no devices were detected? */ 671 - } 672 - 673 - kthread_complete_and_exit(&dev->scanning_done, 0); 674 - } 675 - 676 - static void rtsx_init_options(struct rtsx_chip *chip) 677 - { 678 - chip->vendor_id = chip->rtsx->pci->vendor; 679 - chip->product_id = chip->rtsx->pci->device; 680 - chip->adma_mode = 1; 681 - chip->lun_mc = 0; 682 - chip->driver_first_load = 1; 683 - #ifdef HW_AUTO_SWITCH_SD_BUS 684 - chip->sdio_in_charge = 0; 685 - #endif 686 - 687 - chip->mspro_formatter_enable = 1; 688 - chip->ignore_sd = 0; 689 - chip->use_hw_setting = 0; 690 - chip->lun_mode = DEFAULT_SINGLE; 691 - chip->auto_delink_en = auto_delink_en; 692 - chip->ss_en = ss_en; 693 - chip->ss_idle_period = ss_interval * 1000; 694 - chip->remote_wakeup_en = 0; 695 - chip->aspm_l0s_l1_en = aspm_l0s_l1_en; 696 - chip->dynamic_aspm = 1; 697 - chip->fpga_sd_sdr104_clk = CLK_200; 698 - chip->fpga_sd_ddr50_clk = CLK_100; 699 - chip->fpga_sd_sdr50_clk = CLK_100; 700 - chip->fpga_sd_hs_clk = CLK_100; 701 - chip->fpga_mmc_52m_clk = CLK_80; 702 - chip->fpga_ms_hg_clk = CLK_80; 703 - chip->fpga_ms_4bit_clk = CLK_80; 704 - chip->fpga_ms_1bit_clk = CLK_40; 705 - chip->asic_sd_sdr104_clk = 203; 706 - chip->asic_sd_sdr50_clk = 98; 707 - chip->asic_sd_ddr50_clk = 98; 708 - chip->asic_sd_hs_clk = 98; 709 - chip->asic_mmc_52m_clk = 98; 710 - chip->asic_ms_hg_clk = 117; 711 - chip->asic_ms_4bit_clk = 78; 712 - chip->asic_ms_1bit_clk = 39; 713 - chip->ssc_depth_sd_sdr104 = SSC_DEPTH_2M; 714 - chip->ssc_depth_sd_sdr50 = SSC_DEPTH_2M; 715 - chip->ssc_depth_sd_ddr50 = SSC_DEPTH_1M; 716 - chip->ssc_depth_sd_hs = SSC_DEPTH_1M; 717 - chip->ssc_depth_mmc_52m = SSC_DEPTH_1M; 718 - chip->ssc_depth_ms_hg = SSC_DEPTH_1M; 719 - chip->ssc_depth_ms_4bit = SSC_DEPTH_512K; 720 - chip->ssc_depth_low_speed = SSC_DEPTH_512K; 721 - chip->ssc_en = 1; 722 - chip->sd_speed_prior = 0x01040203; 723 - chip->sd_current_prior = 0x00010203; 724 - chip->sd_ctl = SD_PUSH_POINT_AUTO | 725 - SD_SAMPLE_POINT_AUTO | 726 - SUPPORT_MMC_DDR_MODE; 727 - chip->sd_ddr_tx_phase = 0; 728 - chip->mmc_ddr_tx_phase = 1; 729 - chip->sd_default_tx_phase = 15; 730 - chip->sd_default_rx_phase = 15; 731 - chip->pmos_pwr_on_interval = 200; 732 - chip->sd_voltage_switch_delay = 1000; 733 - chip->ms_power_class_en = 3; 734 - 735 - chip->sd_400mA_ocp_thd = 1; 736 - chip->sd_800mA_ocp_thd = 5; 737 - chip->ms_ocp_thd = 2; 738 - 739 - chip->card_drive_sel = 0x55; 740 - chip->sd30_drive_sel_1v8 = 0x03; 741 - chip->sd30_drive_sel_3v3 = 0x01; 742 - 743 - chip->do_delink_before_power_down = 1; 744 - chip->auto_power_down = 1; 745 - chip->polling_config = 0; 746 - 747 - chip->force_clkreq_0 = 1; 748 - chip->ft2_fast_mode = 0; 749 - 750 - chip->sdio_retry_cnt = 1; 751 - 752 - chip->xd_timeout = 2000; 753 - chip->sd_timeout = 10000; 754 - chip->ms_timeout = 2000; 755 - chip->mspro_timeout = 15000; 756 - 757 - chip->power_down_in_ss = 1; 758 - 759 - chip->sdr104_en = 1; 760 - chip->sdr50_en = 1; 761 - chip->ddr50_en = 1; 762 - 763 - chip->delink_stage1_step = 100; 764 - chip->delink_stage2_step = 40; 765 - chip->delink_stage3_step = 20; 766 - 767 - chip->auto_delink_in_L1 = 1; 768 - chip->blink_led = 1; 769 - chip->msi_en = msi_en; 770 - chip->hp_watch_bios_hotplug = 0; 771 - chip->max_payload = 0; 772 - chip->phy_voltage = 0; 773 - 774 - chip->support_ms_8bit = 1; 775 - chip->s3_pwr_off_delay = 1000; 776 - } 777 - 778 - static int rtsx_probe(struct pci_dev *pci, 779 - const struct pci_device_id *pci_id) 780 - { 781 - struct Scsi_Host *host; 782 - struct rtsx_dev *dev; 783 - int err = 0; 784 - struct task_struct *th; 785 - 786 - dev_dbg(&pci->dev, "Realtek PCI-E card reader detected\n"); 787 - 788 - err = pcim_enable_device(pci); 789 - if (err < 0) { 790 - dev_err(&pci->dev, "PCI enable device failed!\n"); 791 - return err; 792 - } 793 - 794 - err = pci_request_regions(pci, CR_DRIVER_NAME); 795 - if (err < 0) { 796 - dev_err(&pci->dev, "PCI request regions for %s failed!\n", 797 - CR_DRIVER_NAME); 798 - return err; 799 - } 800 - 801 - /* 802 - * Ask the SCSI layer to allocate a host structure, with extra 803 - * space at the end for our private rtsx_dev structure. 804 - */ 805 - host = scsi_host_alloc(&rtsx_host_template, sizeof(*dev)); 806 - if (!host) { 807 - dev_err(&pci->dev, "Unable to allocate the scsi host\n"); 808 - err = -ENOMEM; 809 - goto scsi_host_alloc_fail; 810 - } 811 - 812 - dev = host_to_rtsx(host); 813 - memset(dev, 0, sizeof(struct rtsx_dev)); 814 - 815 - dev->chip = kzalloc(sizeof(*dev->chip), GFP_KERNEL); 816 - if (!dev->chip) { 817 - err = -ENOMEM; 818 - goto chip_alloc_fail; 819 - } 820 - 821 - spin_lock_init(&dev->reg_lock); 822 - mutex_init(&dev->dev_mutex); 823 - init_completion(&dev->cmnd_ready); 824 - init_completion(&dev->control_exit); 825 - init_completion(&dev->polling_exit); 826 - init_completion(&dev->notify); 827 - init_completion(&dev->scanning_done); 828 - init_waitqueue_head(&dev->delay_wait); 829 - 830 - dev->pci = pci; 831 - dev->irq = -1; 832 - 833 - dev_info(&pci->dev, "Resource length: 0x%x\n", 834 - (unsigned int)pci_resource_len(pci, 0)); 835 - dev->addr = pci_resource_start(pci, 0); 836 - dev->remap_addr = ioremap(dev->addr, pci_resource_len(pci, 0)); 837 - if (!dev->remap_addr) { 838 - dev_err(&pci->dev, "ioremap error\n"); 839 - err = -ENXIO; 840 - goto ioremap_fail; 841 - } 842 - 843 - /* 844 - * Using "unsigned long" cast here to eliminate gcc warning in 845 - * 64-bit system 846 - */ 847 - dev_info(&pci->dev, "Original address: 0x%lx, remapped address: 0x%lx\n", 848 - (unsigned long)(dev->addr), (unsigned long)(dev->remap_addr)); 849 - 850 - dev->rtsx_resv_buf = dmam_alloc_coherent(&pci->dev, RTSX_RESV_BUF_LEN, 851 - &dev->rtsx_resv_buf_addr, 852 - GFP_KERNEL); 853 - if (!dev->rtsx_resv_buf) { 854 - dev_err(&pci->dev, "alloc dma buffer fail\n"); 855 - err = -ENXIO; 856 - goto dma_alloc_fail; 857 - } 858 - dev->chip->host_cmds_ptr = dev->rtsx_resv_buf; 859 - dev->chip->host_cmds_addr = dev->rtsx_resv_buf_addr; 860 - dev->chip->host_sg_tbl_ptr = dev->rtsx_resv_buf + HOST_CMDS_BUF_LEN; 861 - dev->chip->host_sg_tbl_addr = dev->rtsx_resv_buf_addr + 862 - HOST_CMDS_BUF_LEN; 863 - 864 - dev->chip->rtsx = dev; 865 - 866 - rtsx_init_options(dev->chip); 867 - 868 - dev_info(&pci->dev, "pci->irq = %d\n", pci->irq); 869 - 870 - if (dev->chip->msi_en) { 871 - if (pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI) < 0) 872 - dev->chip->msi_en = 0; 873 - } 874 - 875 - if (rtsx_acquire_irq(dev) < 0) { 876 - err = -EBUSY; 877 - goto irq_acquire_fail; 878 - } 879 - 880 - pci_set_master(pci); 881 - synchronize_irq(dev->irq); 882 - 883 - rtsx_init_chip(dev->chip); 884 - 885 - /* 886 - * set the supported max_lun and max_id for the scsi host 887 - * NOTE: the minimal value of max_id is 1 888 - */ 889 - host->max_id = 1; 890 - host->max_lun = dev->chip->max_lun; 891 - 892 - /* Start up our control thread */ 893 - th = kthread_run(rtsx_control_thread, dev, CR_DRIVER_NAME); 894 - if (IS_ERR(th)) { 895 - dev_err(&pci->dev, "Unable to start control thread\n"); 896 - err = PTR_ERR(th); 897 - goto control_thread_fail; 898 - } 899 - dev->ctl_thread = th; 900 - 901 - err = scsi_add_host(host, &pci->dev); 902 - if (err) { 903 - dev_err(&pci->dev, "Unable to add the scsi host\n"); 904 - goto scsi_add_host_fail; 905 - } 906 - 907 - /* Start up the thread for delayed SCSI-device scanning */ 908 - th = kthread_run(rtsx_scan_thread, dev, "rtsx-scan"); 909 - if (IS_ERR(th)) { 910 - dev_err(&pci->dev, "Unable to start the device-scanning thread\n"); 911 - complete(&dev->scanning_done); 912 - err = PTR_ERR(th); 913 - goto scan_thread_fail; 914 - } 915 - 916 - /* Start up the thread for polling thread */ 917 - th = kthread_run(rtsx_polling_thread, dev, "rtsx-polling"); 918 - if (IS_ERR(th)) { 919 - dev_err(&pci->dev, "Unable to start the device-polling thread\n"); 920 - err = PTR_ERR(th); 921 - goto scan_thread_fail; 922 - } 923 - dev->polling_thread = th; 924 - 925 - pci_set_drvdata(pci, dev); 926 - 927 - return 0; 928 - 929 - /* We come here if there are any problems */ 930 - scan_thread_fail: 931 - quiesce_and_remove_host(dev); 932 - scsi_add_host_fail: 933 - complete(&dev->cmnd_ready); 934 - wait_for_completion(&dev->control_exit); 935 - control_thread_fail: 936 - free_irq(dev->irq, (void *)dev); 937 - rtsx_release_chip(dev->chip); 938 - irq_acquire_fail: 939 - dev->chip->host_cmds_ptr = NULL; 940 - dev->chip->host_sg_tbl_ptr = NULL; 941 - if (dev->chip->msi_en) 942 - pci_free_irq_vectors(dev->pci); 943 - dma_alloc_fail: 944 - iounmap(dev->remap_addr); 945 - ioremap_fail: 946 - kfree(dev->chip); 947 - chip_alloc_fail: 948 - dev_err(&pci->dev, "%s failed\n", __func__); 949 - scsi_host_put(host); 950 - scsi_host_alloc_fail: 951 - pci_release_regions(pci); 952 - return err; 953 - } 954 - 955 - static void rtsx_remove(struct pci_dev *pci) 956 - { 957 - struct rtsx_dev *dev = pci_get_drvdata(pci); 958 - 959 - quiesce_and_remove_host(dev); 960 - release_everything(dev); 961 - pci_release_regions(pci); 962 - } 963 - 964 - /* PCI IDs */ 965 - static const struct pci_device_id rtsx_ids[] = { 966 - { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x5208), 967 - PCI_CLASS_OTHERS << 16, 0xFF0000 }, 968 - { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x5288), 969 - PCI_CLASS_OTHERS << 16, 0xFF0000 }, 970 - { 0, }, 971 - }; 972 - 973 - MODULE_DEVICE_TABLE(pci, rtsx_ids); 974 - 975 - static SIMPLE_DEV_PM_OPS(rtsx_pm_ops, rtsx_suspend, rtsx_resume); 976 - 977 - /* pci_driver definition */ 978 - static struct pci_driver rtsx_driver = { 979 - .name = CR_DRIVER_NAME, 980 - .id_table = rtsx_ids, 981 - .probe = rtsx_probe, 982 - .remove = rtsx_remove, 983 - .driver.pm = &rtsx_pm_ops, 984 - .shutdown = rtsx_shutdown, 985 - }; 986 - 987 - module_pci_driver(rtsx_driver);
-164
drivers/staging/rts5208/rtsx.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_H 13 - #define __REALTEK_RTSX_H 14 - 15 - #include <linux/io.h> 16 - #include <linux/bitops.h> 17 - #include <linux/delay.h> 18 - #include <linux/interrupt.h> 19 - #include <linux/kernel.h> 20 - #include <linux/module.h> 21 - #include <linux/moduleparam.h> 22 - #include <linux/slab.h> 23 - #include <linux/pci.h> 24 - #include <linux/mutex.h> 25 - #include <linux/cdrom.h> 26 - #include <linux/workqueue.h> 27 - #include <linux/timer.h> 28 - #include <linux/time64.h> 29 - 30 - #include <scsi/scsi.h> 31 - #include <scsi/scsi_cmnd.h> 32 - #include <scsi/scsi_device.h> 33 - #include <scsi/scsi_devinfo.h> 34 - #include <scsi/scsi_eh.h> 35 - #include <scsi/scsi_host.h> 36 - 37 - #define CR_DRIVER_NAME "rts5208" 38 - 39 - /* 40 - * macros for easy use 41 - */ 42 - #define wait_timeout_x(task_state, msecs) \ 43 - do { \ 44 - set_current_state((task_state)); \ 45 - schedule_timeout((msecs) * HZ / 1000); \ 46 - } while (0) 47 - #define wait_timeout(msecs) wait_timeout_x(TASK_INTERRUPTIBLE, (msecs)) 48 - 49 - #define STATE_TRANS_NONE 0 50 - #define STATE_TRANS_CMD 1 51 - #define STATE_TRANS_BUF 2 52 - #define STATE_TRANS_SG 3 53 - 54 - #define TRANS_NOT_READY 0 55 - #define TRANS_RESULT_OK 1 56 - #define TRANS_RESULT_FAIL 2 57 - 58 - #define SCSI_LUN(srb) ((srb)->device->lun) 59 - 60 - struct rtsx_chip; 61 - 62 - struct rtsx_dev { 63 - struct pci_dev *pci; 64 - 65 - /* pci resources */ 66 - unsigned long addr; 67 - void __iomem *remap_addr; 68 - int irq; 69 - 70 - /* locks */ 71 - spinlock_t reg_lock; 72 - 73 - struct task_struct *ctl_thread; /* the control thread */ 74 - struct task_struct *polling_thread; /* the polling thread */ 75 - 76 - /* mutual exclusion and synchronization structures */ 77 - struct completion cmnd_ready; /* to sleep thread on */ 78 - struct completion control_exit; /* control thread exit */ 79 - struct completion polling_exit; /* polling thread exit */ 80 - struct completion notify; /* thread begin/end */ 81 - struct completion scanning_done; /* wait for scan thread */ 82 - 83 - wait_queue_head_t delay_wait; /* wait during scan, reset */ 84 - struct mutex dev_mutex; 85 - 86 - /* host reserved buffer */ 87 - void *rtsx_resv_buf; 88 - dma_addr_t rtsx_resv_buf_addr; 89 - 90 - char trans_result; 91 - char trans_state; 92 - 93 - struct completion *done; 94 - /* Whether interrupt handler should care card cd info */ 95 - u32 check_card_cd; 96 - 97 - struct rtsx_chip *chip; 98 - }; 99 - 100 - /* Convert between rtsx_dev and the corresponding Scsi_Host */ 101 - static inline struct Scsi_Host *rtsx_to_host(struct rtsx_dev *dev) 102 - { 103 - return container_of((void *)dev, struct Scsi_Host, hostdata); 104 - } 105 - 106 - static inline struct rtsx_dev *host_to_rtsx(struct Scsi_Host *host) 107 - { 108 - return (struct rtsx_dev *)host->hostdata; 109 - } 110 - 111 - #define lock_state(chip) spin_lock_irq(&((chip)->rtsx->reg_lock)) 112 - #define unlock_state(chip) spin_unlock_irq(&((chip)->rtsx->reg_lock)) 113 - 114 - /* struct scsi_cmnd transfer buffer access utilities */ 115 - enum xfer_buf_dir {TO_XFER_BUF, FROM_XFER_BUF}; 116 - 117 - #include "rtsx_chip.h" 118 - #include "rtsx_transport.h" 119 - #include "rtsx_scsi.h" 120 - #include "rtsx_card.h" 121 - #include "rtsx_sys.h" 122 - #include "general.h" 123 - 124 - static inline void rtsx_writel(struct rtsx_chip *chip, u32 reg, u32 value) 125 - { 126 - iowrite32(value, chip->rtsx->remap_addr + reg); 127 - } 128 - 129 - static inline u32 rtsx_readl(struct rtsx_chip *chip, u32 reg) 130 - { 131 - return ioread32(chip->rtsx->remap_addr + reg); 132 - } 133 - 134 - static inline void rtsx_writew(struct rtsx_chip *chip, u32 reg, u16 value) 135 - { 136 - iowrite16(value, chip->rtsx->remap_addr + reg); 137 - } 138 - 139 - static inline u16 rtsx_readw(struct rtsx_chip *chip, u32 reg) 140 - { 141 - return ioread16(chip->rtsx->remap_addr + reg); 142 - } 143 - 144 - static inline void rtsx_writeb(struct rtsx_chip *chip, u32 reg, u8 value) 145 - { 146 - iowrite8(value, chip->rtsx->remap_addr + reg); 147 - } 148 - 149 - static inline u8 rtsx_readb(struct rtsx_chip *chip, u32 reg) 150 - { 151 - return ioread8((chip)->rtsx->remap_addr + reg); 152 - } 153 - 154 - static inline int rtsx_read_config_byte(struct rtsx_chip *chip, int where, u8 *val) 155 - { 156 - return pci_read_config_byte(chip->rtsx->pci, where, val); 157 - } 158 - 159 - static inline int rtsx_write_config_byte(struct rtsx_chip *chip, int where, u8 val) 160 - { 161 - return pci_write_config_byte(chip->rtsx->pci, where, val); 162 - } 163 - 164 - #endif /* __REALTEK_RTSX_H */
-1151
drivers/staging/rts5208/rtsx_card.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/workqueue.h> 16 - #include <linux/kernel.h> 17 - 18 - #include "rtsx.h" 19 - #include "sd.h" 20 - #include "xd.h" 21 - #include "ms.h" 22 - 23 - void do_remaining_work(struct rtsx_chip *chip) 24 - { 25 - struct sd_info *sd_card = &chip->sd_card; 26 - #ifdef XD_DELAY_WRITE 27 - struct xd_info *xd_card = &chip->xd_card; 28 - #endif 29 - struct ms_info *ms_card = &chip->ms_card; 30 - 31 - if (chip->card_ready & SD_CARD) { 32 - if (sd_card->seq_mode) { 33 - rtsx_set_stat(chip, RTSX_STAT_RUN); 34 - sd_card->cleanup_counter++; 35 - } else { 36 - sd_card->cleanup_counter = 0; 37 - } 38 - } 39 - 40 - #ifdef XD_DELAY_WRITE 41 - if (chip->card_ready & XD_CARD) { 42 - if (xd_card->delay_write.delay_write_flag) { 43 - rtsx_set_stat(chip, RTSX_STAT_RUN); 44 - xd_card->cleanup_counter++; 45 - } else { 46 - xd_card->cleanup_counter = 0; 47 - } 48 - } 49 - #endif 50 - 51 - if (chip->card_ready & MS_CARD) { 52 - if (CHK_MSPRO(ms_card)) { 53 - if (ms_card->seq_mode) { 54 - rtsx_set_stat(chip, RTSX_STAT_RUN); 55 - ms_card->cleanup_counter++; 56 - } else { 57 - ms_card->cleanup_counter = 0; 58 - } 59 - } else { 60 - #ifdef MS_DELAY_WRITE 61 - if (ms_card->delay_write.delay_write_flag) { 62 - rtsx_set_stat(chip, RTSX_STAT_RUN); 63 - ms_card->cleanup_counter++; 64 - } else { 65 - ms_card->cleanup_counter = 0; 66 - } 67 - #endif 68 - } 69 - } 70 - 71 - if (sd_card->cleanup_counter > POLLING_WAIT_CNT) 72 - sd_cleanup_work(chip); 73 - 74 - if (xd_card->cleanup_counter > POLLING_WAIT_CNT) 75 - xd_cleanup_work(chip); 76 - 77 - if (ms_card->cleanup_counter > POLLING_WAIT_CNT) 78 - ms_cleanup_work(chip); 79 - } 80 - 81 - void try_to_switch_sdio_ctrl(struct rtsx_chip *chip) 82 - { 83 - u8 reg1 = 0, reg2 = 0; 84 - 85 - rtsx_read_register(chip, 0xFF34, &reg1); 86 - rtsx_read_register(chip, 0xFF38, &reg2); 87 - dev_dbg(rtsx_dev(chip), "reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", 88 - reg1, reg2); 89 - if ((reg1 & 0xC0) && (reg2 & 0xC0)) { 90 - chip->sd_int = 1; 91 - rtsx_write_register(chip, SDIO_CTRL, 0xFF, 92 - SDIO_BUS_CTRL | SDIO_CD_CTRL); 93 - rtsx_write_register(chip, PWR_GATE_CTRL, 94 - LDO3318_PWR_MASK, LDO_ON); 95 - } 96 - } 97 - 98 - #ifdef SUPPORT_SDIO_ASPM 99 - void dynamic_configure_sdio_aspm(struct rtsx_chip *chip) 100 - { 101 - u8 buf[12], reg; 102 - int i; 103 - 104 - for (i = 0; i < 12; i++) 105 - rtsx_read_register(chip, 0xFF08 + i, &buf[i]); 106 - rtsx_read_register(chip, 0xFF25, &reg); 107 - if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) { 108 - chip->sdio_counter = 0; 109 - chip->sdio_idle = 0; 110 - } else { 111 - if (!chip->sdio_idle) { 112 - chip->sdio_counter++; 113 - if (chip->sdio_counter >= SDIO_IDLE_COUNT) { 114 - chip->sdio_counter = 0; 115 - chip->sdio_idle = 1; 116 - } 117 - } 118 - } 119 - memcpy(chip->sdio_raw_data, buf, 12); 120 - 121 - if (chip->sdio_idle) { 122 - if (!chip->sdio_aspm) { 123 - dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n"); 124 - rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 125 - 0x30 | (chip->aspm_level[1] << 2)); 126 - chip->sdio_aspm = 1; 127 - } 128 - } else { 129 - if (chip->sdio_aspm) { 130 - dev_dbg(rtsx_dev(chip), "SDIO exit ASPM!\n"); 131 - rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30); 132 - chip->sdio_aspm = 0; 133 - } 134 - } 135 - } 136 - #endif 137 - 138 - void do_reset_sd_card(struct rtsx_chip *chip) 139 - { 140 - int retval; 141 - 142 - dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 143 - chip->sd_reset_counter, chip->card2lun[SD_CARD]); 144 - 145 - if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) { 146 - clear_bit(SD_NR, &chip->need_reset); 147 - chip->sd_reset_counter = 0; 148 - chip->sd_show_cnt = 0; 149 - return; 150 - } 151 - 152 - chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0; 153 - 154 - rtsx_set_stat(chip, RTSX_STAT_RUN); 155 - rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 156 - 157 - retval = reset_sd_card(chip); 158 - if (chip->need_release & SD_CARD) 159 - return; 160 - if (retval == STATUS_SUCCESS) { 161 - clear_bit(SD_NR, &chip->need_reset); 162 - chip->sd_reset_counter = 0; 163 - chip->sd_show_cnt = 0; 164 - chip->card_ready |= SD_CARD; 165 - chip->card_fail &= ~SD_CARD; 166 - chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw; 167 - } else { 168 - if (chip->sd_io || chip->sd_reset_counter >= MAX_RESET_CNT) { 169 - clear_bit(SD_NR, &chip->need_reset); 170 - chip->sd_reset_counter = 0; 171 - chip->sd_show_cnt = 0; 172 - } else { 173 - chip->sd_reset_counter++; 174 - } 175 - chip->card_ready &= ~SD_CARD; 176 - chip->card_fail |= SD_CARD; 177 - chip->capacity[chip->card2lun[SD_CARD]] = 0; 178 - chip->rw_card[chip->card2lun[SD_CARD]] = NULL; 179 - 180 - rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 181 - if (!chip->ft2_fast_mode) 182 - card_power_off(chip, SD_CARD); 183 - if (chip->sd_io) { 184 - chip->sd_int = 0; 185 - try_to_switch_sdio_ctrl(chip); 186 - } else { 187 - disable_card_clock(chip, SD_CARD); 188 - } 189 - } 190 - } 191 - 192 - void do_reset_xd_card(struct rtsx_chip *chip) 193 - { 194 - int retval; 195 - 196 - dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 197 - chip->xd_reset_counter, chip->card2lun[XD_CARD]); 198 - 199 - if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) { 200 - clear_bit(XD_NR, &chip->need_reset); 201 - chip->xd_reset_counter = 0; 202 - chip->xd_show_cnt = 0; 203 - return; 204 - } 205 - 206 - chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0; 207 - 208 - rtsx_set_stat(chip, RTSX_STAT_RUN); 209 - rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 210 - 211 - retval = reset_xd_card(chip); 212 - if (chip->need_release & XD_CARD) 213 - return; 214 - if (retval == STATUS_SUCCESS) { 215 - clear_bit(XD_NR, &chip->need_reset); 216 - chip->xd_reset_counter = 0; 217 - chip->card_ready |= XD_CARD; 218 - chip->card_fail &= ~XD_CARD; 219 - chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw; 220 - } else { 221 - if (chip->xd_reset_counter >= MAX_RESET_CNT) { 222 - clear_bit(XD_NR, &chip->need_reset); 223 - chip->xd_reset_counter = 0; 224 - chip->xd_show_cnt = 0; 225 - } else { 226 - chip->xd_reset_counter++; 227 - } 228 - chip->card_ready &= ~XD_CARD; 229 - chip->card_fail |= XD_CARD; 230 - chip->capacity[chip->card2lun[XD_CARD]] = 0; 231 - chip->rw_card[chip->card2lun[XD_CARD]] = NULL; 232 - 233 - rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 234 - if (!chip->ft2_fast_mode) 235 - card_power_off(chip, XD_CARD); 236 - disable_card_clock(chip, XD_CARD); 237 - } 238 - } 239 - 240 - void do_reset_ms_card(struct rtsx_chip *chip) 241 - { 242 - int retval; 243 - 244 - dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 245 - chip->ms_reset_counter, chip->card2lun[MS_CARD]); 246 - 247 - if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) { 248 - clear_bit(MS_NR, &chip->need_reset); 249 - chip->ms_reset_counter = 0; 250 - chip->ms_show_cnt = 0; 251 - return; 252 - } 253 - 254 - chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0; 255 - 256 - rtsx_set_stat(chip, RTSX_STAT_RUN); 257 - rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 258 - 259 - retval = reset_ms_card(chip); 260 - if (chip->need_release & MS_CARD) 261 - return; 262 - if (retval == STATUS_SUCCESS) { 263 - clear_bit(MS_NR, &chip->need_reset); 264 - chip->ms_reset_counter = 0; 265 - chip->card_ready |= MS_CARD; 266 - chip->card_fail &= ~MS_CARD; 267 - chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw; 268 - } else { 269 - if (chip->ms_reset_counter >= MAX_RESET_CNT) { 270 - clear_bit(MS_NR, &chip->need_reset); 271 - chip->ms_reset_counter = 0; 272 - chip->ms_show_cnt = 0; 273 - } else { 274 - chip->ms_reset_counter++; 275 - } 276 - chip->card_ready &= ~MS_CARD; 277 - chip->card_fail |= MS_CARD; 278 - chip->capacity[chip->card2lun[MS_CARD]] = 0; 279 - chip->rw_card[chip->card2lun[MS_CARD]] = NULL; 280 - 281 - rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 282 - if (!chip->ft2_fast_mode) 283 - card_power_off(chip, MS_CARD); 284 - disable_card_clock(chip, MS_CARD); 285 - } 286 - } 287 - 288 - static void release_sdio(struct rtsx_chip *chip) 289 - { 290 - if (chip->sd_io) { 291 - rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 292 - SD_STOP | SD_CLR_ERR); 293 - 294 - if (chip->chip_insert_with_sdio) { 295 - chip->chip_insert_with_sdio = 0; 296 - 297 - if (CHECK_PID(chip, 0x5288)) 298 - rtsx_write_register(chip, 0xFE5A, 0x08, 0x00); 299 - else 300 - rtsx_write_register(chip, 0xFE70, 0x80, 0x00); 301 - } 302 - 303 - rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0); 304 - chip->sd_io = 0; 305 - } 306 - } 307 - 308 - void rtsx_power_off_card(struct rtsx_chip *chip) 309 - { 310 - if ((chip->card_ready & SD_CARD) || chip->sd_io) { 311 - sd_cleanup_work(chip); 312 - sd_power_off_card3v3(chip); 313 - } 314 - 315 - if (chip->card_ready & XD_CARD) { 316 - xd_cleanup_work(chip); 317 - xd_power_off_card3v3(chip); 318 - } 319 - 320 - if (chip->card_ready & MS_CARD) { 321 - ms_cleanup_work(chip); 322 - ms_power_off_card3v3(chip); 323 - } 324 - } 325 - 326 - void rtsx_release_cards(struct rtsx_chip *chip) 327 - { 328 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 329 - 330 - if ((chip->card_ready & SD_CARD) || chip->sd_io) { 331 - if (chip->int_reg & SD_EXIST) 332 - sd_cleanup_work(chip); 333 - release_sd_card(chip); 334 - } 335 - 336 - if (chip->card_ready & XD_CARD) { 337 - if (chip->int_reg & XD_EXIST) 338 - xd_cleanup_work(chip); 339 - release_xd_card(chip); 340 - } 341 - 342 - if (chip->card_ready & MS_CARD) { 343 - if (chip->int_reg & MS_EXIST) 344 - ms_cleanup_work(chip); 345 - release_ms_card(chip); 346 - } 347 - } 348 - 349 - void rtsx_reset_cards(struct rtsx_chip *chip) 350 - { 351 - if (!chip->need_reset) 352 - return; 353 - 354 - rtsx_set_stat(chip, RTSX_STAT_RUN); 355 - 356 - rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 357 - 358 - rtsx_disable_aspm(chip); 359 - 360 - if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio) 361 - clear_bit(SD_NR, &chip->need_reset); 362 - 363 - if (chip->need_reset & XD_CARD) { 364 - chip->card_exist |= XD_CARD; 365 - 366 - if (chip->xd_show_cnt >= MAX_SHOW_CNT) 367 - do_reset_xd_card(chip); 368 - else 369 - chip->xd_show_cnt++; 370 - } 371 - if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) { 372 - if (chip->card_exist & XD_CARD) { 373 - clear_bit(SD_NR, &chip->need_reset); 374 - clear_bit(MS_NR, &chip->need_reset); 375 - } 376 - } 377 - if (chip->need_reset & SD_CARD) { 378 - chip->card_exist |= SD_CARD; 379 - 380 - if (chip->sd_show_cnt >= MAX_SHOW_CNT) { 381 - rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 382 - do_reset_sd_card(chip); 383 - } else { 384 - chip->sd_show_cnt++; 385 - } 386 - } 387 - if (chip->need_reset & MS_CARD) { 388 - chip->card_exist |= MS_CARD; 389 - 390 - if (chip->ms_show_cnt >= MAX_SHOW_CNT) 391 - do_reset_ms_card(chip); 392 - else 393 - chip->ms_show_cnt++; 394 - } 395 - } 396 - 397 - void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip) 398 - { 399 - rtsx_set_stat(chip, RTSX_STAT_RUN); 400 - 401 - rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 402 - 403 - if (reset_chip) 404 - rtsx_reset_chip(chip); 405 - 406 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 407 - 408 - if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) { 409 - release_sdio(chip); 410 - release_sd_card(chip); 411 - 412 - wait_timeout(100); 413 - 414 - chip->card_exist |= SD_CARD; 415 - do_reset_sd_card(chip); 416 - } 417 - 418 - if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) { 419 - release_xd_card(chip); 420 - 421 - wait_timeout(100); 422 - 423 - chip->card_exist |= XD_CARD; 424 - do_reset_xd_card(chip); 425 - } 426 - 427 - if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) { 428 - release_ms_card(chip); 429 - 430 - wait_timeout(100); 431 - 432 - chip->card_exist |= MS_CARD; 433 - do_reset_ms_card(chip); 434 - } 435 - 436 - chip->need_reinit = 0; 437 - } 438 - 439 - #ifdef DISABLE_CARD_INT 440 - void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset, 441 - unsigned long *need_release) 442 - { 443 - u8 release_map = 0, reset_map = 0; 444 - 445 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 446 - 447 - if (chip->card_exist) { 448 - if (chip->card_exist & XD_CARD) { 449 - if (!(chip->int_reg & XD_EXIST)) 450 - release_map |= XD_CARD; 451 - } else if (chip->card_exist & SD_CARD) { 452 - if (!(chip->int_reg & SD_EXIST)) 453 - release_map |= SD_CARD; 454 - } else if (chip->card_exist & MS_CARD) { 455 - if (!(chip->int_reg & MS_EXIST)) 456 - release_map |= MS_CARD; 457 - } 458 - } else { 459 - if (chip->int_reg & XD_EXIST) 460 - reset_map |= XD_CARD; 461 - else if (chip->int_reg & SD_EXIST) 462 - reset_map |= SD_CARD; 463 - else if (chip->int_reg & MS_EXIST) 464 - reset_map |= MS_CARD; 465 - } 466 - 467 - if (reset_map) { 468 - int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0; 469 - int i; 470 - 471 - for (i = 0; i < (DEBOUNCE_CNT); i++) { 472 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 473 - 474 - if (chip->int_reg & XD_EXIST) 475 - xd_cnt++; 476 - else 477 - xd_cnt = 0; 478 - 479 - if (chip->int_reg & SD_EXIST) 480 - sd_cnt++; 481 - else 482 - sd_cnt = 0; 483 - 484 - if (chip->int_reg & MS_EXIST) 485 - ms_cnt++; 486 - else 487 - ms_cnt = 0; 488 - 489 - wait_timeout(30); 490 - } 491 - 492 - reset_map = 0; 493 - if (!(chip->card_exist & XD_CARD) && 494 - (xd_cnt > (DEBOUNCE_CNT - 1))) 495 - reset_map |= XD_CARD; 496 - if (!(chip->card_exist & SD_CARD) && 497 - (sd_cnt > (DEBOUNCE_CNT - 1))) 498 - reset_map |= SD_CARD; 499 - if (!(chip->card_exist & MS_CARD) && 500 - (ms_cnt > (DEBOUNCE_CNT - 1))) 501 - reset_map |= MS_CARD; 502 - } 503 - 504 - if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) 505 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00); 506 - 507 - if (need_reset) 508 - *need_reset = reset_map; 509 - if (need_release) 510 - *need_release = release_map; 511 - } 512 - #endif 513 - 514 - void rtsx_init_cards(struct rtsx_chip *chip) 515 - { 516 - if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 517 - dev_dbg(rtsx_dev(chip), "Reset chip in polling thread!\n"); 518 - rtsx_reset_chip(chip); 519 - RTSX_CLR_DELINK(chip); 520 - } 521 - 522 - #ifdef DISABLE_CARD_INT 523 - card_cd_debounce(chip, &chip->need_reset, &chip->need_release); 524 - #endif 525 - 526 - if (chip->need_release) { 527 - if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) { 528 - if (chip->int_reg & XD_EXIST) { 529 - clear_bit(SD_NR, &chip->need_release); 530 - clear_bit(MS_NR, &chip->need_release); 531 - } 532 - } 533 - 534 - if (!(chip->card_exist & SD_CARD) && !chip->sd_io) 535 - clear_bit(SD_NR, &chip->need_release); 536 - if (!(chip->card_exist & XD_CARD)) 537 - clear_bit(XD_NR, &chip->need_release); 538 - if (!(chip->card_exist & MS_CARD)) 539 - clear_bit(MS_NR, &chip->need_release); 540 - 541 - dev_dbg(rtsx_dev(chip), "chip->need_release = 0x%x\n", 542 - (unsigned int)(chip->need_release)); 543 - 544 - #ifdef SUPPORT_OCP 545 - if (chip->need_release) { 546 - if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER)) 547 - rtsx_write_register(chip, OCPCLR, 548 - CARD_OC_INT_CLR | 549 - CARD_OC_CLR, 550 - CARD_OC_INT_CLR | 551 - CARD_OC_CLR); 552 - chip->ocp_stat = 0; 553 - } 554 - #endif 555 - if (chip->need_release) { 556 - rtsx_set_stat(chip, RTSX_STAT_RUN); 557 - rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 558 - } 559 - 560 - if (chip->need_release & SD_CARD) { 561 - clear_bit(SD_NR, &chip->need_release); 562 - chip->card_exist &= ~SD_CARD; 563 - chip->card_ejected &= ~SD_CARD; 564 - chip->card_fail &= ~SD_CARD; 565 - CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]); 566 - chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0; 567 - rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 568 - 569 - release_sdio(chip); 570 - release_sd_card(chip); 571 - } 572 - 573 - if (chip->need_release & XD_CARD) { 574 - clear_bit(XD_NR, &chip->need_release); 575 - chip->card_exist &= ~XD_CARD; 576 - chip->card_ejected &= ~XD_CARD; 577 - chip->card_fail &= ~XD_CARD; 578 - CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]); 579 - chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0; 580 - 581 - release_xd_card(chip); 582 - 583 - if (CHECK_PID(chip, 0x5288) && 584 - CHECK_BARO_PKG(chip, QFN)) 585 - rtsx_write_register(chip, HOST_SLEEP_STATE, 586 - 0xC0, 0xC0); 587 - } 588 - 589 - if (chip->need_release & MS_CARD) { 590 - clear_bit(MS_NR, &chip->need_release); 591 - chip->card_exist &= ~MS_CARD; 592 - chip->card_ejected &= ~MS_CARD; 593 - chip->card_fail &= ~MS_CARD; 594 - CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]); 595 - chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0; 596 - 597 - release_ms_card(chip); 598 - } 599 - 600 - dev_dbg(rtsx_dev(chip), "chip->card_exist = 0x%x\n", 601 - chip->card_exist); 602 - 603 - if (!chip->card_exist) 604 - turn_off_led(chip, LED_GPIO); 605 - } 606 - 607 - if (chip->need_reset) { 608 - dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x\n", 609 - (unsigned int)(chip->need_reset)); 610 - 611 - rtsx_reset_cards(chip); 612 - } 613 - 614 - if (chip->need_reinit) { 615 - dev_dbg(rtsx_dev(chip), "chip->need_reinit = 0x%x\n", 616 - (unsigned int)(chip->need_reinit)); 617 - 618 - rtsx_reinit_cards(chip, 0); 619 - } 620 - } 621 - 622 - int switch_ssc_clock(struct rtsx_chip *chip, int clk) 623 - { 624 - int retval; 625 - u8 n = (u8)(clk - 2), min_n, max_n; 626 - u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask; 627 - int sd_vpclk_phase_reset = 0; 628 - 629 - if (chip->cur_clk == clk) 630 - return STATUS_SUCCESS; 631 - 632 - min_n = 60; 633 - max_n = 120; 634 - max_div = CLK_DIV_4; 635 - 636 - dev_dbg(rtsx_dev(chip), "Switch SSC clock to %dMHz (cur_clk = %d)\n", 637 - clk, chip->cur_clk); 638 - 639 - if (clk <= 2 || n > max_n) 640 - return STATUS_FAIL; 641 - 642 - mcu_cnt = (u8)(125 / clk + 3); 643 - if (mcu_cnt > 7) 644 - mcu_cnt = 7; 645 - 646 - div = CLK_DIV_1; 647 - while ((n < min_n) && (div < max_div)) { 648 - n = (n + 2) * 2 - 2; 649 - div++; 650 - } 651 - dev_dbg(rtsx_dev(chip), "n = %d, div = %d\n", n, div); 652 - 653 - if (chip->ssc_en) { 654 - ssc_depth = 0x01; 655 - n -= 2; 656 - } else { 657 - ssc_depth = 0; 658 - } 659 - 660 - ssc_depth_mask = 0x03; 661 - 662 - dev_dbg(rtsx_dev(chip), "ssc_depth = %d\n", ssc_depth); 663 - 664 - rtsx_init_cmd(chip); 665 - rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 666 - rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); 667 - rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 668 - rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); 669 - rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 670 - rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 671 - if (sd_vpclk_phase_reset) { 672 - rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 673 - PHASE_NOT_RESET, 0); 674 - rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 675 - PHASE_NOT_RESET, PHASE_NOT_RESET); 676 - } 677 - 678 - retval = rtsx_send_cmd(chip, 0, WAIT_TIME); 679 - if (retval < 0) 680 - return STATUS_ERROR; 681 - 682 - udelay(10); 683 - retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); 684 - if (retval) 685 - return retval; 686 - 687 - chip->cur_clk = clk; 688 - 689 - return STATUS_SUCCESS; 690 - } 691 - 692 - int switch_normal_clock(struct rtsx_chip *chip, int clk) 693 - { 694 - int retval; 695 - u8 sel, div, mcu_cnt; 696 - int sd_vpclk_phase_reset = 0; 697 - 698 - if (chip->cur_clk == clk) 699 - return STATUS_SUCCESS; 700 - 701 - switch (clk) { 702 - case CLK_20: 703 - dev_dbg(rtsx_dev(chip), "Switch clock to 20MHz\n"); 704 - sel = SSC_80; 705 - div = CLK_DIV_4; 706 - mcu_cnt = 7; 707 - break; 708 - 709 - case CLK_30: 710 - dev_dbg(rtsx_dev(chip), "Switch clock to 30MHz\n"); 711 - sel = SSC_120; 712 - div = CLK_DIV_4; 713 - mcu_cnt = 7; 714 - break; 715 - 716 - case CLK_40: 717 - dev_dbg(rtsx_dev(chip), "Switch clock to 40MHz\n"); 718 - sel = SSC_80; 719 - div = CLK_DIV_2; 720 - mcu_cnt = 7; 721 - break; 722 - 723 - case CLK_50: 724 - dev_dbg(rtsx_dev(chip), "Switch clock to 50MHz\n"); 725 - sel = SSC_100; 726 - div = CLK_DIV_2; 727 - mcu_cnt = 6; 728 - break; 729 - 730 - case CLK_60: 731 - dev_dbg(rtsx_dev(chip), "Switch clock to 60MHz\n"); 732 - sel = SSC_120; 733 - div = CLK_DIV_2; 734 - mcu_cnt = 6; 735 - break; 736 - 737 - case CLK_80: 738 - dev_dbg(rtsx_dev(chip), "Switch clock to 80MHz\n"); 739 - sel = SSC_80; 740 - div = CLK_DIV_1; 741 - mcu_cnt = 5; 742 - break; 743 - 744 - case CLK_100: 745 - dev_dbg(rtsx_dev(chip), "Switch clock to 100MHz\n"); 746 - sel = SSC_100; 747 - div = CLK_DIV_1; 748 - mcu_cnt = 5; 749 - break; 750 - 751 - case CLK_120: 752 - dev_dbg(rtsx_dev(chip), "Switch clock to 120MHz\n"); 753 - sel = SSC_120; 754 - div = CLK_DIV_1; 755 - mcu_cnt = 5; 756 - break; 757 - 758 - case CLK_150: 759 - dev_dbg(rtsx_dev(chip), "Switch clock to 150MHz\n"); 760 - sel = SSC_150; 761 - div = CLK_DIV_1; 762 - mcu_cnt = 4; 763 - break; 764 - 765 - case CLK_200: 766 - dev_dbg(rtsx_dev(chip), "Switch clock to 200MHz\n"); 767 - sel = SSC_200; 768 - div = CLK_DIV_1; 769 - mcu_cnt = 4; 770 - break; 771 - 772 - default: 773 - dev_dbg(rtsx_dev(chip), "Try to switch to an illegal clock (%d)\n", 774 - clk); 775 - return STATUS_FAIL; 776 - } 777 - 778 - retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); 779 - if (retval) 780 - return retval; 781 - if (sd_vpclk_phase_reset) { 782 - retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 783 - PHASE_NOT_RESET, 0); 784 - if (retval) 785 - return retval; 786 - retval = rtsx_write_register(chip, SD_VPCLK1_CTL, 787 - PHASE_NOT_RESET, 0); 788 - if (retval) 789 - return retval; 790 - } 791 - retval = rtsx_write_register(chip, CLK_DIV, 0xFF, 792 - (div << 4) | mcu_cnt); 793 - if (retval) 794 - return retval; 795 - retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel); 796 - if (retval) 797 - return retval; 798 - 799 - if (sd_vpclk_phase_reset) { 800 - udelay(200); 801 - retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 802 - PHASE_NOT_RESET, PHASE_NOT_RESET); 803 - if (retval) 804 - return retval; 805 - retval = rtsx_write_register(chip, SD_VPCLK1_CTL, 806 - PHASE_NOT_RESET, PHASE_NOT_RESET); 807 - if (retval) 808 - return retval; 809 - udelay(200); 810 - } 811 - retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); 812 - if (retval) 813 - return retval; 814 - 815 - chip->cur_clk = clk; 816 - 817 - return STATUS_SUCCESS; 818 - } 819 - 820 - void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, 821 - u32 byte_cnt, u8 pack_size) 822 - { 823 - if (pack_size > DMA_1024) 824 - pack_size = DMA_512; 825 - 826 - rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); 827 - 828 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24)); 829 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16)); 830 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8)); 831 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt); 832 - 833 - if (dir == DMA_FROM_DEVICE) { 834 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 835 - 0x03 | DMA_PACK_SIZE_MASK, 836 - DMA_DIR_FROM_CARD | DMA_EN | pack_size); 837 - } else { 838 - rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 839 - 0x03 | DMA_PACK_SIZE_MASK, 840 - DMA_DIR_TO_CARD | DMA_EN | pack_size); 841 - } 842 - 843 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 844 - } 845 - 846 - int enable_card_clock(struct rtsx_chip *chip, u8 card) 847 - { 848 - int retval; 849 - u8 clk_en = 0; 850 - 851 - if (card & XD_CARD) 852 - clk_en |= XD_CLK_EN; 853 - if (card & SD_CARD) 854 - clk_en |= SD_CLK_EN; 855 - if (card & MS_CARD) 856 - clk_en |= MS_CLK_EN; 857 - 858 - retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en); 859 - if (retval) 860 - return retval; 861 - 862 - return STATUS_SUCCESS; 863 - } 864 - 865 - int disable_card_clock(struct rtsx_chip *chip, u8 card) 866 - { 867 - int retval; 868 - u8 clk_en = 0; 869 - 870 - if (card & XD_CARD) 871 - clk_en |= XD_CLK_EN; 872 - if (card & SD_CARD) 873 - clk_en |= SD_CLK_EN; 874 - if (card & MS_CARD) 875 - clk_en |= MS_CLK_EN; 876 - 877 - retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0); 878 - if (retval) 879 - return retval; 880 - 881 - return STATUS_SUCCESS; 882 - } 883 - 884 - int card_power_on(struct rtsx_chip *chip, u8 card) 885 - { 886 - int retval; 887 - u8 mask, val1, val2; 888 - 889 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && card == MS_CARD) { 890 - mask = MS_POWER_MASK; 891 - val1 = MS_PARTIAL_POWER_ON; 892 - val2 = MS_POWER_ON; 893 - } else { 894 - mask = SD_POWER_MASK; 895 - val1 = SD_PARTIAL_POWER_ON; 896 - val2 = SD_POWER_ON; 897 - } 898 - 899 - rtsx_init_cmd(chip); 900 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1); 901 - 902 - retval = rtsx_send_cmd(chip, 0, 100); 903 - if (retval != STATUS_SUCCESS) 904 - return STATUS_FAIL; 905 - 906 - udelay(chip->pmos_pwr_on_interval); 907 - 908 - rtsx_init_cmd(chip); 909 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2); 910 - 911 - retval = rtsx_send_cmd(chip, 0, 100); 912 - if (retval != STATUS_SUCCESS) 913 - return STATUS_FAIL; 914 - 915 - return STATUS_SUCCESS; 916 - } 917 - 918 - int card_power_off(struct rtsx_chip *chip, u8 card) 919 - { 920 - int retval; 921 - u8 mask, val; 922 - 923 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && card == MS_CARD) { 924 - mask = MS_POWER_MASK; 925 - val = MS_POWER_OFF; 926 - } else { 927 - mask = SD_POWER_MASK; 928 - val = SD_POWER_OFF; 929 - } 930 - 931 - retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); 932 - if (retval) 933 - return retval; 934 - 935 - return STATUS_SUCCESS; 936 - } 937 - 938 - int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 939 - u32 sec_addr, u16 sec_cnt) 940 - { 941 - int retval; 942 - unsigned int lun = SCSI_LUN(srb); 943 - int i; 944 - 945 - if (!chip->rw_card[lun]) 946 - return STATUS_FAIL; 947 - 948 - for (i = 0; i < 3; i++) { 949 - chip->rw_need_retry = 0; 950 - 951 - retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt); 952 - if (retval != STATUS_SUCCESS) { 953 - if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) { 954 - rtsx_release_chip(chip); 955 - return STATUS_FAIL; 956 - } 957 - if (detect_card_cd(chip, chip->cur_card) != 958 - STATUS_SUCCESS) { 959 - return STATUS_FAIL; 960 - } 961 - 962 - if (!chip->rw_need_retry) { 963 - dev_dbg(rtsx_dev(chip), "RW fail, but no need to retry\n"); 964 - break; 965 - } 966 - } else { 967 - chip->rw_need_retry = 0; 968 - break; 969 - } 970 - 971 - dev_dbg(rtsx_dev(chip), "Retry RW, (i = %d)\n", i); 972 - } 973 - 974 - return retval; 975 - } 976 - 977 - int card_share_mode(struct rtsx_chip *chip, int card) 978 - { 979 - int retval; 980 - u8 mask, value; 981 - 982 - if (CHECK_PID(chip, 0x5208)) { 983 - mask = CARD_SHARE_MASK; 984 - if (card == SD_CARD) 985 - value = CARD_SHARE_48_SD; 986 - else if (card == MS_CARD) 987 - value = CARD_SHARE_48_MS; 988 - else if (card == XD_CARD) 989 - value = CARD_SHARE_48_XD; 990 - else 991 - return STATUS_FAIL; 992 - 993 - } else if (CHECK_PID(chip, 0x5288)) { 994 - mask = 0x03; 995 - if (card == SD_CARD) 996 - value = CARD_SHARE_BAROSSA_SD; 997 - else if (card == MS_CARD) 998 - value = CARD_SHARE_BAROSSA_MS; 999 - else if (card == XD_CARD) 1000 - value = CARD_SHARE_BAROSSA_XD; 1001 - else 1002 - return STATUS_FAIL; 1003 - 1004 - } else { 1005 - return STATUS_FAIL; 1006 - } 1007 - 1008 - retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value); 1009 - if (retval) 1010 - return retval; 1011 - 1012 - return STATUS_SUCCESS; 1013 - } 1014 - 1015 - int select_card(struct rtsx_chip *chip, int card) 1016 - { 1017 - int retval; 1018 - 1019 - if (chip->cur_card != card) { 1020 - u8 mod; 1021 - 1022 - if (card == SD_CARD) 1023 - mod = SD_MOD_SEL; 1024 - else if (card == MS_CARD) 1025 - mod = MS_MOD_SEL; 1026 - else if (card == XD_CARD) 1027 - mod = XD_MOD_SEL; 1028 - else if (card == SPI_CARD) 1029 - mod = SPI_MOD_SEL; 1030 - else 1031 - return STATUS_FAIL; 1032 - 1033 - retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod); 1034 - if (retval) 1035 - return retval; 1036 - chip->cur_card = card; 1037 - 1038 - retval = card_share_mode(chip, card); 1039 - if (retval != STATUS_SUCCESS) 1040 - return STATUS_FAIL; 1041 - } 1042 - 1043 - return STATUS_SUCCESS; 1044 - } 1045 - 1046 - void toggle_gpio(struct rtsx_chip *chip, u8 gpio) 1047 - { 1048 - u8 temp_reg; 1049 - 1050 - rtsx_read_register(chip, CARD_GPIO, &temp_reg); 1051 - temp_reg ^= (0x01 << gpio); 1052 - rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg); 1053 - } 1054 - 1055 - void turn_on_led(struct rtsx_chip *chip, u8 gpio) 1056 - { 1057 - if (CHECK_PID(chip, 0x5288)) 1058 - rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 1059 - (u8)(1 << gpio)); 1060 - else 1061 - rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); 1062 - } 1063 - 1064 - void turn_off_led(struct rtsx_chip *chip, u8 gpio) 1065 - { 1066 - if (CHECK_PID(chip, 0x5288)) 1067 - rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); 1068 - else 1069 - rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 1070 - (u8)(1 << gpio)); 1071 - } 1072 - 1073 - int detect_card_cd(struct rtsx_chip *chip, int card) 1074 - { 1075 - u32 card_cd, status; 1076 - 1077 - if (card == SD_CARD) { 1078 - card_cd = SD_EXIST; 1079 - } else if (card == MS_CARD) { 1080 - card_cd = MS_EXIST; 1081 - } else if (card == XD_CARD) { 1082 - card_cd = XD_EXIST; 1083 - } else { 1084 - dev_dbg(rtsx_dev(chip), "Wrong card type: 0x%x\n", card); 1085 - return STATUS_FAIL; 1086 - } 1087 - 1088 - status = rtsx_readl(chip, RTSX_BIPR); 1089 - if (!(status & card_cd)) 1090 - return STATUS_FAIL; 1091 - 1092 - return STATUS_SUCCESS; 1093 - } 1094 - 1095 - int check_card_exist(struct rtsx_chip *chip, unsigned int lun) 1096 - { 1097 - if (chip->card_exist & chip->lun2card[lun]) 1098 - return 1; 1099 - 1100 - return 0; 1101 - } 1102 - 1103 - int check_card_ready(struct rtsx_chip *chip, unsigned int lun) 1104 - { 1105 - if (chip->card_ready & chip->lun2card[lun]) 1106 - return 1; 1107 - 1108 - return 0; 1109 - } 1110 - 1111 - int check_card_wp(struct rtsx_chip *chip, unsigned int lun) 1112 - { 1113 - if (chip->card_wp & chip->lun2card[lun]) 1114 - return 1; 1115 - 1116 - return 0; 1117 - } 1118 - 1119 - u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun) 1120 - { 1121 - if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) 1122 - return (u8)XD_CARD; 1123 - else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) 1124 - return (u8)SD_CARD; 1125 - else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) 1126 - return (u8)MS_CARD; 1127 - 1128 - return 0; 1129 - } 1130 - 1131 - void eject_card(struct rtsx_chip *chip, unsigned int lun) 1132 - { 1133 - do_remaining_work(chip); 1134 - 1135 - if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) { 1136 - release_sd_card(chip); 1137 - chip->card_ejected |= SD_CARD; 1138 - chip->card_ready &= ~SD_CARD; 1139 - chip->capacity[lun] = 0; 1140 - } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) { 1141 - release_xd_card(chip); 1142 - chip->card_ejected |= XD_CARD; 1143 - chip->card_ready &= ~XD_CARD; 1144 - chip->capacity[lun] = 0; 1145 - } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) { 1146 - release_ms_card(chip); 1147 - chip->card_ejected |= MS_CARD; 1148 - chip->card_ready &= ~MS_CARD; 1149 - chip->capacity[lun] = 0; 1150 - } 1151 - }
-1087
drivers/staging/rts5208/rtsx_card.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_CARD_H 13 - #define __REALTEK_RTSX_CARD_H 14 - 15 - #include "rtsx.h" 16 - #include "rtsx_chip.h" 17 - #include "rtsx_transport.h" 18 - #include "sd.h" 19 - 20 - #define SSC_POWER_DOWN 0x01 21 - #define SD_OC_POWER_DOWN 0x02 22 - #define MS_OC_POWER_DOWN 0x04 23 - #define ALL_POWER_DOWN 0x07 24 - #define OC_POWER_DOWN 0x06 25 - 26 - #define PMOS_STRG_MASK 0x10 27 - #define PMOS_STRG_800mA 0x10 28 - #define PMOS_STRG_400mA 0x00 29 - 30 - #define POWER_OFF 0x03 31 - #define PARTIAL_POWER_ON 0x01 32 - #define POWER_ON 0x00 33 - 34 - #define MS_POWER_OFF 0x0C 35 - #define MS_PARTIAL_POWER_ON 0x04 36 - #define MS_POWER_ON 0x00 37 - #define MS_POWER_MASK 0x0C 38 - 39 - #define SD_POWER_OFF 0x03 40 - #define SD_PARTIAL_POWER_ON 0x01 41 - #define SD_POWER_ON 0x00 42 - #define SD_POWER_MASK 0x03 43 - 44 - #define XD_OUTPUT_EN 0x02 45 - #define SD_OUTPUT_EN 0x04 46 - #define MS_OUTPUT_EN 0x08 47 - #define SPI_OUTPUT_EN 0x10 48 - 49 - #define CLK_LOW_FREQ 0x01 50 - 51 - #define CLK_DIV_1 0x01 52 - #define CLK_DIV_2 0x02 53 - #define CLK_DIV_4 0x03 54 - #define CLK_DIV_8 0x04 55 - 56 - #define SSC_80 0 57 - #define SSC_100 1 58 - #define SSC_120 2 59 - #define SSC_150 3 60 - #define SSC_200 4 61 - 62 - #define XD_CLK_EN 0x02 63 - #define SD_CLK_EN 0x04 64 - #define MS_CLK_EN 0x08 65 - #define SPI_CLK_EN 0x10 66 - 67 - #define XD_MOD_SEL 1 68 - #define SD_MOD_SEL 2 69 - #define MS_MOD_SEL 3 70 - #define SPI_MOD_SEL 4 71 - 72 - #define CHANGE_CLK 0x01 73 - 74 - #define SD_CRC7_ERR 0x80 75 - #define SD_CRC16_ERR 0x40 76 - #define SD_CRC_WRITE_ERR 0x20 77 - #define SD_CRC_WRITE_ERR_MASK 0x1C 78 - #define GET_CRC_TIME_OUT 0x02 79 - #define SD_TUNING_COMPARE_ERR 0x01 80 - 81 - #define SD_RSP_80CLK_TIMEOUT 0x01 82 - 83 - #define SD_CLK_TOGGLE_EN 0x80 84 - #define SD_CLK_FORCE_STOP 0x40 85 - #define SD_DAT3_STATUS 0x10 86 - #define SD_DAT2_STATUS 0x08 87 - #define SD_DAT1_STATUS 0x04 88 - #define SD_DAT0_STATUS 0x02 89 - #define SD_CMD_STATUS 0x01 90 - 91 - #define SD_IO_USING_1V8 0x80 92 - #define SD_IO_USING_3V3 0x7F 93 - #define TYPE_A_DRIVING 0x00 94 - #define TYPE_B_DRIVING 0x01 95 - #define TYPE_C_DRIVING 0x02 96 - #define TYPE_D_DRIVING 0x03 97 - 98 - #define DDR_FIX_RX_DAT 0x00 99 - #define DDR_VAR_RX_DAT 0x80 100 - #define DDR_FIX_RX_DAT_EDGE 0x00 101 - #define DDR_FIX_RX_DAT_14_DELAY 0x40 102 - #define DDR_FIX_RX_CMD 0x00 103 - #define DDR_VAR_RX_CMD 0x20 104 - #define DDR_FIX_RX_CMD_POS_EDGE 0x00 105 - #define DDR_FIX_RX_CMD_14_DELAY 0x10 106 - #define SD20_RX_POS_EDGE 0x00 107 - #define SD20_RX_14_DELAY 0x08 108 - #define SD20_RX_SEL_MASK 0x08 109 - 110 - #define DDR_FIX_TX_CMD_DAT 0x00 111 - #define DDR_VAR_TX_CMD_DAT 0x80 112 - #define DDR_FIX_TX_DAT_14_TSU 0x00 113 - #define DDR_FIX_TX_DAT_12_TSU 0x40 114 - #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 115 - #define DDR_FIX_TX_CMD_14_AHEAD 0x20 116 - #define SD20_TX_NEG_EDGE 0x00 117 - #define SD20_TX_14_AHEAD 0x10 118 - #define SD20_TX_SEL_MASK 0x10 119 - #define DDR_VAR_SDCLK_POL_SWAP 0x01 120 - 121 - #define SD_TRANSFER_START 0x80 122 - #define SD_TRANSFER_END 0x40 123 - #define SD_STAT_IDLE 0x20 124 - #define SD_TRANSFER_ERR 0x10 125 - #define SD_TM_NORMAL_WRITE 0x00 126 - #define SD_TM_AUTO_WRITE_3 0x01 127 - #define SD_TM_AUTO_WRITE_4 0x02 128 - #define SD_TM_AUTO_READ_3 0x05 129 - #define SD_TM_AUTO_READ_4 0x06 130 - #define SD_TM_CMD_RSP 0x08 131 - #define SD_TM_AUTO_WRITE_1 0x09 132 - #define SD_TM_AUTO_WRITE_2 0x0A 133 - #define SD_TM_NORMAL_READ 0x0C 134 - #define SD_TM_AUTO_READ_1 0x0D 135 - #define SD_TM_AUTO_READ_2 0x0E 136 - #define SD_TM_AUTO_TUNING 0x0F 137 - 138 - #define PHASE_CHANGE 0x80 139 - #define PHASE_NOT_RESET 0x40 140 - 141 - #define DCMPS_CHANGE 0x80 142 - #define DCMPS_CHANGE_DONE 0x40 143 - #define DCMPS_ERROR 0x20 144 - #define DCMPS_CURRENT_PHASE 0x1F 145 - 146 - #define SD_CLK_DIVIDE_0 0x00 147 - #define SD_CLK_DIVIDE_256 0xC0 148 - #define SD_CLK_DIVIDE_128 0x80 149 - #define SD_BUS_WIDTH_1 0x00 150 - #define SD_BUS_WIDTH_4 0x01 151 - #define SD_BUS_WIDTH_8 0x02 152 - #define SD_ASYNC_FIFO_NOT_RST 0x10 153 - #define SD_20_MODE 0x00 154 - #define SD_DDR_MODE 0x04 155 - #define SD_30_MODE 0x08 156 - 157 - #define SD_CLK_DIVIDE_MASK 0xC0 158 - 159 - #define SD_CMD_IDLE 0x80 160 - 161 - #define SD_DATA_IDLE 0x80 162 - 163 - #define DCM_RESET 0x08 164 - #define DCM_LOCKED 0x04 165 - #define DCM_208M 0x00 166 - #define DCM_TX 0x01 167 - #define DCM_RX 0x02 168 - 169 - #define DRP_START 0x80 170 - #define DRP_DONE 0x40 171 - 172 - #define DRP_WRITE 0x80 173 - #define DRP_READ 0x00 174 - #define DCM_WRITE_ADDRESS_50 0x50 175 - #define DCM_WRITE_ADDRESS_51 0x51 176 - #define DCM_READ_ADDRESS_00 0x00 177 - #define DCM_READ_ADDRESS_51 0x51 178 - 179 - #define SD_CALCULATE_CRC7 0x00 180 - #define SD_NO_CALCULATE_CRC7 0x80 181 - #define SD_CHECK_CRC16 0x00 182 - #define SD_NO_CHECK_CRC16 0x40 183 - #define SD_NO_CHECK_WAIT_CRC_TO 0x20 184 - #define SD_WAIT_BUSY_END 0x08 185 - #define SD_NO_WAIT_BUSY_END 0x00 186 - #define SD_CHECK_CRC7 0x00 187 - #define SD_NO_CHECK_CRC7 0x04 188 - #define SD_RSP_LEN_0 0x00 189 - #define SD_RSP_LEN_6 0x01 190 - #define SD_RSP_LEN_17 0x02 191 - #define SD_RSP_TYPE_R0 0x04 192 - #define SD_RSP_TYPE_R1 0x01 193 - #define SD_RSP_TYPE_R1b 0x09 194 - #define SD_RSP_TYPE_R2 0x02 195 - #define SD_RSP_TYPE_R3 0x05 196 - #define SD_RSP_TYPE_R4 0x05 197 - #define SD_RSP_TYPE_R5 0x01 198 - #define SD_RSP_TYPE_R6 0x01 199 - #define SD_RSP_TYPE_R7 0x01 200 - 201 - #define SD_RSP_80CLK_TIMEOUT_EN 0x01 202 - 203 - #define SAMPLE_TIME_RISING 0x00 204 - #define SAMPLE_TIME_FALLING 0x80 205 - #define PUSH_TIME_DEFAULT 0x00 206 - #define PUSH_TIME_ODD 0x40 207 - #define NO_EXTEND_TOGGLE 0x00 208 - #define EXTEND_TOGGLE_CHK 0x20 209 - #define MS_BUS_WIDTH_1 0x00 210 - #define MS_BUS_WIDTH_4 0x10 211 - #define MS_BUS_WIDTH_8 0x18 212 - #define MS_2K_SECTOR_MODE 0x04 213 - #define MS_512_SECTOR_MODE 0x00 214 - #define MS_TOGGLE_TIMEOUT_EN 0x00 215 - #define MS_TOGGLE_TIMEOUT_DISEN 0x01 216 - #define MS_NO_CHECK_INT 0x02 217 - 218 - #define WAIT_INT 0x80 219 - #define NO_WAIT_INT 0x00 220 - #define NO_AUTO_READ_INT_REG 0x00 221 - #define AUTO_READ_INT_REG 0x40 222 - #define MS_CRC16_ERR 0x20 223 - #define MS_RDY_TIMEOUT 0x10 224 - #define MS_INT_CMDNK 0x08 225 - #define MS_INT_BREQ 0x04 226 - #define MS_INT_ERR 0x02 227 - #define MS_INT_CED 0x01 228 - 229 - #define MS_TRANSFER_START 0x80 230 - #define MS_TRANSFER_END 0x40 231 - #define MS_TRANSFER_ERR 0x20 232 - #define MS_BS_STATE 0x10 233 - #define MS_TM_READ_BYTES 0x00 234 - #define MS_TM_NORMAL_READ 0x01 235 - #define MS_TM_WRITE_BYTES 0x04 236 - #define MS_TM_NORMAL_WRITE 0x05 237 - #define MS_TM_AUTO_READ 0x08 238 - #define MS_TM_AUTO_WRITE 0x0C 239 - 240 - #define CARD_SHARE_MASK 0x0F 241 - #define CARD_SHARE_MULTI_LUN 0x00 242 - #define CARD_SHARE_NORMAL 0x00 243 - #define CARD_SHARE_48_XD 0x02 244 - #define CARD_SHARE_48_SD 0x04 245 - #define CARD_SHARE_48_MS 0x08 246 - #define CARD_SHARE_BAROSSA_XD 0x00 247 - #define CARD_SHARE_BAROSSA_SD 0x01 248 - #define CARD_SHARE_BAROSSA_MS 0x02 249 - 250 - #define MS_DRIVE_8 0x00 251 - #define MS_DRIVE_4 0x40 252 - #define MS_DRIVE_12 0x80 253 - #define SD_DRIVE_8 0x00 254 - #define SD_DRIVE_4 0x10 255 - #define SD_DRIVE_12 0x20 256 - #define XD_DRIVE_8 0x00 257 - #define XD_DRIVE_4 0x04 258 - #define XD_DRIVE_12 0x08 259 - 260 - #define SPI_STOP 0x01 261 - #define XD_STOP 0x02 262 - #define SD_STOP 0x04 263 - #define MS_STOP 0x08 264 - #define SPI_CLR_ERR 0x10 265 - #define XD_CLR_ERR 0x20 266 - #define SD_CLR_ERR 0x40 267 - #define MS_CLR_ERR 0x80 268 - 269 - #define CRC_FIX_CLK (0x00 << 0) 270 - #define CRC_VAR_CLK0 (0x01 << 0) 271 - #define CRC_VAR_CLK1 (0x02 << 0) 272 - #define SD30_FIX_CLK (0x00 << 2) 273 - #define SD30_VAR_CLK0 (0x01 << 2) 274 - #define SD30_VAR_CLK1 (0x02 << 2) 275 - #define SAMPLE_FIX_CLK (0x00 << 4) 276 - #define SAMPLE_VAR_CLK0 (0x01 << 4) 277 - #define SAMPLE_VAR_CLK1 (0x02 << 4) 278 - 279 - #define SDIO_VER_20 0x80 280 - #define SDIO_VER_10 0x00 281 - #define SDIO_VER_CHG 0x40 282 - #define SDIO_BUS_AUTO_SWITCH 0x10 283 - 284 - #define PINGPONG_BUFFER 0x01 285 - #define RING_BUFFER 0x00 286 - 287 - #define RB_FLUSH 0x80 288 - 289 - #define DMA_DONE_INT_EN 0x80 290 - #define SUSPEND_INT_EN 0x40 291 - #define LINK_RDY_INT_EN 0x20 292 - #define LINK_DOWN_INT_EN 0x10 293 - 294 - #define DMA_DONE_INT 0x80 295 - #define SUSPEND_INT 0x40 296 - #define LINK_RDY_INT 0x20 297 - #define LINK_DOWN_INT 0x10 298 - 299 - #define MRD_ERR_INT_EN 0x40 300 - #define MWR_ERR_INT_EN 0x20 301 - #define SCSI_CMD_INT_EN 0x10 302 - #define TLP_RCV_INT_EN 0x08 303 - #define TLP_TRSMT_INT_EN 0x04 304 - #define MRD_COMPLETE_INT_EN 0x02 305 - #define MWR_COMPLETE_INT_EN 0x01 306 - 307 - #define MRD_ERR_INT 0x40 308 - #define MWR_ERR_INT 0x20 309 - #define SCSI_CMD_INT 0x10 310 - #define TLP_RX_INT 0x08 311 - #define TLP_TX_INT 0x04 312 - #define MRD_COMPLETE_INT 0x02 313 - #define MWR_COMPLETE_INT 0x01 314 - 315 - #define MSG_RX_INT_EN 0x08 316 - #define MRD_RX_INT_EN 0x04 317 - #define MWR_RX_INT_EN 0x02 318 - #define CPLD_RX_INT_EN 0x01 319 - 320 - #define MSG_RX_INT 0x08 321 - #define MRD_RX_INT 0x04 322 - #define MWR_RX_INT 0x02 323 - #define CPLD_RX_INT 0x01 324 - 325 - #define MSG_TX_INT_EN 0x08 326 - #define MRD_TX_INT_EN 0x04 327 - #define MWR_TX_INT_EN 0x02 328 - #define CPLD_TX_INT_EN 0x01 329 - 330 - #define MSG_TX_INT 0x08 331 - #define MRD_TX_INT 0x04 332 - #define MWR_TX_INT 0x02 333 - #define CPLD_TX_INT 0x01 334 - 335 - #define DMA_RST 0x80 336 - #define DMA_BUSY 0x04 337 - #define DMA_DIR_TO_CARD 0x00 338 - #define DMA_DIR_FROM_CARD 0x02 339 - #define DMA_EN 0x01 340 - #define DMA_128 (0 << 4) 341 - #define DMA_256 (1 << 4) 342 - #define DMA_512 (2 << 4) 343 - #define DMA_1024 (3 << 4) 344 - #define DMA_PACK_SIZE_MASK 0x30 345 - 346 - #define XD_PWR_OFF_DELAY0 0x00 347 - #define XD_PWR_OFF_DELAY1 0x02 348 - #define XD_PWR_OFF_DELAY2 0x04 349 - #define XD_PWR_OFF_DELAY3 0x06 350 - #define XD_AUTO_PWR_OFF_EN 0xF7 351 - #define XD_NO_AUTO_PWR_OFF 0x08 352 - 353 - #define XD_TIME_RWN_1 0x00 354 - #define XD_TIME_RWN_STEP 0x20 355 - #define XD_TIME_RW_1 0x00 356 - #define XD_TIME_RW_STEP 0x04 357 - #define XD_TIME_SETUP_1 0x00 358 - #define XD_TIME_SETUP_STEP 0x01 359 - 360 - #define XD_ECC2_UNCORRECTABLE 0x80 361 - #define XD_ECC2_ERROR 0x40 362 - #define XD_ECC1_UNCORRECTABLE 0x20 363 - #define XD_ECC1_ERROR 0x10 364 - #define XD_RDY 0x04 365 - #define XD_CE_EN 0xFD 366 - #define XD_CE_DISEN 0x02 367 - #define XD_WP_EN 0xFE 368 - #define XD_WP_DISEN 0x01 369 - 370 - #define XD_TRANSFER_START 0x80 371 - #define XD_TRANSFER_END 0x40 372 - #define XD_PPB_EMPTY 0x20 373 - #define XD_RESET 0x00 374 - #define XD_ERASE 0x01 375 - #define XD_READ_STATUS 0x02 376 - #define XD_READ_ID 0x03 377 - #define XD_READ_REDUNDANT 0x04 378 - #define XD_READ_PAGES 0x05 379 - #define XD_SET_CMD 0x06 380 - #define XD_NORMAL_READ 0x07 381 - #define XD_WRITE_PAGES 0x08 382 - #define XD_NORMAL_WRITE 0x09 383 - #define XD_WRITE_REDUNDANT 0x0A 384 - #define XD_SET_ADDR 0x0B 385 - 386 - #define XD_PPB_TO_SIE 0x80 387 - #define XD_TO_PPB_ONLY 0x00 388 - #define XD_BA_TRANSFORM 0x40 389 - #define XD_BA_NO_TRANSFORM 0x00 390 - #define XD_NO_CALC_ECC 0x20 391 - #define XD_CALC_ECC 0x00 392 - #define XD_IGNORE_ECC 0x10 393 - #define XD_CHECK_ECC 0x00 394 - #define XD_DIRECT_TO_RB 0x08 395 - #define XD_ADDR_LENGTH_0 0x00 396 - #define XD_ADDR_LENGTH_1 0x01 397 - #define XD_ADDR_LENGTH_2 0x02 398 - #define XD_ADDR_LENGTH_3 0x03 399 - #define XD_ADDR_LENGTH_4 0x04 400 - 401 - #define XD_GPG 0xFF 402 - #define XD_BPG 0x00 403 - 404 - #define XD_GBLK 0xFF 405 - #define XD_LATER_BBLK 0xF0 406 - 407 - #define XD_ECC2_ALL1 0x80 408 - #define XD_ECC1_ALL1 0x40 409 - #define XD_BA2_ALL0 0x20 410 - #define XD_BA1_ALL0 0x10 411 - #define XD_BA1_BA2_EQL 0x04 412 - #define XD_BA2_VALID 0x02 413 - #define XD_BA1_VALID 0x01 414 - 415 - #define XD_PGSTS_ZEROBIT_OVER4 0x00 416 - #define XD_PGSTS_NOT_FF 0x02 417 - #define XD_AUTO_CHK_DATA_STATUS 0x01 418 - 419 - #define RSTB_MODE_DETECT 0x80 420 - #define MODE_OUT_VLD 0x40 421 - #define MODE_OUT_0_NONE 0x00 422 - #define MODE_OUT_10_NONE 0x04 423 - #define MODE_OUT_10_47 0x05 424 - #define MODE_OUT_10_180 0x06 425 - #define MODE_OUT_10_680 0x07 426 - #define MODE_OUT_16_NONE 0x08 427 - #define MODE_OUT_16_47 0x09 428 - #define MODE_OUT_16_180 0x0A 429 - #define MODE_OUT_16_680 0x0B 430 - #define MODE_OUT_NONE_NONE 0x0C 431 - #define MODE_OUT_NONE_47 0x0D 432 - #define MODE_OUT_NONE_180 0x0E 433 - #define MODE_OUT_NONE_680 0x0F 434 - 435 - #define CARD_OC_INT_EN 0x20 436 - #define CARD_DETECT_EN 0x08 437 - 438 - #define MS_DETECT_EN 0x80 439 - #define MS_OCP_INT_EN 0x40 440 - #define MS_OCP_INT_CLR 0x20 441 - #define MS_OC_CLR 0x10 442 - #define SD_DETECT_EN 0x08 443 - #define SD_OCP_INT_EN 0x04 444 - #define SD_OCP_INT_CLR 0x02 445 - #define SD_OC_CLR 0x01 446 - 447 - #define CARD_OCP_DETECT 0x80 448 - #define CARD_OC_NOW 0x08 449 - #define CARD_OC_EVER 0x04 450 - 451 - #define MS_OCP_DETECT 0x80 452 - #define MS_OC_NOW 0x40 453 - #define MS_OC_EVER 0x20 454 - #define SD_OCP_DETECT 0x08 455 - #define SD_OC_NOW 0x04 456 - #define SD_OC_EVER 0x02 457 - 458 - #define CARD_OC_INT_CLR 0x08 459 - #define CARD_OC_CLR 0x02 460 - 461 - #define SD_OCP_GLITCH_MASK 0x07 462 - #define SD_OCP_GLITCH_6_4 0x00 463 - #define SD_OCP_GLITCH_64 0x01 464 - #define SD_OCP_GLITCH_640 0x02 465 - #define SD_OCP_GLITCH_1000 0x03 466 - #define SD_OCP_GLITCH_2000 0x04 467 - #define SD_OCP_GLITCH_4000 0x05 468 - #define SD_OCP_GLITCH_8000 0x06 469 - #define SD_OCP_GLITCH_10000 0x07 470 - 471 - #define MS_OCP_GLITCH_MASK 0x70 472 - #define MS_OCP_GLITCH_6_4 (0x00 << 4) 473 - #define MS_OCP_GLITCH_64 (0x01 << 4) 474 - #define MS_OCP_GLITCH_640 (0x02 << 4) 475 - #define MS_OCP_GLITCH_1000 (0x03 << 4) 476 - #define MS_OCP_GLITCH_2000 (0x04 << 4) 477 - #define MS_OCP_GLITCH_4000 (0x05 << 4) 478 - #define MS_OCP_GLITCH_8000 (0x06 << 4) 479 - #define MS_OCP_GLITCH_10000 (0x07 << 4) 480 - 481 - #define OCP_TIME_60 0x00 482 - #define OCP_TIME_100 (0x01 << 3) 483 - #define OCP_TIME_200 (0x02 << 3) 484 - #define OCP_TIME_400 (0x03 << 3) 485 - #define OCP_TIME_600 (0x04 << 3) 486 - #define OCP_TIME_800 (0x05 << 3) 487 - #define OCP_TIME_1100 (0x06 << 3) 488 - #define OCP_TIME_MASK 0x38 489 - 490 - #define MS_OCP_TIME_60 0x00 491 - #define MS_OCP_TIME_100 (0x01 << 4) 492 - #define MS_OCP_TIME_200 (0x02 << 4) 493 - #define MS_OCP_TIME_400 (0x03 << 4) 494 - #define MS_OCP_TIME_600 (0x04 << 4) 495 - #define MS_OCP_TIME_800 (0x05 << 4) 496 - #define MS_OCP_TIME_1100 (0x06 << 4) 497 - #define MS_OCP_TIME_MASK 0x70 498 - 499 - #define SD_OCP_TIME_60 0x00 500 - #define SD_OCP_TIME_100 0x01 501 - #define SD_OCP_TIME_200 0x02 502 - #define SD_OCP_TIME_400 0x03 503 - #define SD_OCP_TIME_600 0x04 504 - #define SD_OCP_TIME_800 0x05 505 - #define SD_OCP_TIME_1100 0x06 506 - #define SD_OCP_TIME_MASK 0x07 507 - 508 - #define OCP_THD_315_417 0x00 509 - #define OCP_THD_283_783 (0x01 << 6) 510 - #define OCP_THD_244_946 (0x02 << 6) 511 - #define OCP_THD_191_1080 (0x03 << 6) 512 - #define OCP_THD_MASK 0xC0 513 - 514 - #define MS_OCP_THD_450 0x00 515 - #define MS_OCP_THD_550 (0x01 << 4) 516 - #define MS_OCP_THD_650 (0x02 << 4) 517 - #define MS_OCP_THD_750 (0x03 << 4) 518 - #define MS_OCP_THD_850 (0x04 << 4) 519 - #define MS_OCP_THD_950 (0x05 << 4) 520 - #define MS_OCP_THD_1050 (0x06 << 4) 521 - #define MS_OCP_THD_1150 (0x07 << 4) 522 - #define MS_OCP_THD_MASK 0x70 523 - 524 - #define SD_OCP_THD_450 0x00 525 - #define SD_OCP_THD_550 0x01 526 - #define SD_OCP_THD_650 0x02 527 - #define SD_OCP_THD_750 0x03 528 - #define SD_OCP_THD_850 0x04 529 - #define SD_OCP_THD_950 0x05 530 - #define SD_OCP_THD_1050 0x06 531 - #define SD_OCP_THD_1150 0x07 532 - #define SD_OCP_THD_MASK 0x07 533 - 534 - #define FPGA_MS_PULL_CTL_EN 0xEF 535 - #define FPGA_SD_PULL_CTL_EN 0xF7 536 - #define FPGA_XD_PULL_CTL_EN1 0xFE 537 - #define FPGA_XD_PULL_CTL_EN2 0xFD 538 - #define FPGA_XD_PULL_CTL_EN3 0xFB 539 - 540 - #define FPGA_MS_PULL_CTL_BIT 0x10 541 - #define FPGA_SD_PULL_CTL_BIT 0x08 542 - 543 - #define BLINK_EN 0x08 544 - #define LED_GPIO0 (0 << 4) 545 - #define LED_GPIO1 (1 << 4) 546 - #define LED_GPIO2 (2 << 4) 547 - 548 - #define SDIO_BUS_CTRL 0x01 549 - #define SDIO_CD_CTRL 0x02 550 - 551 - #define SSC_RSTB 0x80 552 - #define SSC_8X_EN 0x40 553 - #define SSC_FIX_FRAC 0x20 554 - #define SSC_SEL_1M 0x00 555 - #define SSC_SEL_2M 0x08 556 - #define SSC_SEL_4M 0x10 557 - #define SSC_SEL_8M 0x18 558 - 559 - #define SSC_DEPTH_MASK 0x07 560 - #define SSC_DEPTH_DISALBE 0x00 561 - #define SSC_DEPTH_4M 0x01 562 - #define SSC_DEPTH_2M 0x02 563 - #define SSC_DEPTH_1M 0x03 564 - #define SSC_DEPTH_512K 0x04 565 - #define SSC_DEPTH_256K 0x05 566 - #define SSC_DEPTH_128K 0x06 567 - #define SSC_DEPTH_64K 0x07 568 - 569 - #define XD_D3_NP 0x00 570 - #define XD_D3_PD (0x01 << 6) 571 - #define XD_D3_PU (0x02 << 6) 572 - #define XD_D2_NP 0x00 573 - #define XD_D2_PD (0x01 << 4) 574 - #define XD_D2_PU (0x02 << 4) 575 - #define XD_D1_NP 0x00 576 - #define XD_D1_PD (0x01 << 2) 577 - #define XD_D1_PU (0x02 << 2) 578 - #define XD_D0_NP 0x00 579 - #define XD_D0_PD 0x01 580 - #define XD_D0_PU 0x02 581 - 582 - #define SD_D7_NP 0x00 583 - #define SD_D7_PD (0x01 << 4) 584 - #define SD_DAT7_PU (0x02 << 4) 585 - #define SD_CLK_NP 0x00 586 - #define SD_CLK_PD (0x01 << 2) 587 - #define SD_CLK_PU (0x02 << 2) 588 - #define SD_D5_NP 0x00 589 - #define SD_D5_PD 0x01 590 - #define SD_D5_PU 0x02 591 - 592 - #define MS_D1_NP 0x00 593 - #define MS_D1_PD (0x01 << 6) 594 - #define MS_D1_PU (0x02 << 6) 595 - #define MS_D2_NP 0x00 596 - #define MS_D2_PD (0x01 << 4) 597 - #define MS_D2_PU (0x02 << 4) 598 - #define MS_CLK_NP 0x00 599 - #define MS_CLK_PD (0x01 << 2) 600 - #define MS_CLK_PU (0x02 << 2) 601 - #define MS_D6_NP 0x00 602 - #define MS_D6_PD 0x01 603 - #define MS_D6_PU 0x02 604 - 605 - #define XD_D7_NP 0x00 606 - #define XD_D7_PD (0x01 << 6) 607 - #define XD_D7_PU (0x02 << 6) 608 - #define XD_D6_NP 0x00 609 - #define XD_D6_PD (0x01 << 4) 610 - #define XD_D6_PU (0x02 << 4) 611 - #define XD_D5_NP 0x00 612 - #define XD_D5_PD (0x01 << 2) 613 - #define XD_D5_PU (0x02 << 2) 614 - #define XD_D4_NP 0x00 615 - #define XD_D4_PD 0x01 616 - #define XD_D4_PU 0x02 617 - 618 - #define SD_D6_NP 0x00 619 - #define SD_D6_PD (0x01 << 6) 620 - #define SD_D6_PU (0x02 << 6) 621 - #define SD_D0_NP 0x00 622 - #define SD_D0_PD (0x01 << 4) 623 - #define SD_D0_PU (0x02 << 4) 624 - #define SD_D1_NP 0x00 625 - #define SD_D1_PD 0x01 626 - #define SD_D1_PU 0x02 627 - 628 - #define MS_D3_NP 0x00 629 - #define MS_D3_PD (0x01 << 6) 630 - #define MS_D3_PU (0x02 << 6) 631 - #define MS_D0_NP 0x00 632 - #define MS_D0_PD (0x01 << 4) 633 - #define MS_D0_PU (0x02 << 4) 634 - #define MS_BS_NP 0x00 635 - #define MS_BS_PD (0x01 << 2) 636 - #define MS_BS_PU (0x02 << 2) 637 - 638 - #define XD_WP_NP 0x00 639 - #define XD_WP_PD (0x01 << 6) 640 - #define XD_WP_PU (0x02 << 6) 641 - #define XD_CE_NP 0x00 642 - #define XD_CE_PD (0x01 << 3) 643 - #define XD_CE_PU (0x02 << 3) 644 - #define XD_CLE_NP 0x00 645 - #define XD_CLE_PD (0x01 << 1) 646 - #define XD_CLE_PU (0x02 << 1) 647 - #define XD_CD_PD 0x00 648 - #define XD_CD_PU 0x01 649 - 650 - #define SD_D4_NP 0x00 651 - #define SD_D4_PD (0x01 << 6) 652 - #define SD_D4_PU (0x02 << 6) 653 - 654 - #define MS_D7_NP 0x00 655 - #define MS_D7_PD (0x01 << 6) 656 - #define MS_D7_PU (0x02 << 6) 657 - 658 - #define XD_RDY_NP 0x00 659 - #define XD_RDY_PD (0x01 << 6) 660 - #define XD_RDY_PU (0x02 << 6) 661 - #define XD_WE_NP 0x00 662 - #define XD_WE_PD (0x01 << 4) 663 - #define XD_WE_PU (0x02 << 4) 664 - #define XD_RE_NP 0x00 665 - #define XD_RE_PD (0x01 << 2) 666 - #define XD_RE_PU (0x02 << 2) 667 - #define XD_ALE_NP 0x00 668 - #define XD_ALE_PD 0x01 669 - #define XD_ALE_PU 0x02 670 - 671 - #define SD_D3_NP 0x00 672 - #define SD_D3_PD (0x01 << 4) 673 - #define SD_D3_PU (0x02 << 4) 674 - #define SD_D2_NP 0x00 675 - #define SD_D2_PD (0x01 << 2) 676 - #define SD_D2_PU (0x02 << 2) 677 - 678 - #define MS_INS_PD 0x00 679 - #define MS_INS_PU (0x01 << 7) 680 - #define SD_WP_NP 0x00 681 - #define SD_WP_PD (0x01 << 5) 682 - #define SD_WP_PU (0x02 << 5) 683 - #define SD_CD_PD 0x00 684 - #define SD_CD_PU (0x01 << 4) 685 - #define SD_CMD_NP 0x00 686 - #define SD_CMD_PD (0x01 << 2) 687 - #define SD_CMD_PU (0x02 << 2) 688 - 689 - #define MS_D5_NP 0x00 690 - #define MS_D5_PD (0x01 << 2) 691 - #define MS_D5_PU (0x02 << 2) 692 - #define MS_D4_NP 0x00 693 - #define MS_D4_PD 0x01 694 - #define MS_D4_PU 0x02 695 - 696 - #define FORCE_PM_CLOCK 0x10 697 - #define EN_CLOCK_PM 0x01 698 - 699 - #define HOST_ENTER_S3 0x02 700 - #define HOST_ENTER_S1 0x01 701 - 702 - #define AUX_PWR_DETECTED 0x01 703 - 704 - #define PHY_DEBUG_MODE 0x01 705 - 706 - #define SPI_COMMAND_BIT_8 0xE0 707 - #define SPI_ADDRESS_BIT_24 0x17 708 - #define SPI_ADDRESS_BIT_32 0x1F 709 - 710 - #define SPI_TRANSFER0_START 0x80 711 - #define SPI_TRANSFER0_END 0x40 712 - #define SPI_C_MODE0 0x00 713 - #define SPI_CA_MODE0 0x01 714 - #define SPI_CDO_MODE0 0x02 715 - #define SPI_CDI_MODE0 0x03 716 - #define SPI_CADO_MODE0 0x04 717 - #define SPI_CADI_MODE0 0x05 718 - #define SPI_POLLING_MODE0 0x06 719 - 720 - #define SPI_TRANSFER1_START 0x80 721 - #define SPI_TRANSFER1_END 0x40 722 - #define SPI_DO_MODE1 0x00 723 - #define SPI_DI_MODE1 0x01 724 - 725 - #define CS_POLARITY_HIGH 0x40 726 - #define CS_POLARITY_LOW 0x00 727 - #define DTO_MSB_FIRST 0x00 728 - #define DTO_LSB_FIRST 0x20 729 - #define SPI_MASTER 0x00 730 - #define SPI_SLAVE 0x10 731 - #define SPI_MODE0 0x00 732 - #define SPI_MODE1 0x04 733 - #define SPI_MODE2 0x08 734 - #define SPI_MODE3 0x0C 735 - #define SPI_MANUAL 0x00 736 - #define SPI_HALF_AUTO 0x01 737 - #define SPI_AUTO 0x02 738 - #define SPI_EEPROM_AUTO 0x03 739 - 740 - #define EDO_TIMING_MASK 0x03 741 - #define SAMPLE_RISING 0x00 742 - #define SAMPLE_DELAY_HALF 0x01 743 - #define SAMPLE_DELAY_ONE 0x02 744 - #define SAPMLE_DELAY_ONE_HALF 0x03 745 - #define TCS_MASK 0x0C 746 - 747 - #define NOT_BYPASS_SD 0x02 748 - #define DISABLE_SDIO_FUNC 0x04 749 - #define SELECT_1LUN 0x08 750 - 751 - #define PWR_GATE_EN 0x01 752 - #define LDO3318_PWR_MASK 0x06 753 - #define LDO_ON 0x00 754 - #define LDO_SUSPEND 0x04 755 - #define LDO_OFF 0x06 756 - 757 - #define SD_CFG1 0xFDA0 758 - #define SD_CFG2 0xFDA1 759 - #define SD_CFG3 0xFDA2 760 - #define SD_STAT1 0xFDA3 761 - #define SD_STAT2 0xFDA4 762 - #define SD_BUS_STAT 0xFDA5 763 - #define SD_PAD_CTL 0xFDA6 764 - #define SD_SAMPLE_POINT_CTL 0xFDA7 765 - #define SD_PUSH_POINT_CTL 0xFDA8 766 - #define SD_CMD0 0xFDA9 767 - #define SD_CMD1 0xFDAA 768 - #define SD_CMD2 0xFDAB 769 - #define SD_CMD3 0xFDAC 770 - #define SD_CMD4 0xFDAD 771 - #define SD_CMD5 0xFDAE 772 - #define SD_BYTE_CNT_L 0xFDAF 773 - #define SD_BYTE_CNT_H 0xFDB0 774 - #define SD_BLOCK_CNT_L 0xFDB1 775 - #define SD_BLOCK_CNT_H 0xFDB2 776 - #define SD_TRANSFER 0xFDB3 777 - #define SD_CMD_STATE 0xFDB5 778 - #define SD_DATA_STATE 0xFDB6 779 - 780 - #define DCM_DRP_CTL 0xFC23 781 - #define DCM_DRP_TRIG 0xFC24 782 - #define DCM_DRP_CFG 0xFC25 783 - #define DCM_DRP_WR_DATA_L 0xFC26 784 - #define DCM_DRP_WR_DATA_H 0xFC27 785 - #define DCM_DRP_RD_DATA_L 0xFC28 786 - #define DCM_DRP_RD_DATA_H 0xFC29 787 - #define SD_VPCLK0_CTL 0xFC2A 788 - #define SD_VPCLK1_CTL 0xFC2B 789 - #define SD_DCMPS0_CTL 0xFC2C 790 - #define SD_DCMPS1_CTL 0xFC2D 791 - #define SD_VPTX_CTL SD_VPCLK0_CTL 792 - #define SD_VPRX_CTL SD_VPCLK1_CTL 793 - #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL 794 - #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL 795 - 796 - #define CARD_CLK_SOURCE 0xFC2E 797 - 798 - #define CARD_PWR_CTL 0xFD50 799 - #define CARD_CLK_SWITCH 0xFD51 800 - #define CARD_SHARE_MODE 0xFD52 801 - #define CARD_DRIVE_SEL 0xFD53 802 - #define CARD_STOP 0xFD54 803 - #define CARD_OE 0xFD55 804 - #define CARD_AUTO_BLINK 0xFD56 805 - #define CARD_GPIO_DIR 0xFD57 806 - #define CARD_GPIO 0xFD58 807 - 808 - #define CARD_DATA_SOURCE 0xFD5B 809 - #define CARD_SELECT 0xFD5C 810 - #define SD30_DRIVE_SEL 0xFD5E 811 - 812 - #define CARD_CLK_EN 0xFD69 813 - 814 - #define SDIO_CTRL 0xFD6B 815 - 816 - #define FPDCTL 0xFC00 817 - #define PDINFO 0xFC01 818 - 819 - #define CLK_CTL 0xFC02 820 - #define CLK_DIV 0xFC03 821 - #define CLK_SEL 0xFC04 822 - 823 - #define SSC_DIV_N_0 0xFC0F 824 - #define SSC_DIV_N_1 0xFC10 825 - 826 - #define RCCTL 0xFC14 827 - 828 - #define FPGA_PULL_CTL 0xFC1D 829 - 830 - #define CARD_PULL_CTL1 0xFD60 831 - #define CARD_PULL_CTL2 0xFD61 832 - #define CARD_PULL_CTL3 0xFD62 833 - #define CARD_PULL_CTL4 0xFD63 834 - #define CARD_PULL_CTL5 0xFD64 835 - #define CARD_PULL_CTL6 0xFD65 836 - 837 - #define IRQEN0 0xFE20 838 - #define IRQSTAT0 0xFE21 839 - #define IRQEN1 0xFE22 840 - #define IRQSTAT1 0xFE23 841 - #define TLPRIEN 0xFE24 842 - #define TLPRISTAT 0xFE25 843 - #define TLPTIEN 0xFE26 844 - #define TLPTISTAT 0xFE27 845 - #define DMATC0 0xFE28 846 - #define DMATC1 0xFE29 847 - #define DMATC2 0xFE2A 848 - #define DMATC3 0xFE2B 849 - #define DMACTL 0xFE2C 850 - #define BCTL 0xFE2D 851 - #define RBBC0 0xFE2E 852 - #define RBBC1 0xFE2F 853 - #define RBDAT 0xFE30 854 - #define RBCTL 0xFE34 855 - #define CFGADDR0 0xFE35 856 - #define CFGADDR1 0xFE36 857 - #define CFGDATA0 0xFE37 858 - #define CFGDATA1 0xFE38 859 - #define CFGDATA2 0xFE39 860 - #define CFGDATA3 0xFE3A 861 - #define CFGRWCTL 0xFE3B 862 - #define PHYRWCTL 0xFE3C 863 - #define PHYDATA0 0xFE3D 864 - #define PHYDATA1 0xFE3E 865 - #define PHYADDR 0xFE3F 866 - #define MSGRXDATA0 0xFE40 867 - #define MSGRXDATA1 0xFE41 868 - #define MSGRXDATA2 0xFE42 869 - #define MSGRXDATA3 0xFE43 870 - #define MSGTXDATA0 0xFE44 871 - #define MSGTXDATA1 0xFE45 872 - #define MSGTXDATA2 0xFE46 873 - #define MSGTXDATA3 0xFE47 874 - #define MSGTXCTL 0xFE48 875 - #define PETXCFG 0xFE49 876 - 877 - #define CDRESUMECTL 0xFE52 878 - #define WAKE_SEL_CTL 0xFE54 879 - #define PME_FORCE_CTL 0xFE56 880 - #define ASPM_FORCE_CTL 0xFE57 881 - #define PM_CLK_FORCE_CTL 0xFE58 882 - #define PERST_GLITCH_WIDTH 0xFE5C 883 - #define CHANGE_LINK_STATE 0xFE5B 884 - #define RESET_LOAD_REG 0xFE5E 885 - #define HOST_SLEEP_STATE 0xFE60 886 - #define MAIN_PWR_OFF_CTL 0xFE70 /* RTS5208 */ 887 - 888 - #define NFTS_TX_CTRL 0xFE72 889 - 890 - #define PWR_GATE_CTRL 0xFE75 891 - #define PWD_SUSPEND_EN 0xFE76 892 - 893 - #define EFUSE_CONTENT 0xFE5F 894 - 895 - #define XD_INIT 0xFD10 896 - #define XD_DTCTL 0xFD11 897 - #define XD_CTL 0xFD12 898 - #define XD_TRANSFER 0xFD13 899 - #define XD_CFG 0xFD14 900 - #define XD_ADDRESS0 0xFD15 901 - #define XD_ADDRESS1 0xFD16 902 - #define XD_ADDRESS2 0xFD17 903 - #define XD_ADDRESS3 0xFD18 904 - #define XD_ADDRESS4 0xFD19 905 - #define XD_DAT 0xFD1A 906 - #define XD_PAGE_CNT 0xFD1B 907 - #define XD_PAGE_STATUS 0xFD1C 908 - #define XD_BLOCK_STATUS 0xFD1D 909 - #define XD_BLOCK_ADDR1_L 0xFD1E 910 - #define XD_BLOCK_ADDR1_H 0xFD1F 911 - #define XD_BLOCK_ADDR2_L 0xFD20 912 - #define XD_BLOCK_ADDR2_H 0xFD21 913 - #define XD_BYTE_CNT_L 0xFD22 914 - #define XD_BYTE_CNT_H 0xFD23 915 - #define XD_PARITY 0xFD24 916 - #define XD_ECC_BIT1 0xFD25 917 - #define XD_ECC_BYTE1 0xFD26 918 - #define XD_ECC_BIT2 0xFD27 919 - #define XD_ECC_BYTE2 0xFD28 920 - #define XD_RESERVED0 0xFD29 921 - #define XD_RESERVED1 0xFD2A 922 - #define XD_RESERVED2 0xFD2B 923 - #define XD_RESERVED3 0xFD2C 924 - #define XD_CHK_DATA_STATUS 0xFD2D 925 - #define XD_CATCTL 0xFD2E 926 - 927 - #define MS_CFG 0xFD40 928 - #define MS_TPC 0xFD41 929 - #define MS_TRANS_CFG 0xFD42 930 - #define MS_TRANSFER 0xFD43 931 - #define MS_INT_REG 0xFD44 932 - #define MS_BYTE_CNT 0xFD45 933 - #define MS_SECTOR_CNT_L 0xFD46 934 - #define MS_SECTOR_CNT_H 0xFD47 935 - #define MS_DBUS_H 0xFD48 936 - 937 - #define SSC_CTL1 0xFC11 938 - #define SSC_CTL2 0xFC12 939 - 940 - #define OCPCTL 0xFC15 941 - #define OCPSTAT 0xFC16 942 - #define OCPCLR 0xFC17 /* 5208 */ 943 - #define OCPPARA1 0xFC18 944 - #define OCPPARA2 0xFC19 945 - 946 - #define EFUSE_OP 0xFC20 947 - #define EFUSE_CTRL 0xFC21 948 - #define EFUSE_DATA 0xFC22 949 - 950 - #define SPI_COMMAND 0xFD80 951 - #define SPI_ADDR0 0xFD81 952 - #define SPI_ADDR1 0xFD82 953 - #define SPI_ADDR2 0xFD83 954 - #define SPI_ADDR3 0xFD84 955 - #define SPI_CA_NUMBER 0xFD85 956 - #define SPI_LENGTH0 0xFD86 957 - #define SPI_LENGTH1 0xFD87 958 - #define SPI_DATA 0xFD88 959 - #define SPI_DATA_NUMBER 0xFD89 960 - #define SPI_TRANSFER0 0xFD90 961 - #define SPI_TRANSFER1 0xFD91 962 - #define SPI_CONTROL 0xFD92 963 - #define SPI_SIG 0xFD93 964 - #define SPI_TCTL 0xFD94 965 - #define SPI_SLAVE_NUM 0xFD95 966 - #define SPI_CLK_DIVIDER0 0xFD96 967 - #define SPI_CLK_DIVIDER1 0xFD97 968 - 969 - #define SRAM_BASE 0xE600 970 - #define RBUF_BASE 0xF400 971 - #define PPBUF_BASE1 0xF800 972 - #define PPBUF_BASE2 0xFA00 973 - #define IMAGE_FLAG_ADDR0 0xCE80 974 - #define IMAGE_FLAG_ADDR1 0xCE81 975 - 976 - #define READ_OP 1 977 - #define WRITE_OP 2 978 - 979 - #define LCTLR 0x80 980 - 981 - #define POLLING_WAIT_CNT 1 982 - #define IDLE_MAX_COUNT 10 983 - #define SDIO_IDLE_COUNT 10 984 - 985 - #define DEBOUNCE_CNT 5 986 - 987 - void do_remaining_work(struct rtsx_chip *chip); 988 - void try_to_switch_sdio_ctrl(struct rtsx_chip *chip); 989 - void do_reset_sd_card(struct rtsx_chip *chip); 990 - void do_reset_xd_card(struct rtsx_chip *chip); 991 - void do_reset_ms_card(struct rtsx_chip *chip); 992 - void rtsx_power_off_card(struct rtsx_chip *chip); 993 - void rtsx_release_cards(struct rtsx_chip *chip); 994 - void rtsx_reset_cards(struct rtsx_chip *chip); 995 - void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip); 996 - void rtsx_init_cards(struct rtsx_chip *chip); 997 - int switch_ssc_clock(struct rtsx_chip *chip, int clk); 998 - int switch_normal_clock(struct rtsx_chip *chip, int clk); 999 - int enable_card_clock(struct rtsx_chip *chip, u8 card); 1000 - int disable_card_clock(struct rtsx_chip *chip, u8 card); 1001 - int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 1002 - u32 sec_addr, u16 sec_cnt); 1003 - void trans_dma_enable(enum dma_data_direction dir, 1004 - struct rtsx_chip *chip, u32 byte_cnt, u8 pack_size); 1005 - void toggle_gpio(struct rtsx_chip *chip, u8 gpio); 1006 - void turn_on_led(struct rtsx_chip *chip, u8 gpio); 1007 - void turn_off_led(struct rtsx_chip *chip, u8 gpio); 1008 - 1009 - int card_share_mode(struct rtsx_chip *chip, int card); 1010 - int select_card(struct rtsx_chip *chip, int card); 1011 - int detect_card_cd(struct rtsx_chip *chip, int card); 1012 - int check_card_exist(struct rtsx_chip *chip, unsigned int lun); 1013 - int check_card_ready(struct rtsx_chip *chip, unsigned int lun); 1014 - int check_card_wp(struct rtsx_chip *chip, unsigned int lun); 1015 - void eject_card(struct rtsx_chip *chip, unsigned int lun); 1016 - u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun); 1017 - 1018 - static inline u32 get_card_size(struct rtsx_chip *chip, unsigned int lun) 1019 - { 1020 - #ifdef SUPPORT_SD_LOCK 1021 - struct sd_info *sd_card = &chip->sd_card; 1022 - 1023 - if ((get_lun_card(chip, lun) == SD_CARD) && 1024 - (sd_card->sd_lock_status & SD_LOCKED)) 1025 - return 0; 1026 - 1027 - return chip->capacity[lun]; 1028 - #else 1029 - return chip->capacity[lun]; 1030 - #endif 1031 - } 1032 - 1033 - static inline int switch_clock(struct rtsx_chip *chip, int clk) 1034 - { 1035 - int retval = 0; 1036 - 1037 - if (chip->asic_code) 1038 - retval = switch_ssc_clock(chip, clk); 1039 - else 1040 - retval = switch_normal_clock(chip, clk); 1041 - 1042 - return retval; 1043 - } 1044 - 1045 - int card_power_on(struct rtsx_chip *chip, u8 card); 1046 - int card_power_off(struct rtsx_chip *chip, u8 card); 1047 - 1048 - static inline int card_power_off_all(struct rtsx_chip *chip) 1049 - { 1050 - int retval; 1051 - 1052 - retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F); 1053 - if (retval) 1054 - return retval; 1055 - 1056 - return STATUS_SUCCESS; 1057 - } 1058 - 1059 - static inline void rtsx_clear_xd_error(struct rtsx_chip *chip) 1060 - { 1061 - rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, 1062 - XD_STOP | XD_CLR_ERR); 1063 - } 1064 - 1065 - static inline void rtsx_clear_sd_error(struct rtsx_chip *chip) 1066 - { 1067 - rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 1068 - SD_STOP | SD_CLR_ERR); 1069 - } 1070 - 1071 - static inline void rtsx_clear_ms_error(struct rtsx_chip *chip) 1072 - { 1073 - rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 1074 - MS_STOP | MS_CLR_ERR); 1075 - } 1076 - 1077 - static inline void rtsx_clear_spi_error(struct rtsx_chip *chip) 1078 - { 1079 - rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, 1080 - SPI_STOP | SPI_CLR_ERR); 1081 - } 1082 - 1083 - #ifdef SUPPORT_SDIO_ASPM 1084 - void dynamic_configure_sdio_aspm(struct rtsx_chip *chip); 1085 - #endif 1086 - 1087 - #endif /* __REALTEK_RTSX_CARD_H */
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drivers/staging/rts5208/rtsx_chip.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/workqueue.h> 16 - #include <linux/vmalloc.h> 17 - 18 - #include "rtsx.h" 19 - #include "sd.h" 20 - #include "xd.h" 21 - #include "ms.h" 22 - 23 - static void rtsx_calibration(struct rtsx_chip *chip) 24 - { 25 - rtsx_write_phy_register(chip, 0x1B, 0x135E); 26 - wait_timeout(10); 27 - rtsx_write_phy_register(chip, 0x00, 0x0280); 28 - rtsx_write_phy_register(chip, 0x01, 0x7112); 29 - rtsx_write_phy_register(chip, 0x01, 0x7110); 30 - rtsx_write_phy_register(chip, 0x01, 0x7112); 31 - rtsx_write_phy_register(chip, 0x01, 0x7113); 32 - rtsx_write_phy_register(chip, 0x00, 0x0288); 33 - } 34 - 35 - void rtsx_enable_card_int(struct rtsx_chip *chip) 36 - { 37 - u32 reg = rtsx_readl(chip, RTSX_BIER); 38 - int i; 39 - 40 - for (i = 0; i <= chip->max_lun; i++) { 41 - if (chip->lun2card[i] & XD_CARD) 42 - reg |= XD_INT_EN; 43 - if (chip->lun2card[i] & SD_CARD) 44 - reg |= SD_INT_EN; 45 - if (chip->lun2card[i] & MS_CARD) 46 - reg |= MS_INT_EN; 47 - } 48 - if (chip->hw_bypass_sd) 49 - reg &= ~((u32)SD_INT_EN); 50 - 51 - rtsx_writel(chip, RTSX_BIER, reg); 52 - } 53 - 54 - void rtsx_enable_bus_int(struct rtsx_chip *chip) 55 - { 56 - u32 reg = 0; 57 - #ifndef DISABLE_CARD_INT 58 - int i; 59 - #endif 60 - 61 - reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN; 62 - 63 - #ifndef DISABLE_CARD_INT 64 - for (i = 0; i <= chip->max_lun; i++) { 65 - dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n", 66 - i, chip->lun2card[i]); 67 - 68 - if (chip->lun2card[i] & XD_CARD) 69 - reg |= XD_INT_EN; 70 - if (chip->lun2card[i] & SD_CARD) 71 - reg |= SD_INT_EN; 72 - if (chip->lun2card[i] & MS_CARD) 73 - reg |= MS_INT_EN; 74 - } 75 - if (chip->hw_bypass_sd) 76 - reg &= ~((u32)SD_INT_EN); 77 - #endif 78 - 79 - if (chip->ic_version >= IC_VER_C) 80 - reg |= DELINK_INT_EN; 81 - #ifdef SUPPORT_OCP 82 - reg |= OC_INT_EN; 83 - #endif 84 - if (!chip->adma_mode) 85 - reg |= DATA_DONE_INT_EN; 86 - 87 - /* Enable Bus Interrupt */ 88 - rtsx_writel(chip, RTSX_BIER, reg); 89 - 90 - dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg); 91 - } 92 - 93 - void rtsx_disable_bus_int(struct rtsx_chip *chip) 94 - { 95 - rtsx_writel(chip, RTSX_BIER, 0); 96 - } 97 - 98 - static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip) 99 - { 100 - int retval; 101 - 102 - if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) { 103 - if (chip->asic_code) { 104 - retval = rtsx_write_register(chip, CARD_PULL_CTL5, 105 - 0xFF, 106 - MS_INS_PU | SD_WP_PU | 107 - SD_CD_PU | SD_CMD_PU); 108 - if (retval) 109 - return retval; 110 - } else { 111 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 112 - 0xFF, 113 - FPGA_SD_PULL_CTL_EN); 114 - if (retval) 115 - return retval; 116 - } 117 - retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF, 118 - CARD_SHARE_48_SD); 119 - if (retval) 120 - return retval; 121 - 122 - /* Enable SDIO internal clock */ 123 - retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01); 124 - if (retval) 125 - return retval; 126 - 127 - retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF, 128 - SDIO_BUS_CTRL | SDIO_CD_CTRL); 129 - if (retval) 130 - return retval; 131 - 132 - chip->sd_int = 1; 133 - chip->sd_io = 1; 134 - } else { 135 - chip->need_reset |= SD_CARD; 136 - } 137 - 138 - return STATUS_SUCCESS; 139 - } 140 - 141 - #ifdef HW_AUTO_SWITCH_SD_BUS 142 - static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip) 143 - { 144 - u8 tmp; 145 - bool sw_bypass_sd = false; 146 - int retval; 147 - 148 - if (chip->driver_first_load) { 149 - if (CHECK_PID(chip, 0x5288)) { 150 - retval = rtsx_read_register(chip, 0xFE5A, &tmp); 151 - if (retval) 152 - return retval; 153 - if (tmp & 0x08) 154 - sw_bypass_sd = true; 155 - } else if (CHECK_PID(chip, 0x5208)) { 156 - retval = rtsx_read_register(chip, 0xFE70, &tmp); 157 - if (retval) 158 - return retval; 159 - if (tmp & 0x80) 160 - sw_bypass_sd = true; 161 - } 162 - } else { 163 - if (chip->sdio_in_charge) 164 - sw_bypass_sd = true; 165 - } 166 - dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n", 167 - chip->sdio_in_charge); 168 - dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n", 169 - chip->driver_first_load); 170 - dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n", 171 - sw_bypass_sd); 172 - 173 - if (sw_bypass_sd) { 174 - u8 cd_toggle_mask = 0; 175 - 176 - retval = rtsx_read_register(chip, TLPTISTAT, &tmp); 177 - if (retval) 178 - return retval; 179 - cd_toggle_mask = 0x08; 180 - 181 - if (tmp & cd_toggle_mask) { 182 - /* Disable sdio_bus_auto_switch */ 183 - if (CHECK_PID(chip, 0x5288)) { 184 - retval = rtsx_write_register(chip, 0xFE5A, 185 - 0x08, 0x00); 186 - if (retval) 187 - return retval; 188 - } else if (CHECK_PID(chip, 0x5208)) { 189 - retval = rtsx_write_register(chip, 0xFE70, 190 - 0x80, 0x00); 191 - if (retval) 192 - return retval; 193 - } 194 - 195 - retval = rtsx_write_register(chip, TLPTISTAT, 0xFF, 196 - tmp); 197 - if (retval) 198 - return retval; 199 - 200 - chip->need_reset |= SD_CARD; 201 - } else { 202 - dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n"); 203 - 204 - if (chip->asic_code) { 205 - retval = sd_pull_ctl_enable(chip); 206 - if (retval != STATUS_SUCCESS) 207 - return STATUS_FAIL; 208 - } else { 209 - retval = rtsx_write_register 210 - (chip, FPGA_PULL_CTL, 211 - FPGA_SD_PULL_CTL_BIT | 0x20, 212 - 0); 213 - if (retval) 214 - return retval; 215 - } 216 - retval = card_share_mode(chip, SD_CARD); 217 - if (retval != STATUS_SUCCESS) 218 - return STATUS_FAIL; 219 - 220 - /* Enable sdio_bus_auto_switch */ 221 - if (CHECK_PID(chip, 0x5288)) { 222 - retval = rtsx_write_register(chip, 0xFE5A, 223 - 0x08, 0x08); 224 - if (retval) 225 - return retval; 226 - } else if (CHECK_PID(chip, 0x5208)) { 227 - retval = rtsx_write_register(chip, 0xFE70, 228 - 0x80, 0x80); 229 - if (retval) 230 - return retval; 231 - } 232 - 233 - chip->chip_insert_with_sdio = 1; 234 - chip->sd_io = 1; 235 - } 236 - } else { 237 - retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 238 - if (retval) 239 - return retval; 240 - 241 - chip->need_reset |= SD_CARD; 242 - } 243 - 244 - return STATUS_SUCCESS; 245 - } 246 - #endif 247 - 248 - static int rtsx_reset_aspm(struct rtsx_chip *chip) 249 - { 250 - int ret; 251 - 252 - if (chip->dynamic_aspm) { 253 - if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288)) 254 - return STATUS_SUCCESS; 255 - 256 - ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, 257 - chip->aspm_l0s_l1_en); 258 - if (ret != STATUS_SUCCESS) 259 - return STATUS_FAIL; 260 - 261 - return STATUS_SUCCESS; 262 - } 263 - 264 - if (CHECK_PID(chip, 0x5208)) { 265 - ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); 266 - if (ret) 267 - return ret; 268 - } 269 - ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en); 270 - if (ret != STATUS_SUCCESS) 271 - return STATUS_FAIL; 272 - 273 - chip->aspm_level[0] = chip->aspm_l0s_l1_en; 274 - if (CHK_SDIO_EXIST(chip)) { 275 - chip->aspm_level[1] = chip->aspm_l0s_l1_en; 276 - ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 277 - 0xC0, 0xFF, chip->aspm_l0s_l1_en); 278 - if (ret != STATUS_SUCCESS) 279 - return STATUS_FAIL; 280 - } 281 - 282 - chip->aspm_enabled = 1; 283 - 284 - return STATUS_SUCCESS; 285 - } 286 - 287 - static int rtsx_enable_pcie_intr(struct rtsx_chip *chip) 288 - { 289 - int ret; 290 - 291 - if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) { 292 - rtsx_enable_bus_int(chip); 293 - return STATUS_SUCCESS; 294 - } 295 - 296 - if (chip->phy_debug_mode) { 297 - ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); 298 - if (ret) 299 - return ret; 300 - rtsx_disable_bus_int(chip); 301 - } else { 302 - rtsx_enable_bus_int(chip); 303 - } 304 - 305 - if (chip->ic_version >= IC_VER_D) { 306 - u16 reg; 307 - 308 - ret = rtsx_read_phy_register(chip, 0x00, &reg); 309 - if (ret != STATUS_SUCCESS) 310 - return STATUS_FAIL; 311 - 312 - reg &= 0xFE7F; 313 - reg |= 0x80; 314 - ret = rtsx_write_phy_register(chip, 0x00, reg); 315 - if (ret != STATUS_SUCCESS) 316 - return STATUS_FAIL; 317 - 318 - ret = rtsx_read_phy_register(chip, 0x1C, &reg); 319 - if (ret != STATUS_SUCCESS) 320 - return STATUS_FAIL; 321 - 322 - reg &= 0xFFF7; 323 - ret = rtsx_write_phy_register(chip, 0x1C, reg); 324 - if (ret != STATUS_SUCCESS) 325 - return STATUS_FAIL; 326 - } 327 - 328 - if (chip->driver_first_load && chip->ic_version < IC_VER_C) 329 - rtsx_calibration(chip); 330 - 331 - return STATUS_SUCCESS; 332 - } 333 - 334 - int rtsx_reset_chip(struct rtsx_chip *chip) 335 - { 336 - int retval; 337 - 338 - rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); 339 - 340 - rtsx_disable_aspm(chip); 341 - 342 - retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); 343 - if (retval) 344 - return retval; 345 - 346 - /* Disable card clock */ 347 - retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0); 348 - if (retval) 349 - return retval; 350 - 351 - #ifdef SUPPORT_OCP 352 - /* SSC power on, OCD power on */ 353 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 354 - retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0); 355 - if (retval) 356 - return retval; 357 - } else { 358 - retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 359 - MS_OC_POWER_DOWN); 360 - if (retval) 361 - return retval; 362 - } 363 - 364 - retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK, 365 - OCP_TIME_800); 366 - if (retval) 367 - return retval; 368 - retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK, 369 - OCP_THD_244_946); 370 - if (retval) 371 - return retval; 372 - retval = rtsx_write_register(chip, OCPCTL, 0xFF, 373 - CARD_OC_INT_EN | CARD_DETECT_EN); 374 - if (retval) 375 - return retval; 376 - #else 377 - /* OC power down */ 378 - retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 379 - OC_POWER_DOWN); 380 - if (retval) 381 - return retval; 382 - #endif 383 - 384 - if (!CHECK_PID(chip, 0x5288)) { 385 - retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03); 386 - if (retval) 387 - return retval; 388 - } 389 - 390 - /* Turn off LED */ 391 - retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03); 392 - if (retval) 393 - return retval; 394 - 395 - /* Reset delink mode */ 396 - retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0); 397 - if (retval) 398 - return retval; 399 - 400 - /* Card driving select */ 401 - retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF, 402 - chip->card_drive_sel); 403 - if (retval) 404 - return retval; 405 - 406 - #ifdef LED_AUTO_BLINK 407 - retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF, 408 - LED_BLINK_SPEED | BLINK_EN | LED_GPIO0); 409 - if (retval) 410 - return retval; 411 - #endif 412 - 413 - if (chip->asic_code) { 414 - /* Enable SSC Clock */ 415 - retval = rtsx_write_register(chip, SSC_CTL1, 0xFF, 416 - SSC_8X_EN | SSC_SEL_4M); 417 - if (retval) 418 - return retval; 419 - retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12); 420 - if (retval) 421 - return retval; 422 - } 423 - 424 - /* 425 - * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0) 426 - * 0xFE5B 427 - * bit[1] u_cd_rst_core_en rst_value = 0 428 - * bit[2] u_force_rst_core_en rst_value = 0 429 - * bit[5] u_mac_phy_rst_n_dbg rst_value = 1 430 - * bit[4] u_non_sticky_rst_n_dbg rst_value = 0 431 - */ 432 - retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10); 433 - if (retval) 434 - return retval; 435 - 436 - /* Enable ASPM */ 437 - if (chip->aspm_l0s_l1_en) { 438 - retval = rtsx_reset_aspm(chip); 439 - if (retval != STATUS_SUCCESS) 440 - return STATUS_FAIL; 441 - } else { 442 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 443 - retval = rtsx_write_phy_register(chip, 0x07, 0x0129); 444 - if (retval != STATUS_SUCCESS) 445 - return STATUS_FAIL; 446 - } 447 - retval = rtsx_write_config_byte(chip, LCTLR, 448 - chip->aspm_l0s_l1_en); 449 - if (retval != STATUS_SUCCESS) 450 - return STATUS_FAIL; 451 - } 452 - 453 - retval = rtsx_write_config_byte(chip, 0x81, 1); 454 - if (retval != STATUS_SUCCESS) 455 - return STATUS_FAIL; 456 - 457 - if (CHK_SDIO_EXIST(chip)) { 458 - retval = rtsx_write_cfg_dw(chip, 459 - CHECK_PID(chip, 0x5288) ? 2 : 1, 460 - 0xC0, 0xFF00, 0x0100); 461 - 462 - if (retval != STATUS_SUCCESS) 463 - return STATUS_FAIL; 464 - } 465 - 466 - if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) { 467 - retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103); 468 - if (retval != STATUS_SUCCESS) 469 - return STATUS_FAIL; 470 - 471 - retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03); 472 - if (retval != STATUS_SUCCESS) 473 - return STATUS_FAIL; 474 - } 475 - 476 - retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, 477 - LINK_RDY_INT); 478 - if (retval) 479 - return retval; 480 - 481 - retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); 482 - if (retval) 483 - return retval; 484 - 485 - retval = rtsx_enable_pcie_intr(chip); 486 - if (retval != STATUS_SUCCESS) 487 - return STATUS_FAIL; 488 - 489 - chip->need_reset = 0; 490 - 491 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 492 - 493 - if (chip->hw_bypass_sd) 494 - goto nextcard; 495 - dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__, 496 - chip->int_reg); 497 - if (chip->int_reg & SD_EXIST) { 498 - #ifdef HW_AUTO_SWITCH_SD_BUS 499 - if (CHECK_PID(chip, 0x5208) && chip->ic_version < IC_VER_C) 500 - retval = rtsx_pre_handle_sdio_old(chip); 501 - else 502 - retval = rtsx_pre_handle_sdio_new(chip); 503 - 504 - dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (%s)\n", 505 - (unsigned int)(chip->need_reset), __func__); 506 - #else /* HW_AUTO_SWITCH_SD_BUS */ 507 - retval = rtsx_pre_handle_sdio_old(chip); 508 - #endif /* HW_AUTO_SWITCH_SD_BUS */ 509 - if (retval != STATUS_SUCCESS) 510 - return STATUS_FAIL; 511 - 512 - } else { 513 - chip->sd_io = 0; 514 - retval = rtsx_write_register(chip, SDIO_CTRL, 515 - SDIO_BUS_CTRL | SDIO_CD_CTRL, 0); 516 - if (retval) 517 - return retval; 518 - } 519 - 520 - nextcard: 521 - if (chip->int_reg & XD_EXIST) 522 - chip->need_reset |= XD_CARD; 523 - if (chip->int_reg & MS_EXIST) 524 - chip->need_reset |= MS_CARD; 525 - if (chip->int_reg & CARD_EXIST) { 526 - retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB, 527 - SSC_RSTB); 528 - if (retval) 529 - return retval; 530 - } 531 - 532 - dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__, 533 - (unsigned int)(chip->need_reset)); 534 - 535 - retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00); 536 - if (retval) 537 - return retval; 538 - 539 - if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { 540 - /* Turn off main power when entering S3/S4 state */ 541 - retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03, 542 - 0x03); 543 - if (retval) 544 - return retval; 545 - } 546 - 547 - if (chip->remote_wakeup_en && !chip->auto_delink_en) { 548 - retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07); 549 - if (retval) 550 - return retval; 551 - if (chip->aux_pwr_exist) { 552 - retval = rtsx_write_register(chip, PME_FORCE_CTL, 553 - 0xFF, 0x33); 554 - if (retval) 555 - return retval; 556 - } 557 - } else { 558 - retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04); 559 - if (retval) 560 - return retval; 561 - retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30); 562 - if (retval) 563 - return retval; 564 - } 565 - 566 - if (CHECK_PID(chip, 0x5208) && chip->ic_version >= IC_VER_D) { 567 - retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14); 568 - if (retval) 569 - return retval; 570 - } 571 - 572 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) { 573 - retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2); 574 - if (retval != STATUS_SUCCESS) 575 - return STATUS_FAIL; 576 - } 577 - 578 - if (chip->ft2_fast_mode) { 579 - retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, 580 - MS_PARTIAL_POWER_ON | 581 - SD_PARTIAL_POWER_ON); 582 - if (retval) 583 - return retval; 584 - udelay(chip->pmos_pwr_on_interval); 585 - retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, 586 - MS_POWER_ON | SD_POWER_ON); 587 - if (retval) 588 - return retval; 589 - 590 - wait_timeout(200); 591 - } 592 - 593 - /* Reset card */ 594 - rtsx_reset_detected_cards(chip, 0); 595 - 596 - chip->driver_first_load = 0; 597 - 598 - return STATUS_SUCCESS; 599 - } 600 - 601 - static inline int valid_sd_speed_prior(u32 sd_speed_prior) 602 - { 603 - bool valid_para = true; 604 - int i; 605 - 606 - for (i = 0; i < 4; i++) { 607 - u8 tmp = (u8)(sd_speed_prior >> (i * 8)); 608 - 609 - if (tmp < 0x01 || tmp > 0x04) { 610 - valid_para = false; 611 - break; 612 - } 613 - } 614 - 615 - return valid_para; 616 - } 617 - 618 - static inline int valid_sd_current_prior(u32 sd_current_prior) 619 - { 620 - bool valid_para = true; 621 - int i; 622 - 623 - for (i = 0; i < 4; i++) { 624 - u8 tmp = (u8)(sd_current_prior >> (i * 8)); 625 - 626 - if (tmp > 0x03) { 627 - valid_para = false; 628 - break; 629 - } 630 - } 631 - 632 - return valid_para; 633 - } 634 - 635 - static int rts5208_init(struct rtsx_chip *chip) 636 - { 637 - int retval; 638 - u16 reg = 0; 639 - u8 val = 0; 640 - 641 - retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); 642 - if (retval) 643 - return retval; 644 - retval = rtsx_read_register(chip, CLK_SEL, &val); 645 - if (retval) 646 - return retval; 647 - chip->asic_code = val == 0 ? 1 : 0; 648 - 649 - if (chip->asic_code) { 650 - retval = rtsx_read_phy_register(chip, 0x1C, &reg); 651 - if (retval != STATUS_SUCCESS) 652 - return STATUS_FAIL; 653 - 654 - dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n", 655 - reg); 656 - chip->ic_version = (reg >> 4) & 0x07; 657 - chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0; 658 - 659 - } else { 660 - retval = rtsx_read_register(chip, 0xFE80, &val); 661 - if (retval) 662 - return retval; 663 - chip->ic_version = val; 664 - chip->phy_debug_mode = 0; 665 - } 666 - 667 - retval = rtsx_read_register(chip, PDINFO, &val); 668 - if (retval) 669 - return retval; 670 - dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); 671 - chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; 672 - 673 - retval = rtsx_read_register(chip, 0xFE50, &val); 674 - if (retval) 675 - return retval; 676 - chip->hw_bypass_sd = val & 0x01 ? 1 : 0; 677 - 678 - rtsx_read_config_byte(chip, 0x0E, &val); 679 - if (val & 0x80) 680 - SET_SDIO_EXIST(chip); 681 - else 682 - CLR_SDIO_EXIST(chip); 683 - 684 - if (chip->use_hw_setting) { 685 - retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); 686 - if (retval) 687 - return retval; 688 - chip->auto_delink_en = val & 0x80 ? 1 : 0; 689 - } 690 - 691 - return STATUS_SUCCESS; 692 - } 693 - 694 - static int rts5288_init(struct rtsx_chip *chip) 695 - { 696 - int retval; 697 - u8 val = 0, max_func; 698 - u32 lval = 0; 699 - 700 - retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); 701 - if (retval) 702 - return retval; 703 - retval = rtsx_read_register(chip, CLK_SEL, &val); 704 - if (retval) 705 - return retval; 706 - chip->asic_code = val == 0 ? 1 : 0; 707 - 708 - chip->ic_version = 0; 709 - chip->phy_debug_mode = 0; 710 - 711 - retval = rtsx_read_register(chip, PDINFO, &val); 712 - if (retval) 713 - return retval; 714 - dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val); 715 - chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0; 716 - 717 - retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val); 718 - if (retval) 719 - return retval; 720 - dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val); 721 - chip->baro_pkg = val & 0x04 ? QFN : LQFP; 722 - 723 - retval = rtsx_read_register(chip, 0xFE5A, &val); 724 - if (retval) 725 - return retval; 726 - chip->hw_bypass_sd = val & 0x10 ? 1 : 0; 727 - 728 - retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval); 729 - if (retval != STATUS_SUCCESS) 730 - return STATUS_FAIL; 731 - 732 - max_func = (u8)((lval >> 29) & 0x07); 733 - dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func); 734 - if (max_func == 0x02) 735 - SET_SDIO_EXIST(chip); 736 - else 737 - CLR_SDIO_EXIST(chip); 738 - 739 - if (chip->use_hw_setting) { 740 - retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val); 741 - if (retval) 742 - return retval; 743 - chip->auto_delink_en = val & 0x80 ? 1 : 0; 744 - 745 - if (CHECK_BARO_PKG(chip, LQFP)) 746 - chip->lun_mode = SD_MS_1LUN; 747 - else 748 - chip->lun_mode = DEFAULT_SINGLE; 749 - } 750 - 751 - return STATUS_SUCCESS; 752 - } 753 - 754 - int rtsx_init_chip(struct rtsx_chip *chip) 755 - { 756 - struct sd_info *sd_card = &chip->sd_card; 757 - struct xd_info *xd_card = &chip->xd_card; 758 - struct ms_info *ms_card = &chip->ms_card; 759 - int retval; 760 - unsigned int i; 761 - 762 - dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n", 763 - chip->vendor_id, chip->product_id); 764 - 765 - chip->ic_version = 0; 766 - 767 - memset(xd_card, 0, sizeof(struct xd_info)); 768 - memset(sd_card, 0, sizeof(struct sd_info)); 769 - memset(ms_card, 0, sizeof(struct ms_info)); 770 - 771 - chip->xd_reset_counter = 0; 772 - chip->sd_reset_counter = 0; 773 - chip->ms_reset_counter = 0; 774 - 775 - chip->xd_show_cnt = MAX_SHOW_CNT; 776 - chip->sd_show_cnt = MAX_SHOW_CNT; 777 - chip->ms_show_cnt = MAX_SHOW_CNT; 778 - 779 - chip->sd_io = 0; 780 - chip->auto_delink_cnt = 0; 781 - chip->auto_delink_allowed = 1; 782 - rtsx_set_stat(chip, RTSX_STAT_INIT); 783 - 784 - chip->aspm_enabled = 0; 785 - chip->chip_insert_with_sdio = 0; 786 - chip->sdio_aspm = 0; 787 - chip->sdio_idle = 0; 788 - chip->sdio_counter = 0; 789 - chip->cur_card = 0; 790 - chip->phy_debug_mode = 0; 791 - chip->sdio_func_exist = 0; 792 - memset(chip->sdio_raw_data, 0, 12); 793 - 794 - for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) { 795 - set_sense_type(chip, i, SENSE_TYPE_NO_SENSE); 796 - chip->rw_fail_cnt[i] = 0; 797 - } 798 - 799 - if (!valid_sd_speed_prior(chip->sd_speed_prior)) 800 - chip->sd_speed_prior = 0x01040203; 801 - 802 - dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n", 803 - chip->sd_speed_prior); 804 - 805 - if (!valid_sd_current_prior(chip->sd_current_prior)) 806 - chip->sd_current_prior = 0x00010203; 807 - 808 - dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n", 809 - chip->sd_current_prior); 810 - 811 - if (chip->sd_ddr_tx_phase > 31 || chip->sd_ddr_tx_phase < 0) 812 - chip->sd_ddr_tx_phase = 0; 813 - 814 - if (chip->mmc_ddr_tx_phase > 31 || chip->mmc_ddr_tx_phase < 0) 815 - chip->mmc_ddr_tx_phase = 0; 816 - 817 - retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0); 818 - if (retval) 819 - return retval; 820 - wait_timeout(200); 821 - retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); 822 - if (retval) 823 - return retval; 824 - dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n", 825 - chip->use_hw_setting); 826 - 827 - if (CHECK_PID(chip, 0x5208)) { 828 - retval = rts5208_init(chip); 829 - if (retval != STATUS_SUCCESS) 830 - return STATUS_FAIL; 831 - 832 - } else if (CHECK_PID(chip, 0x5288)) { 833 - retval = rts5288_init(chip); 834 - if (retval != STATUS_SUCCESS) 835 - return STATUS_FAIL; 836 - } 837 - 838 - if (chip->ss_en == 2) 839 - chip->ss_en = 0; 840 - 841 - dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code); 842 - dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version); 843 - dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n", 844 - chip->phy_debug_mode); 845 - dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n", 846 - chip->aux_pwr_exist); 847 - dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n", 848 - chip->sdio_func_exist); 849 - dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n", 850 - chip->hw_bypass_sd); 851 - dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n", 852 - chip->aspm_l0s_l1_en); 853 - dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode); 854 - dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n", 855 - chip->auto_delink_en); 856 - dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en); 857 - dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg); 858 - 859 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 860 - chip->card2lun[SD_CARD] = 0; 861 - chip->card2lun[MS_CARD] = 1; 862 - chip->card2lun[XD_CARD] = 0xFF; 863 - chip->lun2card[0] = SD_CARD; 864 - chip->lun2card[1] = MS_CARD; 865 - chip->max_lun = 1; 866 - SET_SDIO_IGNORED(chip); 867 - } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) { 868 - chip->card2lun[SD_CARD] = 0; 869 - chip->card2lun[MS_CARD] = 0; 870 - chip->card2lun[XD_CARD] = 0xFF; 871 - chip->lun2card[0] = SD_CARD | MS_CARD; 872 - chip->max_lun = 0; 873 - } else { 874 - chip->card2lun[XD_CARD] = 0; 875 - chip->card2lun[SD_CARD] = 0; 876 - chip->card2lun[MS_CARD] = 0; 877 - chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD; 878 - chip->max_lun = 0; 879 - } 880 - 881 - retval = rtsx_reset_chip(chip); 882 - if (retval != STATUS_SUCCESS) 883 - return STATUS_FAIL; 884 - 885 - return STATUS_SUCCESS; 886 - } 887 - 888 - void rtsx_release_chip(struct rtsx_chip *chip) 889 - { 890 - xd_free_l2p_tbl(chip); 891 - ms_free_l2p_tbl(chip); 892 - chip->card_exist = 0; 893 - chip->card_ready = 0; 894 - } 895 - 896 - #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 897 - static inline void rtsx_blink_led(struct rtsx_chip *chip) 898 - { 899 - if (chip->card_exist && chip->blink_led) { 900 - if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) { 901 - chip->led_toggle_counter++; 902 - } else { 903 - chip->led_toggle_counter = 0; 904 - toggle_gpio(chip, LED_GPIO); 905 - } 906 - } 907 - } 908 - #endif 909 - 910 - static void rtsx_monitor_aspm_config(struct rtsx_chip *chip) 911 - { 912 - bool reg_changed, maybe_support_aspm; 913 - u32 tmp = 0; 914 - u8 reg0 = 0, reg1 = 0; 915 - 916 - maybe_support_aspm = false; 917 - reg_changed = false; 918 - rtsx_read_config_byte(chip, LCTLR, &reg0); 919 - if (chip->aspm_level[0] != reg0) { 920 - reg_changed = true; 921 - chip->aspm_level[0] = reg0; 922 - } 923 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 924 - rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp); 925 - reg1 = (u8)tmp; 926 - if (chip->aspm_level[1] != reg1) { 927 - reg_changed = true; 928 - chip->aspm_level[1] = reg1; 929 - } 930 - 931 - if ((reg0 & 0x03) && (reg1 & 0x03)) 932 - maybe_support_aspm = true; 933 - 934 - } else { 935 - if (reg0 & 0x03) 936 - maybe_support_aspm = true; 937 - } 938 - 939 - if (reg_changed) { 940 - if (maybe_support_aspm) 941 - chip->aspm_l0s_l1_en = 0x03; 942 - 943 - dev_dbg(rtsx_dev(chip), 944 - "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n", 945 - chip->aspm_level[0], chip->aspm_level[1]); 946 - 947 - if (chip->aspm_l0s_l1_en) { 948 - chip->aspm_enabled = 1; 949 - } else { 950 - chip->aspm_enabled = 0; 951 - chip->sdio_aspm = 0; 952 - } 953 - rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 954 - 0x30 | chip->aspm_level[0] | 955 - (chip->aspm_level[1] << 2)); 956 - } 957 - } 958 - 959 - static void rtsx_manage_ocp(struct rtsx_chip *chip) 960 - { 961 - #ifdef SUPPORT_OCP 962 - if (!chip->ocp_int) 963 - return; 964 - 965 - rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat); 966 - 967 - if (chip->card_exist & SD_CARD) 968 - sd_power_off_card3v3(chip); 969 - else if (chip->card_exist & MS_CARD) 970 - ms_power_off_card3v3(chip); 971 - else if (chip->card_exist & XD_CARD) 972 - xd_power_off_card3v3(chip); 973 - 974 - chip->ocp_int = 0; 975 - #endif 976 - } 977 - 978 - static void rtsx_manage_sd_lock(struct rtsx_chip *chip) 979 - { 980 - #ifdef SUPPORT_SD_LOCK 981 - struct sd_info *sd_card = &chip->sd_card; 982 - u8 val; 983 - 984 - if (!sd_card->sd_erase_status) 985 - return; 986 - 987 - if (chip->card_exist & SD_CARD) { 988 - rtsx_read_register(chip, 0xFD30, &val); 989 - if (val & 0x02) { 990 - sd_card->sd_erase_status = SD_NOT_ERASE; 991 - sd_card->sd_lock_notify = 1; 992 - chip->need_reinit |= SD_CARD; 993 - } 994 - } else { 995 - sd_card->sd_erase_status = SD_NOT_ERASE; 996 - } 997 - #endif 998 - } 999 - 1000 - static bool rtsx_is_ss_allowed(struct rtsx_chip *chip) 1001 - { 1002 - u32 val; 1003 - 1004 - if (!chip->ss_en || CHECK_PID(chip, 0x5288)) 1005 - return false; 1006 - 1007 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) { 1008 - rtsx_read_cfg_dw(chip, 1, 0x04, &val); 1009 - if (val & 0x07) 1010 - return false; 1011 - } 1012 - 1013 - return true; 1014 - } 1015 - 1016 - static void rtsx_manage_ss(struct rtsx_chip *chip) 1017 - { 1018 - if (!rtsx_is_ss_allowed(chip) || chip->sd_io) 1019 - return; 1020 - 1021 - if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) { 1022 - chip->ss_counter = 0; 1023 - return; 1024 - } 1025 - 1026 - if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL)) 1027 - chip->ss_counter++; 1028 - else 1029 - rtsx_exclusive_enter_ss(chip); 1030 - } 1031 - 1032 - static void rtsx_manage_aspm(struct rtsx_chip *chip) 1033 - { 1034 - u8 data; 1035 - 1036 - if (!CHECK_PID(chip, 0x5208)) 1037 - return; 1038 - 1039 - rtsx_monitor_aspm_config(chip); 1040 - 1041 - #ifdef SUPPORT_SDIO_ASPM 1042 - if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) || 1043 - !chip->aspm_l0s_l1_en || !chip->dynamic_aspm) 1044 - return; 1045 - 1046 - if (chip->sd_io) { 1047 - dynamic_configure_sdio_aspm(chip); 1048 - return; 1049 - } 1050 - 1051 - if (chip->sdio_aspm) 1052 - return; 1053 - 1054 - dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n"); 1055 - data = 0x30 | (chip->aspm_level[1] << 2); 1056 - rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data); 1057 - chip->sdio_aspm = 1; 1058 - #endif 1059 - } 1060 - 1061 - static void rtsx_manage_idle(struct rtsx_chip *chip) 1062 - { 1063 - if (chip->idle_counter < IDLE_MAX_COUNT) { 1064 - chip->idle_counter++; 1065 - return; 1066 - } 1067 - 1068 - if (rtsx_get_stat(chip) == RTSX_STAT_IDLE) 1069 - return; 1070 - 1071 - dev_dbg(rtsx_dev(chip), "Idle state!\n"); 1072 - rtsx_set_stat(chip, RTSX_STAT_IDLE); 1073 - 1074 - #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1075 - chip->led_toggle_counter = 0; 1076 - #endif 1077 - rtsx_force_power_on(chip, SSC_PDCTL); 1078 - 1079 - turn_off_led(chip, LED_GPIO); 1080 - 1081 - if (chip->auto_power_down && !chip->card_ready && !chip->sd_io) 1082 - rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1083 - } 1084 - 1085 - static void rtsx_manage_2lun_mode(struct rtsx_chip *chip) 1086 - { 1087 - #ifdef SUPPORT_OCP 1088 - u8 sd_oc, ms_oc; 1089 - 1090 - sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER); 1091 - ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER); 1092 - 1093 - if (sd_oc || ms_oc) 1094 - dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 1095 - chip->ocp_stat); 1096 - 1097 - if (sd_oc && (chip->card_exist & SD_CARD)) { 1098 - rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1099 - card_power_off(chip, SD_CARD); 1100 - chip->card_fail |= SD_CARD; 1101 - } 1102 - 1103 - if (ms_oc && (chip->card_exist & MS_CARD)) { 1104 - rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1105 - card_power_off(chip, MS_CARD); 1106 - chip->card_fail |= MS_CARD; 1107 - } 1108 - #endif 1109 - } 1110 - 1111 - static void rtsx_manage_1lun_mode(struct rtsx_chip *chip) 1112 - { 1113 - #ifdef SUPPORT_OCP 1114 - if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER))) 1115 - return; 1116 - 1117 - dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 1118 - chip->ocp_stat); 1119 - 1120 - if (chip->card_exist & SD_CARD) { 1121 - rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 1122 - chip->card_fail |= SD_CARD; 1123 - } else if (chip->card_exist & MS_CARD) { 1124 - rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 1125 - chip->card_fail |= MS_CARD; 1126 - } else if (chip->card_exist & XD_CARD) { 1127 - rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 1128 - chip->card_fail |= XD_CARD; 1129 - } 1130 - card_power_off(chip, SD_CARD); 1131 - #endif 1132 - } 1133 - 1134 - static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1, 1135 - int stage3_cnt) 1136 - { 1137 - u8 val; 1138 - 1139 - rtsx_set_stat(chip, RTSX_STAT_DELINK); 1140 - 1141 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1142 - rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1143 - 1144 - if (chip->card_exist) 1145 - dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n"); 1146 - else 1147 - dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n"); 1148 - 1149 - if (enter_L1) 1150 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); 1151 - 1152 - if (chip->card_exist) 1153 - val = 0x02; 1154 - else 1155 - val = 0x0A; 1156 - 1157 - rtsx_write_register(chip, CHANGE_LINK_STATE, val, val); 1158 - 1159 - if (enter_L1) 1160 - rtsx_enter_L1(chip); 1161 - 1162 - if (chip->card_exist) 1163 - chip->auto_delink_cnt = stage3_cnt + 1; 1164 - } 1165 - 1166 - static void rtsx_delink_stage(struct rtsx_chip *chip) 1167 - { 1168 - int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt; 1169 - int enter_L1; 1170 - 1171 - if (!chip->auto_delink_en || !chip->auto_delink_allowed || 1172 - chip->card_ready || chip->card_ejected || chip->sd_io) { 1173 - chip->auto_delink_cnt = 0; 1174 - return; 1175 - } 1176 - 1177 - enter_L1 = chip->auto_delink_in_L1 && 1178 - (chip->aspm_l0s_l1_en || chip->ss_en); 1179 - 1180 - delink_stage1_cnt = chip->delink_stage1_step; 1181 - delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step; 1182 - delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step; 1183 - 1184 - if (chip->auto_delink_cnt > delink_stage3_cnt) 1185 - return; 1186 - 1187 - if (chip->auto_delink_cnt == delink_stage1_cnt) 1188 - rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt); 1189 - 1190 - if (chip->auto_delink_cnt == delink_stage2_cnt) { 1191 - dev_dbg(rtsx_dev(chip), "Try to do force delink\n"); 1192 - 1193 - if (enter_L1) 1194 - rtsx_exit_L1(chip); 1195 - 1196 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1197 - rtsx_set_phy_reg_bit(chip, 0x1C, 2); 1198 - 1199 - rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A); 1200 - } 1201 - 1202 - chip->auto_delink_cnt++; 1203 - } 1204 - 1205 - void rtsx_polling_func(struct rtsx_chip *chip) 1206 - { 1207 - if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND)) 1208 - return; 1209 - 1210 - if (rtsx_chk_stat(chip, RTSX_STAT_DELINK)) 1211 - goto delink_stage; 1212 - 1213 - if (chip->polling_config) { 1214 - u8 val; 1215 - 1216 - rtsx_read_config_byte(chip, 0, &val); 1217 - } 1218 - 1219 - if (rtsx_chk_stat(chip, RTSX_STAT_SS)) 1220 - return; 1221 - 1222 - rtsx_manage_ocp(chip); 1223 - 1224 - rtsx_manage_sd_lock(chip); 1225 - 1226 - rtsx_init_cards(chip); 1227 - 1228 - rtsx_manage_ss(chip); 1229 - 1230 - rtsx_manage_aspm(chip); 1231 - 1232 - rtsx_manage_idle(chip); 1233 - 1234 - switch (rtsx_get_stat(chip)) { 1235 - case RTSX_STAT_RUN: 1236 - #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK) 1237 - rtsx_blink_led(chip); 1238 - #endif 1239 - do_remaining_work(chip); 1240 - break; 1241 - 1242 - case RTSX_STAT_IDLE: 1243 - if (chip->sd_io && !chip->sd_int) 1244 - try_to_switch_sdio_ctrl(chip); 1245 - 1246 - rtsx_enable_aspm(chip); 1247 - break; 1248 - 1249 - default: 1250 - break; 1251 - } 1252 - 1253 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 1254 - rtsx_manage_2lun_mode(chip); 1255 - else 1256 - rtsx_manage_1lun_mode(chip); 1257 - 1258 - delink_stage: 1259 - rtsx_delink_stage(chip); 1260 - } 1261 - 1262 - /** 1263 - * rtsx_stop_cmd - stop command transfer and DMA transfer 1264 - * @chip: Realtek's card reader chip 1265 - * @card: flash card type 1266 - * 1267 - * Stop command transfer and DMA transfer. 1268 - * This function is called in error handler. 1269 - */ 1270 - void rtsx_stop_cmd(struct rtsx_chip *chip, int card) 1271 - { 1272 - int i; 1273 - 1274 - for (i = 0; i <= 8; i++) { 1275 - int addr = RTSX_HCBAR + i * 4; 1276 - u32 reg; 1277 - 1278 - reg = rtsx_readl(chip, addr); 1279 - dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg); 1280 - } 1281 - rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD); 1282 - rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA); 1283 - 1284 - for (i = 0; i < 16; i++) { 1285 - u16 addr = 0xFE20 + (u16)i; 1286 - u8 val; 1287 - 1288 - rtsx_read_register(chip, addr, &val); 1289 - dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val); 1290 - } 1291 - 1292 - rtsx_write_register(chip, DMACTL, 0x80, 0x80); 1293 - rtsx_write_register(chip, RBCTL, 0x80, 0x80); 1294 - } 1295 - 1296 - #define MAX_RW_REG_CNT 1024 1297 - 1298 - int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) 1299 - { 1300 - int i; 1301 - u32 val = 3 << 30; 1302 - 1303 - val |= (u32)(addr & 0x3FFF) << 16; 1304 - val |= (u32)mask << 8; 1305 - val |= (u32)data; 1306 - 1307 - rtsx_writel(chip, RTSX_HAIMR, val); 1308 - 1309 - for (i = 0; i < MAX_RW_REG_CNT; i++) { 1310 - val = rtsx_readl(chip, RTSX_HAIMR); 1311 - if ((val & BIT(31)) == 0) { 1312 - if (data != (u8)val) 1313 - return STATUS_FAIL; 1314 - 1315 - return STATUS_SUCCESS; 1316 - } 1317 - } 1318 - 1319 - return STATUS_TIMEDOUT; 1320 - } 1321 - 1322 - int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data) 1323 - { 1324 - u32 val = 2 << 30; 1325 - int i; 1326 - 1327 - if (data) 1328 - *data = 0; 1329 - 1330 - val |= (u32)(addr & 0x3FFF) << 16; 1331 - 1332 - rtsx_writel(chip, RTSX_HAIMR, val); 1333 - 1334 - for (i = 0; i < MAX_RW_REG_CNT; i++) { 1335 - val = rtsx_readl(chip, RTSX_HAIMR); 1336 - if ((val & BIT(31)) == 0) 1337 - break; 1338 - } 1339 - 1340 - if (i >= MAX_RW_REG_CNT) 1341 - return STATUS_TIMEDOUT; 1342 - 1343 - if (data) 1344 - *data = (u8)(val & 0xFF); 1345 - 1346 - return STATUS_SUCCESS; 1347 - } 1348 - 1349 - int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, 1350 - u32 val) 1351 - { 1352 - int retval; 1353 - u8 mode = 0, tmp; 1354 - int i; 1355 - 1356 - for (i = 0; i < 4; i++) { 1357 - if (mask & 0xFF) { 1358 - retval = rtsx_write_register(chip, CFGDATA0 + i, 1359 - 0xFF, 1360 - (u8)(val & mask & 0xFF)); 1361 - if (retval) 1362 - return retval; 1363 - mode |= (1 << i); 1364 - } 1365 - mask >>= 8; 1366 - val >>= 8; 1367 - } 1368 - 1369 - if (mode) { 1370 - retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); 1371 - if (retval) 1372 - return retval; 1373 - retval = rtsx_write_register(chip, CFGADDR1, 0xFF, 1374 - (u8)(addr >> 8)); 1375 - if (retval) 1376 - return retval; 1377 - 1378 - retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, 1379 - 0x80 | mode | 1380 - ((func_no & 0x03) << 4)); 1381 - if (retval) 1382 - return retval; 1383 - 1384 - for (i = 0; i < MAX_RW_REG_CNT; i++) { 1385 - retval = rtsx_read_register(chip, CFGRWCTL, &tmp); 1386 - if (retval) 1387 - return retval; 1388 - if ((tmp & 0x80) == 0) 1389 - break; 1390 - } 1391 - } 1392 - 1393 - return STATUS_SUCCESS; 1394 - } 1395 - 1396 - int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val) 1397 - { 1398 - int retval; 1399 - int i; 1400 - u8 tmp; 1401 - u32 data = 0; 1402 - 1403 - retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); 1404 - if (retval) 1405 - return retval; 1406 - retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); 1407 - if (retval) 1408 - return retval; 1409 - retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, 1410 - 0x80 | ((func_no & 0x03) << 4)); 1411 - if (retval) 1412 - return retval; 1413 - 1414 - for (i = 0; i < MAX_RW_REG_CNT; i++) { 1415 - retval = rtsx_read_register(chip, CFGRWCTL, &tmp); 1416 - if (retval) 1417 - return retval; 1418 - if ((tmp & 0x80) == 0) 1419 - break; 1420 - } 1421 - 1422 - for (i = 0; i < 4; i++) { 1423 - retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp); 1424 - if (retval) 1425 - return retval; 1426 - data |= (u32)tmp << (i * 8); 1427 - } 1428 - 1429 - if (val) 1430 - *val = data; 1431 - 1432 - return STATUS_SUCCESS; 1433 - } 1434 - 1435 - int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, 1436 - int len) 1437 - { 1438 - u32 *data, *mask; 1439 - u16 offset = addr % 4; 1440 - u16 aligned_addr = addr - offset; 1441 - int dw_len, i, j; 1442 - int retval; 1443 - size_t size; 1444 - 1445 - if (!buf) 1446 - return STATUS_NOMEM; 1447 - 1448 - if ((len + offset) % 4) 1449 - dw_len = (len + offset) / 4 + 1; 1450 - else 1451 - dw_len = (len + offset) / 4; 1452 - 1453 - dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len); 1454 - 1455 - size = array_size(dw_len, 4); 1456 - data = vzalloc(size); 1457 - if (!data) 1458 - return STATUS_NOMEM; 1459 - 1460 - mask = vzalloc(size); 1461 - if (!mask) { 1462 - vfree(data); 1463 - return STATUS_NOMEM; 1464 - } 1465 - 1466 - j = 0; 1467 - for (i = 0; i < len; i++) { 1468 - mask[j] |= 0xFF << (offset * 8); 1469 - data[j] |= buf[i] << (offset * 8); 1470 - if (++offset == 4) { 1471 - j++; 1472 - offset = 0; 1473 - } 1474 - } 1475 - 1476 - print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask, size); 1477 - print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data, size); 1478 - 1479 - for (i = 0; i < dw_len; i++) { 1480 - retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, 1481 - mask[i], data[i]); 1482 - if (retval != STATUS_SUCCESS) { 1483 - vfree(data); 1484 - vfree(mask); 1485 - return STATUS_FAIL; 1486 - } 1487 - } 1488 - 1489 - vfree(data); 1490 - vfree(mask); 1491 - 1492 - return STATUS_SUCCESS; 1493 - } 1494 - 1495 - int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, 1496 - int len) 1497 - { 1498 - u32 *data; 1499 - u16 offset = addr % 4; 1500 - u16 aligned_addr = addr - offset; 1501 - int dw_len, i, j; 1502 - int retval; 1503 - 1504 - if ((len + offset) % 4) 1505 - dw_len = (len + offset) / 4 + 1; 1506 - else 1507 - dw_len = (len + offset) / 4; 1508 - 1509 - dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len); 1510 - 1511 - data = vmalloc(array_size(dw_len, 4)); 1512 - if (!data) 1513 - return STATUS_NOMEM; 1514 - 1515 - for (i = 0; i < dw_len; i++) { 1516 - retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, 1517 - data + i); 1518 - if (retval != STATUS_SUCCESS) { 1519 - vfree(data); 1520 - return STATUS_FAIL; 1521 - } 1522 - } 1523 - 1524 - if (buf) { 1525 - j = 0; 1526 - 1527 - for (i = 0; i < len; i++) { 1528 - buf[i] = (u8)(data[j] >> (offset * 8)); 1529 - if (++offset == 4) { 1530 - j++; 1531 - offset = 0; 1532 - } 1533 - } 1534 - } 1535 - 1536 - vfree(data); 1537 - 1538 - return STATUS_SUCCESS; 1539 - } 1540 - 1541 - int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val) 1542 - { 1543 - int retval; 1544 - bool finished = false; 1545 - int i; 1546 - u8 tmp; 1547 - 1548 - retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); 1549 - if (retval) 1550 - return retval; 1551 - retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); 1552 - if (retval) 1553 - return retval; 1554 - retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); 1555 - if (retval) 1556 - return retval; 1557 - retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81); 1558 - if (retval) 1559 - return retval; 1560 - 1561 - for (i = 0; i < 100000; i++) { 1562 - retval = rtsx_read_register(chip, PHYRWCTL, &tmp); 1563 - if (retval) 1564 - return retval; 1565 - if (!(tmp & 0x80)) { 1566 - finished = true; 1567 - break; 1568 - } 1569 - } 1570 - 1571 - if (!finished) 1572 - return STATUS_FAIL; 1573 - 1574 - return STATUS_SUCCESS; 1575 - } 1576 - 1577 - int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val) 1578 - { 1579 - int retval; 1580 - bool finished = false; 1581 - int i; 1582 - u16 data = 0; 1583 - u8 tmp; 1584 - 1585 - retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); 1586 - if (retval) 1587 - return retval; 1588 - retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80); 1589 - if (retval) 1590 - return retval; 1591 - 1592 - for (i = 0; i < 100000; i++) { 1593 - retval = rtsx_read_register(chip, PHYRWCTL, &tmp); 1594 - if (retval) 1595 - return retval; 1596 - if (!(tmp & 0x80)) { 1597 - finished = true; 1598 - break; 1599 - } 1600 - } 1601 - 1602 - if (!finished) 1603 - return STATUS_FAIL; 1604 - 1605 - retval = rtsx_read_register(chip, PHYDATA0, &tmp); 1606 - if (retval) 1607 - return retval; 1608 - data = tmp; 1609 - retval = rtsx_read_register(chip, PHYDATA1, &tmp); 1610 - if (retval) 1611 - return retval; 1612 - data |= (u16)tmp << 8; 1613 - 1614 - if (val) 1615 - *val = data; 1616 - 1617 - return STATUS_SUCCESS; 1618 - } 1619 - 1620 - int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val) 1621 - { 1622 - int retval; 1623 - int i; 1624 - u8 data = 0; 1625 - 1626 - retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr); 1627 - if (retval) 1628 - return retval; 1629 - 1630 - for (i = 0; i < 100; i++) { 1631 - retval = rtsx_read_register(chip, EFUSE_CTRL, &data); 1632 - if (retval) 1633 - return retval; 1634 - if (!(data & 0x80)) 1635 - break; 1636 - udelay(1); 1637 - } 1638 - 1639 - if (data & 0x80) 1640 - return STATUS_TIMEDOUT; 1641 - 1642 - retval = rtsx_read_register(chip, EFUSE_DATA, &data); 1643 - if (retval) 1644 - return retval; 1645 - if (val) 1646 - *val = data; 1647 - 1648 - return STATUS_SUCCESS; 1649 - } 1650 - 1651 - int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val) 1652 - { 1653 - int retval; 1654 - int i, j; 1655 - u8 data = 0, tmp = 0xFF; 1656 - 1657 - for (i = 0; i < 8; i++) { 1658 - if (val & (u8)(1 << i)) 1659 - continue; 1660 - 1661 - tmp &= (~(u8)(1 << i)); 1662 - dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr); 1663 - 1664 - retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp); 1665 - if (retval) 1666 - return retval; 1667 - retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 1668 - 0xA0 | addr); 1669 - if (retval) 1670 - return retval; 1671 - 1672 - for (j = 0; j < 100; j++) { 1673 - retval = rtsx_read_register(chip, EFUSE_CTRL, &data); 1674 - if (retval) 1675 - return retval; 1676 - if (!(data & 0x80)) 1677 - break; 1678 - wait_timeout(3); 1679 - } 1680 - 1681 - if (data & 0x80) 1682 - return STATUS_TIMEDOUT; 1683 - 1684 - wait_timeout(5); 1685 - } 1686 - 1687 - return STATUS_SUCCESS; 1688 - } 1689 - 1690 - int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1691 - { 1692 - int retval; 1693 - u16 value; 1694 - 1695 - retval = rtsx_read_phy_register(chip, reg, &value); 1696 - if (retval != STATUS_SUCCESS) 1697 - return STATUS_FAIL; 1698 - 1699 - if (value & (1 << bit)) { 1700 - value &= ~(1 << bit); 1701 - retval = rtsx_write_phy_register(chip, reg, value); 1702 - if (retval != STATUS_SUCCESS) 1703 - return STATUS_FAIL; 1704 - } 1705 - 1706 - return STATUS_SUCCESS; 1707 - } 1708 - 1709 - int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit) 1710 - { 1711 - int retval; 1712 - u16 value; 1713 - 1714 - retval = rtsx_read_phy_register(chip, reg, &value); 1715 - if (retval != STATUS_SUCCESS) 1716 - return STATUS_FAIL; 1717 - 1718 - if ((value & (1 << bit)) == 0) { 1719 - value |= (1 << bit); 1720 - retval = rtsx_write_phy_register(chip, reg, value); 1721 - if (retval != STATUS_SUCCESS) 1722 - return STATUS_FAIL; 1723 - } 1724 - 1725 - return STATUS_SUCCESS; 1726 - } 1727 - 1728 - static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate) 1729 - { 1730 - u32 ultmp; 1731 - 1732 - dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n", 1733 - chip->product_id, dstate); 1734 - 1735 - if (CHK_SDIO_EXIST(chip)) { 1736 - u8 func_no; 1737 - 1738 - if (CHECK_PID(chip, 0x5288)) 1739 - func_no = 2; 1740 - else 1741 - func_no = 1; 1742 - 1743 - rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp); 1744 - dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n", 1745 - (int)func_no, ultmp); 1746 - rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate); 1747 - } 1748 - 1749 - rtsx_write_config_byte(chip, 0x44, dstate); 1750 - rtsx_write_config_byte(chip, 0x45, 0); 1751 - } 1752 - 1753 - void rtsx_enter_L1(struct rtsx_chip *chip) 1754 - { 1755 - rtsx_handle_pm_dstate(chip, 2); 1756 - } 1757 - 1758 - void rtsx_exit_L1(struct rtsx_chip *chip) 1759 - { 1760 - rtsx_write_config_byte(chip, 0x44, 0); 1761 - rtsx_write_config_byte(chip, 0x45, 0); 1762 - } 1763 - 1764 - void rtsx_enter_ss(struct rtsx_chip *chip) 1765 - { 1766 - dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n"); 1767 - 1768 - rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); 1769 - 1770 - if (chip->power_down_in_ss) { 1771 - rtsx_power_off_card(chip); 1772 - rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1773 - } 1774 - 1775 - if (CHK_SDIO_EXIST(chip)) 1776 - rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 1777 - 0xC0, 0xFF00, 0x0100); 1778 - 1779 - if (chip->auto_delink_en) { 1780 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01); 1781 - } else { 1782 - if (!chip->phy_debug_mode) { 1783 - u32 tmp; 1784 - 1785 - tmp = rtsx_readl(chip, RTSX_BIER); 1786 - tmp |= CARD_INT; 1787 - rtsx_writel(chip, RTSX_BIER, tmp); 1788 - } 1789 - 1790 - rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0); 1791 - } 1792 - 1793 - rtsx_enter_L1(chip); 1794 - 1795 - RTSX_CLR_DELINK(chip); 1796 - rtsx_set_stat(chip, RTSX_STAT_SS); 1797 - } 1798 - 1799 - void rtsx_exit_ss(struct rtsx_chip *chip) 1800 - { 1801 - dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n"); 1802 - 1803 - rtsx_exit_L1(chip); 1804 - 1805 - if (chip->power_down_in_ss) { 1806 - rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 1807 - udelay(1000); 1808 - } 1809 - 1810 - if (RTSX_TST_DELINK(chip)) { 1811 - chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1812 - rtsx_reinit_cards(chip, 1); 1813 - RTSX_CLR_DELINK(chip); 1814 - } else if (chip->power_down_in_ss) { 1815 - chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 1816 - rtsx_reinit_cards(chip, 0); 1817 - } 1818 - } 1819 - 1820 - int rtsx_pre_handle_interrupt(struct rtsx_chip *chip) 1821 - { 1822 - u32 status, int_enable; 1823 - bool exit_ss = false; 1824 - #ifdef SUPPORT_OCP 1825 - u32 ocp_int = 0; 1826 - 1827 - ocp_int = OC_INT; 1828 - #endif 1829 - 1830 - if (chip->ss_en) { 1831 - chip->ss_counter = 0; 1832 - if (rtsx_get_stat(chip) == RTSX_STAT_SS) { 1833 - exit_ss = true; 1834 - rtsx_exit_L1(chip); 1835 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1836 - } 1837 - } 1838 - 1839 - int_enable = rtsx_readl(chip, RTSX_BIER); 1840 - chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 1841 - 1842 - if (((chip->int_reg & int_enable) == 0) || 1843 - chip->int_reg == 0xFFFFFFFF) 1844 - return STATUS_FAIL; 1845 - 1846 - status = chip->int_reg &= (int_enable | 0x7FFFFF); 1847 - 1848 - if (status & CARD_INT) { 1849 - chip->auto_delink_cnt = 0; 1850 - 1851 - if (status & SD_INT) { 1852 - if (status & SD_EXIST) { 1853 - set_bit(SD_NR, &chip->need_reset); 1854 - } else { 1855 - set_bit(SD_NR, &chip->need_release); 1856 - chip->sd_reset_counter = 0; 1857 - chip->sd_show_cnt = 0; 1858 - clear_bit(SD_NR, &chip->need_reset); 1859 - } 1860 - } else { 1861 - /* 1862 - * If multi-luns, it's possible that 1863 - * when plugging/unplugging one card 1864 - * there is another card which still 1865 - * exists in the slot. In this case, 1866 - * all existed cards should be reset. 1867 - */ 1868 - if (exit_ss && (status & SD_EXIST)) 1869 - set_bit(SD_NR, &chip->need_reinit); 1870 - } 1871 - if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) { 1872 - if (status & XD_INT) { 1873 - if (status & XD_EXIST) { 1874 - set_bit(XD_NR, &chip->need_reset); 1875 - } else { 1876 - set_bit(XD_NR, &chip->need_release); 1877 - chip->xd_reset_counter = 0; 1878 - chip->xd_show_cnt = 0; 1879 - clear_bit(XD_NR, &chip->need_reset); 1880 - } 1881 - } else { 1882 - if (exit_ss && (status & XD_EXIST)) 1883 - set_bit(XD_NR, &chip->need_reinit); 1884 - } 1885 - } 1886 - if (status & MS_INT) { 1887 - if (status & MS_EXIST) { 1888 - set_bit(MS_NR, &chip->need_reset); 1889 - } else { 1890 - set_bit(MS_NR, &chip->need_release); 1891 - chip->ms_reset_counter = 0; 1892 - chip->ms_show_cnt = 0; 1893 - clear_bit(MS_NR, &chip->need_reset); 1894 - } 1895 - } else { 1896 - if (exit_ss && (status & MS_EXIST)) 1897 - set_bit(MS_NR, &chip->need_reinit); 1898 - } 1899 - } 1900 - 1901 - #ifdef SUPPORT_OCP 1902 - chip->ocp_int = ocp_int & status; 1903 - #endif 1904 - 1905 - if (chip->sd_io && (chip->int_reg & DATA_DONE_INT)) 1906 - chip->int_reg &= ~(u32)DATA_DONE_INT; 1907 - 1908 - return STATUS_SUCCESS; 1909 - } 1910 - 1911 - void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat) 1912 - { 1913 - int retval; 1914 - 1915 - dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat); 1916 - 1917 - rtsx_set_stat(chip, RTSX_STAT_SUSPEND); 1918 - 1919 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1920 - if (retval != STATUS_SUCCESS) 1921 - return; 1922 - 1923 - rtsx_release_cards(chip); 1924 - rtsx_disable_bus_int(chip); 1925 - turn_off_led(chip, LED_GPIO); 1926 - 1927 - #ifdef HW_AUTO_SWITCH_SD_BUS 1928 - if (chip->sd_io) { 1929 - chip->sdio_in_charge = 1; 1930 - if (CHECK_PID(chip, 0x5208)) { 1931 - rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 1932 - /* Enable sdio_bus_auto_switch */ 1933 - rtsx_write_register(chip, 0xFE70, 0x80, 0x80); 1934 - } else if (CHECK_PID(chip, 0x5288)) { 1935 - rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); 1936 - /* Enable sdio_bus_auto_switch */ 1937 - rtsx_write_register(chip, 0xFE5A, 0x08, 0x08); 1938 - } 1939 - } 1940 - #endif 1941 - 1942 - if (CHECK_PID(chip, 0x5208) && chip->ic_version >= IC_VER_D) { 1943 - /* u_force_clkreq_0 */ 1944 - rtsx_write_register(chip, PETXCFG, 0x08, 0x08); 1945 - } 1946 - 1947 - if (pm_stat == PM_S1) { 1948 - dev_dbg(rtsx_dev(chip), "Host enter S1\n"); 1949 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1950 - HOST_ENTER_S1); 1951 - } else if (pm_stat == PM_S3) { 1952 - if (chip->s3_pwr_off_delay > 0) 1953 - wait_timeout(chip->s3_pwr_off_delay); 1954 - 1955 - dev_dbg(rtsx_dev(chip), "Host enter S3\n"); 1956 - rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1957 - HOST_ENTER_S3); 1958 - } 1959 - 1960 - if (chip->do_delink_before_power_down && chip->auto_delink_en) 1961 - rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2); 1962 - 1963 - rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL); 1964 - 1965 - chip->cur_clk = 0; 1966 - chip->cur_card = 0; 1967 - chip->card_exist = 0; 1968 - } 1969 - 1970 - void rtsx_enable_aspm(struct rtsx_chip *chip) 1971 - { 1972 - if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) { 1973 - dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n"); 1974 - chip->aspm_enabled = 1; 1975 - 1976 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) 1977 - rtsx_write_phy_register(chip, 0x07, 0); 1978 - if (CHECK_PID(chip, 0x5208)) { 1979 - rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 1980 - 0x30 | chip->aspm_level[0]); 1981 - } else { 1982 - rtsx_write_config_byte(chip, LCTLR, 1983 - chip->aspm_l0s_l1_en); 1984 - } 1985 - 1986 - if (CHK_SDIO_EXIST(chip)) { 1987 - u16 val = chip->aspm_l0s_l1_en | 0x0100; 1988 - 1989 - rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1, 1990 - 0xC0, 0xFFF, val); 1991 - } 1992 - } 1993 - } 1994 - 1995 - void rtsx_disable_aspm(struct rtsx_chip *chip) 1996 - { 1997 - if (CHECK_PID(chip, 0x5208)) 1998 - rtsx_monitor_aspm_config(chip); 1999 - 2000 - if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) { 2001 - dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n"); 2002 - chip->aspm_enabled = 0; 2003 - 2004 - if (chip->asic_code && CHECK_PID(chip, 0x5208)) 2005 - rtsx_write_phy_register(chip, 0x07, 0x0129); 2006 - if (CHECK_PID(chip, 0x5208)) 2007 - rtsx_write_register(chip, ASPM_FORCE_CTL, 2008 - 0xF3, 0x30); 2009 - else 2010 - rtsx_write_config_byte(chip, LCTLR, 0x00); 2011 - 2012 - wait_timeout(1); 2013 - } 2014 - } 2015 - 2016 - int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2017 - { 2018 - int retval; 2019 - int i, j; 2020 - u16 reg_addr; 2021 - u8 *ptr; 2022 - 2023 - if (!buf) 2024 - return STATUS_ERROR; 2025 - 2026 - ptr = buf; 2027 - reg_addr = PPBUF_BASE2; 2028 - for (i = 0; i < buf_len / 256; i++) { 2029 - rtsx_init_cmd(chip); 2030 - 2031 - for (j = 0; j < 256; j++) 2032 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2033 - 2034 - retval = rtsx_send_cmd(chip, 0, 250); 2035 - if (retval < 0) 2036 - return STATUS_FAIL; 2037 - 2038 - memcpy(ptr, rtsx_get_cmd_data(chip), 256); 2039 - ptr += 256; 2040 - } 2041 - 2042 - if (buf_len % 256) { 2043 - rtsx_init_cmd(chip); 2044 - 2045 - for (j = 0; j < buf_len % 256; j++) 2046 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); 2047 - 2048 - retval = rtsx_send_cmd(chip, 0, 250); 2049 - if (retval < 0) 2050 - return STATUS_FAIL; 2051 - } 2052 - 2053 - memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256); 2054 - 2055 - return STATUS_SUCCESS; 2056 - } 2057 - 2058 - int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len) 2059 - { 2060 - int retval; 2061 - int i, j; 2062 - u16 reg_addr; 2063 - u8 *ptr; 2064 - 2065 - if (!buf) 2066 - return STATUS_ERROR; 2067 - 2068 - ptr = buf; 2069 - reg_addr = PPBUF_BASE2; 2070 - for (i = 0; i < buf_len / 256; i++) { 2071 - rtsx_init_cmd(chip); 2072 - 2073 - for (j = 0; j < 256; j++) { 2074 - rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, 2075 - *ptr); 2076 - ptr++; 2077 - } 2078 - 2079 - retval = rtsx_send_cmd(chip, 0, 250); 2080 - if (retval < 0) 2081 - return STATUS_FAIL; 2082 - } 2083 - 2084 - if (buf_len % 256) { 2085 - rtsx_init_cmd(chip); 2086 - 2087 - for (j = 0; j < buf_len % 256; j++) { 2088 - rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, 2089 - *ptr); 2090 - ptr++; 2091 - } 2092 - 2093 - retval = rtsx_send_cmd(chip, 0, 250); 2094 - if (retval < 0) 2095 - return STATUS_FAIL; 2096 - } 2097 - 2098 - return STATUS_SUCCESS; 2099 - } 2100 - 2101 - int rtsx_check_chip_exist(struct rtsx_chip *chip) 2102 - { 2103 - if (rtsx_readl(chip, 0) == 0xFFFFFFFF) 2104 - return STATUS_FAIL; 2105 - 2106 - return STATUS_SUCCESS; 2107 - } 2108 - 2109 - int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl) 2110 - { 2111 - int retval; 2112 - u8 mask = 0; 2113 - 2114 - if (ctl & SSC_PDCTL) 2115 - mask |= SSC_POWER_DOWN; 2116 - 2117 - #ifdef SUPPORT_OCP 2118 - if (ctl & OC_PDCTL) { 2119 - mask |= SD_OC_POWER_DOWN; 2120 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2121 - mask |= MS_OC_POWER_DOWN; 2122 - } 2123 - #endif 2124 - 2125 - if (mask) { 2126 - retval = rtsx_write_register(chip, FPDCTL, mask, 0); 2127 - if (retval != STATUS_SUCCESS) 2128 - return STATUS_FAIL; 2129 - 2130 - if (CHECK_PID(chip, 0x5288)) 2131 - wait_timeout(200); 2132 - } 2133 - 2134 - return STATUS_SUCCESS; 2135 - } 2136 - 2137 - int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl) 2138 - { 2139 - int retval; 2140 - u8 mask = 0, val = 0; 2141 - 2142 - if (ctl & SSC_PDCTL) 2143 - mask |= SSC_POWER_DOWN; 2144 - 2145 - #ifdef SUPPORT_OCP 2146 - if (ctl & OC_PDCTL) { 2147 - mask |= SD_OC_POWER_DOWN; 2148 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2149 - mask |= MS_OC_POWER_DOWN; 2150 - } 2151 - #endif 2152 - 2153 - if (mask) { 2154 - val = mask; 2155 - retval = rtsx_write_register(chip, FPDCTL, mask, val); 2156 - if (retval != STATUS_SUCCESS) 2157 - return STATUS_FAIL; 2158 - } 2159 - 2160 - return STATUS_SUCCESS; 2161 - }
-987
drivers/staging/rts5208/rtsx_chip.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_CHIP_H 13 - #define __REALTEK_RTSX_CHIP_H 14 - 15 - #include "rtsx.h" 16 - 17 - #define SUPPORT_CPRM 18 - #define SUPPORT_OCP 19 - #define SUPPORT_SDIO_ASPM 20 - #define SUPPORT_MAGIC_GATE 21 - #define SUPPORT_MSXC 22 - #define SUPPORT_SD_LOCK 23 - /* Hardware switch bus_ctl and cd_ctl automatically */ 24 - #define HW_AUTO_SWITCH_SD_BUS 25 - /* Enable hardware interrupt write clear */ 26 - #define HW_INT_WRITE_CLR 27 - /* #define LED_AUTO_BLINK */ 28 - /* #define DISABLE_CARD_INT */ 29 - 30 - #ifdef SUPPORT_MAGIC_GATE 31 - /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */ 32 - #define MG_SET_ICV_SLOW 33 - /* HW may miss ERR/CMDNK signal when sampling INT status. */ 34 - #define MS_SAMPLE_INT_ERR 35 - /* 36 - * HW DO NOT support Wait_INT function 37 - * during READ_BYTES transfer mode 38 - */ 39 - #define READ_BYTES_WAIT_INT 40 - #endif 41 - 42 - #ifdef SUPPORT_MSXC 43 - #define XC_POWERCLASS 44 - #define SUPPORT_PCGL_1P18 45 - #endif 46 - 47 - #ifndef LED_AUTO_BLINK 48 - #define REGULAR_BLINK 49 - #endif 50 - 51 - #define LED_BLINK_SPEED 5 52 - #define LED_TOGGLE_INTERVAL 6 53 - #define GPIO_TOGGLE_THRESHOLD 1024 54 - #define LED_GPIO 0 55 - 56 - #define POLLING_INTERVAL 30 57 - 58 - #define TRACE_ITEM_CNT 64 59 - 60 - #ifndef STATUS_SUCCESS 61 - #define STATUS_SUCCESS 0 62 - #endif 63 - #ifndef STATUS_FAIL 64 - #define STATUS_FAIL 1 65 - #endif 66 - #ifndef STATUS_TIMEDOUT 67 - #define STATUS_TIMEDOUT 2 68 - #endif 69 - #ifndef STATUS_NOMEM 70 - #define STATUS_NOMEM 3 71 - #endif 72 - #ifndef STATUS_READ_FAIL 73 - #define STATUS_READ_FAIL 4 74 - #endif 75 - #ifndef STATUS_WRITE_FAIL 76 - #define STATUS_WRITE_FAIL 5 77 - #endif 78 - #ifndef STATUS_ERROR 79 - #define STATUS_ERROR 10 80 - #endif 81 - 82 - #define PM_S1 1 83 - #define PM_S3 3 84 - 85 - /* 86 - * Transport return codes 87 - */ 88 - 89 - #define TRANSPORT_GOOD 0 /* Transport good, command good */ 90 - #define TRANSPORT_FAILED 1 /* Transport good, command failed */ 91 - #define TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */ 92 - #define TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */ 93 - 94 - /* 95 - * Start-Stop-Unit 96 - */ 97 - #define STOP_MEDIUM 0x00 /* access disable */ 98 - #define MAKE_MEDIUM_READY 0x01 /* access enable */ 99 - #define UNLOAD_MEDIUM 0x02 /* unload */ 100 - #define LOAD_MEDIUM 0x03 /* load */ 101 - 102 - /* 103 - * STANDARD_INQUIRY 104 - */ 105 - #define QULIFIRE 0x00 106 - #define AENC_FNC 0x00 107 - #define TRML_IOP 0x00 108 - #define REL_ADR 0x00 109 - #define WBUS_32 0x00 110 - #define WBUS_16 0x00 111 - #define SYNC 0x00 112 - #define LINKED 0x00 113 - #define CMD_QUE 0x00 114 - #define SFT_RE 0x00 115 - 116 - #define VEN_ID_LEN 8 /* Vendor ID Length */ 117 - #define PRDCT_ID_LEN 16 /* Product ID Length */ 118 - #define PRDCT_REV_LEN 4 /* Product LOT Length */ 119 - 120 - /* Dynamic flag definitions: used in set_bit() etc. */ 121 - /* 0x00040000 transfer is active */ 122 - #define RTSX_FLIDX_TRANS_ACTIVE 18 123 - /* 0x00100000 abort is in progress */ 124 - #define RTSX_FLIDX_ABORTING 20 125 - /* 0x00200000 disconnect in progress */ 126 - #define RTSX_FLIDX_DISCONNECTING 21 127 - 128 - #define ABORTING_OR_DISCONNECTING ((1UL << US_FLIDX_ABORTING) | \ 129 - (1UL << US_FLIDX_DISCONNECTING)) 130 - 131 - /* 0x00400000 device reset in progress */ 132 - #define RTSX_FLIDX_RESETTING 22 133 - /* 0x00800000 SCSI midlayer timed out */ 134 - #define RTSX_FLIDX_TIMED_OUT 23 135 - #define DRCT_ACCESS_DEV 0x00 /* Direct Access Device */ 136 - #define RMB_DISC 0x80 /* The Device is Removable */ 137 - #define ANSI_SCSI2 0x02 /* Based on ANSI-SCSI2 */ 138 - 139 - #define SCSI 0x00 /* Interface ID */ 140 - 141 - #define WRITE_PROTECTED_MEDIA 0x07 142 - 143 - /*---- sense key ----*/ 144 - #define ILI 0x20 /* ILI bit is on */ 145 - 146 - #define NO_SENSE 0x00 /* not exist sense key */ 147 - #define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */ 148 - #define NOT_READY 0x02 /* Logical unit is not ready */ 149 - #define MEDIA_ERR 0x03 /* medium/data error */ 150 - #define HARDWARE_ERR 0x04 /* hardware error */ 151 - #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */ 152 - #define UNIT_ATTENTION 0x06 /* unit attention condition occur */ 153 - #define DAT_PRTCT 0x07 /* read/write is desable */ 154 - #define BLNC_CHK 0x08 /* find blank/DOF in read */ 155 - /* write to unblank area */ 156 - #define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illegal */ 157 - #define ABRT_CMD 0x0b /* Target make the command in error */ 158 - #define EQUAL 0x0c /* Search Data end with Equal */ 159 - #define VLM_OVRFLW 0x0d /* Some data are left in buffer */ 160 - #define MISCMP 0x0e /* find inequality */ 161 - 162 - #define READ_ERR -1 163 - #define WRITE_ERR -2 164 - 165 - #define FIRST_RESET 0x01 166 - #define USED_EXIST 0x02 167 - 168 - /* 169 - * SENSE_DATA 170 - */ 171 - /*---- valid ----*/ 172 - #define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */ 173 - #define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */ 174 - 175 - /*---- error code ----*/ 176 - #define CUR_ERR 0x70 /* current error */ 177 - #define DEF_ERR 0x71 /* specific command error */ 178 - 179 - /*---- sense key Information ----*/ 180 - #define SNSKEYINFO_LEN 3 /* length of sense key information */ 181 - 182 - #define SKSV 0x80 183 - #define CDB_ILLEGAL 0x40 184 - #define DAT_ILLEGAL 0x00 185 - #define BPV 0x08 186 - #define BIT_ILLEGAL0 0 /* bit0 is illegal */ 187 - #define BIT_ILLEGAL1 1 /* bit1 is illegal */ 188 - #define BIT_ILLEGAL2 2 /* bit2 is illegal */ 189 - #define BIT_ILLEGAL3 3 /* bit3 is illegal */ 190 - #define BIT_ILLEGAL4 4 /* bit4 is illegal */ 191 - #define BIT_ILLEGAL5 5 /* bit5 is illegal */ 192 - #define BIT_ILLEGAL6 6 /* bit6 is illegal */ 193 - #define BIT_ILLEGAL7 7 /* bit7 is illegal */ 194 - 195 - /*---- ASC ----*/ 196 - #define ASC_NO_INFO 0x00 197 - #define ASC_MISCMP 0x1d 198 - #define ASC_INVLD_CDB 0x24 199 - #define ASC_INVLD_PARA 0x26 200 - #define ASC_LU_NOT_READY 0x04 201 - #define ASC_WRITE_ERR 0x0c 202 - #define ASC_READ_ERR 0x11 203 - #define ASC_LOAD_EJCT_ERR 0x53 204 - #define ASC_MEDIA_NOT_PRESENT 0x3A 205 - #define ASC_MEDIA_CHANGED 0x28 206 - #define ASC_MEDIA_IN_PROCESS 0x04 207 - #define ASC_WRITE_PROTECT 0x27 208 - #define ASC_LUN_NOT_SUPPORTED 0x25 209 - 210 - /*---- ASQC ----*/ 211 - #define ASCQ_NO_INFO 0x00 212 - #define ASCQ_MEDIA_IN_PROCESS 0x01 213 - #define ASCQ_MISCMP 0x00 214 - #define ASCQ_INVLD_CDB 0x00 215 - #define ASCQ_INVLD_PARA 0x02 216 - #define ASCQ_LU_NOT_READY 0x02 217 - #define ASCQ_WRITE_ERR 0x02 218 - #define ASCQ_READ_ERR 0x00 219 - #define ASCQ_LOAD_EJCT_ERR 0x00 220 - #define ASCQ_WRITE_PROTECT 0x00 221 - 222 - struct sense_data_t { 223 - unsigned char err_code; /* error code */ 224 - /* bit7 : valid */ 225 - /* (1 : SCSI2) */ 226 - /* (0 : Vendor * specific) */ 227 - /* bit6-0 : error * code */ 228 - /* (0x70 : current * error) */ 229 - /* (0x71 : specific command error) */ 230 - unsigned char seg_no; /* segment No. */ 231 - unsigned char sense_key; /* byte5 : ILI */ 232 - /* bit3-0 : sense key */ 233 - unsigned char info[4]; /* information */ 234 - unsigned char ad_sense_len; /* additional sense data length */ 235 - unsigned char cmd_info[4]; /* command specific information */ 236 - unsigned char asc; /* ASC */ 237 - unsigned char ascq; /* ASCQ */ 238 - unsigned char rfu; /* FRU */ 239 - unsigned char sns_key_info[3];/* sense key specific information */ 240 - }; 241 - 242 - /* PCI Operation Register Address */ 243 - #define RTSX_HCBAR 0x00 244 - #define RTSX_HCBCTLR 0x04 245 - #define RTSX_HDBAR 0x08 246 - #define RTSX_HDBCTLR 0x0C 247 - #define RTSX_HAIMR 0x10 248 - #define RTSX_BIPR 0x14 249 - #define RTSX_BIER 0x18 250 - 251 - /* Host command buffer control register */ 252 - #define STOP_CMD (0x01 << 28) 253 - 254 - /* Host data buffer control register */ 255 - #define SDMA_MODE 0x00 256 - #define ADMA_MODE (0x02 << 26) 257 - #define STOP_DMA (0x01 << 28) 258 - #define TRIG_DMA (0x01 << 31) 259 - 260 - /* Bus interrupt pending register */ 261 - #define CMD_DONE_INT BIT(31) 262 - #define DATA_DONE_INT BIT(30) 263 - #define TRANS_OK_INT BIT(29) 264 - #define TRANS_FAIL_INT BIT(28) 265 - #define XD_INT BIT(27) 266 - #define MS_INT BIT(26) 267 - #define SD_INT BIT(25) 268 - #define GPIO0_INT BIT(24) 269 - #define OC_INT BIT(23) 270 - #define SD_WRITE_PROTECT BIT(19) 271 - #define XD_EXIST BIT(18) 272 - #define MS_EXIST BIT(17) 273 - #define SD_EXIST BIT(16) 274 - #define DELINK_INT GPIO0_INT 275 - #define MS_OC_INT BIT(23) 276 - #define SD_OC_INT BIT(22) 277 - 278 - #define CARD_INT (XD_INT | MS_INT | SD_INT) 279 - #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) 280 - #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | \ 281 - GPIO0_INT | OC_INT) 282 - 283 - #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) 284 - 285 - /* Bus interrupt enable register */ 286 - #define CMD_DONE_INT_EN BIT(31) 287 - #define DATA_DONE_INT_EN BIT(30) 288 - #define TRANS_OK_INT_EN BIT(29) 289 - #define TRANS_FAIL_INT_EN BIT(28) 290 - #define XD_INT_EN BIT(27) 291 - #define MS_INT_EN BIT(26) 292 - #define SD_INT_EN BIT(25) 293 - #define GPIO0_INT_EN BIT(24) 294 - #define OC_INT_EN BIT(23) 295 - #define DELINK_INT_EN GPIO0_INT_EN 296 - #define MS_OC_INT_EN BIT(23) 297 - #define SD_OC_INT_EN BIT(22) 298 - 299 - #define READ_REG_CMD 0 300 - #define WRITE_REG_CMD 1 301 - #define CHECK_REG_CMD 2 302 - 303 - #define HOST_TO_DEVICE 0 304 - #define DEVICE_TO_HOST 1 305 - 306 - #define RTSX_RESV_BUF_LEN 4096 307 - #define HOST_CMDS_BUF_LEN 1024 308 - #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) 309 - 310 - #define SD_NR 2 311 - #define MS_NR 3 312 - #define XD_NR 4 313 - #define SPI_NR 7 314 - #define SD_CARD BIT(SD_NR) 315 - #define MS_CARD BIT(MS_NR) 316 - #define XD_CARD BIT(XD_NR) 317 - #define SPI_CARD BIT(SPI_NR) 318 - 319 - #define MAX_ALLOWED_LUN_CNT 8 320 - 321 - #define XD_FREE_TABLE_CNT 1200 322 - #define MS_FREE_TABLE_CNT 512 323 - 324 - /* Bit Operation */ 325 - #define SET_BIT(data, idx) ((data) |= 1 << (idx)) 326 - #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) 327 - #define CHK_BIT(data, idx) ((data) & (1 << (idx))) 328 - 329 - /* SG descriptor */ 330 - #define RTSX_SG_INT 0x04 331 - #define RTSX_SG_END 0x02 332 - #define RTSX_SG_VALID 0x01 333 - 334 - #define RTSX_SG_NO_OP 0x00 335 - #define RTSX_SG_TRANS_DATA (0x02 << 4) 336 - #define RTSX_SG_LINK_DESC (0x03 << 4) 337 - 338 - struct rtsx_chip; 339 - 340 - typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, 341 - u32 sec_addr, u16 sec_cnt); 342 - 343 - /* Supported Clock */ 344 - enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, 345 - CLK_80, CLK_100, CLK_120, CLK_150, CLK_200}; 346 - 347 - enum RTSX_STAT {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS, 348 - RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, 349 - RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT}; 350 - enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3}; 351 - 352 - #define MAX_RESET_CNT 3 353 - 354 - /* For MS Card */ 355 - #define MAX_DEFECTIVE_BLOCK 10 356 - 357 - struct zone_entry { 358 - u16 *l2p_table; 359 - u16 *free_table; 360 - u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */ 361 - int set_index; 362 - int get_index; 363 - int unused_blk_cnt; 364 - int disable_count; 365 - /* To indicate whether the L2P table of this zone has been built. */ 366 - int build_flag; 367 - }; 368 - 369 - #define TYPE_SD 0x0000 370 - #define TYPE_MMC 0x0001 371 - 372 - /* TYPE_SD */ 373 - #define SD_HS 0x0100 374 - #define SD_SDR50 0x0200 375 - #define SD_DDR50 0x0400 376 - #define SD_SDR104 0x0800 377 - #define SD_HCXC 0x1000 378 - 379 - /* TYPE_MMC */ 380 - #define MMC_26M 0x0100 381 - #define MMC_52M 0x0200 382 - #define MMC_4BIT 0x0400 383 - #define MMC_8BIT 0x0800 384 - #define MMC_SECTOR_MODE 0x1000 385 - #define MMC_DDR52 0x2000 386 - 387 - /* SD card */ 388 - #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD) 389 - #define CHK_SD_HS(sd_card) (CHK_SD(sd_card) && \ 390 - ((sd_card)->sd_type & SD_HS)) 391 - #define CHK_SD_SDR50(sd_card) (CHK_SD(sd_card) && \ 392 - ((sd_card)->sd_type & SD_SDR50)) 393 - #define CHK_SD_DDR50(sd_card) (CHK_SD(sd_card) && \ 394 - ((sd_card)->sd_type & SD_DDR50)) 395 - #define CHK_SD_SDR104(sd_card) (CHK_SD(sd_card) && \ 396 - ((sd_card)->sd_type & SD_SDR104)) 397 - #define CHK_SD_HCXC(sd_card) (CHK_SD(sd_card) && \ 398 - ((sd_card)->sd_type & SD_HCXC)) 399 - #define CHK_SD_HC(sd_card) (CHK_SD_HCXC(sd_card) && \ 400 - ((sd_card)->capacity <= 0x4000000)) 401 - #define CHK_SD_XC(sd_card) (CHK_SD_HCXC(sd_card) && \ 402 - ((sd_card)->capacity > 0x4000000)) 403 - #define CHK_SD30_SPEED(sd_card) (CHK_SD_SDR50(sd_card) || \ 404 - CHK_SD_DDR50(sd_card) || \ 405 - CHK_SD_SDR104(sd_card)) 406 - 407 - #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD) 408 - #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS) 409 - #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50) 410 - #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50) 411 - #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104) 412 - #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC) 413 - 414 - #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS) 415 - #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50) 416 - #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50) 417 - #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104) 418 - #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC) 419 - 420 - /* MMC card */ 421 - #define CHK_MMC(sd_card) (((sd_card)->sd_type & 0xFF) == \ 422 - TYPE_MMC) 423 - #define CHK_MMC_26M(sd_card) (CHK_MMC(sd_card) && \ 424 - ((sd_card)->sd_type & MMC_26M)) 425 - #define CHK_MMC_52M(sd_card) (CHK_MMC(sd_card) && \ 426 - ((sd_card)->sd_type & MMC_52M)) 427 - #define CHK_MMC_4BIT(sd_card) (CHK_MMC(sd_card) && \ 428 - ((sd_card)->sd_type & MMC_4BIT)) 429 - #define CHK_MMC_8BIT(sd_card) (CHK_MMC(sd_card) && \ 430 - ((sd_card)->sd_type & MMC_8BIT)) 431 - #define CHK_MMC_SECTOR_MODE(sd_card) (CHK_MMC(sd_card) && \ 432 - ((sd_card)->sd_type & MMC_SECTOR_MODE)) 433 - #define CHK_MMC_DDR52(sd_card) (CHK_MMC(sd_card) && \ 434 - ((sd_card)->sd_type & MMC_DDR52)) 435 - 436 - #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC) 437 - #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M) 438 - #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M) 439 - #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT) 440 - #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT) 441 - #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE) 442 - #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52) 443 - 444 - #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M) 445 - #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M) 446 - #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT) 447 - #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT) 448 - #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE) 449 - #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52) 450 - 451 - #define CHK_MMC_HS(sd_card) (CHK_MMC_52M(sd_card) && \ 452 - CHK_MMC_26M(sd_card)) 453 - #define CLR_MMC_HS(sd_card) \ 454 - do { \ 455 - CLR_MMC_DDR52(sd_card); \ 456 - CLR_MMC_52M(sd_card); \ 457 - CLR_MMC_26M(sd_card); \ 458 - } while (0) 459 - 460 - #define SD_SUPPORT_CLASS_TEN 0x01 461 - #define SD_SUPPORT_1V8 0x02 462 - 463 - #define SD_SET_CLASS_TEN(sd_card) ((sd_card)->sd_setting |= \ 464 - SD_SUPPORT_CLASS_TEN) 465 - #define SD_CHK_CLASS_TEN(sd_card) ((sd_card)->sd_setting & \ 466 - SD_SUPPORT_CLASS_TEN) 467 - #define SD_CLR_CLASS_TEN(sd_card) ((sd_card)->sd_setting &= \ 468 - ~SD_SUPPORT_CLASS_TEN) 469 - #define SD_SET_1V8(sd_card) ((sd_card)->sd_setting |= \ 470 - SD_SUPPORT_1V8) 471 - #define SD_CHK_1V8(sd_card) ((sd_card)->sd_setting & \ 472 - SD_SUPPORT_1V8) 473 - #define SD_CLR_1V8(sd_card) ((sd_card)->sd_setting &= \ 474 - ~SD_SUPPORT_1V8) 475 - 476 - struct sd_info { 477 - u16 sd_type; 478 - u8 err_code; 479 - u8 sd_data_buf_ready; 480 - u32 sd_addr; 481 - u32 capacity; 482 - 483 - u8 raw_csd[16]; 484 - u8 raw_scr[8]; 485 - 486 - /* Sequential RW */ 487 - int seq_mode; 488 - enum dma_data_direction pre_dir; 489 - u32 pre_sec_addr; 490 - u16 pre_sec_cnt; 491 - 492 - int cleanup_counter; 493 - 494 - int sd_clock; 495 - 496 - int mmc_dont_switch_bus; 497 - 498 - #ifdef SUPPORT_CPRM 499 - int sd_pass_thru_en; 500 - int pre_cmd_err; 501 - u8 last_rsp_type; 502 - u8 rsp[17]; 503 - #endif 504 - 505 - u8 func_group1_mask; 506 - u8 func_group2_mask; 507 - u8 func_group3_mask; 508 - u8 func_group4_mask; 509 - 510 - u8 sd_switch_fail; 511 - u8 sd_read_phase; 512 - 513 - #ifdef SUPPORT_SD_LOCK 514 - u8 sd_lock_status; 515 - u8 sd_erase_status; 516 - u8 sd_lock_notify; 517 - #endif 518 - int need_retune; 519 - }; 520 - 521 - struct xd_delay_write_tag { 522 - u32 old_phyblock; 523 - u32 new_phyblock; 524 - u32 logblock; 525 - u8 pageoff; 526 - u8 delay_write_flag; 527 - }; 528 - 529 - struct xd_info { 530 - u8 maker_code; 531 - u8 device_code; 532 - u8 block_shift; 533 - u8 page_off; 534 - u8 addr_cycle; 535 - u16 cis_block; 536 - u8 multi_flag; 537 - u8 err_code; 538 - u32 capacity; 539 - 540 - struct zone_entry *zone; 541 - int zone_cnt; 542 - 543 - struct xd_delay_write_tag delay_write; 544 - int cleanup_counter; 545 - 546 - int xd_clock; 547 - }; 548 - 549 - #define MODE_512_SEQ 0x01 550 - #define MODE_2K_SEQ 0x02 551 - 552 - #define TYPE_MS 0x0000 553 - #define TYPE_MSPRO 0x0001 554 - 555 - #define MS_4BIT 0x0100 556 - #define MS_8BIT 0x0200 557 - #define MS_HG 0x0400 558 - #define MS_XC 0x0800 559 - 560 - #define HG8BIT (MS_HG | MS_8BIT) 561 - 562 - #define CHK_MSPRO(ms_card) (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO) 563 - #define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && \ 564 - (((ms_card)->ms_type & HG8BIT) == HG8BIT)) 565 - #define CHK_MSXC(ms_card) (CHK_MSPRO(ms_card) && \ 566 - ((ms_card)->ms_type & MS_XC)) 567 - #define CHK_MSHG(ms_card) (CHK_MSPRO(ms_card) && \ 568 - ((ms_card)->ms_type & MS_HG)) 569 - 570 - #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT)) 571 - #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT)) 572 - 573 - struct ms_delay_write_tag { 574 - u16 old_phyblock; 575 - u16 new_phyblock; 576 - u16 logblock; 577 - u8 pageoff; 578 - u8 delay_write_flag; 579 - }; 580 - 581 - struct ms_info { 582 - u16 ms_type; 583 - u8 block_shift; 584 - u8 page_off; 585 - u16 total_block; 586 - u16 boot_block; 587 - u32 capacity; 588 - 589 - u8 check_ms_flow; 590 - u8 switch_8bit_fail; 591 - u8 err_code; 592 - 593 - struct zone_entry *segment; 594 - int segment_cnt; 595 - 596 - int pro_under_formatting; 597 - int format_status; 598 - u16 progress; 599 - u8 raw_sys_info[96]; 600 - #ifdef SUPPORT_PCGL_1P18 601 - u8 raw_model_name[48]; 602 - #endif 603 - 604 - u8 multi_flag; 605 - 606 - /* Sequential RW */ 607 - u8 seq_mode; 608 - enum dma_data_direction pre_dir; 609 - u32 pre_sec_addr; 610 - u16 pre_sec_cnt; 611 - u32 total_sec_cnt; 612 - 613 - struct ms_delay_write_tag delay_write; 614 - 615 - int cleanup_counter; 616 - 617 - int ms_clock; 618 - 619 - #ifdef SUPPORT_MAGIC_GATE 620 - u8 magic_gate_id[16]; 621 - u8 mg_entry_num; 622 - int mg_auth; /* flag to indicate authentication process */ 623 - #endif 624 - }; 625 - 626 - struct spi_info { 627 - u8 use_clk; 628 - u8 write_en; 629 - u16 clk_div; 630 - u8 err_code; 631 - 632 - int spi_clock; 633 - }; 634 - 635 - /************/ 636 - /* LUN mode */ 637 - /************/ 638 - /* Single LUN, support xD/SD/MS */ 639 - #define DEFAULT_SINGLE 0 640 - /* 2 LUN mode, support SD/MS */ 641 - #define SD_MS_2LUN 1 642 - /* Single LUN, but only support SD/MS, for Barossa LQFP */ 643 - #define SD_MS_1LUN 2 644 - 645 - #define LAST_LUN_MODE 2 646 - 647 - /* Barossa package */ 648 - #define QFN 0 649 - #define LQFP 1 650 - 651 - /******************/ 652 - /* sd_ctl bit map */ 653 - /******************/ 654 - /* SD push point control, bit 0, 1 */ 655 - #define SD_PUSH_POINT_CTL_MASK 0x03 656 - #define SD_PUSH_POINT_DELAY 0x01 657 - #define SD_PUSH_POINT_AUTO 0x02 658 - /* SD sample point control, bit 2, 3 */ 659 - #define SD_SAMPLE_POINT_CTL_MASK 0x0C 660 - #define SD_SAMPLE_POINT_DELAY 0x04 661 - #define SD_SAMPLE_POINT_AUTO 0x08 662 - /* SD DDR Tx phase set by user, bit 4 */ 663 - #define SD_DDR_TX_PHASE_SET_BY_USER 0x10 664 - /* MMC DDR Tx phase set by user, bit 5 */ 665 - #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20 666 - /* Support MMC DDR mode, bit 6 */ 667 - #define SUPPORT_MMC_DDR_MODE 0x40 668 - /* Reset MMC at first */ 669 - #define RESET_MMC_FIRST 0x80 670 - 671 - #define SEQ_START_CRITERIA 0x20 672 - 673 - /* MS Power Class En */ 674 - #define POWER_CLASS_2_EN 0x02 675 - #define POWER_CLASS_1_EN 0x01 676 - 677 - #define MAX_SHOW_CNT 10 678 - #define MAX_RESET_CNT 3 679 - 680 - #define SDIO_EXIST 0x01 681 - #define SDIO_IGNORED 0x02 682 - 683 - #define CHK_SDIO_EXIST(chip) ((chip)->sdio_func_exist & SDIO_EXIST) 684 - #define SET_SDIO_EXIST(chip) ((chip)->sdio_func_exist |= SDIO_EXIST) 685 - #define CLR_SDIO_EXIST(chip) ((chip)->sdio_func_exist &= ~SDIO_EXIST) 686 - 687 - #define CHK_SDIO_IGNORED(chip) ((chip)->sdio_func_exist & SDIO_IGNORED) 688 - #define SET_SDIO_IGNORED(chip) ((chip)->sdio_func_exist |= \ 689 - SDIO_IGNORED) 690 - #define CLR_SDIO_IGNORED(chip) ((chip)->sdio_func_exist &= \ 691 - ~SDIO_IGNORED) 692 - 693 - struct rtsx_chip { 694 - struct rtsx_dev *rtsx; 695 - 696 - u32 int_reg; /* Bus interrupt pending register */ 697 - char max_lun; 698 - void *context; 699 - 700 - void *host_cmds_ptr; /* host commands buffer pointer */ 701 - dma_addr_t host_cmds_addr; 702 - int ci; /* Command Index */ 703 - 704 - void *host_sg_tbl_ptr; /* SG descriptor table */ 705 - dma_addr_t host_sg_tbl_addr; 706 - int sgi; /* SG entry index */ 707 - 708 - struct scsi_cmnd *srb; /* current srb */ 709 - struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT]; 710 - 711 - int cur_clk; /* current card clock */ 712 - 713 - /* Current accessed card */ 714 - int cur_card; 715 - 716 - unsigned long need_release; /* need release bit map */ 717 - unsigned long need_reset; /* need reset bit map */ 718 - /* 719 - * Flag to indicate that this card is just resumed from SS state, 720 - * and need released before being resetted 721 - */ 722 - unsigned long need_reinit; 723 - 724 - int rw_need_retry; 725 - 726 - #ifdef SUPPORT_OCP 727 - u32 ocp_int; 728 - u8 ocp_stat; 729 - #endif 730 - 731 - u8 card_exist; /* card exist bit map (physical exist) */ 732 - u8 card_ready; /* card ready bit map (reset successfully) */ 733 - u8 card_fail; /* card reset fail bit map */ 734 - u8 card_ejected; /* card ejected bit map */ 735 - u8 card_wp; /* card write protected bit map */ 736 - 737 - u8 lun_mc; /* 738 - * flag to indicate whether to answer 739 - * MediaChange 740 - */ 741 - 742 - #ifndef LED_AUTO_BLINK 743 - int led_toggle_counter; 744 - #endif 745 - 746 - int sd_reset_counter; 747 - int xd_reset_counter; 748 - int ms_reset_counter; 749 - 750 - /* card bus width */ 751 - u8 card_bus_width[MAX_ALLOWED_LUN_CNT]; 752 - /* card capacity */ 753 - u32 capacity[MAX_ALLOWED_LUN_CNT]; 754 - /* read/write card function pointer */ 755 - card_rw_func rw_card[MAX_ALLOWED_LUN_CNT]; 756 - /* read/write capacity, used for GPIO Toggle */ 757 - u32 rw_cap[MAX_ALLOWED_LUN_CNT]; 758 - /* card to lun mapping table */ 759 - u8 card2lun[32]; 760 - /* lun to card mapping table */ 761 - u8 lun2card[MAX_ALLOWED_LUN_CNT]; 762 - 763 - int rw_fail_cnt[MAX_ALLOWED_LUN_CNT]; 764 - 765 - int sd_show_cnt; 766 - int xd_show_cnt; 767 - int ms_show_cnt; 768 - 769 - /* card information */ 770 - struct sd_info sd_card; 771 - struct xd_info xd_card; 772 - struct ms_info ms_card; 773 - 774 - struct spi_info spi; 775 - 776 - int auto_delink_cnt; 777 - int auto_delink_allowed; 778 - 779 - int aspm_enabled; 780 - 781 - int sdio_aspm; 782 - int sdio_idle; 783 - int sdio_counter; 784 - u8 sdio_raw_data[12]; 785 - 786 - u8 sd_io; 787 - u8 sd_int; 788 - 789 - u8 rtsx_flag; 790 - 791 - int ss_counter; 792 - int idle_counter; 793 - enum RTSX_STAT rtsx_stat; 794 - 795 - u16 vendor_id; 796 - u16 product_id; 797 - u8 ic_version; 798 - 799 - int driver_first_load; 800 - 801 - #ifdef HW_AUTO_SWITCH_SD_BUS 802 - int sdio_in_charge; 803 - #endif 804 - 805 - u8 aspm_level[2]; 806 - 807 - int chip_insert_with_sdio; 808 - 809 - /* Options */ 810 - 811 - int adma_mode; 812 - 813 - int auto_delink_en; 814 - int ss_en; 815 - u8 lun_mode; 816 - u8 aspm_l0s_l1_en; 817 - 818 - int power_down_in_ss; 819 - 820 - int sdr104_en; 821 - int ddr50_en; 822 - int sdr50_en; 823 - 824 - int baro_pkg; 825 - 826 - int asic_code; 827 - int phy_debug_mode; 828 - int hw_bypass_sd; 829 - int sdio_func_exist; 830 - int aux_pwr_exist; 831 - u8 ms_power_class_en; 832 - 833 - int mspro_formatter_enable; 834 - 835 - int remote_wakeup_en; 836 - 837 - int ignore_sd; 838 - int use_hw_setting; 839 - 840 - int ss_idle_period; 841 - 842 - int dynamic_aspm; 843 - 844 - int fpga_sd_sdr104_clk; 845 - int fpga_sd_ddr50_clk; 846 - int fpga_sd_sdr50_clk; 847 - int fpga_sd_hs_clk; 848 - int fpga_mmc_52m_clk; 849 - int fpga_ms_hg_clk; 850 - int fpga_ms_4bit_clk; 851 - int fpga_ms_1bit_clk; 852 - 853 - int asic_sd_sdr104_clk; 854 - int asic_sd_ddr50_clk; 855 - int asic_sd_sdr50_clk; 856 - int asic_sd_hs_clk; 857 - int asic_mmc_52m_clk; 858 - int asic_ms_hg_clk; 859 - int asic_ms_4bit_clk; 860 - int asic_ms_1bit_clk; 861 - 862 - u8 ssc_depth_sd_sdr104; 863 - u8 ssc_depth_sd_ddr50; 864 - u8 ssc_depth_sd_sdr50; 865 - u8 ssc_depth_sd_hs; 866 - u8 ssc_depth_mmc_52m; 867 - u8 ssc_depth_ms_hg; 868 - u8 ssc_depth_ms_4bit; 869 - u8 ssc_depth_low_speed; 870 - 871 - u8 card_drive_sel; 872 - u8 sd30_drive_sel_1v8; 873 - u8 sd30_drive_sel_3v3; 874 - 875 - u8 sd_400mA_ocp_thd; 876 - u8 sd_800mA_ocp_thd; 877 - u8 ms_ocp_thd; 878 - 879 - int ssc_en; 880 - int msi_en; 881 - 882 - int xd_timeout; 883 - int sd_timeout; 884 - int ms_timeout; 885 - int mspro_timeout; 886 - 887 - int auto_power_down; 888 - 889 - int sd_ddr_tx_phase; 890 - int mmc_ddr_tx_phase; 891 - int sd_default_tx_phase; 892 - int sd_default_rx_phase; 893 - 894 - int pmos_pwr_on_interval; 895 - int sd_voltage_switch_delay; 896 - int s3_pwr_off_delay; 897 - 898 - int force_clkreq_0; 899 - int ft2_fast_mode; 900 - 901 - int do_delink_before_power_down; 902 - int polling_config; 903 - int sdio_retry_cnt; 904 - 905 - int delink_stage1_step; 906 - int delink_stage2_step; 907 - int delink_stage3_step; 908 - 909 - int auto_delink_in_L1; 910 - int hp_watch_bios_hotplug; 911 - int support_ms_8bit; 912 - 913 - u8 blink_led; 914 - u8 phy_voltage; 915 - u8 max_payload; 916 - 917 - u32 sd_speed_prior; 918 - u32 sd_current_prior; 919 - u32 sd_ctl; 920 - }; 921 - 922 - static inline struct device *rtsx_dev(const struct rtsx_chip *chip) 923 - { 924 - return &chip->rtsx->pci->dev; 925 - } 926 - 927 - #define rtsx_set_stat(chip, stat) \ 928 - do { \ 929 - if ((stat) != RTSX_STAT_IDLE) { \ 930 - (chip)->idle_counter = 0; \ 931 - } \ 932 - (chip)->rtsx_stat = (enum RTSX_STAT)(stat); \ 933 - } while (0) 934 - #define rtsx_get_stat(chip) ((chip)->rtsx_stat) 935 - #define rtsx_chk_stat(chip, stat) ((chip)->rtsx_stat == (stat)) 936 - 937 - #define RTSX_SET_DELINK(chip) ((chip)->rtsx_flag |= 0x01) 938 - #define RTSX_CLR_DELINK(chip) ((chip)->rtsx_flag &= 0xFE) 939 - #define RTSX_TST_DELINK(chip) ((chip)->rtsx_flag & 0x01) 940 - 941 - #define CHECK_PID(chip, pid) ((chip)->product_id == (pid)) 942 - #define CHECK_BARO_PKG(chip, pkg) ((chip)->baro_pkg == (pkg)) 943 - #define CHECK_LUN_MODE(chip, mode) ((chip)->lun_mode == (mode)) 944 - 945 - /* Power down control */ 946 - #define SSC_PDCTL 0x01 947 - #define OC_PDCTL 0x02 948 - 949 - int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl); 950 - int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl); 951 - 952 - void rtsx_enable_card_int(struct rtsx_chip *chip); 953 - void rtsx_enable_bus_int(struct rtsx_chip *chip); 954 - void rtsx_disable_bus_int(struct rtsx_chip *chip); 955 - int rtsx_reset_chip(struct rtsx_chip *chip); 956 - int rtsx_init_chip(struct rtsx_chip *chip); 957 - void rtsx_release_chip(struct rtsx_chip *chip); 958 - void rtsx_polling_func(struct rtsx_chip *chip); 959 - void rtsx_stop_cmd(struct rtsx_chip *chip, int card); 960 - int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); 961 - int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data); 962 - int rtsx_write_cfg_dw(struct rtsx_chip *chip, 963 - u8 func_no, u16 addr, u32 mask, u32 val); 964 - int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); 965 - int rtsx_write_cfg_seq(struct rtsx_chip *chip, 966 - u8 func, u16 addr, u8 *buf, int len); 967 - int rtsx_read_cfg_seq(struct rtsx_chip *chip, 968 - u8 func, u16 addr, u8 *buf, int len); 969 - int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); 970 - int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); 971 - int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); 972 - int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); 973 - int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); 974 - int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); 975 - void rtsx_enter_ss(struct rtsx_chip *chip); 976 - void rtsx_exit_ss(struct rtsx_chip *chip); 977 - int rtsx_pre_handle_interrupt(struct rtsx_chip *chip); 978 - void rtsx_enter_L1(struct rtsx_chip *chip); 979 - void rtsx_exit_L1(struct rtsx_chip *chip); 980 - void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat); 981 - void rtsx_enable_aspm(struct rtsx_chip *chip); 982 - void rtsx_disable_aspm(struct rtsx_chip *chip); 983 - int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); 984 - int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); 985 - int rtsx_check_chip_exist(struct rtsx_chip *chip); 986 - 987 - #endif /* __REALTEK_RTSX_CHIP_H */
-3279
drivers/staging/rts5208/rtsx_scsi.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/vmalloc.h> 16 - 17 - #include "rtsx.h" 18 - #include "sd.h" 19 - #include "ms.h" 20 - #include "spi.h" 21 - 22 - void scsi_show_command(struct rtsx_chip *chip) 23 - { 24 - struct scsi_cmnd *srb = chip->srb; 25 - char *what = NULL; 26 - bool unknown_cmd = false; 27 - int len; 28 - 29 - switch (srb->cmnd[0]) { 30 - case TEST_UNIT_READY: 31 - what = "TEST_UNIT_READY"; 32 - break; 33 - case REZERO_UNIT: 34 - what = "REZERO_UNIT"; 35 - break; 36 - case REQUEST_SENSE: 37 - what = "REQUEST_SENSE"; 38 - break; 39 - case FORMAT_UNIT: 40 - what = "FORMAT_UNIT"; 41 - break; 42 - case READ_BLOCK_LIMITS: 43 - what = "READ_BLOCK_LIMITS"; 44 - break; 45 - case REASSIGN_BLOCKS: 46 - what = "REASSIGN_BLOCKS"; 47 - break; 48 - case READ_6: 49 - what = "READ_6"; 50 - break; 51 - case WRITE_6: 52 - what = "WRITE_6"; 53 - break; 54 - case SEEK_6: 55 - what = "SEEK_6"; 56 - break; 57 - case READ_REVERSE: 58 - what = "READ_REVERSE"; 59 - break; 60 - case WRITE_FILEMARKS: 61 - what = "WRITE_FILEMARKS"; 62 - break; 63 - case SPACE: 64 - what = "SPACE"; 65 - break; 66 - case INQUIRY: 67 - what = "INQUIRY"; 68 - break; 69 - case RECOVER_BUFFERED_DATA: 70 - what = "RECOVER_BUFFERED_DATA"; 71 - break; 72 - case MODE_SELECT: 73 - what = "MODE_SELECT"; 74 - break; 75 - case RESERVE: 76 - what = "RESERVE"; 77 - break; 78 - case RELEASE: 79 - what = "RELEASE"; 80 - break; 81 - case COPY: 82 - what = "COPY"; 83 - break; 84 - case ERASE: 85 - what = "ERASE"; 86 - break; 87 - case MODE_SENSE: 88 - what = "MODE_SENSE"; 89 - break; 90 - case START_STOP: 91 - what = "START_STOP"; 92 - break; 93 - case RECEIVE_DIAGNOSTIC: 94 - what = "RECEIVE_DIAGNOSTIC"; 95 - break; 96 - case SEND_DIAGNOSTIC: 97 - what = "SEND_DIAGNOSTIC"; 98 - break; 99 - case ALLOW_MEDIUM_REMOVAL: 100 - what = "ALLOW_MEDIUM_REMOVAL"; 101 - break; 102 - case SET_WINDOW: 103 - what = "SET_WINDOW"; 104 - break; 105 - case READ_CAPACITY: 106 - what = "READ_CAPACITY"; 107 - break; 108 - case READ_10: 109 - what = "READ_10"; 110 - break; 111 - case WRITE_10: 112 - what = "WRITE_10"; 113 - break; 114 - case SEEK_10: 115 - what = "SEEK_10"; 116 - break; 117 - case WRITE_VERIFY: 118 - what = "WRITE_VERIFY"; 119 - break; 120 - case VERIFY: 121 - what = "VERIFY"; 122 - break; 123 - case SEARCH_HIGH: 124 - what = "SEARCH_HIGH"; 125 - break; 126 - case SEARCH_EQUAL: 127 - what = "SEARCH_EQUAL"; 128 - break; 129 - case SEARCH_LOW: 130 - what = "SEARCH_LOW"; 131 - break; 132 - case SET_LIMITS: 133 - what = "SET_LIMITS"; 134 - break; 135 - case READ_POSITION: 136 - what = "READ_POSITION"; 137 - break; 138 - case SYNCHRONIZE_CACHE: 139 - what = "SYNCHRONIZE_CACHE"; 140 - break; 141 - case LOCK_UNLOCK_CACHE: 142 - what = "LOCK_UNLOCK_CACHE"; 143 - break; 144 - case READ_DEFECT_DATA: 145 - what = "READ_DEFECT_DATA"; 146 - break; 147 - case MEDIUM_SCAN: 148 - what = "MEDIUM_SCAN"; 149 - break; 150 - case COMPARE: 151 - what = "COMPARE"; 152 - break; 153 - case COPY_VERIFY: 154 - what = "COPY_VERIFY"; 155 - break; 156 - case WRITE_BUFFER: 157 - what = "WRITE_BUFFER"; 158 - break; 159 - case READ_BUFFER: 160 - what = "READ_BUFFER"; 161 - break; 162 - case UPDATE_BLOCK: 163 - what = "UPDATE_BLOCK"; 164 - break; 165 - case READ_LONG: 166 - what = "READ_LONG"; 167 - break; 168 - case WRITE_LONG: 169 - what = "WRITE_LONG"; 170 - break; 171 - case CHANGE_DEFINITION: 172 - what = "CHANGE_DEFINITION"; 173 - break; 174 - case WRITE_SAME: 175 - what = "WRITE_SAME"; 176 - break; 177 - case GPCMD_READ_SUBCHANNEL: 178 - what = "READ SUBCHANNEL"; 179 - break; 180 - case READ_TOC: 181 - what = "READ_TOC"; 182 - break; 183 - case GPCMD_READ_HEADER: 184 - what = "READ HEADER"; 185 - break; 186 - case GPCMD_PLAY_AUDIO_10: 187 - what = "PLAY AUDIO (10)"; 188 - break; 189 - case GPCMD_PLAY_AUDIO_MSF: 190 - what = "PLAY AUDIO MSF"; 191 - break; 192 - case GPCMD_GET_EVENT_STATUS_NOTIFICATION: 193 - what = "GET EVENT/STATUS NOTIFICATION"; 194 - break; 195 - case GPCMD_PAUSE_RESUME: 196 - what = "PAUSE/RESUME"; 197 - break; 198 - case LOG_SELECT: 199 - what = "LOG_SELECT"; 200 - break; 201 - case LOG_SENSE: 202 - what = "LOG_SENSE"; 203 - break; 204 - case GPCMD_STOP_PLAY_SCAN: 205 - what = "STOP PLAY/SCAN"; 206 - break; 207 - case GPCMD_READ_DISC_INFO: 208 - what = "READ DISC INFORMATION"; 209 - break; 210 - case GPCMD_READ_TRACK_RZONE_INFO: 211 - what = "READ TRACK INFORMATION"; 212 - break; 213 - case GPCMD_RESERVE_RZONE_TRACK: 214 - what = "RESERVE TRACK"; 215 - break; 216 - case GPCMD_SEND_OPC: 217 - what = "SEND OPC"; 218 - break; 219 - case MODE_SELECT_10: 220 - what = "MODE_SELECT_10"; 221 - break; 222 - case GPCMD_REPAIR_RZONE_TRACK: 223 - what = "REPAIR TRACK"; 224 - break; 225 - case 0x59: 226 - what = "READ MASTER CUE"; 227 - break; 228 - case MODE_SENSE_10: 229 - what = "MODE_SENSE_10"; 230 - break; 231 - case GPCMD_CLOSE_TRACK: 232 - what = "CLOSE TRACK/SESSION"; 233 - break; 234 - case 0x5C: 235 - what = "READ BUFFER CAPACITY"; 236 - break; 237 - case 0x5D: 238 - what = "SEND CUE SHEET"; 239 - break; 240 - case GPCMD_BLANK: 241 - what = "BLANK"; 242 - break; 243 - case REPORT_LUNS: 244 - what = "REPORT LUNS"; 245 - break; 246 - case MOVE_MEDIUM: 247 - what = "MOVE_MEDIUM or PLAY AUDIO (12)"; 248 - break; 249 - case READ_12: 250 - what = "READ_12"; 251 - break; 252 - case WRITE_12: 253 - what = "WRITE_12"; 254 - break; 255 - case WRITE_VERIFY_12: 256 - what = "WRITE_VERIFY_12"; 257 - break; 258 - case SEARCH_HIGH_12: 259 - what = "SEARCH_HIGH_12"; 260 - break; 261 - case SEARCH_EQUAL_12: 262 - what = "SEARCH_EQUAL_12"; 263 - break; 264 - case SEARCH_LOW_12: 265 - what = "SEARCH_LOW_12"; 266 - break; 267 - case SEND_VOLUME_TAG: 268 - what = "SEND_VOLUME_TAG"; 269 - break; 270 - case READ_ELEMENT_STATUS: 271 - what = "READ_ELEMENT_STATUS"; 272 - break; 273 - case GPCMD_READ_CD_MSF: 274 - what = "READ CD MSF"; 275 - break; 276 - case GPCMD_SCAN: 277 - what = "SCAN"; 278 - break; 279 - case GPCMD_SET_SPEED: 280 - what = "SET CD SPEED"; 281 - break; 282 - case GPCMD_MECHANISM_STATUS: 283 - what = "MECHANISM STATUS"; 284 - break; 285 - case GPCMD_READ_CD: 286 - what = "READ CD"; 287 - break; 288 - case 0xE1: 289 - what = "WRITE CONTINUE"; 290 - break; 291 - case WRITE_LONG_2: 292 - what = "WRITE_LONG_2"; 293 - break; 294 - case VENDOR_CMND: 295 - what = "Realtek's vendor command"; 296 - break; 297 - default: 298 - what = "(unknown command)"; 299 - unknown_cmd = true; 300 - break; 301 - } 302 - 303 - if (srb->cmnd[0] != TEST_UNIT_READY) 304 - dev_dbg(rtsx_dev(chip), "Command %s (%d bytes)\n", 305 - what, srb->cmd_len); 306 - 307 - if (unknown_cmd) { 308 - len = min_t(unsigned short, srb->cmd_len, 16); 309 - dev_dbg(rtsx_dev(chip), "%*ph\n", len, srb->cmnd); 310 - } 311 - } 312 - 313 - void set_sense_type(struct rtsx_chip *chip, unsigned int lun, int sense_type) 314 - { 315 - switch (sense_type) { 316 - case SENSE_TYPE_MEDIA_CHANGE: 317 - set_sense_data(chip, lun, CUR_ERR, 0x06, 0, 0x28, 0, 0, 0); 318 - break; 319 - 320 - case SENSE_TYPE_MEDIA_NOT_PRESENT: 321 - set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x3A, 0, 0, 0); 322 - break; 323 - 324 - case SENSE_TYPE_MEDIA_LBA_OVER_RANGE: 325 - set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x21, 0, 0, 0); 326 - break; 327 - 328 - case SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT: 329 - set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x25, 0, 0, 0); 330 - break; 331 - 332 - case SENSE_TYPE_MEDIA_WRITE_PROTECT: 333 - set_sense_data(chip, lun, CUR_ERR, 0x07, 0, 0x27, 0, 0, 0); 334 - break; 335 - 336 - case SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR: 337 - set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x11, 0, 0, 0); 338 - break; 339 - 340 - case SENSE_TYPE_MEDIA_WRITE_ERR: 341 - set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x0C, 0x02, 0, 0); 342 - break; 343 - 344 - case SENSE_TYPE_MEDIA_INVALID_CMD_FIELD: 345 - set_sense_data(chip, lun, CUR_ERR, ILGAL_REQ, 0, 346 - ASC_INVLD_CDB, ASCQ_INVLD_CDB, CDB_ILLEGAL, 1); 347 - break; 348 - 349 - case SENSE_TYPE_FORMAT_IN_PROGRESS: 350 - set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04, 0, 0); 351 - break; 352 - 353 - case SENSE_TYPE_FORMAT_CMD_FAILED: 354 - set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x31, 0x01, 0, 0); 355 - break; 356 - 357 - #ifdef SUPPORT_MAGIC_GATE 358 - case SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB: 359 - set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x6F, 0x02, 0, 0); 360 - break; 361 - 362 - case SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN: 363 - set_sense_data(chip, lun, CUR_ERR, 0x05, 0, 0x6F, 0x00, 0, 0); 364 - break; 365 - 366 - case SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM: 367 - set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x30, 0x00, 0, 0); 368 - break; 369 - 370 - case SENSE_TYPE_MG_WRITE_ERR: 371 - set_sense_data(chip, lun, CUR_ERR, 0x03, 0, 0x0C, 0x00, 0, 0); 372 - break; 373 - #endif 374 - 375 - #ifdef SUPPORT_SD_LOCK 376 - case SENSE_TYPE_MEDIA_READ_FORBIDDEN: 377 - set_sense_data(chip, lun, CUR_ERR, 0x07, 0, 0x11, 0x13, 0, 0); 378 - break; 379 - #endif 380 - 381 - case SENSE_TYPE_NO_SENSE: 382 - default: 383 - set_sense_data(chip, lun, CUR_ERR, 0, 0, 0, 0, 0, 0); 384 - break; 385 - } 386 - } 387 - 388 - void set_sense_data(struct rtsx_chip *chip, unsigned int lun, u8 err_code, 389 - u8 sense_key, u32 info, u8 asc, u8 ascq, u8 sns_key_info0, 390 - u16 sns_key_info1) 391 - { 392 - struct sense_data_t *sense = &chip->sense_buffer[lun]; 393 - 394 - sense->err_code = err_code; 395 - sense->sense_key = sense_key; 396 - sense->info[0] = (u8)(info >> 24); 397 - sense->info[1] = (u8)(info >> 16); 398 - sense->info[2] = (u8)(info >> 8); 399 - sense->info[3] = (u8)info; 400 - 401 - sense->ad_sense_len = sizeof(struct sense_data_t) - 8; 402 - sense->asc = asc; 403 - sense->ascq = ascq; 404 - if (sns_key_info0 != 0) { 405 - sense->sns_key_info[0] = SKSV | sns_key_info0; 406 - sense->sns_key_info[1] = (sns_key_info1 & 0xf0) >> 4; 407 - sense->sns_key_info[2] = sns_key_info1 & 0x0f; 408 - } 409 - } 410 - 411 - static int test_unit_ready(struct scsi_cmnd *srb, struct rtsx_chip *chip) 412 - { 413 - unsigned int lun = SCSI_LUN(srb); 414 - 415 - if (!check_card_ready(chip, lun)) { 416 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 417 - return TRANSPORT_FAILED; 418 - } 419 - 420 - if (!(CHK_BIT(chip->lun_mc, lun))) { 421 - SET_BIT(chip->lun_mc, lun); 422 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 423 - return TRANSPORT_FAILED; 424 - } 425 - 426 - #ifdef SUPPORT_SD_LOCK 427 - if (get_lun_card(chip, SCSI_LUN(srb)) == SD_CARD) { 428 - struct sd_info *sd_card = &chip->sd_card; 429 - 430 - if (sd_card->sd_lock_notify) { 431 - sd_card->sd_lock_notify = 0; 432 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 433 - return TRANSPORT_FAILED; 434 - } else if (sd_card->sd_lock_status & SD_LOCKED) { 435 - set_sense_type(chip, lun, 436 - SENSE_TYPE_MEDIA_READ_FORBIDDEN); 437 - return TRANSPORT_FAILED; 438 - } 439 - } 440 - #endif 441 - 442 - return TRANSPORT_GOOD; 443 - } 444 - 445 - static unsigned char formatter_inquiry_str[20] = { 446 - 'M', 'E', 'M', 'O', 'R', 'Y', 'S', 'T', 'I', 'C', 'K', 447 - #ifdef SUPPORT_MAGIC_GATE 448 - '-', 'M', 'G', /* Byte[47:49] */ 449 - #else 450 - 0x20, 0x20, 0x20, /* Byte[47:49] */ 451 - #endif 452 - 453 - #ifdef SUPPORT_MAGIC_GATE 454 - 0x0B, /* Byte[50]: MG, MS, MSPro, MSXC */ 455 - #else 456 - 0x09, /* Byte[50]: MS, MSPro, MSXC */ 457 - #endif 458 - 0x00, /* Byte[51]: Category Specific Commands */ 459 - 0x00, /* Byte[52]: Access Control and feature */ 460 - 0x20, 0x20, 0x20, /* Byte[53:55] */ 461 - }; 462 - 463 - static int inquiry(struct scsi_cmnd *srb, struct rtsx_chip *chip) 464 - { 465 - unsigned int lun = SCSI_LUN(srb); 466 - char *inquiry_default = (char *)"Generic-xD/SD/M.S. 1.00"; 467 - char *inquiry_sdms = (char *)"Generic-SD/MemoryStick 1.00"; 468 - char *inquiry_sd = (char *)"Generic-SD/MMC 1.00"; 469 - char *inquiry_ms = (char *)"Generic-MemoryStick 1.00"; 470 - char *inquiry_string; 471 - unsigned char sendbytes; 472 - unsigned char *buf; 473 - u8 card = get_lun_card(chip, lun); 474 - bool pro_formatter_flag = false; 475 - unsigned char inquiry_buf[] = { 476 - QULIFIRE | DRCT_ACCESS_DEV, 477 - RMB_DISC | 0x0D, 478 - 0x00, 479 - 0x01, 480 - 0x1f, 481 - 0x02, 482 - 0, 483 - REL_ADR | WBUS_32 | WBUS_16 | SYNC | LINKED | CMD_QUE | SFT_RE, 484 - }; 485 - 486 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 487 - if (chip->lun2card[lun] == SD_CARD) 488 - inquiry_string = inquiry_sd; 489 - else 490 - inquiry_string = inquiry_ms; 491 - 492 - } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) { 493 - inquiry_string = inquiry_sdms; 494 - } else { 495 - inquiry_string = inquiry_default; 496 - } 497 - 498 - buf = vmalloc(scsi_bufflen(srb)); 499 - if (!buf) 500 - return TRANSPORT_ERROR; 501 - 502 - #ifdef SUPPORT_MAGIC_GATE 503 - if (chip->mspro_formatter_enable && 504 - (chip->lun2card[lun] & MS_CARD)) 505 - #else 506 - if (chip->mspro_formatter_enable) 507 - #endif 508 - if (!card || card == MS_CARD) 509 - pro_formatter_flag = true; 510 - 511 - if (pro_formatter_flag) { 512 - if (scsi_bufflen(srb) < 56) 513 - sendbytes = (unsigned char)(scsi_bufflen(srb)); 514 - else 515 - sendbytes = 56; 516 - 517 - } else { 518 - if (scsi_bufflen(srb) < 36) 519 - sendbytes = (unsigned char)(scsi_bufflen(srb)); 520 - else 521 - sendbytes = 36; 522 - } 523 - 524 - if (sendbytes > 8) { 525 - memcpy(buf, inquiry_buf, 8); 526 - memcpy(buf + 8, inquiry_string, min(sendbytes, 36) - 8); 527 - if (pro_formatter_flag) { 528 - /* Additional Length */ 529 - buf[4] = 0x33; 530 - } 531 - } else { 532 - memcpy(buf, inquiry_buf, sendbytes); 533 - } 534 - 535 - if (pro_formatter_flag) { 536 - if (sendbytes > 36) 537 - memcpy(buf + 36, formatter_inquiry_str, sendbytes - 36); 538 - } 539 - 540 - scsi_set_resid(srb, 0); 541 - 542 - rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 543 - vfree(buf); 544 - 545 - return TRANSPORT_GOOD; 546 - } 547 - 548 - static int start_stop_unit(struct scsi_cmnd *srb, struct rtsx_chip *chip) 549 - { 550 - unsigned int lun = SCSI_LUN(srb); 551 - 552 - scsi_set_resid(srb, scsi_bufflen(srb)); 553 - 554 - if (srb->cmnd[1] == 1) 555 - return TRANSPORT_GOOD; 556 - 557 - switch (srb->cmnd[0x4]) { 558 - case STOP_MEDIUM: 559 - /* Media disabled */ 560 - return TRANSPORT_GOOD; 561 - 562 - case UNLOAD_MEDIUM: 563 - /* Media shall be unload */ 564 - if (check_card_ready(chip, lun)) 565 - eject_card(chip, lun); 566 - return TRANSPORT_GOOD; 567 - 568 - case MAKE_MEDIUM_READY: 569 - case LOAD_MEDIUM: 570 - if (check_card_ready(chip, lun)) 571 - return TRANSPORT_GOOD; 572 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 573 - return TRANSPORT_FAILED; 574 - 575 - break; 576 - } 577 - 578 - return TRANSPORT_ERROR; 579 - } 580 - 581 - static int allow_medium_removal(struct scsi_cmnd *srb, struct rtsx_chip *chip) 582 - { 583 - int prevent; 584 - 585 - prevent = srb->cmnd[4] & 0x1; 586 - 587 - scsi_set_resid(srb, 0); 588 - 589 - if (prevent) { 590 - set_sense_type(chip, SCSI_LUN(srb), 591 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 592 - return TRANSPORT_FAILED; 593 - } 594 - 595 - return TRANSPORT_GOOD; 596 - } 597 - 598 - static int request_sense(struct scsi_cmnd *srb, struct rtsx_chip *chip) 599 - { 600 - struct sense_data_t *sense; 601 - unsigned int lun = SCSI_LUN(srb); 602 - struct ms_info *ms_card = &chip->ms_card; 603 - unsigned char *tmp, *buf; 604 - 605 - sense = &chip->sense_buffer[lun]; 606 - 607 - if ((get_lun_card(chip, lun) == MS_CARD) && 608 - ms_card->pro_under_formatting) { 609 - if (ms_card->format_status == FORMAT_SUCCESS) { 610 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 611 - ms_card->pro_under_formatting = 0; 612 - ms_card->progress = 0; 613 - } else if (ms_card->format_status == FORMAT_IN_PROGRESS) { 614 - /* Logical Unit Not Ready Format in Progress */ 615 - set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04, 616 - 0, (u16)(ms_card->progress)); 617 - } else { 618 - /* Format Command Failed */ 619 - set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED); 620 - ms_card->pro_under_formatting = 0; 621 - ms_card->progress = 0; 622 - } 623 - 624 - rtsx_set_stat(chip, RTSX_STAT_RUN); 625 - } 626 - 627 - buf = vmalloc(scsi_bufflen(srb)); 628 - if (!buf) 629 - return TRANSPORT_ERROR; 630 - 631 - tmp = (unsigned char *)sense; 632 - memcpy(buf, tmp, scsi_bufflen(srb)); 633 - 634 - rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 635 - vfree(buf); 636 - 637 - scsi_set_resid(srb, 0); 638 - /* Reset Sense Data */ 639 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 640 - return TRANSPORT_GOOD; 641 - } 642 - 643 - static void ms_mode_sense(struct rtsx_chip *chip, u8 cmd, 644 - int lun, u8 *buf, int buf_len) 645 - { 646 - struct ms_info *ms_card = &chip->ms_card; 647 - int sys_info_offset; 648 - int data_size = buf_len; 649 - bool support_format = false; 650 - int i = 0; 651 - 652 - if (cmd == MODE_SENSE) { 653 - sys_info_offset = 8; 654 - if (data_size > 0x68) 655 - data_size = 0x68; 656 - 657 - buf[i++] = 0x67; /* Mode Data Length */ 658 - } else { 659 - sys_info_offset = 12; 660 - if (data_size > 0x6C) 661 - data_size = 0x6C; 662 - 663 - buf[i++] = 0x00; /* Mode Data Length (MSB) */ 664 - buf[i++] = 0x6A; /* Mode Data Length (LSB) */ 665 - } 666 - 667 - /* Medium Type Code */ 668 - if (check_card_ready(chip, lun)) { 669 - if (CHK_MSXC(ms_card)) { 670 - support_format = true; 671 - buf[i++] = 0x40; 672 - } else if (CHK_MSPRO(ms_card)) { 673 - support_format = true; 674 - buf[i++] = 0x20; 675 - } else { 676 - buf[i++] = 0x10; 677 - } 678 - 679 - /* WP */ 680 - if (check_card_wp(chip, lun)) 681 - buf[i++] = 0x80; 682 - else 683 - buf[i++] = 0x00; 684 - 685 - } else { 686 - buf[i++] = 0x00; /* MediaType */ 687 - buf[i++] = 0x00; /* WP */ 688 - } 689 - 690 - buf[i++] = 0x00; /* Reserved */ 691 - 692 - if (cmd == MODE_SENSE_10) { 693 - buf[i++] = 0x00; /* Reserved */ 694 - buf[i++] = 0x00; /* Block descriptor length(MSB) */ 695 - buf[i++] = 0x00; /* Block descriptor length(LSB) */ 696 - 697 - /* The Following Data is the content of "Page 0x20" */ 698 - if (data_size >= 9) 699 - buf[i++] = 0x20; /* Page Code */ 700 - if (data_size >= 10) 701 - buf[i++] = 0x62; /* Page Length */ 702 - if (data_size >= 11) 703 - buf[i++] = 0x00; /* No Access Control */ 704 - if (data_size >= 12) { 705 - if (support_format) 706 - buf[i++] = 0xC0; /* SF, SGM */ 707 - else 708 - buf[i++] = 0x00; 709 - } 710 - } else { 711 - /* The Following Data is the content of "Page 0x20" */ 712 - if (data_size >= 5) 713 - buf[i++] = 0x20; /* Page Code */ 714 - if (data_size >= 6) 715 - buf[i++] = 0x62; /* Page Length */ 716 - if (data_size >= 7) 717 - buf[i++] = 0x00; /* No Access Control */ 718 - if (data_size >= 8) { 719 - if (support_format) 720 - buf[i++] = 0xC0; /* SF, SGM */ 721 - else 722 - buf[i++] = 0x00; 723 - } 724 - } 725 - 726 - if (data_size > sys_info_offset) { 727 - /* 96 Bytes Attribute Data */ 728 - int len = data_size - sys_info_offset; 729 - 730 - len = (len < 96) ? len : 96; 731 - 732 - memcpy(buf + sys_info_offset, ms_card->raw_sys_info, len); 733 - } 734 - } 735 - 736 - static int mode_sense(struct scsi_cmnd *srb, struct rtsx_chip *chip) 737 - { 738 - unsigned int lun = SCSI_LUN(srb); 739 - unsigned int data_size; 740 - int status; 741 - bool pro_formatter_flag; 742 - unsigned char page_code, *buf; 743 - u8 card = get_lun_card(chip, lun); 744 - 745 - #ifndef SUPPORT_MAGIC_GATE 746 - if (!check_card_ready(chip, lun)) { 747 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 748 - scsi_set_resid(srb, scsi_bufflen(srb)); 749 - return TRANSPORT_FAILED; 750 - } 751 - #endif 752 - 753 - pro_formatter_flag = false; 754 - data_size = 8; 755 - #ifdef SUPPORT_MAGIC_GATE 756 - if ((chip->lun2card[lun] & MS_CARD)) { 757 - if (!card || card == MS_CARD) { 758 - data_size = 108; 759 - if (chip->mspro_formatter_enable) 760 - pro_formatter_flag = true; 761 - } 762 - } 763 - #else 764 - if (card == MS_CARD) { 765 - if (chip->mspro_formatter_enable) { 766 - pro_formatter_flag = true; 767 - data_size = 108; 768 - } 769 - } 770 - #endif 771 - 772 - buf = kmalloc(data_size, GFP_KERNEL); 773 - if (!buf) 774 - return TRANSPORT_ERROR; 775 - 776 - page_code = srb->cmnd[2] & 0x3f; 777 - 778 - if (page_code == 0x3F || page_code == 0x1C || 779 - page_code == 0x00 || 780 - (pro_formatter_flag && page_code == 0x20)) { 781 - if (srb->cmnd[0] == MODE_SENSE) { 782 - if (page_code == 0x3F || page_code == 0x20) { 783 - ms_mode_sense(chip, srb->cmnd[0], 784 - lun, buf, data_size); 785 - } else { 786 - data_size = 4; 787 - buf[0] = 0x03; 788 - buf[1] = 0x00; 789 - if (check_card_wp(chip, lun)) 790 - buf[2] = 0x80; 791 - else 792 - buf[2] = 0x00; 793 - 794 - buf[3] = 0x00; 795 - } 796 - } else { 797 - if (page_code == 0x3F || page_code == 0x20) { 798 - ms_mode_sense(chip, srb->cmnd[0], 799 - lun, buf, data_size); 800 - } else { 801 - data_size = 8; 802 - buf[0] = 0x00; 803 - buf[1] = 0x06; 804 - buf[2] = 0x00; 805 - if (check_card_wp(chip, lun)) 806 - buf[3] = 0x80; 807 - else 808 - buf[3] = 0x00; 809 - buf[4] = 0x00; 810 - buf[5] = 0x00; 811 - buf[6] = 0x00; 812 - buf[7] = 0x00; 813 - } 814 - } 815 - status = TRANSPORT_GOOD; 816 - } else { 817 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 818 - scsi_set_resid(srb, scsi_bufflen(srb)); 819 - status = TRANSPORT_FAILED; 820 - } 821 - 822 - if (status == TRANSPORT_GOOD) { 823 - unsigned int len = min_t(unsigned int, scsi_bufflen(srb), 824 - data_size); 825 - rtsx_stor_set_xfer_buf(buf, len, srb); 826 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 827 - } 828 - kfree(buf); 829 - 830 - return status; 831 - } 832 - 833 - static int read_write(struct scsi_cmnd *srb, struct rtsx_chip *chip) 834 - { 835 - #ifdef SUPPORT_SD_LOCK 836 - struct sd_info *sd_card = &chip->sd_card; 837 - #endif 838 - unsigned int lun = SCSI_LUN(srb); 839 - int retval; 840 - u32 start_sec; 841 - u16 sec_cnt; 842 - 843 - rtsx_disable_aspm(chip); 844 - 845 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 846 - rtsx_exit_ss(chip); 847 - wait_timeout(100); 848 - } 849 - rtsx_set_stat(chip, RTSX_STAT_RUN); 850 - 851 - if (!check_card_ready(chip, lun) || (get_card_size(chip, lun) == 0)) { 852 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 853 - return TRANSPORT_FAILED; 854 - } 855 - 856 - if (!(CHK_BIT(chip->lun_mc, lun))) { 857 - SET_BIT(chip->lun_mc, lun); 858 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 859 - return TRANSPORT_FAILED; 860 - } 861 - 862 - #ifdef SUPPORT_SD_LOCK 863 - if (sd_card->sd_erase_status) { 864 - /* Accessing to any card is forbidden 865 - * until the erase procedure of SD is completed 866 - */ 867 - dev_dbg(rtsx_dev(chip), "SD card being erased!\n"); 868 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_READ_FORBIDDEN); 869 - return TRANSPORT_FAILED; 870 - } 871 - 872 - if (get_lun_card(chip, lun) == SD_CARD) { 873 - if (sd_card->sd_lock_status & SD_LOCKED) { 874 - dev_dbg(rtsx_dev(chip), "SD card locked!\n"); 875 - set_sense_type(chip, lun, 876 - SENSE_TYPE_MEDIA_READ_FORBIDDEN); 877 - return TRANSPORT_FAILED; 878 - } 879 - } 880 - #endif 881 - 882 - if (srb->cmnd[0] == READ_10 || srb->cmnd[0] == WRITE_10) { 883 - start_sec = ((u32)srb->cmnd[2] << 24) | 884 - ((u32)srb->cmnd[3] << 16) | 885 - ((u32)srb->cmnd[4] << 8) | ((u32)srb->cmnd[5]); 886 - sec_cnt = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 887 - } else if ((srb->cmnd[0] == READ_6) || (srb->cmnd[0] == WRITE_6)) { 888 - start_sec = ((u32)(srb->cmnd[1] & 0x1F) << 16) | 889 - ((u32)srb->cmnd[2] << 8) | ((u32)srb->cmnd[3]); 890 - sec_cnt = srb->cmnd[4]; 891 - if (sec_cnt == 0) 892 - sec_cnt = 256; 893 - } else if ((srb->cmnd[0] == VENDOR_CMND) && 894 - (srb->cmnd[1] == SCSI_APP_CMD) && 895 - ((srb->cmnd[2] == PP_READ10) || (srb->cmnd[2] == PP_WRITE10))) { 896 - start_sec = ((u32)srb->cmnd[4] << 24) | 897 - ((u32)srb->cmnd[5] << 16) | 898 - ((u32)srb->cmnd[6] << 8) | ((u32)srb->cmnd[7]); 899 - sec_cnt = ((u16)(srb->cmnd[9]) << 8) | srb->cmnd[10]; 900 - } else { 901 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 902 - return TRANSPORT_FAILED; 903 - } 904 - 905 - /* In some test, we will receive a start_sec like 0xFFFFFFFF. 906 - * In this situation, start_sec + sec_cnt will overflow, so we 907 - * need to judge start_sec at first 908 - */ 909 - if (start_sec > get_card_size(chip, lun) || 910 - ((start_sec + sec_cnt) > get_card_size(chip, lun))) { 911 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LBA_OVER_RANGE); 912 - return TRANSPORT_FAILED; 913 - } 914 - 915 - if (sec_cnt == 0) { 916 - scsi_set_resid(srb, 0); 917 - return TRANSPORT_GOOD; 918 - } 919 - 920 - if (chip->rw_fail_cnt[lun] == 3) { 921 - dev_dbg(rtsx_dev(chip), "read/write fail three times in succession\n"); 922 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 923 - set_sense_type(chip, lun, 924 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 925 - else 926 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 927 - 928 - return TRANSPORT_FAILED; 929 - } 930 - 931 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 932 - if (check_card_wp(chip, lun)) { 933 - dev_dbg(rtsx_dev(chip), "Write protected card!\n"); 934 - set_sense_type(chip, lun, 935 - SENSE_TYPE_MEDIA_WRITE_PROTECT); 936 - return TRANSPORT_FAILED; 937 - } 938 - } 939 - 940 - retval = card_rw(srb, chip, start_sec, sec_cnt); 941 - if (retval != STATUS_SUCCESS) { 942 - if (chip->need_release & chip->lun2card[lun]) { 943 - chip->rw_fail_cnt[lun] = 0; 944 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 945 - } else { 946 - chip->rw_fail_cnt[lun]++; 947 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 948 - set_sense_type 949 - (chip, lun, 950 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 951 - else 952 - set_sense_type(chip, lun, 953 - SENSE_TYPE_MEDIA_WRITE_ERR); 954 - } 955 - retval = TRANSPORT_FAILED; 956 - goto exit; 957 - } else { 958 - chip->rw_fail_cnt[lun] = 0; 959 - retval = TRANSPORT_GOOD; 960 - } 961 - 962 - scsi_set_resid(srb, 0); 963 - 964 - exit: 965 - return retval; 966 - } 967 - 968 - static int read_format_capacity(struct scsi_cmnd *srb, struct rtsx_chip *chip) 969 - { 970 - unsigned char *buf; 971 - unsigned int lun = SCSI_LUN(srb); 972 - unsigned int buf_len; 973 - u8 card = get_lun_card(chip, lun); 974 - u32 card_size; 975 - int desc_cnt; 976 - int i = 0; 977 - 978 - if (!check_card_ready(chip, lun)) { 979 - if (!chip->mspro_formatter_enable) { 980 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 981 - return TRANSPORT_FAILED; 982 - } 983 - } 984 - 985 - buf_len = (scsi_bufflen(srb) > 12) ? 0x14 : 12; 986 - 987 - buf = kmalloc(buf_len, GFP_KERNEL); 988 - if (!buf) 989 - return TRANSPORT_ERROR; 990 - 991 - buf[i++] = 0; 992 - buf[i++] = 0; 993 - buf[i++] = 0; 994 - 995 - /* Capacity List Length */ 996 - if (buf_len > 12 && chip->mspro_formatter_enable && 997 - (chip->lun2card[lun] & MS_CARD) && 998 - (!card || card == MS_CARD)) { 999 - buf[i++] = 0x10; 1000 - desc_cnt = 2; 1001 - } else { 1002 - buf[i++] = 0x08; 1003 - desc_cnt = 1; 1004 - } 1005 - 1006 - while (desc_cnt) { 1007 - if (check_card_ready(chip, lun)) { 1008 - card_size = get_card_size(chip, lun); 1009 - buf[i++] = (unsigned char)(card_size >> 24); 1010 - buf[i++] = (unsigned char)(card_size >> 16); 1011 - buf[i++] = (unsigned char)(card_size >> 8); 1012 - buf[i++] = (unsigned char)card_size; 1013 - 1014 - if (desc_cnt == 2) 1015 - buf[i++] = 2; 1016 - else 1017 - buf[i++] = 0; 1018 - } else { 1019 - buf[i++] = 0xFF; 1020 - buf[i++] = 0xFF; 1021 - buf[i++] = 0xFF; 1022 - buf[i++] = 0xFF; 1023 - 1024 - if (desc_cnt == 2) 1025 - buf[i++] = 3; 1026 - else 1027 - buf[i++] = 0; 1028 - } 1029 - 1030 - buf[i++] = 0x00; 1031 - buf[i++] = 0x02; 1032 - buf[i++] = 0x00; 1033 - 1034 - desc_cnt--; 1035 - } 1036 - 1037 - buf_len = min_t(unsigned int, scsi_bufflen(srb), buf_len); 1038 - rtsx_stor_set_xfer_buf(buf, buf_len, srb); 1039 - kfree(buf); 1040 - 1041 - scsi_set_resid(srb, scsi_bufflen(srb) - buf_len); 1042 - 1043 - return TRANSPORT_GOOD; 1044 - } 1045 - 1046 - static int read_capacity(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1047 - { 1048 - unsigned char *buf; 1049 - unsigned int lun = SCSI_LUN(srb); 1050 - u32 card_size; 1051 - 1052 - if (!check_card_ready(chip, lun)) { 1053 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1054 - return TRANSPORT_FAILED; 1055 - } 1056 - 1057 - if (!(CHK_BIT(chip->lun_mc, lun))) { 1058 - SET_BIT(chip->lun_mc, lun); 1059 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 1060 - return TRANSPORT_FAILED; 1061 - } 1062 - 1063 - buf = kmalloc(8, GFP_KERNEL); 1064 - if (!buf) 1065 - return TRANSPORT_ERROR; 1066 - 1067 - card_size = get_card_size(chip, lun); 1068 - buf[0] = (unsigned char)((card_size - 1) >> 24); 1069 - buf[1] = (unsigned char)((card_size - 1) >> 16); 1070 - buf[2] = (unsigned char)((card_size - 1) >> 8); 1071 - buf[3] = (unsigned char)(card_size - 1); 1072 - 1073 - buf[4] = 0x00; 1074 - buf[5] = 0x00; 1075 - buf[6] = 0x02; 1076 - buf[7] = 0x00; 1077 - 1078 - rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 1079 - kfree(buf); 1080 - 1081 - scsi_set_resid(srb, 0); 1082 - 1083 - return TRANSPORT_GOOD; 1084 - } 1085 - 1086 - static int read_eeprom(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1087 - { 1088 - unsigned short len, i; 1089 - int retval; 1090 - u8 *buf; 1091 - 1092 - rtsx_disable_aspm(chip); 1093 - 1094 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1095 - rtsx_exit_ss(chip); 1096 - wait_timeout(100); 1097 - } 1098 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1099 - 1100 - len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1101 - 1102 - buf = vmalloc(len); 1103 - if (!buf) 1104 - return TRANSPORT_ERROR; 1105 - 1106 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1107 - if (retval != STATUS_SUCCESS) { 1108 - vfree(buf); 1109 - set_sense_type(chip, SCSI_LUN(srb), 1110 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1111 - return TRANSPORT_FAILED; 1112 - } 1113 - 1114 - for (i = 0; i < len; i++) { 1115 - retval = spi_read_eeprom(chip, i, buf + i); 1116 - if (retval != STATUS_SUCCESS) { 1117 - vfree(buf); 1118 - set_sense_type(chip, SCSI_LUN(srb), 1119 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1120 - return TRANSPORT_FAILED; 1121 - } 1122 - } 1123 - 1124 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 1125 - rtsx_stor_set_xfer_buf(buf, len, srb); 1126 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1127 - 1128 - vfree(buf); 1129 - 1130 - return TRANSPORT_GOOD; 1131 - } 1132 - 1133 - static int write_eeprom(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1134 - { 1135 - unsigned short len, i; 1136 - int retval; 1137 - u8 *buf; 1138 - 1139 - rtsx_disable_aspm(chip); 1140 - 1141 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1142 - rtsx_exit_ss(chip); 1143 - wait_timeout(100); 1144 - } 1145 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1146 - 1147 - len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1148 - 1149 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1150 - if (retval != STATUS_SUCCESS) { 1151 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 1152 - return TRANSPORT_FAILED; 1153 - } 1154 - 1155 - if (len == 511) { 1156 - retval = spi_erase_eeprom_chip(chip); 1157 - if (retval != STATUS_SUCCESS) { 1158 - set_sense_type(chip, SCSI_LUN(srb), 1159 - SENSE_TYPE_MEDIA_WRITE_ERR); 1160 - return TRANSPORT_FAILED; 1161 - } 1162 - } else { 1163 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), 1164 - len); 1165 - buf = vmalloc(len); 1166 - if (!buf) 1167 - return TRANSPORT_ERROR; 1168 - 1169 - rtsx_stor_get_xfer_buf(buf, len, srb); 1170 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1171 - 1172 - for (i = 0; i < len; i++) { 1173 - retval = spi_write_eeprom(chip, i, buf[i]); 1174 - if (retval != STATUS_SUCCESS) { 1175 - vfree(buf); 1176 - set_sense_type(chip, SCSI_LUN(srb), 1177 - SENSE_TYPE_MEDIA_WRITE_ERR); 1178 - return TRANSPORT_FAILED; 1179 - } 1180 - } 1181 - 1182 - vfree(buf); 1183 - } 1184 - 1185 - return TRANSPORT_GOOD; 1186 - } 1187 - 1188 - static int read_mem(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1189 - { 1190 - unsigned short addr, len, i; 1191 - int retval; 1192 - u8 *buf; 1193 - 1194 - rtsx_disable_aspm(chip); 1195 - 1196 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1197 - rtsx_exit_ss(chip); 1198 - wait_timeout(100); 1199 - } 1200 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1201 - 1202 - addr = ((u16)srb->cmnd[2] << 8) | srb->cmnd[3]; 1203 - len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1204 - 1205 - if (addr < 0xFC00) { 1206 - set_sense_type(chip, SCSI_LUN(srb), 1207 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1208 - return TRANSPORT_FAILED; 1209 - } 1210 - 1211 - buf = vmalloc(len); 1212 - if (!buf) 1213 - return TRANSPORT_ERROR; 1214 - 1215 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1216 - if (retval != STATUS_SUCCESS) { 1217 - vfree(buf); 1218 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 1219 - return TRANSPORT_FAILED; 1220 - } 1221 - 1222 - for (i = 0; i < len; i++) { 1223 - retval = rtsx_read_register(chip, addr + i, buf + i); 1224 - if (retval != STATUS_SUCCESS) { 1225 - vfree(buf); 1226 - set_sense_type(chip, SCSI_LUN(srb), 1227 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1228 - return TRANSPORT_FAILED; 1229 - } 1230 - } 1231 - 1232 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 1233 - rtsx_stor_set_xfer_buf(buf, len, srb); 1234 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1235 - 1236 - vfree(buf); 1237 - 1238 - return TRANSPORT_GOOD; 1239 - } 1240 - 1241 - static int write_mem(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1242 - { 1243 - unsigned short addr, len, i; 1244 - int retval; 1245 - u8 *buf; 1246 - 1247 - rtsx_disable_aspm(chip); 1248 - 1249 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1250 - rtsx_exit_ss(chip); 1251 - wait_timeout(100); 1252 - } 1253 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1254 - 1255 - addr = ((u16)srb->cmnd[2] << 8) | srb->cmnd[3]; 1256 - len = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1257 - 1258 - if (addr < 0xFC00) { 1259 - set_sense_type(chip, SCSI_LUN(srb), 1260 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1261 - return TRANSPORT_FAILED; 1262 - } 1263 - 1264 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 1265 - buf = vmalloc(len); 1266 - if (!buf) 1267 - return TRANSPORT_ERROR; 1268 - 1269 - rtsx_stor_get_xfer_buf(buf, len, srb); 1270 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1271 - 1272 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1273 - if (retval != STATUS_SUCCESS) { 1274 - vfree(buf); 1275 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 1276 - return TRANSPORT_FAILED; 1277 - } 1278 - 1279 - for (i = 0; i < len; i++) { 1280 - retval = rtsx_write_register(chip, addr + i, 0xFF, buf[i]); 1281 - if (retval != STATUS_SUCCESS) { 1282 - vfree(buf); 1283 - set_sense_type(chip, SCSI_LUN(srb), 1284 - SENSE_TYPE_MEDIA_WRITE_ERR); 1285 - return TRANSPORT_FAILED; 1286 - } 1287 - } 1288 - 1289 - vfree(buf); 1290 - 1291 - return TRANSPORT_GOOD; 1292 - } 1293 - 1294 - static int get_sd_csd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1295 - { 1296 - struct sd_info *sd_card = &chip->sd_card; 1297 - unsigned int lun = SCSI_LUN(srb); 1298 - 1299 - if (!check_card_ready(chip, lun)) { 1300 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1301 - return TRANSPORT_FAILED; 1302 - } 1303 - 1304 - if (get_lun_card(chip, lun) != SD_CARD) { 1305 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1306 - return TRANSPORT_FAILED; 1307 - } 1308 - 1309 - scsi_set_resid(srb, 0); 1310 - rtsx_stor_set_xfer_buf(sd_card->raw_csd, scsi_bufflen(srb), srb); 1311 - 1312 - return TRANSPORT_GOOD; 1313 - } 1314 - 1315 - static int toggle_gpio_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1316 - { 1317 - u8 gpio = srb->cmnd[2]; 1318 - 1319 - rtsx_disable_aspm(chip); 1320 - 1321 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1322 - rtsx_exit_ss(chip); 1323 - wait_timeout(100); 1324 - } 1325 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1326 - 1327 - if (gpio > 3) 1328 - gpio = 1; 1329 - toggle_gpio(chip, gpio); 1330 - 1331 - return TRANSPORT_GOOD; 1332 - } 1333 - 1334 - static int read_host_reg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1335 - { 1336 - u8 addr, buf[4]; 1337 - u32 val; 1338 - unsigned int len; 1339 - 1340 - rtsx_disable_aspm(chip); 1341 - 1342 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1343 - rtsx_exit_ss(chip); 1344 - wait_timeout(100); 1345 - } 1346 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1347 - 1348 - addr = srb->cmnd[4]; 1349 - 1350 - val = rtsx_readl(chip, addr); 1351 - dev_dbg(rtsx_dev(chip), "Host register (0x%x): 0x%x\n", addr, val); 1352 - 1353 - buf[0] = (u8)(val >> 24); 1354 - buf[1] = (u8)(val >> 16); 1355 - buf[2] = (u8)(val >> 8); 1356 - buf[3] = (u8)val; 1357 - 1358 - len = min_t(unsigned int, scsi_bufflen(srb), 4); 1359 - rtsx_stor_set_xfer_buf(buf, len, srb); 1360 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1361 - 1362 - return TRANSPORT_GOOD; 1363 - } 1364 - 1365 - static int write_host_reg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1366 - { 1367 - u8 addr, buf[4]; 1368 - u32 val; 1369 - unsigned int len; 1370 - 1371 - rtsx_disable_aspm(chip); 1372 - 1373 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1374 - rtsx_exit_ss(chip); 1375 - wait_timeout(100); 1376 - } 1377 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1378 - 1379 - addr = srb->cmnd[4]; 1380 - 1381 - len = min_t(unsigned int, scsi_bufflen(srb), 4); 1382 - rtsx_stor_get_xfer_buf(buf, len, srb); 1383 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1384 - 1385 - val = ((u32)buf[0] << 24) | ((u32)buf[1] << 16) | ((u32)buf[2] 1386 - << 8) | buf[3]; 1387 - 1388 - rtsx_writel(chip, addr, val); 1389 - 1390 - return TRANSPORT_GOOD; 1391 - } 1392 - 1393 - static int set_variable(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1394 - { 1395 - unsigned int lun = SCSI_LUN(srb); 1396 - 1397 - if (srb->cmnd[3] == 1) { 1398 - /* Variable Clock */ 1399 - struct xd_info *xd_card = &chip->xd_card; 1400 - struct sd_info *sd_card = &chip->sd_card; 1401 - struct ms_info *ms_card = &chip->ms_card; 1402 - 1403 - switch (srb->cmnd[4]) { 1404 - case XD_CARD: 1405 - xd_card->xd_clock = srb->cmnd[5]; 1406 - break; 1407 - 1408 - case SD_CARD: 1409 - sd_card->sd_clock = srb->cmnd[5]; 1410 - break; 1411 - 1412 - case MS_CARD: 1413 - ms_card->ms_clock = srb->cmnd[5]; 1414 - break; 1415 - 1416 - default: 1417 - set_sense_type(chip, lun, 1418 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1419 - return TRANSPORT_FAILED; 1420 - } 1421 - } else if (srb->cmnd[3] == 2) { 1422 - if (srb->cmnd[4]) { 1423 - chip->blink_led = 1; 1424 - } else { 1425 - int retval; 1426 - 1427 - chip->blink_led = 0; 1428 - 1429 - rtsx_disable_aspm(chip); 1430 - 1431 - if (chip->ss_en && 1432 - (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1433 - rtsx_exit_ss(chip); 1434 - wait_timeout(100); 1435 - } 1436 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1437 - 1438 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1439 - if (retval != STATUS_SUCCESS) { 1440 - set_sense_type(chip, SCSI_LUN(srb), 1441 - SENSE_TYPE_MEDIA_WRITE_ERR); 1442 - return TRANSPORT_FAILED; 1443 - } 1444 - 1445 - turn_off_led(chip, LED_GPIO); 1446 - } 1447 - } else { 1448 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1449 - return TRANSPORT_FAILED; 1450 - } 1451 - 1452 - return TRANSPORT_GOOD; 1453 - } 1454 - 1455 - static int get_variable(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1456 - { 1457 - unsigned int lun = SCSI_LUN(srb); 1458 - 1459 - if (srb->cmnd[3] == 1) { 1460 - struct xd_info *xd_card = &chip->xd_card; 1461 - struct sd_info *sd_card = &chip->sd_card; 1462 - struct ms_info *ms_card = &chip->ms_card; 1463 - u8 tmp; 1464 - 1465 - switch (srb->cmnd[4]) { 1466 - case XD_CARD: 1467 - tmp = (u8)(xd_card->xd_clock); 1468 - break; 1469 - 1470 - case SD_CARD: 1471 - tmp = (u8)(sd_card->sd_clock); 1472 - break; 1473 - 1474 - case MS_CARD: 1475 - tmp = (u8)(ms_card->ms_clock); 1476 - break; 1477 - 1478 - default: 1479 - set_sense_type(chip, lun, 1480 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1481 - return TRANSPORT_FAILED; 1482 - } 1483 - 1484 - rtsx_stor_set_xfer_buf(&tmp, 1, srb); 1485 - } else if (srb->cmnd[3] == 2) { 1486 - u8 tmp = chip->blink_led; 1487 - 1488 - rtsx_stor_set_xfer_buf(&tmp, 1, srb); 1489 - } else { 1490 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1491 - return TRANSPORT_FAILED; 1492 - } 1493 - 1494 - return TRANSPORT_GOOD; 1495 - } 1496 - 1497 - static int dma_access_ring_buffer(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1498 - { 1499 - int retval; 1500 - unsigned int lun = SCSI_LUN(srb); 1501 - u16 len; 1502 - 1503 - rtsx_disable_aspm(chip); 1504 - 1505 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1506 - rtsx_exit_ss(chip); 1507 - wait_timeout(100); 1508 - } 1509 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1510 - 1511 - len = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 1512 - len = min_t(u16, len, scsi_bufflen(srb)); 1513 - 1514 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 1515 - dev_dbg(rtsx_dev(chip), "Read from device\n"); 1516 - else 1517 - dev_dbg(rtsx_dev(chip), "Write to device\n"); 1518 - 1519 - retval = rtsx_transfer_data(chip, 0, scsi_sglist(srb), len, 1520 - scsi_sg_count(srb), srb->sc_data_direction, 1521 - 1000); 1522 - if (retval < 0) { 1523 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 1524 - set_sense_type(chip, lun, 1525 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1526 - else 1527 - set_sense_type(chip, lun, 1528 - SENSE_TYPE_MEDIA_WRITE_ERR); 1529 - 1530 - return TRANSPORT_FAILED; 1531 - } 1532 - scsi_set_resid(srb, 0); 1533 - 1534 - return TRANSPORT_GOOD; 1535 - } 1536 - 1537 - static int get_dev_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1538 - { 1539 - struct sd_info *sd_card = &chip->sd_card; 1540 - struct ms_info *ms_card = &chip->ms_card; 1541 - int buf_len; 1542 - unsigned int lun = SCSI_LUN(srb); 1543 - u8 card = get_lun_card(chip, lun); 1544 - u8 status[32]; 1545 - #ifdef SUPPORT_OCP 1546 - u8 oc_now_mask = 0, oc_ever_mask = 0; 1547 - #endif 1548 - 1549 - memset(status, 0, 32); 1550 - 1551 - status[0] = (u8)(chip->product_id); 1552 - status[1] = chip->ic_version; 1553 - 1554 - if (chip->auto_delink_en) 1555 - status[2] = 0x10; 1556 - else 1557 - status[2] = 0x00; 1558 - 1559 - status[3] = 20; 1560 - status[4] = 10; 1561 - status[5] = 05; 1562 - status[6] = 21; 1563 - 1564 - if (chip->card_wp) 1565 - status[7] = 0x20; 1566 - else 1567 - status[7] = 0x00; 1568 - 1569 - #ifdef SUPPORT_OCP 1570 - status[8] = 0; 1571 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && 1572 - chip->lun2card[lun] == MS_CARD) { 1573 - oc_now_mask = MS_OC_NOW; 1574 - oc_ever_mask = MS_OC_EVER; 1575 - } else { 1576 - oc_now_mask = SD_OC_NOW; 1577 - oc_ever_mask = SD_OC_EVER; 1578 - } 1579 - 1580 - if (chip->ocp_stat & oc_now_mask) 1581 - status[8] |= 0x02; 1582 - 1583 - if (chip->ocp_stat & oc_ever_mask) 1584 - status[8] |= 0x01; 1585 - #endif 1586 - 1587 - if (card == SD_CARD) { 1588 - if (CHK_SD(sd_card)) { 1589 - if (CHK_SD_HCXC(sd_card)) { 1590 - if (sd_card->capacity > 0x4000000) 1591 - status[0x0E] = 0x02; 1592 - else 1593 - status[0x0E] = 0x01; 1594 - } else { 1595 - status[0x0E] = 0x00; 1596 - } 1597 - 1598 - if (CHK_SD_SDR104(sd_card)) 1599 - status[0x0F] = 0x03; 1600 - else if (CHK_SD_DDR50(sd_card)) 1601 - status[0x0F] = 0x04; 1602 - else if (CHK_SD_SDR50(sd_card)) 1603 - status[0x0F] = 0x02; 1604 - else if (CHK_SD_HS(sd_card)) 1605 - status[0x0F] = 0x01; 1606 - else 1607 - status[0x0F] = 0x00; 1608 - } else { 1609 - if (CHK_MMC_SECTOR_MODE(sd_card)) 1610 - status[0x0E] = 0x01; 1611 - else 1612 - status[0x0E] = 0x00; 1613 - 1614 - if (CHK_MMC_DDR52(sd_card)) 1615 - status[0x0F] = 0x03; 1616 - else if (CHK_MMC_52M(sd_card)) 1617 - status[0x0F] = 0x02; 1618 - else if (CHK_MMC_26M(sd_card)) 1619 - status[0x0F] = 0x01; 1620 - else 1621 - status[0x0F] = 0x00; 1622 - } 1623 - } else if (card == MS_CARD) { 1624 - if (CHK_MSPRO(ms_card)) { 1625 - if (CHK_MSXC(ms_card)) 1626 - status[0x0E] = 0x01; 1627 - else 1628 - status[0x0E] = 0x00; 1629 - 1630 - if (CHK_HG8BIT(ms_card)) 1631 - status[0x0F] = 0x01; 1632 - else 1633 - status[0x0F] = 0x00; 1634 - } 1635 - } 1636 - 1637 - #ifdef SUPPORT_SD_LOCK 1638 - if (card == SD_CARD) { 1639 - status[0x17] = 0x80; 1640 - if (sd_card->sd_erase_status) 1641 - status[0x17] |= 0x01; 1642 - if (sd_card->sd_lock_status & SD_LOCKED) { 1643 - status[0x17] |= 0x02; 1644 - status[0x07] |= 0x40; 1645 - } 1646 - if (sd_card->sd_lock_status & SD_PWD_EXIST) 1647 - status[0x17] |= 0x04; 1648 - } else { 1649 - status[0x17] = 0x00; 1650 - } 1651 - 1652 - dev_dbg(rtsx_dev(chip), "status[0x17] = 0x%x\n", status[0x17]); 1653 - #endif 1654 - 1655 - status[0x18] = 0x8A; 1656 - status[0x1A] = 0x28; 1657 - #ifdef SUPPORT_SD_LOCK 1658 - status[0x1F] = 0x01; 1659 - #endif 1660 - 1661 - buf_len = min_t(unsigned int, scsi_bufflen(srb), sizeof(status)); 1662 - rtsx_stor_set_xfer_buf(status, buf_len, srb); 1663 - scsi_set_resid(srb, scsi_bufflen(srb) - buf_len); 1664 - 1665 - return TRANSPORT_GOOD; 1666 - } 1667 - 1668 - static int set_chip_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1669 - { 1670 - int phy_debug_mode; 1671 - int retval; 1672 - u16 reg; 1673 - 1674 - if (!CHECK_PID(chip, 0x5208)) { 1675 - set_sense_type(chip, SCSI_LUN(srb), 1676 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1677 - return TRANSPORT_FAILED; 1678 - } 1679 - 1680 - phy_debug_mode = (int)(srb->cmnd[3]); 1681 - 1682 - if (phy_debug_mode) { 1683 - chip->phy_debug_mode = 1; 1684 - retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); 1685 - if (retval != STATUS_SUCCESS) 1686 - return TRANSPORT_FAILED; 1687 - 1688 - rtsx_disable_bus_int(chip); 1689 - 1690 - retval = rtsx_read_phy_register(chip, 0x1C, &reg); 1691 - if (retval != STATUS_SUCCESS) 1692 - return TRANSPORT_FAILED; 1693 - 1694 - reg |= 0x0001; 1695 - retval = rtsx_write_phy_register(chip, 0x1C, reg); 1696 - if (retval != STATUS_SUCCESS) 1697 - return TRANSPORT_FAILED; 1698 - } else { 1699 - chip->phy_debug_mode = 0; 1700 - retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0x77); 1701 - if (retval != STATUS_SUCCESS) 1702 - return TRANSPORT_FAILED; 1703 - 1704 - rtsx_enable_bus_int(chip); 1705 - 1706 - retval = rtsx_read_phy_register(chip, 0x1C, &reg); 1707 - if (retval != STATUS_SUCCESS) 1708 - return TRANSPORT_FAILED; 1709 - 1710 - reg &= 0xFFFE; 1711 - retval = rtsx_write_phy_register(chip, 0x1C, reg); 1712 - if (retval != STATUS_SUCCESS) 1713 - return TRANSPORT_FAILED; 1714 - } 1715 - 1716 - return TRANSPORT_GOOD; 1717 - } 1718 - 1719 - static int rw_mem_cmd_buf(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1720 - { 1721 - int retval = STATUS_SUCCESS; 1722 - unsigned int lun = SCSI_LUN(srb); 1723 - u8 cmd_type, mask, value, idx; 1724 - u16 addr; 1725 - 1726 - rtsx_disable_aspm(chip); 1727 - 1728 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1729 - rtsx_exit_ss(chip); 1730 - wait_timeout(100); 1731 - } 1732 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1733 - 1734 - switch (srb->cmnd[3]) { 1735 - case INIT_BATCHCMD: 1736 - rtsx_init_cmd(chip); 1737 - break; 1738 - 1739 - case ADD_BATCHCMD: 1740 - cmd_type = srb->cmnd[4]; 1741 - if (cmd_type > 2) { 1742 - set_sense_type(chip, lun, 1743 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1744 - return TRANSPORT_FAILED; 1745 - } 1746 - addr = (srb->cmnd[5] << 8) | srb->cmnd[6]; 1747 - mask = srb->cmnd[7]; 1748 - value = srb->cmnd[8]; 1749 - rtsx_add_cmd(chip, cmd_type, addr, mask, value); 1750 - break; 1751 - 1752 - case SEND_BATCHCMD: 1753 - retval = rtsx_send_cmd(chip, 0, 1000); 1754 - break; 1755 - 1756 - case GET_BATCHRSP: 1757 - idx = srb->cmnd[4]; 1758 - value = *(rtsx_get_cmd_data(chip) + idx); 1759 - if (scsi_bufflen(srb) < 1) { 1760 - set_sense_type(chip, lun, 1761 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1762 - return TRANSPORT_FAILED; 1763 - } 1764 - rtsx_stor_set_xfer_buf(&value, 1, srb); 1765 - scsi_set_resid(srb, 0); 1766 - break; 1767 - 1768 - default: 1769 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1770 - return TRANSPORT_FAILED; 1771 - } 1772 - 1773 - if (retval != STATUS_SUCCESS) { 1774 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 1775 - return TRANSPORT_FAILED; 1776 - } 1777 - 1778 - return TRANSPORT_GOOD; 1779 - } 1780 - 1781 - static int suit_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1782 - { 1783 - switch (srb->cmnd[3]) { 1784 - case INIT_BATCHCMD: 1785 - case ADD_BATCHCMD: 1786 - case SEND_BATCHCMD: 1787 - case GET_BATCHRSP: 1788 - return rw_mem_cmd_buf(srb, chip); 1789 - default: 1790 - return TRANSPORT_ERROR; 1791 - } 1792 - } 1793 - 1794 - static int read_phy_register(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1795 - { 1796 - unsigned short addr, len, i; 1797 - int retval; 1798 - u8 *buf; 1799 - u16 val; 1800 - 1801 - rtsx_disable_aspm(chip); 1802 - 1803 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1804 - rtsx_exit_ss(chip); 1805 - wait_timeout(100); 1806 - } 1807 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1808 - 1809 - addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1810 - len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7]; 1811 - 1812 - if (len % 2) 1813 - len -= len % 2; 1814 - 1815 - if (len) { 1816 - buf = vmalloc(len); 1817 - if (!buf) 1818 - return TRANSPORT_ERROR; 1819 - 1820 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1821 - if (retval != STATUS_SUCCESS) { 1822 - vfree(buf); 1823 - set_sense_type(chip, SCSI_LUN(srb), 1824 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1825 - return TRANSPORT_FAILED; 1826 - } 1827 - 1828 - for (i = 0; i < len / 2; i++) { 1829 - retval = rtsx_read_phy_register(chip, addr + i, &val); 1830 - if (retval != STATUS_SUCCESS) { 1831 - vfree(buf); 1832 - set_sense_type 1833 - (chip, SCSI_LUN(srb), 1834 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1835 - return TRANSPORT_FAILED; 1836 - } 1837 - 1838 - buf[2 * i] = (u8)(val >> 8); 1839 - buf[2 * i + 1] = (u8)val; 1840 - } 1841 - 1842 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), 1843 - len); 1844 - rtsx_stor_set_xfer_buf(buf, len, srb); 1845 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1846 - 1847 - vfree(buf); 1848 - } 1849 - 1850 - return TRANSPORT_GOOD; 1851 - } 1852 - 1853 - static int write_phy_register(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1854 - { 1855 - unsigned short addr, len, i; 1856 - int retval; 1857 - u8 *buf; 1858 - u16 val; 1859 - 1860 - rtsx_disable_aspm(chip); 1861 - 1862 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1863 - rtsx_exit_ss(chip); 1864 - wait_timeout(100); 1865 - } 1866 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1867 - 1868 - addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1869 - len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7]; 1870 - 1871 - if (len % 2) 1872 - len -= len % 2; 1873 - 1874 - if (len) { 1875 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), 1876 - len); 1877 - 1878 - buf = vmalloc(len); 1879 - if (!buf) 1880 - return TRANSPORT_ERROR; 1881 - 1882 - rtsx_stor_get_xfer_buf(buf, len, srb); 1883 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1884 - 1885 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1886 - if (retval != STATUS_SUCCESS) { 1887 - vfree(buf); 1888 - set_sense_type(chip, SCSI_LUN(srb), 1889 - SENSE_TYPE_MEDIA_WRITE_ERR); 1890 - return TRANSPORT_FAILED; 1891 - } 1892 - 1893 - for (i = 0; i < len / 2; i++) { 1894 - val = ((u16)buf[2 * i] << 8) | buf[2 * i + 1]; 1895 - retval = rtsx_write_phy_register(chip, addr + i, val); 1896 - if (retval != STATUS_SUCCESS) { 1897 - vfree(buf); 1898 - set_sense_type(chip, SCSI_LUN(srb), 1899 - SENSE_TYPE_MEDIA_WRITE_ERR); 1900 - return TRANSPORT_FAILED; 1901 - } 1902 - } 1903 - 1904 - vfree(buf); 1905 - } 1906 - 1907 - return TRANSPORT_GOOD; 1908 - } 1909 - 1910 - static int erase_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1911 - { 1912 - unsigned short addr; 1913 - int retval; 1914 - u8 mode; 1915 - 1916 - rtsx_disable_aspm(chip); 1917 - 1918 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1919 - rtsx_exit_ss(chip); 1920 - wait_timeout(100); 1921 - } 1922 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1923 - 1924 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1925 - if (retval != STATUS_SUCCESS) { 1926 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 1927 - return TRANSPORT_FAILED; 1928 - } 1929 - 1930 - mode = srb->cmnd[3]; 1931 - addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1932 - 1933 - if (mode == 0) { 1934 - retval = spi_erase_eeprom_chip(chip); 1935 - if (retval != STATUS_SUCCESS) { 1936 - set_sense_type(chip, SCSI_LUN(srb), 1937 - SENSE_TYPE_MEDIA_WRITE_ERR); 1938 - return TRANSPORT_FAILED; 1939 - } 1940 - } else if (mode == 1) { 1941 - retval = spi_erase_eeprom_byte(chip, addr); 1942 - if (retval != STATUS_SUCCESS) { 1943 - set_sense_type(chip, SCSI_LUN(srb), 1944 - SENSE_TYPE_MEDIA_WRITE_ERR); 1945 - return TRANSPORT_FAILED; 1946 - } 1947 - } else { 1948 - set_sense_type(chip, SCSI_LUN(srb), 1949 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 1950 - return TRANSPORT_FAILED; 1951 - } 1952 - 1953 - return TRANSPORT_GOOD; 1954 - } 1955 - 1956 - static int read_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip) 1957 - { 1958 - unsigned short addr, len, i; 1959 - int retval; 1960 - u8 *buf; 1961 - 1962 - rtsx_disable_aspm(chip); 1963 - 1964 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 1965 - rtsx_exit_ss(chip); 1966 - wait_timeout(100); 1967 - } 1968 - rtsx_set_stat(chip, RTSX_STAT_RUN); 1969 - 1970 - addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 1971 - len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7]; 1972 - 1973 - buf = vmalloc(len); 1974 - if (!buf) 1975 - return TRANSPORT_ERROR; 1976 - 1977 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 1978 - if (retval != STATUS_SUCCESS) { 1979 - vfree(buf); 1980 - set_sense_type(chip, SCSI_LUN(srb), 1981 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1982 - return TRANSPORT_FAILED; 1983 - } 1984 - 1985 - for (i = 0; i < len; i++) { 1986 - retval = spi_read_eeprom(chip, addr + i, buf + i); 1987 - if (retval != STATUS_SUCCESS) { 1988 - vfree(buf); 1989 - set_sense_type(chip, SCSI_LUN(srb), 1990 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1991 - return TRANSPORT_FAILED; 1992 - } 1993 - } 1994 - 1995 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 1996 - rtsx_stor_set_xfer_buf(buf, len, srb); 1997 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 1998 - 1999 - vfree(buf); 2000 - 2001 - return TRANSPORT_GOOD; 2002 - } 2003 - 2004 - static int write_eeprom2(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2005 - { 2006 - unsigned short addr, len, i; 2007 - int retval; 2008 - u8 *buf; 2009 - 2010 - rtsx_disable_aspm(chip); 2011 - 2012 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2013 - rtsx_exit_ss(chip); 2014 - wait_timeout(100); 2015 - } 2016 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2017 - 2018 - addr = ((u16)srb->cmnd[4] << 8) | srb->cmnd[5]; 2019 - len = ((u16)srb->cmnd[6] << 8) | srb->cmnd[7]; 2020 - 2021 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 2022 - buf = vmalloc(len); 2023 - if (!buf) 2024 - return TRANSPORT_ERROR; 2025 - 2026 - rtsx_stor_get_xfer_buf(buf, len, srb); 2027 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 2028 - 2029 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 2030 - if (retval != STATUS_SUCCESS) { 2031 - vfree(buf); 2032 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 2033 - return TRANSPORT_FAILED; 2034 - } 2035 - 2036 - for (i = 0; i < len; i++) { 2037 - retval = spi_write_eeprom(chip, addr + i, buf[i]); 2038 - if (retval != STATUS_SUCCESS) { 2039 - vfree(buf); 2040 - set_sense_type(chip, SCSI_LUN(srb), 2041 - SENSE_TYPE_MEDIA_WRITE_ERR); 2042 - return TRANSPORT_FAILED; 2043 - } 2044 - } 2045 - 2046 - vfree(buf); 2047 - 2048 - return TRANSPORT_GOOD; 2049 - } 2050 - 2051 - static int read_efuse(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2052 - { 2053 - int retval; 2054 - u8 addr, len, i; 2055 - u8 *buf; 2056 - 2057 - rtsx_disable_aspm(chip); 2058 - 2059 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2060 - rtsx_exit_ss(chip); 2061 - wait_timeout(100); 2062 - } 2063 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2064 - 2065 - addr = srb->cmnd[4]; 2066 - len = srb->cmnd[5]; 2067 - 2068 - buf = vmalloc(len); 2069 - if (!buf) 2070 - return TRANSPORT_ERROR; 2071 - 2072 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 2073 - if (retval != STATUS_SUCCESS) { 2074 - vfree(buf); 2075 - set_sense_type(chip, SCSI_LUN(srb), 2076 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2077 - return TRANSPORT_FAILED; 2078 - } 2079 - 2080 - for (i = 0; i < len; i++) { 2081 - retval = rtsx_read_efuse(chip, addr + i, buf + i); 2082 - if (retval != STATUS_SUCCESS) { 2083 - vfree(buf); 2084 - set_sense_type(chip, SCSI_LUN(srb), 2085 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2086 - return TRANSPORT_FAILED; 2087 - } 2088 - } 2089 - 2090 - len = (u8)min_t(unsigned int, scsi_bufflen(srb), len); 2091 - rtsx_stor_set_xfer_buf(buf, len, srb); 2092 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 2093 - 2094 - vfree(buf); 2095 - 2096 - return TRANSPORT_GOOD; 2097 - } 2098 - 2099 - static int write_efuse(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2100 - { 2101 - int retval, result = TRANSPORT_GOOD; 2102 - u16 val; 2103 - u8 addr, len, i; 2104 - u8 *buf; 2105 - 2106 - rtsx_disable_aspm(chip); 2107 - 2108 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2109 - rtsx_exit_ss(chip); 2110 - wait_timeout(100); 2111 - } 2112 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2113 - 2114 - addr = srb->cmnd[4]; 2115 - len = srb->cmnd[5]; 2116 - 2117 - len = (u8)min_t(unsigned int, scsi_bufflen(srb), len); 2118 - buf = vmalloc(len); 2119 - if (!buf) 2120 - return TRANSPORT_ERROR; 2121 - 2122 - rtsx_stor_get_xfer_buf(buf, len, srb); 2123 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 2124 - 2125 - retval = rtsx_force_power_on(chip, SSC_PDCTL); 2126 - if (retval != STATUS_SUCCESS) { 2127 - vfree(buf); 2128 - return TRANSPORT_ERROR; 2129 - } 2130 - 2131 - if (chip->asic_code) { 2132 - retval = rtsx_read_phy_register(chip, 0x08, &val); 2133 - if (retval != STATUS_SUCCESS) { 2134 - vfree(buf); 2135 - return TRANSPORT_ERROR; 2136 - } 2137 - 2138 - retval = rtsx_write_register(chip, PWR_GATE_CTRL, 2139 - LDO3318_PWR_MASK, LDO_OFF); 2140 - if (retval != STATUS_SUCCESS) { 2141 - vfree(buf); 2142 - return TRANSPORT_ERROR; 2143 - } 2144 - 2145 - wait_timeout(600); 2146 - 2147 - retval = rtsx_write_phy_register(chip, 0x08, 2148 - 0x4C00 | chip->phy_voltage); 2149 - if (retval != STATUS_SUCCESS) { 2150 - vfree(buf); 2151 - return TRANSPORT_ERROR; 2152 - } 2153 - 2154 - retval = rtsx_write_register(chip, PWR_GATE_CTRL, 2155 - LDO3318_PWR_MASK, LDO_ON); 2156 - if (retval != STATUS_SUCCESS) { 2157 - vfree(buf); 2158 - return TRANSPORT_ERROR; 2159 - } 2160 - 2161 - wait_timeout(600); 2162 - } 2163 - 2164 - retval = card_power_on(chip, SPI_CARD); 2165 - if (retval != STATUS_SUCCESS) { 2166 - vfree(buf); 2167 - return TRANSPORT_ERROR; 2168 - } 2169 - 2170 - wait_timeout(50); 2171 - 2172 - for (i = 0; i < len; i++) { 2173 - retval = rtsx_write_efuse(chip, addr + i, buf[i]); 2174 - if (retval != STATUS_SUCCESS) { 2175 - set_sense_type(chip, SCSI_LUN(srb), 2176 - SENSE_TYPE_MEDIA_WRITE_ERR); 2177 - result = TRANSPORT_FAILED; 2178 - goto exit; 2179 - } 2180 - } 2181 - 2182 - exit: 2183 - vfree(buf); 2184 - 2185 - retval = card_power_off(chip, SPI_CARD); 2186 - if (retval != STATUS_SUCCESS) 2187 - return TRANSPORT_ERROR; 2188 - 2189 - if (chip->asic_code) { 2190 - retval = rtsx_write_register(chip, PWR_GATE_CTRL, 2191 - LDO3318_PWR_MASK, LDO_OFF); 2192 - if (retval != STATUS_SUCCESS) 2193 - return TRANSPORT_ERROR; 2194 - 2195 - wait_timeout(600); 2196 - 2197 - retval = rtsx_write_phy_register(chip, 0x08, val); 2198 - if (retval != STATUS_SUCCESS) 2199 - return TRANSPORT_ERROR; 2200 - 2201 - retval = rtsx_write_register(chip, PWR_GATE_CTRL, 2202 - LDO3318_PWR_MASK, LDO_ON); 2203 - if (retval != STATUS_SUCCESS) 2204 - return TRANSPORT_ERROR; 2205 - } 2206 - 2207 - return result; 2208 - } 2209 - 2210 - static int read_cfg_byte(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2211 - { 2212 - int retval; 2213 - bool func_max; 2214 - u8 func; 2215 - u16 addr, len; 2216 - u8 *buf; 2217 - 2218 - rtsx_disable_aspm(chip); 2219 - 2220 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2221 - rtsx_exit_ss(chip); 2222 - wait_timeout(100); 2223 - } 2224 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2225 - 2226 - func = srb->cmnd[3]; 2227 - addr = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 2228 - len = ((u16)(srb->cmnd[6]) << 8) | srb->cmnd[7]; 2229 - 2230 - dev_dbg(rtsx_dev(chip), "%s: func = %d, addr = 0x%x, len = %d\n", 2231 - __func__, func, addr, len); 2232 - 2233 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) 2234 - func_max = true; 2235 - else 2236 - func_max = false; 2237 - 2238 - if (func > func_max) { 2239 - set_sense_type(chip, SCSI_LUN(srb), 2240 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2241 - return TRANSPORT_FAILED; 2242 - } 2243 - 2244 - buf = vmalloc(len); 2245 - if (!buf) 2246 - return TRANSPORT_ERROR; 2247 - 2248 - retval = rtsx_read_cfg_seq(chip, func, addr, buf, len); 2249 - if (retval != STATUS_SUCCESS) { 2250 - set_sense_type(chip, SCSI_LUN(srb), 2251 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2252 - vfree(buf); 2253 - return TRANSPORT_FAILED; 2254 - } 2255 - 2256 - len = (u16)min_t(unsigned int, scsi_bufflen(srb), len); 2257 - rtsx_stor_set_xfer_buf(buf, len, srb); 2258 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 2259 - 2260 - vfree(buf); 2261 - 2262 - return TRANSPORT_GOOD; 2263 - } 2264 - 2265 - static int write_cfg_byte(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2266 - { 2267 - int retval; 2268 - bool func_max; 2269 - u8 func; 2270 - u16 addr, len; 2271 - u8 *buf; 2272 - 2273 - rtsx_disable_aspm(chip); 2274 - 2275 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2276 - rtsx_exit_ss(chip); 2277 - wait_timeout(100); 2278 - } 2279 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2280 - 2281 - func = srb->cmnd[3]; 2282 - addr = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 2283 - len = ((u16)(srb->cmnd[6]) << 8) | srb->cmnd[7]; 2284 - 2285 - dev_dbg(rtsx_dev(chip), "%s: func = %d, addr = 0x%x\n", 2286 - __func__, func, addr); 2287 - 2288 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) 2289 - func_max = true; 2290 - else 2291 - func_max = false; 2292 - 2293 - if (func > func_max) { 2294 - set_sense_type(chip, SCSI_LUN(srb), 2295 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2296 - return TRANSPORT_FAILED; 2297 - } 2298 - 2299 - len = (unsigned short)min_t(unsigned int, scsi_bufflen(srb), len); 2300 - buf = vmalloc(len); 2301 - if (!buf) 2302 - return TRANSPORT_ERROR; 2303 - 2304 - rtsx_stor_get_xfer_buf(buf, len, srb); 2305 - scsi_set_resid(srb, scsi_bufflen(srb) - len); 2306 - 2307 - retval = rtsx_write_cfg_seq(chip, func, addr, buf, len); 2308 - if (retval != STATUS_SUCCESS) { 2309 - set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 2310 - vfree(buf); 2311 - return TRANSPORT_FAILED; 2312 - } 2313 - 2314 - vfree(buf); 2315 - 2316 - return TRANSPORT_GOOD; 2317 - } 2318 - 2319 - static int app_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2320 - { 2321 - int result; 2322 - 2323 - switch (srb->cmnd[2]) { 2324 - case PP_READ10: 2325 - case PP_WRITE10: 2326 - result = read_write(srb, chip); 2327 - break; 2328 - 2329 - case READ_HOST_REG: 2330 - result = read_host_reg(srb, chip); 2331 - break; 2332 - 2333 - case WRITE_HOST_REG: 2334 - result = write_host_reg(srb, chip); 2335 - break; 2336 - 2337 - case GET_VAR: 2338 - result = get_variable(srb, chip); 2339 - break; 2340 - 2341 - case SET_VAR: 2342 - result = set_variable(srb, chip); 2343 - break; 2344 - 2345 - case DMA_READ: 2346 - case DMA_WRITE: 2347 - result = dma_access_ring_buffer(srb, chip); 2348 - break; 2349 - 2350 - case READ_PHY: 2351 - result = read_phy_register(srb, chip); 2352 - break; 2353 - 2354 - case WRITE_PHY: 2355 - result = write_phy_register(srb, chip); 2356 - break; 2357 - 2358 - case ERASE_EEPROM2: 2359 - result = erase_eeprom2(srb, chip); 2360 - break; 2361 - 2362 - case READ_EEPROM2: 2363 - result = read_eeprom2(srb, chip); 2364 - break; 2365 - 2366 - case WRITE_EEPROM2: 2367 - result = write_eeprom2(srb, chip); 2368 - break; 2369 - 2370 - case READ_EFUSE: 2371 - result = read_efuse(srb, chip); 2372 - break; 2373 - 2374 - case WRITE_EFUSE: 2375 - result = write_efuse(srb, chip); 2376 - break; 2377 - 2378 - case READ_CFG: 2379 - result = read_cfg_byte(srb, chip); 2380 - break; 2381 - 2382 - case WRITE_CFG: 2383 - result = write_cfg_byte(srb, chip); 2384 - break; 2385 - 2386 - case SET_CHIP_MODE: 2387 - result = set_chip_mode(srb, chip); 2388 - break; 2389 - 2390 - case SUIT_CMD: 2391 - result = suit_cmd(srb, chip); 2392 - break; 2393 - 2394 - case GET_DEV_STATUS: 2395 - result = get_dev_status(srb, chip); 2396 - break; 2397 - 2398 - default: 2399 - set_sense_type(chip, SCSI_LUN(srb), 2400 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2401 - return TRANSPORT_FAILED; 2402 - } 2403 - 2404 - return result; 2405 - } 2406 - 2407 - static int read_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2408 - { 2409 - u8 rtsx_status[16]; 2410 - int buf_len; 2411 - unsigned int lun = SCSI_LUN(srb); 2412 - 2413 - rtsx_status[0] = (u8)(chip->vendor_id >> 8); 2414 - rtsx_status[1] = (u8)(chip->vendor_id); 2415 - 2416 - rtsx_status[2] = (u8)(chip->product_id >> 8); 2417 - rtsx_status[3] = (u8)(chip->product_id); 2418 - 2419 - rtsx_status[4] = (u8)lun; 2420 - 2421 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 2422 - if (chip->lun2card[lun] == SD_CARD) 2423 - rtsx_status[5] = 2; 2424 - else 2425 - rtsx_status[5] = 3; 2426 - } else { 2427 - if (chip->card_exist) { 2428 - if (chip->card_exist & XD_CARD) 2429 - rtsx_status[5] = 4; 2430 - else if (chip->card_exist & SD_CARD) 2431 - rtsx_status[5] = 2; 2432 - else if (chip->card_exist & MS_CARD) 2433 - rtsx_status[5] = 3; 2434 - else 2435 - rtsx_status[5] = 7; 2436 - } else { 2437 - rtsx_status[5] = 7; 2438 - } 2439 - } 2440 - 2441 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2442 - rtsx_status[6] = 2; 2443 - else 2444 - rtsx_status[6] = 1; 2445 - 2446 - rtsx_status[7] = (u8)(chip->product_id); 2447 - rtsx_status[8] = chip->ic_version; 2448 - 2449 - if (check_card_exist(chip, lun)) 2450 - rtsx_status[9] = 1; 2451 - else 2452 - rtsx_status[9] = 0; 2453 - 2454 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 2455 - rtsx_status[10] = 0; 2456 - else 2457 - rtsx_status[10] = 1; 2458 - 2459 - if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) { 2460 - if (chip->lun2card[lun] == SD_CARD) 2461 - rtsx_status[11] = SD_CARD; 2462 - else 2463 - rtsx_status[11] = MS_CARD; 2464 - } else { 2465 - rtsx_status[11] = XD_CARD | SD_CARD | MS_CARD; 2466 - } 2467 - 2468 - if (check_card_ready(chip, lun)) 2469 - rtsx_status[12] = 1; 2470 - else 2471 - rtsx_status[12] = 0; 2472 - 2473 - if (get_lun_card(chip, lun) == XD_CARD) { 2474 - rtsx_status[13] = 0x40; 2475 - } else if (get_lun_card(chip, lun) == SD_CARD) { 2476 - struct sd_info *sd_card = &chip->sd_card; 2477 - 2478 - rtsx_status[13] = 0x20; 2479 - if (CHK_SD(sd_card)) { 2480 - if (CHK_SD_HCXC(sd_card)) 2481 - rtsx_status[13] |= 0x04; 2482 - if (CHK_SD_HS(sd_card)) 2483 - rtsx_status[13] |= 0x02; 2484 - } else { 2485 - rtsx_status[13] |= 0x08; 2486 - if (CHK_MMC_52M(sd_card)) 2487 - rtsx_status[13] |= 0x02; 2488 - if (CHK_MMC_SECTOR_MODE(sd_card)) 2489 - rtsx_status[13] |= 0x04; 2490 - } 2491 - } else if (get_lun_card(chip, lun) == MS_CARD) { 2492 - struct ms_info *ms_card = &chip->ms_card; 2493 - 2494 - if (CHK_MSPRO(ms_card)) { 2495 - rtsx_status[13] = 0x38; 2496 - if (CHK_HG8BIT(ms_card)) 2497 - rtsx_status[13] |= 0x04; 2498 - #ifdef SUPPORT_MSXC 2499 - if (CHK_MSXC(ms_card)) 2500 - rtsx_status[13] |= 0x01; 2501 - #endif 2502 - } else { 2503 - rtsx_status[13] = 0x30; 2504 - } 2505 - } else { 2506 - if (CHECK_LUN_MODE(chip, DEFAULT_SINGLE)) { 2507 - #ifdef SUPPORT_SDIO 2508 - if (chip->sd_io && chip->sd_int) 2509 - rtsx_status[13] = 0x60; 2510 - else 2511 - rtsx_status[13] = 0x70; 2512 - #else 2513 - rtsx_status[13] = 0x70; 2514 - #endif 2515 - } else { 2516 - if (chip->lun2card[lun] == SD_CARD) 2517 - rtsx_status[13] = 0x20; 2518 - else 2519 - rtsx_status[13] = 0x30; 2520 - } 2521 - } 2522 - 2523 - rtsx_status[14] = 0x78; 2524 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) 2525 - rtsx_status[15] = 0x83; 2526 - else 2527 - rtsx_status[15] = 0x82; 2528 - 2529 - buf_len = min_t(unsigned int, scsi_bufflen(srb), sizeof(rtsx_status)); 2530 - rtsx_stor_set_xfer_buf(rtsx_status, buf_len, srb); 2531 - scsi_set_resid(srb, scsi_bufflen(srb) - buf_len); 2532 - 2533 - return TRANSPORT_GOOD; 2534 - } 2535 - 2536 - static int get_card_bus_width(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2537 - { 2538 - unsigned int lun = SCSI_LUN(srb); 2539 - u8 card, bus_width; 2540 - 2541 - if (!check_card_ready(chip, lun)) { 2542 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2543 - return TRANSPORT_FAILED; 2544 - } 2545 - 2546 - card = get_lun_card(chip, lun); 2547 - if (card == SD_CARD || card == MS_CARD) { 2548 - bus_width = chip->card_bus_width[lun]; 2549 - } else { 2550 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2551 - return TRANSPORT_FAILED; 2552 - } 2553 - 2554 - scsi_set_resid(srb, 0); 2555 - rtsx_stor_set_xfer_buf(&bus_width, scsi_bufflen(srb), srb); 2556 - 2557 - return TRANSPORT_GOOD; 2558 - } 2559 - 2560 - static int spi_vendor_cmd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2561 - { 2562 - int result; 2563 - unsigned int lun = SCSI_LUN(srb); 2564 - u8 gpio_dir; 2565 - 2566 - if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) { 2567 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2568 - return TRANSPORT_FAILED; 2569 - } 2570 - 2571 - rtsx_disable_aspm(chip); 2572 - 2573 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2574 - rtsx_exit_ss(chip); 2575 - wait_timeout(100); 2576 - } 2577 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2578 - 2579 - rtsx_force_power_on(chip, SSC_PDCTL); 2580 - 2581 - rtsx_read_register(chip, CARD_GPIO_DIR, &gpio_dir); 2582 - rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir & 0x06); 2583 - 2584 - switch (srb->cmnd[2]) { 2585 - case SCSI_SPI_GETSTATUS: 2586 - result = spi_get_status(srb, chip); 2587 - break; 2588 - 2589 - case SCSI_SPI_SETPARAMETER: 2590 - result = spi_set_parameter(srb, chip); 2591 - break; 2592 - 2593 - case SCSI_SPI_READFALSHID: 2594 - result = spi_read_flash_id(srb, chip); 2595 - break; 2596 - 2597 - case SCSI_SPI_READFLASH: 2598 - result = spi_read_flash(srb, chip); 2599 - break; 2600 - 2601 - case SCSI_SPI_WRITEFLASH: 2602 - result = spi_write_flash(srb, chip); 2603 - break; 2604 - 2605 - case SCSI_SPI_WRITEFLASHSTATUS: 2606 - result = spi_write_flash_status(srb, chip); 2607 - break; 2608 - 2609 - case SCSI_SPI_ERASEFLASH: 2610 - result = spi_erase_flash(srb, chip); 2611 - break; 2612 - 2613 - default: 2614 - rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir); 2615 - 2616 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2617 - return TRANSPORT_FAILED; 2618 - } 2619 - 2620 - rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir); 2621 - 2622 - if (result != STATUS_SUCCESS) 2623 - return TRANSPORT_FAILED; 2624 - 2625 - return TRANSPORT_GOOD; 2626 - } 2627 - 2628 - static int vendor_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2629 - { 2630 - int result; 2631 - 2632 - switch (srb->cmnd[1]) { 2633 - case READ_STATUS: 2634 - result = read_status(srb, chip); 2635 - break; 2636 - 2637 - case READ_MEM: 2638 - result = read_mem(srb, chip); 2639 - break; 2640 - 2641 - case WRITE_MEM: 2642 - result = write_mem(srb, chip); 2643 - break; 2644 - 2645 - case READ_EEPROM: 2646 - result = read_eeprom(srb, chip); 2647 - break; 2648 - 2649 - case WRITE_EEPROM: 2650 - result = write_eeprom(srb, chip); 2651 - break; 2652 - 2653 - case TOGGLE_GPIO: 2654 - result = toggle_gpio_cmd(srb, chip); 2655 - break; 2656 - 2657 - case GET_SD_CSD: 2658 - result = get_sd_csd(srb, chip); 2659 - break; 2660 - 2661 - case GET_BUS_WIDTH: 2662 - result = get_card_bus_width(srb, chip); 2663 - break; 2664 - 2665 - case SCSI_APP_CMD: 2666 - result = app_cmd(srb, chip); 2667 - break; 2668 - 2669 - case SPI_VENDOR_COMMAND: 2670 - result = spi_vendor_cmd(srb, chip); 2671 - break; 2672 - 2673 - default: 2674 - set_sense_type(chip, SCSI_LUN(srb), 2675 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2676 - return TRANSPORT_FAILED; 2677 - } 2678 - 2679 - return result; 2680 - } 2681 - 2682 - #if !defined(LED_AUTO_BLINK) && !defined(REGULAR_BLINK) 2683 - void led_shine(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2684 - { 2685 - unsigned int lun = SCSI_LUN(srb); 2686 - u16 sec_cnt; 2687 - 2688 - if (srb->cmnd[0] == READ_10 || srb->cmnd[0] == WRITE_10) { 2689 - sec_cnt = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 2690 - } else if ((srb->cmnd[0] == READ_6) || (srb->cmnd[0] == WRITE_6)) { 2691 - sec_cnt = srb->cmnd[4]; 2692 - if (sec_cnt == 0) 2693 - sec_cnt = 256; 2694 - } else { 2695 - return; 2696 - } 2697 - 2698 - if (chip->rw_cap[lun] >= GPIO_TOGGLE_THRESHOLD) { 2699 - toggle_gpio(chip, LED_GPIO); 2700 - chip->rw_cap[lun] = 0; 2701 - } else { 2702 - chip->rw_cap[lun] += sec_cnt; 2703 - } 2704 - } 2705 - #endif 2706 - 2707 - static int ms_format_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2708 - { 2709 - struct ms_info *ms_card = &chip->ms_card; 2710 - unsigned int lun = SCSI_LUN(srb); 2711 - bool quick_format; 2712 - int retval; 2713 - 2714 - if (get_lun_card(chip, lun) != MS_CARD) { 2715 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 2716 - return TRANSPORT_FAILED; 2717 - } 2718 - 2719 - if (srb->cmnd[3] != 0x4D || srb->cmnd[4] != 0x47 || 2720 - srb->cmnd[5] != 0x66 || srb->cmnd[6] != 0x6D || 2721 - srb->cmnd[7] != 0x74) { 2722 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2723 - return TRANSPORT_FAILED; 2724 - } 2725 - 2726 - rtsx_disable_aspm(chip); 2727 - 2728 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2729 - rtsx_exit_ss(chip); 2730 - wait_timeout(100); 2731 - 2732 - if (!check_card_ready(chip, lun) || 2733 - (get_card_size(chip, lun) == 0)) { 2734 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2735 - return TRANSPORT_FAILED; 2736 - } 2737 - } 2738 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2739 - 2740 - if (srb->cmnd[8] & 0x01) 2741 - quick_format = false; 2742 - else 2743 - quick_format = true; 2744 - 2745 - if (!(chip->card_ready & MS_CARD)) { 2746 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2747 - return TRANSPORT_FAILED; 2748 - } 2749 - 2750 - if (chip->card_wp & MS_CARD) { 2751 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_PROTECT); 2752 - return TRANSPORT_FAILED; 2753 - } 2754 - 2755 - if (!CHK_MSPRO(ms_card)) { 2756 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 2757 - return TRANSPORT_FAILED; 2758 - } 2759 - 2760 - retval = mspro_format(srb, chip, MS_SHORT_DATA_LEN, quick_format); 2761 - if (retval != STATUS_SUCCESS) { 2762 - set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED); 2763 - return TRANSPORT_FAILED; 2764 - } 2765 - 2766 - scsi_set_resid(srb, 0); 2767 - return TRANSPORT_GOOD; 2768 - } 2769 - 2770 - #ifdef SUPPORT_PCGL_1P18 2771 - static int get_ms_information(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2772 - { 2773 - struct ms_info *ms_card = &chip->ms_card; 2774 - unsigned int lun = SCSI_LUN(srb); 2775 - u8 dev_info_id, data_len; 2776 - u8 *buf; 2777 - unsigned int buf_len; 2778 - int i; 2779 - 2780 - if (!check_card_ready(chip, lun)) { 2781 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2782 - return TRANSPORT_FAILED; 2783 - } 2784 - if (get_lun_card(chip, lun) != MS_CARD) { 2785 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 2786 - return TRANSPORT_FAILED; 2787 - } 2788 - 2789 - if (srb->cmnd[2] != 0xB0 || srb->cmnd[4] != 0x4D || 2790 - srb->cmnd[5] != 0x53 || srb->cmnd[6] != 0x49 || 2791 - srb->cmnd[7] != 0x44) { 2792 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2793 - return TRANSPORT_FAILED; 2794 - } 2795 - 2796 - dev_info_id = srb->cmnd[3]; 2797 - if ((CHK_MSXC(ms_card) && dev_info_id == 0x10) || 2798 - (!CHK_MSXC(ms_card) && dev_info_id == 0x13) || 2799 - !CHK_MSPRO(ms_card)) { 2800 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2801 - return TRANSPORT_FAILED; 2802 - } 2803 - 2804 - if (dev_info_id == 0x15) { 2805 - buf_len = 0x3C; 2806 - data_len = 0x3A; 2807 - } else { 2808 - buf_len = 0x6C; 2809 - data_len = 0x6A; 2810 - } 2811 - 2812 - buf = kmalloc(buf_len, GFP_KERNEL); 2813 - if (!buf) 2814 - return TRANSPORT_ERROR; 2815 - 2816 - i = 0; 2817 - /* GET Memory Stick Media Information Response Header */ 2818 - buf[i++] = 0x00; /* Data length MSB */ 2819 - buf[i++] = data_len; /* Data length LSB */ 2820 - /* Device Information Type Code */ 2821 - if (CHK_MSXC(ms_card)) 2822 - buf[i++] = 0x03; 2823 - else 2824 - buf[i++] = 0x02; 2825 - 2826 - /* SGM bit */ 2827 - buf[i++] = 0x01; 2828 - /* Reserved */ 2829 - buf[i++] = 0x00; 2830 - buf[i++] = 0x00; 2831 - buf[i++] = 0x00; 2832 - /* Number of Device Information */ 2833 - buf[i++] = 0x01; 2834 - 2835 - /* Device Information Body */ 2836 - 2837 - /* Device Information ID Number */ 2838 - buf[i++] = dev_info_id; 2839 - /* Device Information Length */ 2840 - if (dev_info_id == 0x15) 2841 - data_len = 0x31; 2842 - else 2843 - data_len = 0x61; 2844 - 2845 - buf[i++] = 0x00; /* Data length MSB */ 2846 - buf[i++] = data_len; /* Data length LSB */ 2847 - /* Valid Bit */ 2848 - buf[i++] = 0x80; 2849 - if (dev_info_id == 0x10 || dev_info_id == 0x13) { 2850 - /* System Information */ 2851 - memcpy(buf + i, ms_card->raw_sys_info, 96); 2852 - } else { 2853 - /* Model Name */ 2854 - memcpy(buf + i, ms_card->raw_model_name, 48); 2855 - } 2856 - 2857 - rtsx_stor_set_xfer_buf(buf, buf_len, srb); 2858 - scsi_set_resid(srb, scsi_bufflen(srb) - buf_len); 2859 - 2860 - kfree(buf); 2861 - return STATUS_SUCCESS; 2862 - } 2863 - #endif 2864 - 2865 - static int ms_sp_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2866 - { 2867 - int retval = TRANSPORT_ERROR; 2868 - 2869 - if (srb->cmnd[2] == MS_FORMAT) 2870 - retval = ms_format_cmnd(srb, chip); 2871 - #ifdef SUPPORT_PCGL_1P18 2872 - else if (srb->cmnd[2] == GET_MS_INFORMATION) 2873 - retval = get_ms_information(srb, chip); 2874 - #endif 2875 - 2876 - return retval; 2877 - } 2878 - 2879 - #ifdef SUPPORT_CPRM 2880 - static int sd_extension_cmnd(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2881 - { 2882 - unsigned int lun = SCSI_LUN(srb); 2883 - int result; 2884 - 2885 - rtsx_disable_aspm(chip); 2886 - 2887 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2888 - rtsx_exit_ss(chip); 2889 - wait_timeout(100); 2890 - } 2891 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2892 - 2893 - sd_cleanup_work(chip); 2894 - 2895 - if (!check_card_ready(chip, lun)) { 2896 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2897 - return TRANSPORT_FAILED; 2898 - } 2899 - if (get_lun_card(chip, lun) != SD_CARD) { 2900 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 2901 - return TRANSPORT_FAILED; 2902 - } 2903 - 2904 - switch (srb->cmnd[0]) { 2905 - case SD_PASS_THRU_MODE: 2906 - result = sd_pass_thru_mode(srb, chip); 2907 - break; 2908 - 2909 - case SD_EXECUTE_NO_DATA: 2910 - result = sd_execute_no_data(srb, chip); 2911 - break; 2912 - 2913 - case SD_EXECUTE_READ: 2914 - result = sd_execute_read_data(srb, chip); 2915 - break; 2916 - 2917 - case SD_EXECUTE_WRITE: 2918 - result = sd_execute_write_data(srb, chip); 2919 - break; 2920 - 2921 - case SD_GET_RSP: 2922 - result = sd_get_cmd_rsp(srb, chip); 2923 - break; 2924 - 2925 - case SD_HW_RST: 2926 - result = sd_hw_rst(srb, chip); 2927 - break; 2928 - 2929 - default: 2930 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2931 - return TRANSPORT_FAILED; 2932 - } 2933 - 2934 - return result; 2935 - } 2936 - #endif 2937 - 2938 - #ifdef SUPPORT_MAGIC_GATE 2939 - static int mg_report_key(struct scsi_cmnd *srb, struct rtsx_chip *chip) 2940 - { 2941 - struct ms_info *ms_card = &chip->ms_card; 2942 - unsigned int lun = SCSI_LUN(srb); 2943 - int retval; 2944 - u8 key_format; 2945 - 2946 - rtsx_disable_aspm(chip); 2947 - 2948 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 2949 - rtsx_exit_ss(chip); 2950 - wait_timeout(100); 2951 - } 2952 - rtsx_set_stat(chip, RTSX_STAT_RUN); 2953 - 2954 - ms_cleanup_work(chip); 2955 - 2956 - if (!check_card_ready(chip, lun)) { 2957 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2958 - return TRANSPORT_FAILED; 2959 - } 2960 - if (get_lun_card(chip, lun) != MS_CARD) { 2961 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 2962 - return TRANSPORT_FAILED; 2963 - } 2964 - 2965 - if (srb->cmnd[7] != KC_MG_R_PRO) { 2966 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2967 - return TRANSPORT_FAILED; 2968 - } 2969 - 2970 - if (!CHK_MSPRO(ms_card)) { 2971 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 2972 - return TRANSPORT_FAILED; 2973 - } 2974 - 2975 - key_format = srb->cmnd[10] & 0x3F; 2976 - dev_dbg(rtsx_dev(chip), "key_format = 0x%x\n", key_format); 2977 - 2978 - switch (key_format) { 2979 - case KF_GET_LOC_EKB: 2980 - if ((scsi_bufflen(srb) == 0x41C) && 2981 - srb->cmnd[8] == 0x04 && 2982 - srb->cmnd[9] == 0x1C) { 2983 - retval = mg_get_local_EKB(srb, chip); 2984 - if (retval != STATUS_SUCCESS) 2985 - return TRANSPORT_FAILED; 2986 - 2987 - } else { 2988 - set_sense_type(chip, lun, 2989 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 2990 - return TRANSPORT_FAILED; 2991 - } 2992 - break; 2993 - 2994 - case KF_RSP_CHG: 2995 - if ((scsi_bufflen(srb) == 0x24) && 2996 - srb->cmnd[8] == 0x00 && 2997 - srb->cmnd[9] == 0x24) { 2998 - retval = mg_get_rsp_chg(srb, chip); 2999 - if (retval != STATUS_SUCCESS) 3000 - return TRANSPORT_FAILED; 3001 - 3002 - } else { 3003 - set_sense_type(chip, lun, 3004 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3005 - return TRANSPORT_FAILED; 3006 - } 3007 - break; 3008 - 3009 - case KF_GET_ICV: 3010 - ms_card->mg_entry_num = srb->cmnd[5]; 3011 - if ((scsi_bufflen(srb) == 0x404) && 3012 - srb->cmnd[8] == 0x04 && 3013 - srb->cmnd[9] == 0x04 && 3014 - srb->cmnd[2] == 0x00 && 3015 - srb->cmnd[3] == 0x00 && 3016 - srb->cmnd[4] == 0x00 && 3017 - srb->cmnd[5] < 32) { 3018 - retval = mg_get_ICV(srb, chip); 3019 - if (retval != STATUS_SUCCESS) 3020 - return TRANSPORT_FAILED; 3021 - 3022 - } else { 3023 - set_sense_type(chip, lun, 3024 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3025 - return TRANSPORT_FAILED; 3026 - } 3027 - break; 3028 - 3029 - default: 3030 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3031 - return TRANSPORT_FAILED; 3032 - } 3033 - 3034 - scsi_set_resid(srb, 0); 3035 - return TRANSPORT_GOOD; 3036 - } 3037 - 3038 - static int mg_send_key(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3039 - { 3040 - struct ms_info *ms_card = &chip->ms_card; 3041 - unsigned int lun = SCSI_LUN(srb); 3042 - int retval; 3043 - u8 key_format; 3044 - 3045 - rtsx_disable_aspm(chip); 3046 - 3047 - if (chip->ss_en && (rtsx_get_stat(chip) == RTSX_STAT_SS)) { 3048 - rtsx_exit_ss(chip); 3049 - wait_timeout(100); 3050 - } 3051 - rtsx_set_stat(chip, RTSX_STAT_RUN); 3052 - 3053 - ms_cleanup_work(chip); 3054 - 3055 - if (!check_card_ready(chip, lun)) { 3056 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3057 - return TRANSPORT_FAILED; 3058 - } 3059 - if (check_card_wp(chip, lun)) { 3060 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_PROTECT); 3061 - return TRANSPORT_FAILED; 3062 - } 3063 - if (get_lun_card(chip, lun) != MS_CARD) { 3064 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT); 3065 - return TRANSPORT_FAILED; 3066 - } 3067 - 3068 - if (srb->cmnd[7] != KC_MG_R_PRO) { 3069 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3070 - return TRANSPORT_FAILED; 3071 - } 3072 - 3073 - if (!CHK_MSPRO(ms_card)) { 3074 - set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3075 - return TRANSPORT_FAILED; 3076 - } 3077 - 3078 - key_format = srb->cmnd[10] & 0x3F; 3079 - dev_dbg(rtsx_dev(chip), "key_format = 0x%x\n", key_format); 3080 - 3081 - switch (key_format) { 3082 - case KF_SET_LEAF_ID: 3083 - if ((scsi_bufflen(srb) == 0x0C) && 3084 - srb->cmnd[8] == 0x00 && 3085 - srb->cmnd[9] == 0x0C) { 3086 - retval = mg_set_leaf_id(srb, chip); 3087 - if (retval != STATUS_SUCCESS) 3088 - return TRANSPORT_FAILED; 3089 - 3090 - } else { 3091 - set_sense_type(chip, lun, 3092 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3093 - return TRANSPORT_FAILED; 3094 - } 3095 - break; 3096 - 3097 - case KF_CHG_HOST: 3098 - if ((scsi_bufflen(srb) == 0x0C) && 3099 - srb->cmnd[8] == 0x00 && 3100 - srb->cmnd[9] == 0x0C) { 3101 - retval = mg_chg(srb, chip); 3102 - if (retval != STATUS_SUCCESS) 3103 - return TRANSPORT_FAILED; 3104 - 3105 - } else { 3106 - set_sense_type(chip, lun, 3107 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3108 - return TRANSPORT_FAILED; 3109 - } 3110 - break; 3111 - 3112 - case KF_RSP_HOST: 3113 - if ((scsi_bufflen(srb) == 0x0C) && 3114 - srb->cmnd[8] == 0x00 && 3115 - srb->cmnd[9] == 0x0C) { 3116 - retval = mg_rsp(srb, chip); 3117 - if (retval != STATUS_SUCCESS) 3118 - return TRANSPORT_FAILED; 3119 - 3120 - } else { 3121 - set_sense_type(chip, lun, 3122 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3123 - return TRANSPORT_FAILED; 3124 - } 3125 - break; 3126 - 3127 - case KF_SET_ICV: 3128 - ms_card->mg_entry_num = srb->cmnd[5]; 3129 - if ((scsi_bufflen(srb) == 0x404) && 3130 - srb->cmnd[8] == 0x04 && 3131 - srb->cmnd[9] == 0x04 && 3132 - srb->cmnd[2] == 0x00 && 3133 - srb->cmnd[3] == 0x00 && 3134 - srb->cmnd[4] == 0x00 && 3135 - srb->cmnd[5] < 32) { 3136 - retval = mg_set_ICV(srb, chip); 3137 - if (retval != STATUS_SUCCESS) 3138 - return TRANSPORT_FAILED; 3139 - 3140 - } else { 3141 - set_sense_type(chip, lun, 3142 - SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3143 - return TRANSPORT_FAILED; 3144 - } 3145 - break; 3146 - 3147 - default: 3148 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3149 - return TRANSPORT_FAILED; 3150 - } 3151 - 3152 - scsi_set_resid(srb, 0); 3153 - return TRANSPORT_GOOD; 3154 - } 3155 - #endif 3156 - 3157 - int rtsx_scsi_handler(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3158 - { 3159 - #ifdef SUPPORT_SD_LOCK 3160 - struct sd_info *sd_card = &chip->sd_card; 3161 - #endif 3162 - struct ms_info *ms_card = &chip->ms_card; 3163 - unsigned int lun = SCSI_LUN(srb); 3164 - int result; 3165 - 3166 - #ifdef SUPPORT_SD_LOCK 3167 - if (sd_card->sd_erase_status) { 3168 - /* Block all SCSI command except for 3169 - * REQUEST_SENSE and rs_ppstatus 3170 - */ 3171 - if (!(srb->cmnd[0] == VENDOR_CMND && 3172 - srb->cmnd[1] == SCSI_APP_CMD && 3173 - srb->cmnd[2] == GET_DEV_STATUS) && 3174 - srb->cmnd[0] != REQUEST_SENSE) { 3175 - /* Logical Unit Not Ready Format in Progress */ 3176 - set_sense_data(chip, lun, CUR_ERR, 3177 - 0x02, 0, 0x04, 0x04, 0, 0); 3178 - return TRANSPORT_FAILED; 3179 - } 3180 - } 3181 - #endif 3182 - 3183 - if ((get_lun_card(chip, lun) == MS_CARD) && 3184 - ms_card->format_status == FORMAT_IN_PROGRESS) { 3185 - if (srb->cmnd[0] != REQUEST_SENSE && 3186 - srb->cmnd[0] != INQUIRY) { 3187 - /* Logical Unit Not Ready Format in Progress */ 3188 - set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04, 3189 - 0, (u16)(ms_card->progress)); 3190 - return TRANSPORT_FAILED; 3191 - } 3192 - } 3193 - 3194 - switch (srb->cmnd[0]) { 3195 - case READ_10: 3196 - case WRITE_10: 3197 - case READ_6: 3198 - case WRITE_6: 3199 - result = read_write(srb, chip); 3200 - #if !defined(LED_AUTO_BLINK) && !defined(REGULAR_BLINK) 3201 - led_shine(srb, chip); 3202 - #endif 3203 - break; 3204 - 3205 - case TEST_UNIT_READY: 3206 - result = test_unit_ready(srb, chip); 3207 - break; 3208 - 3209 - case INQUIRY: 3210 - result = inquiry(srb, chip); 3211 - break; 3212 - 3213 - case READ_CAPACITY: 3214 - result = read_capacity(srb, chip); 3215 - break; 3216 - 3217 - case START_STOP: 3218 - result = start_stop_unit(srb, chip); 3219 - break; 3220 - 3221 - case ALLOW_MEDIUM_REMOVAL: 3222 - result = allow_medium_removal(srb, chip); 3223 - break; 3224 - 3225 - case REQUEST_SENSE: 3226 - result = request_sense(srb, chip); 3227 - break; 3228 - 3229 - case MODE_SENSE: 3230 - case MODE_SENSE_10: 3231 - result = mode_sense(srb, chip); 3232 - break; 3233 - 3234 - case 0x23: 3235 - result = read_format_capacity(srb, chip); 3236 - break; 3237 - 3238 - case VENDOR_CMND: 3239 - result = vendor_cmnd(srb, chip); 3240 - break; 3241 - 3242 - case MS_SP_CMND: 3243 - result = ms_sp_cmnd(srb, chip); 3244 - break; 3245 - 3246 - #ifdef SUPPORT_CPRM 3247 - case SD_PASS_THRU_MODE: 3248 - case SD_EXECUTE_NO_DATA: 3249 - case SD_EXECUTE_READ: 3250 - case SD_EXECUTE_WRITE: 3251 - case SD_GET_RSP: 3252 - case SD_HW_RST: 3253 - result = sd_extension_cmnd(srb, chip); 3254 - break; 3255 - #endif 3256 - 3257 - #ifdef SUPPORT_MAGIC_GATE 3258 - case CMD_MSPRO_MG_RKEY: 3259 - result = mg_report_key(srb, chip); 3260 - break; 3261 - 3262 - case CMD_MSPRO_MG_SKEY: 3263 - result = mg_send_key(srb, chip); 3264 - break; 3265 - #endif 3266 - 3267 - case FORMAT_UNIT: 3268 - case MODE_SELECT: 3269 - case VERIFY: 3270 - result = TRANSPORT_GOOD; 3271 - break; 3272 - 3273 - default: 3274 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3275 - result = TRANSPORT_FAILED; 3276 - } 3277 - 3278 - return result; 3279 - }
-131
drivers/staging/rts5208/rtsx_scsi.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_SCSI_H 13 - #define __REALTEK_RTSX_SCSI_H 14 - 15 - #include "rtsx.h" 16 - #include "rtsx_chip.h" 17 - 18 - #define MS_SP_CMND 0xFA 19 - #define MS_FORMAT 0xA0 20 - #define GET_MS_INFORMATION 0xB0 21 - 22 - #define VENDOR_CMND 0xF0 23 - 24 - #define READ_STATUS 0x09 25 - 26 - #define READ_EEPROM 0x04 27 - #define WRITE_EEPROM 0x05 28 - #define READ_MEM 0x0D 29 - #define WRITE_MEM 0x0E 30 - #define GET_BUS_WIDTH 0x13 31 - #define GET_SD_CSD 0x14 32 - #define TOGGLE_GPIO 0x15 33 - #define TRACE_MSG 0x18 34 - 35 - #define SCSI_APP_CMD 0x10 36 - 37 - #define PP_READ10 0x1A 38 - #define PP_WRITE10 0x0A 39 - #define READ_HOST_REG 0x1D 40 - #define WRITE_HOST_REG 0x0D 41 - #define SET_VAR 0x05 42 - #define GET_VAR 0x15 43 - #define DMA_READ 0x16 44 - #define DMA_WRITE 0x06 45 - #define GET_DEV_STATUS 0x10 46 - #define SET_CHIP_MODE 0x27 47 - #define SUIT_CMD 0xE0 48 - #define WRITE_PHY 0x07 49 - #define READ_PHY 0x17 50 - #define WRITE_EEPROM2 0x03 51 - #define READ_EEPROM2 0x13 52 - #define ERASE_EEPROM2 0x23 53 - #define WRITE_EFUSE 0x04 54 - #define READ_EFUSE 0x14 55 - #define WRITE_CFG 0x0E 56 - #define READ_CFG 0x1E 57 - 58 - #define SPI_VENDOR_COMMAND 0x1C 59 - 60 - #define SCSI_SPI_GETSTATUS 0x00 61 - #define SCSI_SPI_SETPARAMETER 0x01 62 - #define SCSI_SPI_READFALSHID 0x02 63 - #define SCSI_SPI_READFLASH 0x03 64 - #define SCSI_SPI_WRITEFLASH 0x04 65 - #define SCSI_SPI_WRITEFLASHSTATUS 0x05 66 - #define SCSI_SPI_ERASEFLASH 0x06 67 - 68 - #define INIT_BATCHCMD 0x41 69 - #define ADD_BATCHCMD 0x42 70 - #define SEND_BATCHCMD 0x43 71 - #define GET_BATCHRSP 0x44 72 - 73 - #define CHIP_NORMALMODE 0x00 74 - #define CHIP_DEBUGMODE 0x01 75 - 76 - /* SD Pass Through Command Extension */ 77 - #define SD_PASS_THRU_MODE 0xD0 78 - #define SD_EXECUTE_NO_DATA 0xD1 79 - #define SD_EXECUTE_READ 0xD2 80 - #define SD_EXECUTE_WRITE 0xD3 81 - #define SD_GET_RSP 0xD4 82 - #define SD_HW_RST 0xD6 83 - 84 - #ifdef SUPPORT_MAGIC_GATE 85 - #define CMD_MSPRO_MG_RKEY 0xA4 /* Report Key Command */ 86 - #define CMD_MSPRO_MG_SKEY 0xA3 /* Send Key Command */ 87 - 88 - /* CBWCB field: key class */ 89 - #define KC_MG_R_PRO 0xBE /* MG-R PRO*/ 90 - 91 - /* CBWCB field: key format */ 92 - #define KF_SET_LEAF_ID 0x31 /* Set Leaf ID */ 93 - #define KF_GET_LOC_EKB 0x32 /* Get Local EKB */ 94 - #define KF_CHG_HOST 0x33 /* Challenge (host) */ 95 - #define KF_RSP_CHG 0x34 /* Response and Challenge (device) */ 96 - #define KF_RSP_HOST 0x35 /* Response (host) */ 97 - #define KF_GET_ICV 0x36 /* Get ICV */ 98 - #define KF_SET_ICV 0x37 /* SSet ICV */ 99 - #endif 100 - 101 - /* Sense type */ 102 - #define SENSE_TYPE_NO_SENSE 0 103 - #define SENSE_TYPE_MEDIA_CHANGE 1 104 - #define SENSE_TYPE_MEDIA_NOT_PRESENT 2 105 - #define SENSE_TYPE_MEDIA_LBA_OVER_RANGE 3 106 - #define SENSE_TYPE_MEDIA_LUN_NOT_SUPPORT 4 107 - #define SENSE_TYPE_MEDIA_WRITE_PROTECT 5 108 - #define SENSE_TYPE_MEDIA_INVALID_CMD_FIELD 6 109 - #define SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR 7 110 - #define SENSE_TYPE_MEDIA_WRITE_ERR 8 111 - #define SENSE_TYPE_FORMAT_IN_PROGRESS 9 112 - #define SENSE_TYPE_FORMAT_CMD_FAILED 10 113 - #ifdef SUPPORT_MAGIC_GATE 114 - #define SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB 0x0b 115 - #define SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN 0x0c 116 - #define SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM 0x0d 117 - #define SENSE_TYPE_MG_WRITE_ERR 0x0e 118 - #endif 119 - #ifdef SUPPORT_SD_LOCK 120 - /* FOR Locked SD card*/ 121 - #define SENSE_TYPE_MEDIA_READ_FORBIDDEN 0x10 122 - #endif 123 - 124 - void scsi_show_command(struct rtsx_chip *chip); 125 - void set_sense_type(struct rtsx_chip *chip, unsigned int lun, int sense_type); 126 - void set_sense_data(struct rtsx_chip *chip, unsigned int lun, u8 err_code, 127 - u8 sense_key, u32 info, u8 asc, u8 ascq, 128 - u8 sns_key_info0, u16 sns_key_info1); 129 - int rtsx_scsi_handler(struct scsi_cmnd *srb, struct rtsx_chip *chip); 130 - 131 - #endif /* __REALTEK_RTSX_SCSI_H */
-36
drivers/staging/rts5208/rtsx_sys.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __RTSX_SYS_H 13 - #define __RTSX_SYS_H 14 - 15 - #include "rtsx.h" 16 - #include "rtsx_chip.h" 17 - #include "rtsx_card.h" 18 - 19 - static inline void rtsx_exclusive_enter_ss(struct rtsx_chip *chip) 20 - { 21 - struct rtsx_dev *dev = chip->rtsx; 22 - 23 - spin_lock(&dev->reg_lock); 24 - rtsx_enter_ss(chip); 25 - spin_unlock(&dev->reg_lock); 26 - } 27 - 28 - static inline void rtsx_reset_detected_cards(struct rtsx_chip *chip, int flag) 29 - { 30 - rtsx_reset_cards(chip); 31 - } 32 - 33 - #define RTSX_MSG_IN_INT(x) 34 - 35 - #endif /* __RTSX_SYS_H */ 36 -
-768
drivers/staging/rts5208/rtsx_transport.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - 16 - #include "rtsx.h" 17 - 18 - /*********************************************************************** 19 - * Scatter-gather transfer buffer access routines 20 - ***********************************************************************/ 21 - 22 - /* 23 - * Copy a buffer of length buflen to/from the srb's transfer buffer. 24 - * (Note: for scatter-gather transfers (srb->use_sg > 0), srb->request_buffer 25 - * points to a list of s-g entries and we ignore srb->request_bufflen. 26 - * For non-scatter-gather transfers, srb->request_buffer points to the 27 - * transfer buffer itself and srb->request_bufflen is the buffer's length.) 28 - * Update the *index and *offset variables so that the next copy will 29 - * pick up from where this one left off. 30 - */ 31 - 32 - unsigned int rtsx_stor_access_xfer_buf(unsigned char *buffer, 33 - unsigned int buflen, 34 - struct scsi_cmnd *srb, 35 - unsigned int *index, 36 - unsigned int *offset, 37 - enum xfer_buf_dir dir) 38 - { 39 - unsigned int cnt; 40 - 41 - /* If not using scatter-gather, just transfer the data directly. */ 42 - if (scsi_sg_count(srb) == 0) { 43 - unsigned char *sgbuffer; 44 - 45 - if (*offset >= scsi_bufflen(srb)) 46 - return 0; 47 - cnt = min(buflen, scsi_bufflen(srb) - *offset); 48 - 49 - sgbuffer = (unsigned char *)scsi_sglist(srb) + *offset; 50 - 51 - if (dir == TO_XFER_BUF) 52 - memcpy(sgbuffer, buffer, cnt); 53 - else 54 - memcpy(buffer, sgbuffer, cnt); 55 - *offset += cnt; 56 - 57 - /* 58 - * Using scatter-gather. We have to go through the list one entry 59 - * at a time. Each s-g entry contains some number of pages which 60 - * have to be copied one at a time. 61 - */ 62 - } else { 63 - struct scatterlist *sg = 64 - (struct scatterlist *)scsi_sglist(srb) 65 - + *index; 66 - 67 - /* 68 - * This loop handles a single s-g list entry, which may 69 - * include multiple pages. Find the initial page structure 70 - * and the starting offset within the page, and update 71 - * the *offset and *index values for the next loop. 72 - */ 73 - cnt = 0; 74 - while (cnt < buflen && *index < scsi_sg_count(srb)) { 75 - struct page *page = sg_page(sg) + 76 - ((sg->offset + *offset) >> PAGE_SHIFT); 77 - unsigned int poff = (sg->offset + *offset) & 78 - (PAGE_SIZE - 1); 79 - unsigned int sglen = sg->length - *offset; 80 - 81 - if (sglen > buflen - cnt) { 82 - /* Transfer ends within this s-g entry */ 83 - sglen = buflen - cnt; 84 - *offset += sglen; 85 - } else { 86 - /* Transfer continues to next s-g entry */ 87 - *offset = 0; 88 - ++*index; 89 - ++sg; 90 - } 91 - 92 - while (sglen > 0) { 93 - unsigned int plen = min(sglen, (unsigned int) 94 - PAGE_SIZE - poff); 95 - 96 - if (dir == TO_XFER_BUF) 97 - memcpy_to_page(page, poff, buffer + cnt, plen); 98 - else 99 - memcpy_from_page(buffer + cnt, page, poff, plen); 100 - 101 - /* Start at the beginning of the next page */ 102 - poff = 0; 103 - ++page; 104 - cnt += plen; 105 - sglen -= plen; 106 - } 107 - } 108 - } 109 - 110 - /* Return the amount actually transferred */ 111 - return cnt; 112 - } 113 - 114 - /* 115 - * Store the contents of buffer into srb's transfer buffer and set the 116 - * SCSI residue. 117 - */ 118 - void rtsx_stor_set_xfer_buf(unsigned char *buffer, 119 - unsigned int buflen, struct scsi_cmnd *srb) 120 - { 121 - unsigned int index = 0, offset = 0; 122 - 123 - rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset, 124 - TO_XFER_BUF); 125 - if (buflen < scsi_bufflen(srb)) 126 - scsi_set_resid(srb, scsi_bufflen(srb) - buflen); 127 - } 128 - 129 - void rtsx_stor_get_xfer_buf(unsigned char *buffer, 130 - unsigned int buflen, struct scsi_cmnd *srb) 131 - { 132 - unsigned int index = 0, offset = 0; 133 - 134 - rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset, 135 - FROM_XFER_BUF); 136 - if (buflen < scsi_bufflen(srb)) 137 - scsi_set_resid(srb, scsi_bufflen(srb) - buflen); 138 - } 139 - 140 - /*********************************************************************** 141 - * Transport routines 142 - ***********************************************************************/ 143 - 144 - /* 145 - * Invoke the transport and basic error-handling/recovery methods 146 - * 147 - * This is used to send the message to the device and receive the response. 148 - */ 149 - void rtsx_invoke_transport(struct scsi_cmnd *srb, struct rtsx_chip *chip) 150 - { 151 - int result; 152 - 153 - result = rtsx_scsi_handler(srb, chip); 154 - 155 - /* 156 - * if the command gets aborted by the higher layers, we need to 157 - * short-circuit all other processing. 158 - */ 159 - if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) { 160 - dev_dbg(rtsx_dev(chip), "-- command was aborted\n"); 161 - srb->result = DID_ABORT << 16; 162 - goto handle_errors; 163 - } 164 - 165 - /* if there is a transport error, reset and don't auto-sense */ 166 - if (result == TRANSPORT_ERROR) { 167 - dev_dbg(rtsx_dev(chip), "-- transport indicates error, resetting\n"); 168 - srb->result = DID_ERROR << 16; 169 - goto handle_errors; 170 - } 171 - 172 - srb->result = SAM_STAT_GOOD; 173 - 174 - /* 175 - * If we have a failure, we're going to do a REQUEST_SENSE 176 - * automatically. Note that we differentiate between a command 177 - * "failure" and an "error" in the transport mechanism. 178 - */ 179 - if (result == TRANSPORT_FAILED) { 180 - /* set the result so the higher layers expect this data */ 181 - srb->result = SAM_STAT_CHECK_CONDITION; 182 - memcpy(srb->sense_buffer, 183 - (unsigned char *)&chip->sense_buffer[SCSI_LUN(srb)], 184 - sizeof(struct sense_data_t)); 185 - } 186 - 187 - return; 188 - 189 - handle_errors: 190 - return; 191 - } 192 - 193 - void rtsx_add_cmd(struct rtsx_chip *chip, 194 - u8 cmd_type, u16 reg_addr, u8 mask, u8 data) 195 - { 196 - __le32 *cb = (__le32 *)(chip->host_cmds_ptr); 197 - u32 val = 0; 198 - 199 - val |= (u32)(cmd_type & 0x03) << 30; 200 - val |= (u32)(reg_addr & 0x3FFF) << 16; 201 - val |= (u32)mask << 8; 202 - val |= (u32)data; 203 - 204 - spin_lock_irq(&chip->rtsx->reg_lock); 205 - if (chip->ci < (HOST_CMDS_BUF_LEN / 4)) 206 - cb[(chip->ci)++] = cpu_to_le32(val); 207 - 208 - spin_unlock_irq(&chip->rtsx->reg_lock); 209 - } 210 - 211 - void rtsx_send_cmd_no_wait(struct rtsx_chip *chip) 212 - { 213 - u32 val = BIT(31); 214 - 215 - rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); 216 - 217 - val |= (u32)(chip->ci * 4) & 0x00FFFFFF; 218 - /* Hardware Auto Response */ 219 - val |= 0x40000000; 220 - rtsx_writel(chip, RTSX_HCBCTLR, val); 221 - } 222 - 223 - int rtsx_send_cmd(struct rtsx_chip *chip, u8 card, int timeout) 224 - { 225 - struct rtsx_dev *rtsx = chip->rtsx; 226 - struct completion trans_done; 227 - u32 val = BIT(31); 228 - long timeleft; 229 - int err = 0; 230 - 231 - if (card == SD_CARD) 232 - rtsx->check_card_cd = SD_EXIST; 233 - else if (card == MS_CARD) 234 - rtsx->check_card_cd = MS_EXIST; 235 - else if (card == XD_CARD) 236 - rtsx->check_card_cd = XD_EXIST; 237 - else 238 - rtsx->check_card_cd = 0; 239 - 240 - spin_lock_irq(&rtsx->reg_lock); 241 - 242 - /* set up data structures for the wakeup system */ 243 - rtsx->done = &trans_done; 244 - rtsx->trans_result = TRANS_NOT_READY; 245 - init_completion(&trans_done); 246 - rtsx->trans_state = STATE_TRANS_CMD; 247 - 248 - rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr); 249 - 250 - val |= (u32)(chip->ci * 4) & 0x00FFFFFF; 251 - /* Hardware Auto Response */ 252 - val |= 0x40000000; 253 - rtsx_writel(chip, RTSX_HCBCTLR, val); 254 - 255 - spin_unlock_irq(&rtsx->reg_lock); 256 - 257 - /* Wait for TRANS_OK_INT */ 258 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 259 - msecs_to_jiffies(timeout)); 260 - if (timeleft <= 0) { 261 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 262 - chip->int_reg); 263 - err = -ETIMEDOUT; 264 - goto finish_send_cmd; 265 - } 266 - 267 - spin_lock_irq(&rtsx->reg_lock); 268 - if (rtsx->trans_result == TRANS_RESULT_FAIL) 269 - err = -EIO; 270 - else if (rtsx->trans_result == TRANS_RESULT_OK) 271 - err = 0; 272 - 273 - spin_unlock_irq(&rtsx->reg_lock); 274 - 275 - finish_send_cmd: 276 - rtsx->done = NULL; 277 - rtsx->trans_state = STATE_TRANS_NONE; 278 - 279 - if (err < 0) 280 - rtsx_stop_cmd(chip, card); 281 - 282 - return err; 283 - } 284 - 285 - static inline void rtsx_add_sg_tbl(struct rtsx_chip *chip, 286 - u32 addr, u32 len, u8 option) 287 - { 288 - __le64 *sgb = (__le64 *)(chip->host_sg_tbl_ptr); 289 - u64 val = 0; 290 - u32 temp_len = 0; 291 - u8 temp_opt = 0; 292 - 293 - do { 294 - if (len > 0x80000) { 295 - temp_len = 0x80000; 296 - temp_opt = option & (~RTSX_SG_END); 297 - } else { 298 - temp_len = len; 299 - temp_opt = option; 300 - } 301 - val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt; 302 - 303 - if (chip->sgi < (HOST_SG_TBL_BUF_LEN / 8)) 304 - sgb[(chip->sgi)++] = cpu_to_le64(val); 305 - 306 - len -= temp_len; 307 - addr += temp_len; 308 - } while (len); 309 - } 310 - 311 - static int rtsx_transfer_sglist_adma_partial(struct rtsx_chip *chip, u8 card, 312 - struct scatterlist *sg, int num_sg, 313 - unsigned int *index, 314 - unsigned int *offset, int size, 315 - enum dma_data_direction dma_dir, 316 - int timeout) 317 - { 318 - struct rtsx_dev *rtsx = chip->rtsx; 319 - struct completion trans_done; 320 - u8 dir; 321 - int sg_cnt, i, resid; 322 - int err = 0; 323 - long timeleft; 324 - struct scatterlist *sg_ptr; 325 - u32 val = TRIG_DMA; 326 - 327 - if (!sg || num_sg <= 0 || !offset || !index) 328 - return -EIO; 329 - 330 - if (dma_dir == DMA_TO_DEVICE) 331 - dir = HOST_TO_DEVICE; 332 - else if (dma_dir == DMA_FROM_DEVICE) 333 - dir = DEVICE_TO_HOST; 334 - else 335 - return -ENXIO; 336 - 337 - if (card == SD_CARD) 338 - rtsx->check_card_cd = SD_EXIST; 339 - else if (card == MS_CARD) 340 - rtsx->check_card_cd = MS_EXIST; 341 - else if (card == XD_CARD) 342 - rtsx->check_card_cd = XD_EXIST; 343 - else 344 - rtsx->check_card_cd = 0; 345 - 346 - spin_lock_irq(&rtsx->reg_lock); 347 - 348 - /* set up data structures for the wakeup system */ 349 - rtsx->done = &trans_done; 350 - 351 - rtsx->trans_state = STATE_TRANS_SG; 352 - rtsx->trans_result = TRANS_NOT_READY; 353 - 354 - spin_unlock_irq(&rtsx->reg_lock); 355 - 356 - sg_cnt = dma_map_sg(&rtsx->pci->dev, sg, num_sg, dma_dir); 357 - 358 - resid = size; 359 - sg_ptr = sg; 360 - chip->sgi = 0; 361 - /* 362 - * Usually the next entry will be @sg@ + 1, but if this sg element 363 - * is part of a chained scatterlist, it could jump to the start of 364 - * a new scatterlist array. So here we use sg_next to move to 365 - * the proper sg. 366 - */ 367 - for (i = 0; i < *index; i++) 368 - sg_ptr = sg_next(sg_ptr); 369 - for (i = *index; i < sg_cnt; i++) { 370 - dma_addr_t addr; 371 - unsigned int len; 372 - u8 option; 373 - 374 - addr = sg_dma_address(sg_ptr); 375 - len = sg_dma_len(sg_ptr); 376 - 377 - dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n", 378 - (unsigned int)addr, len); 379 - dev_dbg(rtsx_dev(chip), "*index = %d, *offset = %d\n", 380 - *index, *offset); 381 - 382 - addr += *offset; 383 - 384 - if ((len - *offset) > resid) { 385 - *offset += resid; 386 - len = resid; 387 - resid = 0; 388 - } else { 389 - resid -= (len - *offset); 390 - len -= *offset; 391 - *offset = 0; 392 - *index = *index + 1; 393 - } 394 - option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 395 - if ((i == sg_cnt - 1) || !resid) 396 - option |= RTSX_SG_END; 397 - 398 - rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option); 399 - 400 - if (!resid) 401 - break; 402 - 403 - sg_ptr = sg_next(sg_ptr); 404 - } 405 - 406 - dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi); 407 - 408 - val |= (u32)(dir & 0x01) << 29; 409 - val |= ADMA_MODE; 410 - 411 - spin_lock_irq(&rtsx->reg_lock); 412 - 413 - init_completion(&trans_done); 414 - 415 - rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr); 416 - rtsx_writel(chip, RTSX_HDBCTLR, val); 417 - 418 - spin_unlock_irq(&rtsx->reg_lock); 419 - 420 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 421 - msecs_to_jiffies(timeout)); 422 - if (timeleft <= 0) { 423 - dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n", 424 - __func__, __LINE__); 425 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 426 - chip->int_reg); 427 - err = -ETIMEDOUT; 428 - goto out; 429 - } 430 - 431 - spin_lock_irq(&rtsx->reg_lock); 432 - if (rtsx->trans_result == TRANS_RESULT_FAIL) { 433 - err = -EIO; 434 - spin_unlock_irq(&rtsx->reg_lock); 435 - goto out; 436 - } 437 - spin_unlock_irq(&rtsx->reg_lock); 438 - 439 - /* Wait for TRANS_OK_INT */ 440 - spin_lock_irq(&rtsx->reg_lock); 441 - if (rtsx->trans_result == TRANS_NOT_READY) { 442 - init_completion(&trans_done); 443 - spin_unlock_irq(&rtsx->reg_lock); 444 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 445 - msecs_to_jiffies(timeout)); 446 - if (timeleft <= 0) { 447 - dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n", 448 - __func__, __LINE__); 449 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 450 - chip->int_reg); 451 - err = -ETIMEDOUT; 452 - goto out; 453 - } 454 - } else { 455 - spin_unlock_irq(&rtsx->reg_lock); 456 - } 457 - 458 - spin_lock_irq(&rtsx->reg_lock); 459 - if (rtsx->trans_result == TRANS_RESULT_FAIL) 460 - err = -EIO; 461 - else if (rtsx->trans_result == TRANS_RESULT_OK) 462 - err = 0; 463 - 464 - spin_unlock_irq(&rtsx->reg_lock); 465 - 466 - out: 467 - rtsx->done = NULL; 468 - rtsx->trans_state = STATE_TRANS_NONE; 469 - dma_unmap_sg(&rtsx->pci->dev, sg, num_sg, dma_dir); 470 - 471 - if (err < 0) 472 - rtsx_stop_cmd(chip, card); 473 - 474 - return err; 475 - } 476 - 477 - static int rtsx_transfer_sglist_adma(struct rtsx_chip *chip, u8 card, 478 - struct scatterlist *sg, int num_sg, 479 - enum dma_data_direction dma_dir, 480 - int timeout) 481 - { 482 - struct rtsx_dev *rtsx = chip->rtsx; 483 - struct completion trans_done; 484 - u8 dir; 485 - int buf_cnt, i; 486 - int err = 0; 487 - long timeleft; 488 - struct scatterlist *sg_ptr; 489 - 490 - if (!sg || num_sg <= 0) 491 - return -EIO; 492 - 493 - if (dma_dir == DMA_TO_DEVICE) 494 - dir = HOST_TO_DEVICE; 495 - else if (dma_dir == DMA_FROM_DEVICE) 496 - dir = DEVICE_TO_HOST; 497 - else 498 - return -ENXIO; 499 - 500 - if (card == SD_CARD) 501 - rtsx->check_card_cd = SD_EXIST; 502 - else if (card == MS_CARD) 503 - rtsx->check_card_cd = MS_EXIST; 504 - else if (card == XD_CARD) 505 - rtsx->check_card_cd = XD_EXIST; 506 - else 507 - rtsx->check_card_cd = 0; 508 - 509 - spin_lock_irq(&rtsx->reg_lock); 510 - 511 - /* set up data structures for the wakeup system */ 512 - rtsx->done = &trans_done; 513 - 514 - rtsx->trans_state = STATE_TRANS_SG; 515 - rtsx->trans_result = TRANS_NOT_READY; 516 - 517 - spin_unlock_irq(&rtsx->reg_lock); 518 - 519 - buf_cnt = dma_map_sg(&rtsx->pci->dev, sg, num_sg, dma_dir); 520 - 521 - sg_ptr = sg; 522 - 523 - for (i = 0; i <= buf_cnt / (HOST_SG_TBL_BUF_LEN / 8); i++) { 524 - u32 val = TRIG_DMA; 525 - int sg_cnt, j; 526 - 527 - if (i == buf_cnt / (HOST_SG_TBL_BUF_LEN / 8)) 528 - sg_cnt = buf_cnt % (HOST_SG_TBL_BUF_LEN / 8); 529 - else 530 - sg_cnt = HOST_SG_TBL_BUF_LEN / 8; 531 - 532 - chip->sgi = 0; 533 - for (j = 0; j < sg_cnt; j++) { 534 - dma_addr_t addr = sg_dma_address(sg_ptr); 535 - unsigned int len = sg_dma_len(sg_ptr); 536 - u8 option; 537 - 538 - dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n", 539 - (unsigned int)addr, len); 540 - 541 - option = RTSX_SG_VALID | RTSX_SG_TRANS_DATA; 542 - if (j == (sg_cnt - 1)) 543 - option |= RTSX_SG_END; 544 - 545 - rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option); 546 - 547 - sg_ptr = sg_next(sg_ptr); 548 - } 549 - 550 - dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi); 551 - 552 - val |= (u32)(dir & 0x01) << 29; 553 - val |= ADMA_MODE; 554 - 555 - spin_lock_irq(&rtsx->reg_lock); 556 - 557 - init_completion(&trans_done); 558 - 559 - rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr); 560 - rtsx_writel(chip, RTSX_HDBCTLR, val); 561 - 562 - spin_unlock_irq(&rtsx->reg_lock); 563 - 564 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 565 - msecs_to_jiffies(timeout)); 566 - if (timeleft <= 0) { 567 - dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n", 568 - __func__, __LINE__); 569 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 570 - chip->int_reg); 571 - err = -ETIMEDOUT; 572 - goto out; 573 - } 574 - 575 - spin_lock_irq(&rtsx->reg_lock); 576 - if (rtsx->trans_result == TRANS_RESULT_FAIL) { 577 - err = -EIO; 578 - spin_unlock_irq(&rtsx->reg_lock); 579 - goto out; 580 - } 581 - spin_unlock_irq(&rtsx->reg_lock); 582 - 583 - sg_ptr += sg_cnt; 584 - } 585 - 586 - /* Wait for TRANS_OK_INT */ 587 - spin_lock_irq(&rtsx->reg_lock); 588 - if (rtsx->trans_result == TRANS_NOT_READY) { 589 - init_completion(&trans_done); 590 - spin_unlock_irq(&rtsx->reg_lock); 591 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 592 - msecs_to_jiffies(timeout)); 593 - if (timeleft <= 0) { 594 - dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n", 595 - __func__, __LINE__); 596 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 597 - chip->int_reg); 598 - err = -ETIMEDOUT; 599 - goto out; 600 - } 601 - } else { 602 - spin_unlock_irq(&rtsx->reg_lock); 603 - } 604 - 605 - spin_lock_irq(&rtsx->reg_lock); 606 - if (rtsx->trans_result == TRANS_RESULT_FAIL) 607 - err = -EIO; 608 - else if (rtsx->trans_result == TRANS_RESULT_OK) 609 - err = 0; 610 - 611 - spin_unlock_irq(&rtsx->reg_lock); 612 - 613 - out: 614 - rtsx->done = NULL; 615 - rtsx->trans_state = STATE_TRANS_NONE; 616 - dma_unmap_sg(&rtsx->pci->dev, sg, num_sg, dma_dir); 617 - 618 - if (err < 0) 619 - rtsx_stop_cmd(chip, card); 620 - 621 - return err; 622 - } 623 - 624 - static int rtsx_transfer_buf(struct rtsx_chip *chip, u8 card, void *buf, 625 - size_t len, enum dma_data_direction dma_dir, 626 - int timeout) 627 - { 628 - struct rtsx_dev *rtsx = chip->rtsx; 629 - struct completion trans_done; 630 - dma_addr_t addr; 631 - u8 dir; 632 - int err = 0; 633 - u32 val = BIT(31); 634 - long timeleft; 635 - 636 - if (!buf || len <= 0) 637 - return -EIO; 638 - 639 - if (dma_dir == DMA_TO_DEVICE) 640 - dir = HOST_TO_DEVICE; 641 - else if (dma_dir == DMA_FROM_DEVICE) 642 - dir = DEVICE_TO_HOST; 643 - else 644 - return -ENXIO; 645 - 646 - addr = dma_map_single(&rtsx->pci->dev, buf, len, dma_dir); 647 - if (dma_mapping_error(&rtsx->pci->dev, addr)) 648 - return -ENOMEM; 649 - 650 - if (card == SD_CARD) 651 - rtsx->check_card_cd = SD_EXIST; 652 - else if (card == MS_CARD) 653 - rtsx->check_card_cd = MS_EXIST; 654 - else if (card == XD_CARD) 655 - rtsx->check_card_cd = XD_EXIST; 656 - else 657 - rtsx->check_card_cd = 0; 658 - 659 - val |= (u32)(dir & 0x01) << 29; 660 - val |= (u32)(len & 0x00FFFFFF); 661 - 662 - spin_lock_irq(&rtsx->reg_lock); 663 - 664 - /* set up data structures for the wakeup system */ 665 - rtsx->done = &trans_done; 666 - 667 - init_completion(&trans_done); 668 - 669 - rtsx->trans_state = STATE_TRANS_BUF; 670 - rtsx->trans_result = TRANS_NOT_READY; 671 - 672 - rtsx_writel(chip, RTSX_HDBAR, addr); 673 - rtsx_writel(chip, RTSX_HDBCTLR, val); 674 - 675 - spin_unlock_irq(&rtsx->reg_lock); 676 - 677 - /* Wait for TRANS_OK_INT */ 678 - timeleft = wait_for_completion_interruptible_timeout(&trans_done, 679 - msecs_to_jiffies(timeout)); 680 - if (timeleft <= 0) { 681 - dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n", 682 - __func__, __LINE__); 683 - dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n", 684 - chip->int_reg); 685 - err = -ETIMEDOUT; 686 - goto out; 687 - } 688 - 689 - spin_lock_irq(&rtsx->reg_lock); 690 - if (rtsx->trans_result == TRANS_RESULT_FAIL) 691 - err = -EIO; 692 - else if (rtsx->trans_result == TRANS_RESULT_OK) 693 - err = 0; 694 - 695 - spin_unlock_irq(&rtsx->reg_lock); 696 - 697 - out: 698 - rtsx->done = NULL; 699 - rtsx->trans_state = STATE_TRANS_NONE; 700 - dma_unmap_single(&rtsx->pci->dev, addr, len, dma_dir); 701 - 702 - if (err < 0) 703 - rtsx_stop_cmd(chip, card); 704 - 705 - return err; 706 - } 707 - 708 - int rtsx_transfer_data_partial(struct rtsx_chip *chip, u8 card, 709 - void *buf, size_t len, int use_sg, 710 - unsigned int *index, unsigned int *offset, 711 - enum dma_data_direction dma_dir, int timeout) 712 - { 713 - int err = 0; 714 - 715 - /* don't transfer data during abort processing */ 716 - if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) 717 - return -EIO; 718 - 719 - if (use_sg) { 720 - struct scatterlist *sg = buf; 721 - 722 - err = rtsx_transfer_sglist_adma_partial(chip, card, sg, use_sg, 723 - index, offset, (int)len, 724 - dma_dir, timeout); 725 - } else { 726 - err = rtsx_transfer_buf(chip, card, 727 - buf, len, dma_dir, timeout); 728 - } 729 - if (err < 0) { 730 - if (RTSX_TST_DELINK(chip)) { 731 - RTSX_CLR_DELINK(chip); 732 - chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 733 - rtsx_reinit_cards(chip, 1); 734 - } 735 - } 736 - 737 - return err; 738 - } 739 - 740 - int rtsx_transfer_data(struct rtsx_chip *chip, u8 card, void *buf, size_t len, 741 - int use_sg, enum dma_data_direction dma_dir, int timeout) 742 - { 743 - int err = 0; 744 - 745 - dev_dbg(rtsx_dev(chip), "use_sg = %d\n", use_sg); 746 - 747 - /* don't transfer data during abort processing */ 748 - if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) 749 - return -EIO; 750 - 751 - if (use_sg) { 752 - err = rtsx_transfer_sglist_adma(chip, card, buf, 753 - use_sg, dma_dir, timeout); 754 - } else { 755 - err = rtsx_transfer_buf(chip, card, buf, len, dma_dir, timeout); 756 - } 757 - 758 - if (err < 0) { 759 - if (RTSX_TST_DELINK(chip)) { 760 - RTSX_CLR_DELINK(chip); 761 - chip->need_reinit = SD_CARD | MS_CARD | XD_CARD; 762 - rtsx_reinit_cards(chip, 1); 763 - } 764 - } 765 - 766 - return err; 767 - } 768 -
-57
drivers/staging/rts5208/rtsx_transport.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_TRANSPORT_H 13 - #define __REALTEK_RTSX_TRANSPORT_H 14 - 15 - #include "rtsx.h" 16 - #include "rtsx_chip.h" 17 - 18 - #define WAIT_TIME 2000 19 - 20 - unsigned int rtsx_stor_access_xfer_buf(unsigned char *buffer, 21 - unsigned int buflen, 22 - struct scsi_cmnd *srb, 23 - unsigned int *index, 24 - unsigned int *offset, 25 - enum xfer_buf_dir dir); 26 - void rtsx_stor_set_xfer_buf(unsigned char *buffer, unsigned int buflen, 27 - struct scsi_cmnd *srb); 28 - void rtsx_stor_get_xfer_buf(unsigned char *buffer, unsigned int buflen, 29 - struct scsi_cmnd *srb); 30 - void rtsx_invoke_transport(struct scsi_cmnd *srb, struct rtsx_chip *chip); 31 - 32 - #define rtsx_init_cmd(chip) ((chip)->ci = 0) 33 - 34 - void rtsx_add_cmd(struct rtsx_chip *chip, u8 cmd_type, u16 reg_addr, u8 mask, 35 - u8 data); 36 - void rtsx_send_cmd_no_wait(struct rtsx_chip *chip); 37 - int rtsx_send_cmd(struct rtsx_chip *chip, u8 card, int timeout); 38 - 39 - static inline u8 *rtsx_get_cmd_data(struct rtsx_chip *chip) 40 - { 41 - #ifdef CMD_USING_SG 42 - return (u8 *)(chip->host_sg_tbl_ptr); 43 - #else 44 - return (u8 *)(chip->host_cmds_ptr); 45 - #endif 46 - } 47 - 48 - int rtsx_transfer_data(struct rtsx_chip *chip, u8 card, void *buf, size_t len, 49 - int use_sg, enum dma_data_direction dma_dir, 50 - int timeout); 51 - 52 - int rtsx_transfer_data_partial(struct rtsx_chip *chip, u8 card, void *buf, 53 - size_t len, int use_sg, unsigned int *index, 54 - unsigned int *offset, 55 - enum dma_data_direction dma_dir, int timeout); 56 - 57 - #endif /* __REALTEK_RTSX_TRANSPORT_H */
-4717
drivers/staging/rts5208/sd.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - 16 - #include "rtsx.h" 17 - #include "sd.h" 18 - 19 - #define SD_MAX_RETRY_COUNT 3 20 - 21 - static u16 REG_SD_CFG1; 22 - static u16 REG_SD_CFG2; 23 - static u16 REG_SD_CFG3; 24 - static u16 REG_SD_STAT1; 25 - static u16 REG_SD_STAT2; 26 - static u16 REG_SD_BUS_STAT; 27 - static u16 REG_SD_PAD_CTL; 28 - static u16 REG_SD_SAMPLE_POINT_CTL; 29 - static u16 REG_SD_PUSH_POINT_CTL; 30 - static u16 REG_SD_CMD0; 31 - static u16 REG_SD_CMD1; 32 - static u16 REG_SD_CMD2; 33 - static u16 REG_SD_CMD3; 34 - static u16 REG_SD_CMD4; 35 - static u16 REG_SD_CMD5; 36 - static u16 REG_SD_BYTE_CNT_L; 37 - static u16 REG_SD_BYTE_CNT_H; 38 - static u16 REG_SD_BLOCK_CNT_L; 39 - static u16 REG_SD_BLOCK_CNT_H; 40 - static u16 REG_SD_TRANSFER; 41 - static u16 REG_SD_VPCLK0_CTL; 42 - static u16 REG_SD_VPCLK1_CTL; 43 - static u16 REG_SD_DCMPS0_CTL; 44 - static u16 REG_SD_DCMPS1_CTL; 45 - 46 - static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code) 47 - { 48 - struct sd_info *sd_card = &chip->sd_card; 49 - 50 - sd_card->err_code |= err_code; 51 - } 52 - 53 - static inline void sd_clr_err_code(struct rtsx_chip *chip) 54 - { 55 - struct sd_info *sd_card = &chip->sd_card; 56 - 57 - sd_card->err_code = 0; 58 - } 59 - 60 - static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code) 61 - { 62 - struct sd_info *sd_card = &chip->sd_card; 63 - 64 - return sd_card->err_code & err_code; 65 - } 66 - 67 - static void sd_init_reg_addr(struct rtsx_chip *chip) 68 - { 69 - REG_SD_CFG1 = 0xFD31; 70 - REG_SD_CFG2 = 0xFD33; 71 - REG_SD_CFG3 = 0xFD3E; 72 - REG_SD_STAT1 = 0xFD30; 73 - REG_SD_STAT2 = 0; 74 - REG_SD_BUS_STAT = 0; 75 - REG_SD_PAD_CTL = 0; 76 - REG_SD_SAMPLE_POINT_CTL = 0; 77 - REG_SD_PUSH_POINT_CTL = 0; 78 - REG_SD_CMD0 = 0xFD34; 79 - REG_SD_CMD1 = 0xFD35; 80 - REG_SD_CMD2 = 0xFD36; 81 - REG_SD_CMD3 = 0xFD37; 82 - REG_SD_CMD4 = 0xFD38; 83 - REG_SD_CMD5 = 0xFD5A; 84 - REG_SD_BYTE_CNT_L = 0xFD39; 85 - REG_SD_BYTE_CNT_H = 0xFD3A; 86 - REG_SD_BLOCK_CNT_L = 0xFD3B; 87 - REG_SD_BLOCK_CNT_H = 0xFD3C; 88 - REG_SD_TRANSFER = 0xFD32; 89 - REG_SD_VPCLK0_CTL = 0; 90 - REG_SD_VPCLK1_CTL = 0; 91 - REG_SD_DCMPS0_CTL = 0; 92 - REG_SD_DCMPS1_CTL = 0; 93 - } 94 - 95 - static int sd_check_data0_status(struct rtsx_chip *chip) 96 - { 97 - int retval; 98 - u8 stat; 99 - 100 - retval = rtsx_read_register(chip, REG_SD_STAT1, &stat); 101 - if (retval) 102 - return retval; 103 - 104 - if (!(stat & SD_DAT0_STATUS)) { 105 - sd_set_err_code(chip, SD_BUSY); 106 - return STATUS_FAIL; 107 - } 108 - 109 - return STATUS_SUCCESS; 110 - } 111 - 112 - static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 113 - u32 arg, u8 rsp_type, u8 *rsp, int rsp_len) 114 - { 115 - struct sd_info *sd_card = &chip->sd_card; 116 - int retval; 117 - int timeout = 100; 118 - u16 reg_addr; 119 - u8 *ptr; 120 - int stat_idx = 0; 121 - int rty_cnt = 0; 122 - 123 - sd_clr_err_code(chip); 124 - 125 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg); 126 - 127 - if (rsp_type == SD_RSP_TYPE_R1b) 128 - timeout = 3000; 129 - 130 - RTY_SEND_CMD: 131 - 132 - rtsx_init_cmd(chip); 133 - 134 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); 135 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); 136 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); 137 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); 138 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); 139 - 140 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 141 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 142 - 0x01, PINGPONG_BUFFER); 143 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 144 - 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 145 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 146 - SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | 147 - SD_STAT_IDLE); 148 - 149 - if (rsp_type == SD_RSP_TYPE_R2) { 150 - for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 151 - reg_addr++) 152 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 153 - 154 - stat_idx = 16; 155 - } else if (rsp_type != SD_RSP_TYPE_R0) { 156 - for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 157 - reg_addr++) 158 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 159 - 160 - stat_idx = 5; 161 - } 162 - 163 - rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); 164 - 165 - retval = rtsx_send_cmd(chip, SD_CARD, timeout); 166 - if (retval < 0) { 167 - u8 val; 168 - 169 - rtsx_read_register(chip, REG_SD_STAT1, &val); 170 - dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val); 171 - 172 - rtsx_read_register(chip, REG_SD_CFG3, &val); 173 - dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val); 174 - 175 - if (retval == -ETIMEDOUT) { 176 - if (rsp_type & SD_WAIT_BUSY_END) { 177 - retval = sd_check_data0_status(chip); 178 - if (retval != STATUS_SUCCESS) { 179 - rtsx_clear_sd_error(chip); 180 - return retval; 181 - } 182 - } else { 183 - sd_set_err_code(chip, SD_TO_ERR); 184 - } 185 - retval = STATUS_TIMEDOUT; 186 - } else { 187 - retval = STATUS_FAIL; 188 - } 189 - rtsx_clear_sd_error(chip); 190 - 191 - return retval; 192 - } 193 - 194 - if (rsp_type == SD_RSP_TYPE_R0) 195 - return STATUS_SUCCESS; 196 - 197 - ptr = rtsx_get_cmd_data(chip) + 1; 198 - 199 - if ((ptr[0] & 0xC0) != 0) { 200 - sd_set_err_code(chip, SD_STS_ERR); 201 - return STATUS_FAIL; 202 - } 203 - 204 - if (!(rsp_type & SD_NO_CHECK_CRC7)) { 205 - if (ptr[stat_idx] & SD_CRC7_ERR) { 206 - if (cmd_idx == WRITE_MULTIPLE_BLOCK) { 207 - sd_set_err_code(chip, SD_CRC_ERR); 208 - return STATUS_FAIL; 209 - } 210 - if (rty_cnt < SD_MAX_RETRY_COUNT) { 211 - wait_timeout(20); 212 - rty_cnt++; 213 - goto RTY_SEND_CMD; 214 - } else { 215 - sd_set_err_code(chip, SD_CRC_ERR); 216 - return STATUS_FAIL; 217 - } 218 - } 219 - } 220 - 221 - if (rsp_type == SD_RSP_TYPE_R1 || rsp_type == SD_RSP_TYPE_R1b) { 222 - if (cmd_idx != SEND_RELATIVE_ADDR && 223 - cmd_idx != SEND_IF_COND) { 224 - if (cmd_idx != STOP_TRANSMISSION) { 225 - if (ptr[1] & 0x80) 226 - return STATUS_FAIL; 227 - } 228 - #ifdef SUPPORT_SD_LOCK 229 - if (ptr[1] & 0x7D) { 230 - #else 231 - if (ptr[1] & 0x7F) { 232 - #endif 233 - dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n", 234 - ptr[1]); 235 - return STATUS_FAIL; 236 - } 237 - if (ptr[2] & 0xFF) { 238 - dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n", 239 - ptr[2]); 240 - return STATUS_FAIL; 241 - } 242 - if (ptr[3] & 0x80) { 243 - dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n", 244 - ptr[3]); 245 - return STATUS_FAIL; 246 - } 247 - if (ptr[3] & 0x01) 248 - sd_card->sd_data_buf_ready = 1; 249 - else 250 - sd_card->sd_data_buf_ready = 0; 251 - } 252 - } 253 - 254 - if (rsp && rsp_len) 255 - memcpy(rsp, ptr, rsp_len); 256 - 257 - return STATUS_SUCCESS; 258 - } 259 - 260 - static int sd_read_data(struct rtsx_chip *chip, 261 - u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt, 262 - u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, 263 - int timeout) 264 - { 265 - struct sd_info *sd_card = &chip->sd_card; 266 - int retval; 267 - int i; 268 - 269 - sd_clr_err_code(chip); 270 - 271 - if (!buf) 272 - buf_len = 0; 273 - 274 - if (buf_len > 512) 275 - return STATUS_FAIL; 276 - 277 - rtsx_init_cmd(chip); 278 - 279 - if (cmd_len) { 280 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40); 281 - for (i = 0; i < (min(cmd_len, 6)); i++) 282 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 283 - 0xFF, cmd[i]); 284 - } 285 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 286 - (u8)byte_cnt); 287 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 288 - (u8)(byte_cnt >> 8)); 289 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 290 - (u8)blk_cnt); 291 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 292 - (u8)(blk_cnt >> 8)); 293 - 294 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 295 - 296 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 297 - SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | 298 - SD_CHECK_CRC7 | SD_RSP_LEN_6); 299 - if (trans_mode != SD_TM_AUTO_TUNING) 300 - rtsx_add_cmd(chip, WRITE_REG_CMD, 301 - CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 302 - 303 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 304 - trans_mode | SD_TRANSFER_START); 305 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 306 - SD_TRANSFER_END); 307 - 308 - retval = rtsx_send_cmd(chip, SD_CARD, timeout); 309 - if (retval < 0) { 310 - if (retval == -ETIMEDOUT) { 311 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 312 - SD_RSP_TYPE_R1, NULL, 0); 313 - } 314 - 315 - return STATUS_FAIL; 316 - } 317 - 318 - if (buf && buf_len) { 319 - retval = rtsx_read_ppbuf(chip, buf, buf_len); 320 - if (retval != STATUS_SUCCESS) 321 - return STATUS_FAIL; 322 - } 323 - 324 - return STATUS_SUCCESS; 325 - } 326 - 327 - static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode, 328 - u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, 329 - u8 bus_width, u8 *buf, int buf_len, int timeout) 330 - { 331 - struct sd_info *sd_card = &chip->sd_card; 332 - int retval; 333 - int i; 334 - 335 - sd_clr_err_code(chip); 336 - 337 - if (!buf) 338 - buf_len = 0; 339 - 340 - if (buf_len > 512) { 341 - /* This function can't write data more than one page */ 342 - return STATUS_FAIL; 343 - } 344 - 345 - if (buf && buf_len) { 346 - retval = rtsx_write_ppbuf(chip, buf, buf_len); 347 - if (retval != STATUS_SUCCESS) 348 - return STATUS_FAIL; 349 - } 350 - 351 - rtsx_init_cmd(chip); 352 - 353 - if (cmd_len) { 354 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40); 355 - for (i = 0; i < (min(cmd_len, 6)); i++) { 356 - rtsx_add_cmd(chip, WRITE_REG_CMD, 357 - REG_SD_CMD0 + i, 0xFF, cmd[i]); 358 - } 359 - } 360 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 361 - (u8)byte_cnt); 362 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 363 - (u8)(byte_cnt >> 8)); 364 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 365 - (u8)blk_cnt); 366 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 367 - (u8)(blk_cnt >> 8)); 368 - 369 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 370 - 371 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 372 - SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | 373 - SD_CHECK_CRC7 | SD_RSP_LEN_6); 374 - 375 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 376 - trans_mode | SD_TRANSFER_START); 377 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 378 - SD_TRANSFER_END); 379 - 380 - retval = rtsx_send_cmd(chip, SD_CARD, timeout); 381 - if (retval < 0) { 382 - if (retval == -ETIMEDOUT) { 383 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 384 - SD_RSP_TYPE_R1, NULL, 0); 385 - } 386 - 387 - return STATUS_FAIL; 388 - } 389 - 390 - return STATUS_SUCCESS; 391 - } 392 - 393 - static int sd_check_csd(struct rtsx_chip *chip, char check_wp) 394 - { 395 - struct sd_info *sd_card = &chip->sd_card; 396 - int retval; 397 - int i; 398 - u8 csd_ver, trans_speed; 399 - u8 rsp[16]; 400 - 401 - for (i = 0; i < 6; i++) { 402 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 403 - sd_set_err_code(chip, SD_NO_CARD); 404 - return STATUS_FAIL; 405 - } 406 - 407 - retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, 408 - SD_RSP_TYPE_R2, rsp, 16); 409 - if (retval == STATUS_SUCCESS) 410 - break; 411 - } 412 - 413 - if (i == 6) 414 - return STATUS_FAIL; 415 - 416 - memcpy(sd_card->raw_csd, rsp + 1, 15); 417 - 418 - dev_dbg(rtsx_dev(chip), "CSD Response:\n"); 419 - dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd); 420 - 421 - csd_ver = (rsp[1] & 0xc0) >> 6; 422 - dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver); 423 - 424 - trans_speed = rsp[4]; 425 - if ((trans_speed & 0x07) == 0x02) { 426 - if ((trans_speed & 0xf8) >= 0x30) { 427 - if (chip->asic_code) 428 - sd_card->sd_clock = 47; 429 - else 430 - sd_card->sd_clock = CLK_50; 431 - 432 - } else if ((trans_speed & 0xf8) == 0x28) { 433 - if (chip->asic_code) 434 - sd_card->sd_clock = 39; 435 - else 436 - sd_card->sd_clock = CLK_40; 437 - 438 - } else if ((trans_speed & 0xf8) == 0x20) { 439 - if (chip->asic_code) 440 - sd_card->sd_clock = 29; 441 - else 442 - sd_card->sd_clock = CLK_30; 443 - 444 - } else if ((trans_speed & 0xf8) >= 0x10) { 445 - if (chip->asic_code) 446 - sd_card->sd_clock = 23; 447 - else 448 - sd_card->sd_clock = CLK_20; 449 - 450 - } else if ((trans_speed & 0x08) >= 0x08) { 451 - if (chip->asic_code) 452 - sd_card->sd_clock = 19; 453 - else 454 - sd_card->sd_clock = CLK_20; 455 - } else { 456 - return STATUS_FAIL; 457 - } 458 - } else { 459 - return STATUS_FAIL; 460 - } 461 - 462 - if (CHK_MMC_SECTOR_MODE(sd_card)) { 463 - sd_card->capacity = 0; 464 - } else { 465 - if ((!CHK_SD_HCXC(sd_card)) || csd_ver == 0) { 466 - u8 blk_size, c_size_mult; 467 - u16 c_size; 468 - 469 - blk_size = rsp[6] & 0x0F; 470 - c_size = ((u16)(rsp[7] & 0x03) << 10) 471 - + ((u16)rsp[8] << 2) 472 - + ((u16)(rsp[9] & 0xC0) >> 6); 473 - c_size_mult = (u8)((rsp[10] & 0x03) << 1); 474 - c_size_mult += (rsp[11] & 0x80) >> 7; 475 - sd_card->capacity = (((u32)(c_size + 1)) * 476 - (1 << (c_size_mult + 2))) 477 - << (blk_size - 9); 478 - } else { 479 - u32 total_sector = 0; 480 - 481 - total_sector = (((u32)rsp[8] & 0x3f) << 16) | 482 - ((u32)rsp[9] << 8) | (u32)rsp[10]; 483 - sd_card->capacity = (total_sector + 1) << 10; 484 - } 485 - } 486 - 487 - if (check_wp) { 488 - if (rsp[15] & 0x30) 489 - chip->card_wp |= SD_CARD; 490 - 491 - dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]); 492 - } 493 - 494 - return STATUS_SUCCESS; 495 - } 496 - 497 - static int sd_set_sample_push_timing(struct rtsx_chip *chip) 498 - { 499 - int retval; 500 - struct sd_info *sd_card = &chip->sd_card; 501 - u8 val = 0; 502 - 503 - if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) 504 - val |= 0x10; 505 - 506 - if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) { 507 - if (chip->asic_code) { 508 - if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) { 509 - if (val & 0x10) 510 - val |= 0x04; 511 - else 512 - val |= 0x08; 513 - } 514 - } else { 515 - if (val & 0x10) 516 - val |= 0x04; 517 - else 518 - val |= 0x08; 519 - } 520 - } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == 521 - SD_SAMPLE_POINT_DELAY) { 522 - if (val & 0x10) 523 - val |= 0x04; 524 - else 525 - val |= 0x08; 526 - } 527 - 528 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val); 529 - if (retval) 530 - return retval; 531 - 532 - return STATUS_SUCCESS; 533 - } 534 - 535 - static void sd_choose_proper_clock(struct rtsx_chip *chip) 536 - { 537 - struct sd_info *sd_card = &chip->sd_card; 538 - 539 - if (CHK_SD_SDR104(sd_card)) { 540 - if (chip->asic_code) 541 - sd_card->sd_clock = chip->asic_sd_sdr104_clk; 542 - else 543 - sd_card->sd_clock = chip->fpga_sd_sdr104_clk; 544 - 545 - } else if (CHK_SD_DDR50(sd_card)) { 546 - if (chip->asic_code) 547 - sd_card->sd_clock = chip->asic_sd_ddr50_clk; 548 - else 549 - sd_card->sd_clock = chip->fpga_sd_ddr50_clk; 550 - 551 - } else if (CHK_SD_SDR50(sd_card)) { 552 - if (chip->asic_code) 553 - sd_card->sd_clock = chip->asic_sd_sdr50_clk; 554 - else 555 - sd_card->sd_clock = chip->fpga_sd_sdr50_clk; 556 - 557 - } else if (CHK_SD_HS(sd_card)) { 558 - if (chip->asic_code) 559 - sd_card->sd_clock = chip->asic_sd_hs_clk; 560 - else 561 - sd_card->sd_clock = chip->fpga_sd_hs_clk; 562 - 563 - } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) { 564 - if (chip->asic_code) 565 - sd_card->sd_clock = chip->asic_mmc_52m_clk; 566 - else 567 - sd_card->sd_clock = chip->fpga_mmc_52m_clk; 568 - 569 - } else if (CHK_MMC_26M(sd_card)) { 570 - if (chip->asic_code) 571 - sd_card->sd_clock = 48; 572 - else 573 - sd_card->sd_clock = CLK_50; 574 - } 575 - } 576 - 577 - static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) 578 - { 579 - int retval; 580 - u8 mask = 0, val = 0; 581 - 582 - mask = 0x60; 583 - if (clk_div == SD_CLK_DIVIDE_0) 584 - val = 0x00; 585 - else if (clk_div == SD_CLK_DIVIDE_128) 586 - val = 0x40; 587 - else if (clk_div == SD_CLK_DIVIDE_256) 588 - val = 0x20; 589 - 590 - retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); 591 - if (retval) 592 - return retval; 593 - 594 - return STATUS_SUCCESS; 595 - } 596 - 597 - static int sd_set_init_para(struct rtsx_chip *chip) 598 - { 599 - struct sd_info *sd_card = &chip->sd_card; 600 - int retval; 601 - 602 - retval = sd_set_sample_push_timing(chip); 603 - if (retval != STATUS_SUCCESS) 604 - return STATUS_FAIL; 605 - 606 - sd_choose_proper_clock(chip); 607 - 608 - retval = switch_clock(chip, sd_card->sd_clock); 609 - if (retval != STATUS_SUCCESS) 610 - return STATUS_FAIL; 611 - 612 - return STATUS_SUCCESS; 613 - } 614 - 615 - int sd_select_card(struct rtsx_chip *chip, int select) 616 - { 617 - struct sd_info *sd_card = &chip->sd_card; 618 - int retval; 619 - u8 cmd_idx, cmd_type; 620 - u32 addr; 621 - 622 - if (select) { 623 - cmd_idx = SELECT_CARD; 624 - cmd_type = SD_RSP_TYPE_R1; 625 - addr = sd_card->sd_addr; 626 - } else { 627 - cmd_idx = DESELECT_CARD; 628 - cmd_type = SD_RSP_TYPE_R0; 629 - addr = 0; 630 - } 631 - 632 - retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0); 633 - if (retval != STATUS_SUCCESS) 634 - return STATUS_FAIL; 635 - 636 - return STATUS_SUCCESS; 637 - } 638 - 639 - #ifdef SUPPORT_SD_LOCK 640 - static int sd_update_lock_status(struct rtsx_chip *chip) 641 - { 642 - struct sd_info *sd_card = &chip->sd_card; 643 - int retval; 644 - u8 rsp[5]; 645 - 646 - retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 647 - SD_RSP_TYPE_R1, rsp, 5); 648 - if (retval != STATUS_SUCCESS) 649 - return STATUS_FAIL; 650 - 651 - if (rsp[1] & 0x02) 652 - sd_card->sd_lock_status |= SD_LOCKED; 653 - else 654 - sd_card->sd_lock_status &= ~SD_LOCKED; 655 - 656 - dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n", 657 - sd_card->sd_lock_status); 658 - 659 - if (rsp[1] & 0x01) 660 - return STATUS_FAIL; 661 - 662 - return STATUS_SUCCESS; 663 - } 664 - #endif 665 - 666 - static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, 667 - u8 data_ready, int polling_cnt) 668 - { 669 - struct sd_info *sd_card = &chip->sd_card; 670 - int retval, i; 671 - u8 rsp[5]; 672 - 673 - for (i = 0; i < polling_cnt; i++) { 674 - retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 675 - sd_card->sd_addr, SD_RSP_TYPE_R1, 676 - rsp, 5); 677 - if (retval != STATUS_SUCCESS) 678 - return STATUS_FAIL; 679 - 680 - if (((rsp[3] & 0x1E) == state) && 681 - ((rsp[3] & 0x01) == data_ready)) 682 - return STATUS_SUCCESS; 683 - } 684 - 685 - return STATUS_FAIL; 686 - } 687 - 688 - static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) 689 - { 690 - int retval; 691 - 692 - if (voltage == SD_IO_3V3) { 693 - if (chip->asic_code) { 694 - retval = rtsx_write_phy_register(chip, 0x08, 695 - 0x4FC0 | 696 - chip->phy_voltage); 697 - if (retval != STATUS_SUCCESS) 698 - return STATUS_FAIL; 699 - } else { 700 - retval = rtsx_write_register(chip, SD_PAD_CTL, 701 - SD_IO_USING_1V8, 0); 702 - if (retval) 703 - return retval; 704 - } 705 - } else if (voltage == SD_IO_1V8) { 706 - if (chip->asic_code) { 707 - retval = rtsx_write_phy_register(chip, 0x08, 708 - 0x4C40 | 709 - chip->phy_voltage); 710 - if (retval != STATUS_SUCCESS) 711 - return STATUS_FAIL; 712 - } else { 713 - retval = rtsx_write_register(chip, SD_PAD_CTL, 714 - SD_IO_USING_1V8, 715 - SD_IO_USING_1V8); 716 - if (retval) 717 - return retval; 718 - } 719 - } else { 720 - return STATUS_FAIL; 721 - } 722 - 723 - return STATUS_SUCCESS; 724 - } 725 - 726 - static int sd_voltage_switch(struct rtsx_chip *chip) 727 - { 728 - int retval; 729 - u8 stat; 730 - 731 - retval = rtsx_write_register(chip, SD_BUS_STAT, 732 - SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 733 - SD_CLK_TOGGLE_EN); 734 - if (retval) 735 - return retval; 736 - 737 - retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, 738 - NULL, 0); 739 - if (retval != STATUS_SUCCESS) 740 - return STATUS_FAIL; 741 - 742 - udelay(chip->sd_voltage_switch_delay); 743 - 744 - retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); 745 - if (retval) 746 - return retval; 747 - if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 748 - SD_DAT1_STATUS | SD_DAT0_STATUS)) { 749 - return STATUS_FAIL; 750 - } 751 - 752 - retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, 753 - SD_CLK_FORCE_STOP); 754 - if (retval) 755 - return retval; 756 - retval = sd_change_bank_voltage(chip, SD_IO_1V8); 757 - if (retval != STATUS_SUCCESS) 758 - return STATUS_FAIL; 759 - 760 - wait_timeout(50); 761 - 762 - retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, 763 - SD_CLK_TOGGLE_EN); 764 - if (retval) 765 - return retval; 766 - wait_timeout(10); 767 - 768 - retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); 769 - if (retval) 770 - return retval; 771 - if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 772 - SD_DAT1_STATUS | SD_DAT0_STATUS)) != 773 - (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 774 - SD_DAT1_STATUS | SD_DAT0_STATUS)) { 775 - dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat); 776 - rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | 777 - SD_CLK_FORCE_STOP, 0); 778 - rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0); 779 - return STATUS_FAIL; 780 - } 781 - 782 - retval = rtsx_write_register(chip, SD_BUS_STAT, 783 - SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 784 - if (retval) 785 - return retval; 786 - 787 - return STATUS_SUCCESS; 788 - } 789 - 790 - static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir) 791 - { 792 - int retval; 793 - 794 - if (tune_dir == TUNE_RX) { 795 - retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, 796 - DCM_RESET | DCM_RX); 797 - if (retval) 798 - return retval; 799 - retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX); 800 - if (retval) 801 - return retval; 802 - } else { 803 - retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, 804 - DCM_RESET | DCM_TX); 805 - if (retval) 806 - return retval; 807 - retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX); 808 - if (retval) 809 - return retval; 810 - } 811 - 812 - return STATUS_SUCCESS; 813 - } 814 - 815 - static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) 816 - { 817 - struct sd_info *sd_card = &chip->sd_card; 818 - u16 SD_VP_CTL, SD_DCMPS_CTL; 819 - u8 val; 820 - int retval; 821 - bool ddr_rx = false; 822 - 823 - dev_dbg(rtsx_dev(chip), "%s (sample_point = %d, tune_dir = %d)\n", 824 - __func__, sample_point, tune_dir); 825 - 826 - if (tune_dir == TUNE_RX) { 827 - SD_VP_CTL = SD_VPRX_CTL; 828 - SD_DCMPS_CTL = SD_DCMPS_RX_CTL; 829 - if (CHK_SD_DDR50(sd_card)) 830 - ddr_rx = true; 831 - } else { 832 - SD_VP_CTL = SD_VPTX_CTL; 833 - SD_DCMPS_CTL = SD_DCMPS_TX_CTL; 834 - } 835 - 836 - if (chip->asic_code) { 837 - retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 838 - CHANGE_CLK); 839 - if (retval) 840 - return retval; 841 - retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F, 842 - sample_point); 843 - if (retval) 844 - return retval; 845 - retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 846 - PHASE_NOT_RESET, 0); 847 - if (retval) 848 - return retval; 849 - retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 850 - PHASE_NOT_RESET, PHASE_NOT_RESET); 851 - if (retval) 852 - return retval; 853 - retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0); 854 - if (retval) 855 - return retval; 856 - } else { 857 - rtsx_read_register(chip, SD_VP_CTL, &val); 858 - dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); 859 - rtsx_read_register(chip, SD_DCMPS_CTL, &val); 860 - dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); 861 - 862 - if (ddr_rx) { 863 - retval = rtsx_write_register(chip, SD_VP_CTL, 864 - PHASE_CHANGE, 865 - PHASE_CHANGE); 866 - if (retval) 867 - return retval; 868 - udelay(50); 869 - retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, 870 - PHASE_CHANGE | 871 - PHASE_NOT_RESET | 872 - sample_point); 873 - if (retval) 874 - return retval; 875 - } else { 876 - retval = rtsx_write_register(chip, CLK_CTL, 877 - CHANGE_CLK, CHANGE_CLK); 878 - if (retval) 879 - return retval; 880 - udelay(50); 881 - retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, 882 - PHASE_NOT_RESET | 883 - sample_point); 884 - if (retval) 885 - return retval; 886 - } 887 - udelay(100); 888 - 889 - rtsx_init_cmd(chip); 890 - rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, 891 - DCMPS_CHANGE); 892 - rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, 893 - DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE); 894 - retval = rtsx_send_cmd(chip, SD_CARD, 100); 895 - if (retval != STATUS_SUCCESS) 896 - goto fail; 897 - 898 - val = *rtsx_get_cmd_data(chip); 899 - if (val & DCMPS_ERROR) 900 - goto fail; 901 - 902 - if ((val & DCMPS_CURRENT_PHASE) != sample_point) 903 - goto fail; 904 - 905 - retval = rtsx_write_register(chip, SD_DCMPS_CTL, 906 - DCMPS_CHANGE, 0); 907 - if (retval) 908 - return retval; 909 - if (ddr_rx) { 910 - retval = rtsx_write_register(chip, SD_VP_CTL, 911 - PHASE_CHANGE, 0); 912 - if (retval) 913 - return retval; 914 - } else { 915 - retval = rtsx_write_register(chip, CLK_CTL, 916 - CHANGE_CLK, 0); 917 - if (retval) 918 - return retval; 919 - } 920 - 921 - udelay(50); 922 - } 923 - 924 - retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 925 - if (retval) 926 - return retval; 927 - 928 - return STATUS_SUCCESS; 929 - 930 - fail: 931 - rtsx_read_register(chip, SD_VP_CTL, &val); 932 - dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); 933 - rtsx_read_register(chip, SD_DCMPS_CTL, &val); 934 - dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); 935 - 936 - rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); 937 - rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); 938 - mdelay(10); 939 - sd_reset_dcm(chip, tune_dir); 940 - return STATUS_FAIL; 941 - } 942 - 943 - static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) 944 - { 945 - struct sd_info *sd_card = &chip->sd_card; 946 - int retval; 947 - u8 cmd[5], buf[8]; 948 - 949 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 950 - SD_RSP_TYPE_R1, NULL, 0); 951 - if (retval != STATUS_SUCCESS) 952 - return STATUS_FAIL; 953 - 954 - cmd[0] = 0x40 | SEND_SCR; 955 - cmd[1] = 0; 956 - cmd[2] = 0; 957 - cmd[3] = 0; 958 - cmd[4] = 0; 959 - 960 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, 961 - buf, 8, 250); 962 - if (retval != STATUS_SUCCESS) { 963 - rtsx_clear_sd_error(chip); 964 - return STATUS_FAIL; 965 - } 966 - 967 - memcpy(sd_card->raw_scr, buf, 8); 968 - 969 - if ((buf[0] & 0x0F) == 0) 970 - return STATUS_FAIL; 971 - 972 - return STATUS_SUCCESS; 973 - } 974 - 975 - static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, 976 - u8 func_to_switch, u8 *buf, int buf_len) 977 - { 978 - u8 support_mask = 0, query_switch = 0, switch_busy = 0; 979 - int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0; 980 - 981 - if (func_group == SD_FUNC_GROUP_1) { 982 - support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET; 983 - query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET; 984 - check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET; 985 - 986 - switch (func_to_switch) { 987 - case HS_SUPPORT: 988 - support_mask = HS_SUPPORT_MASK; 989 - query_switch = HS_QUERY_SWITCH_OK; 990 - switch_busy = HS_SWITCH_BUSY; 991 - break; 992 - 993 - case SDR50_SUPPORT: 994 - support_mask = SDR50_SUPPORT_MASK; 995 - query_switch = SDR50_QUERY_SWITCH_OK; 996 - switch_busy = SDR50_SWITCH_BUSY; 997 - break; 998 - 999 - case SDR104_SUPPORT: 1000 - support_mask = SDR104_SUPPORT_MASK; 1001 - query_switch = SDR104_QUERY_SWITCH_OK; 1002 - switch_busy = SDR104_SWITCH_BUSY; 1003 - break; 1004 - 1005 - case DDR50_SUPPORT: 1006 - support_mask = DDR50_SUPPORT_MASK; 1007 - query_switch = DDR50_QUERY_SWITCH_OK; 1008 - switch_busy = DDR50_SWITCH_BUSY; 1009 - break; 1010 - 1011 - default: 1012 - return STATUS_FAIL; 1013 - } 1014 - } else if (func_group == SD_FUNC_GROUP_3) { 1015 - support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET; 1016 - query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET; 1017 - check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET; 1018 - 1019 - switch (func_to_switch) { 1020 - case DRIVING_TYPE_A: 1021 - support_mask = DRIVING_TYPE_A_MASK; 1022 - query_switch = TYPE_A_QUERY_SWITCH_OK; 1023 - switch_busy = TYPE_A_SWITCH_BUSY; 1024 - break; 1025 - 1026 - case DRIVING_TYPE_C: 1027 - support_mask = DRIVING_TYPE_C_MASK; 1028 - query_switch = TYPE_C_QUERY_SWITCH_OK; 1029 - switch_busy = TYPE_C_SWITCH_BUSY; 1030 - break; 1031 - 1032 - case DRIVING_TYPE_D: 1033 - support_mask = DRIVING_TYPE_D_MASK; 1034 - query_switch = TYPE_D_QUERY_SWITCH_OK; 1035 - switch_busy = TYPE_D_SWITCH_BUSY; 1036 - break; 1037 - 1038 - default: 1039 - return STATUS_FAIL; 1040 - } 1041 - } else if (func_group == SD_FUNC_GROUP_4) { 1042 - support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET; 1043 - query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET; 1044 - check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET; 1045 - 1046 - switch (func_to_switch) { 1047 - case CURRENT_LIMIT_400: 1048 - support_mask = CURRENT_LIMIT_400_MASK; 1049 - query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK; 1050 - switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY; 1051 - break; 1052 - 1053 - case CURRENT_LIMIT_600: 1054 - support_mask = CURRENT_LIMIT_600_MASK; 1055 - query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK; 1056 - switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY; 1057 - break; 1058 - 1059 - case CURRENT_LIMIT_800: 1060 - support_mask = CURRENT_LIMIT_800_MASK; 1061 - query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK; 1062 - switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY; 1063 - break; 1064 - 1065 - default: 1066 - return STATUS_FAIL; 1067 - } 1068 - } else { 1069 - return STATUS_FAIL; 1070 - } 1071 - 1072 - if (func_group == SD_FUNC_GROUP_1) { 1073 - if (!(buf[support_offset] & support_mask) || 1074 - ((buf[query_switch_offset] & 0x0F) != query_switch)) { 1075 - return STATUS_FAIL; 1076 - } 1077 - } 1078 - 1079 - /* Check 'Busy Status' */ 1080 - if (buf[DATA_STRUCTURE_VER_OFFSET] == 0x01 && 1081 - ((buf[check_busy_offset] & switch_busy) == switch_busy)) { 1082 - return STATUS_FAIL; 1083 - } 1084 - 1085 - return STATUS_SUCCESS; 1086 - } 1087 - 1088 - static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, u8 func_group, 1089 - u8 func_to_switch, u8 bus_width) 1090 - { 1091 - struct sd_info *sd_card = &chip->sd_card; 1092 - int retval; 1093 - u8 cmd[5], buf[64]; 1094 - 1095 - dev_dbg(rtsx_dev(chip), "%s (mode = %d, func_group = %d, func_to_switch = %d)\n", 1096 - __func__, mode, func_group, func_to_switch); 1097 - 1098 - cmd[0] = 0x40 | SWITCH; 1099 - cmd[1] = mode; 1100 - 1101 - if (func_group == SD_FUNC_GROUP_1) { 1102 - cmd[2] = 0xFF; 1103 - cmd[3] = 0xFF; 1104 - cmd[4] = 0xF0 + func_to_switch; 1105 - } else if (func_group == SD_FUNC_GROUP_3) { 1106 - cmd[2] = 0xFF; 1107 - cmd[3] = 0xF0 + func_to_switch; 1108 - cmd[4] = 0xFF; 1109 - } else if (func_group == SD_FUNC_GROUP_4) { 1110 - cmd[2] = 0xFF; 1111 - cmd[3] = 0x0F + (func_to_switch << 4); 1112 - cmd[4] = 0xFF; 1113 - } else { 1114 - cmd[1] = SD_CHECK_MODE; 1115 - cmd[2] = 0xFF; 1116 - cmd[3] = 0xFF; 1117 - cmd[4] = 0xFF; 1118 - } 1119 - 1120 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, 1121 - buf, 64, 250); 1122 - if (retval != STATUS_SUCCESS) { 1123 - rtsx_clear_sd_error(chip); 1124 - return STATUS_FAIL; 1125 - } 1126 - 1127 - dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf); 1128 - 1129 - if (func_group == NO_ARGUMENT) { 1130 - sd_card->func_group1_mask = buf[0x0D]; 1131 - sd_card->func_group2_mask = buf[0x0B]; 1132 - sd_card->func_group3_mask = buf[0x09]; 1133 - sd_card->func_group4_mask = buf[0x07]; 1134 - 1135 - dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n", 1136 - buf[0x0D]); 1137 - dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n", 1138 - buf[0x0B]); 1139 - dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n", 1140 - buf[0x09]); 1141 - dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n", 1142 - buf[0x07]); 1143 - } else { 1144 - /* Maximum current consumption, check whether current is 1145 - * acceptable; bit[511:496] = 0x0000 means some error happened. 1146 - */ 1147 - u16 cc = ((u16)buf[0] << 8) | buf[1]; 1148 - 1149 - dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n", 1150 - cc); 1151 - if (cc == 0 || cc > 800) 1152 - return STATUS_FAIL; 1153 - 1154 - retval = sd_query_switch_result(chip, func_group, 1155 - func_to_switch, buf, 64); 1156 - if (retval != STATUS_SUCCESS) 1157 - return STATUS_FAIL; 1158 - 1159 - if (cc > 400 || func_to_switch > CURRENT_LIMIT_400) { 1160 - retval = rtsx_write_register(chip, OCPPARA2, 1161 - SD_OCP_THD_MASK, 1162 - chip->sd_800mA_ocp_thd); 1163 - if (retval) 1164 - return retval; 1165 - retval = rtsx_write_register(chip, CARD_PWR_CTL, 1166 - PMOS_STRG_MASK, 1167 - PMOS_STRG_800mA); 1168 - if (retval) 1169 - return retval; 1170 - } 1171 - } 1172 - 1173 - return STATUS_SUCCESS; 1174 - } 1175 - 1176 - static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch) 1177 - { 1178 - if (func_group == SD_FUNC_GROUP_1) { 1179 - if (func_to_switch > HS_SUPPORT) 1180 - func_to_switch--; 1181 - 1182 - } else if (func_group == SD_FUNC_GROUP_4) { 1183 - if (func_to_switch > CURRENT_LIMIT_200) 1184 - func_to_switch--; 1185 - } 1186 - 1187 - return func_to_switch; 1188 - } 1189 - 1190 - static int sd_check_switch(struct rtsx_chip *chip, 1191 - u8 func_group, u8 func_to_switch, u8 bus_width) 1192 - { 1193 - int retval; 1194 - int i; 1195 - bool switch_good = false; 1196 - 1197 - for (i = 0; i < 3; i++) { 1198 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1199 - sd_set_err_code(chip, SD_NO_CARD); 1200 - return STATUS_FAIL; 1201 - } 1202 - 1203 - retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group, 1204 - func_to_switch, bus_width); 1205 - if (retval == STATUS_SUCCESS) { 1206 - u8 stat; 1207 - 1208 - retval = sd_check_switch_mode(chip, SD_SWITCH_MODE, 1209 - func_group, 1210 - func_to_switch, 1211 - bus_width); 1212 - if (retval == STATUS_SUCCESS) { 1213 - switch_good = true; 1214 - break; 1215 - } 1216 - 1217 - retval = rtsx_read_register(chip, SD_STAT1, &stat); 1218 - if (retval) 1219 - return retval; 1220 - if (stat & SD_CRC16_ERR) { 1221 - dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n"); 1222 - return STATUS_FAIL; 1223 - } 1224 - } 1225 - 1226 - func_to_switch = downgrade_switch_mode(func_group, 1227 - func_to_switch); 1228 - 1229 - wait_timeout(20); 1230 - } 1231 - 1232 - if (!switch_good) 1233 - return STATUS_FAIL; 1234 - 1235 - return STATUS_SUCCESS; 1236 - } 1237 - 1238 - static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) 1239 - { 1240 - struct sd_info *sd_card = &chip->sd_card; 1241 - int retval; 1242 - int i; 1243 - u8 func_to_switch = 0; 1244 - 1245 - /* Get supported functions */ 1246 - retval = sd_check_switch_mode(chip, SD_CHECK_MODE, NO_ARGUMENT, 1247 - NO_ARGUMENT, bus_width); 1248 - if (retval != STATUS_SUCCESS) 1249 - return STATUS_FAIL; 1250 - 1251 - sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail); 1252 - 1253 - /* Function Group 1: Access Mode */ 1254 - for (i = 0; i < 4; i++) { 1255 - switch ((u8)(chip->sd_speed_prior >> (i * 8))) { 1256 - case SDR104_SUPPORT: 1257 - if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) && 1258 - chip->sdr104_en) { 1259 - func_to_switch = SDR104_SUPPORT; 1260 - } 1261 - break; 1262 - 1263 - case DDR50_SUPPORT: 1264 - if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) && 1265 - chip->ddr50_en) { 1266 - func_to_switch = DDR50_SUPPORT; 1267 - } 1268 - break; 1269 - 1270 - case SDR50_SUPPORT: 1271 - if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) && 1272 - chip->sdr50_en) { 1273 - func_to_switch = SDR50_SUPPORT; 1274 - } 1275 - break; 1276 - 1277 - case HS_SUPPORT: 1278 - if (sd_card->func_group1_mask & HS_SUPPORT_MASK) 1279 - func_to_switch = HS_SUPPORT; 1280 - 1281 - break; 1282 - 1283 - default: 1284 - continue; 1285 - } 1286 - 1287 - if (func_to_switch) 1288 - break; 1289 - } 1290 - dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x", 1291 - func_to_switch); 1292 - 1293 - #ifdef SUPPORT_SD_LOCK 1294 - if ((sd_card->sd_lock_status & SD_SDR_RST) && 1295 - func_to_switch == DDR50_SUPPORT && 1296 - (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) { 1297 - func_to_switch = SDR50_SUPPORT; 1298 - dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n"); 1299 - } 1300 - #endif 1301 - 1302 - if (func_to_switch) { 1303 - retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, 1304 - bus_width); 1305 - if (retval != STATUS_SUCCESS) { 1306 - if (func_to_switch == SDR104_SUPPORT) { 1307 - sd_card->sd_switch_fail = SDR104_SUPPORT_MASK; 1308 - } else if (func_to_switch == DDR50_SUPPORT) { 1309 - sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 1310 - DDR50_SUPPORT_MASK; 1311 - } else if (func_to_switch == SDR50_SUPPORT) { 1312 - sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 1313 - DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; 1314 - } 1315 - return STATUS_FAIL; 1316 - } 1317 - 1318 - if (func_to_switch == SDR104_SUPPORT) 1319 - SET_SD_SDR104(sd_card); 1320 - else if (func_to_switch == DDR50_SUPPORT) 1321 - SET_SD_DDR50(sd_card); 1322 - else if (func_to_switch == SDR50_SUPPORT) 1323 - SET_SD_SDR50(sd_card); 1324 - else 1325 - SET_SD_HS(sd_card); 1326 - } 1327 - 1328 - if (CHK_SD_DDR50(sd_card)) { 1329 - retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 1330 - 0x04); 1331 - if (retval) 1332 - return retval; 1333 - retval = sd_set_sample_push_timing(chip); 1334 - if (retval != STATUS_SUCCESS) 1335 - return STATUS_FAIL; 1336 - } 1337 - 1338 - if (!func_to_switch || func_to_switch == HS_SUPPORT) { 1339 - /* Do not try to switch current limit if the card doesn't 1340 - * support UHS mode or we don't want it to support UHS mode 1341 - */ 1342 - return STATUS_SUCCESS; 1343 - } 1344 - 1345 - /* Function Group 4: Current Limit */ 1346 - func_to_switch = 0xFF; 1347 - 1348 - for (i = 0; i < 4; i++) { 1349 - switch ((u8)(chip->sd_current_prior >> (i * 8))) { 1350 - case CURRENT_LIMIT_800: 1351 - if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) 1352 - func_to_switch = CURRENT_LIMIT_800; 1353 - 1354 - break; 1355 - 1356 - case CURRENT_LIMIT_600: 1357 - if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) 1358 - func_to_switch = CURRENT_LIMIT_600; 1359 - 1360 - break; 1361 - 1362 - case CURRENT_LIMIT_400: 1363 - if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) 1364 - func_to_switch = CURRENT_LIMIT_400; 1365 - 1366 - break; 1367 - 1368 - case CURRENT_LIMIT_200: 1369 - if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) 1370 - func_to_switch = CURRENT_LIMIT_200; 1371 - 1372 - break; 1373 - 1374 - default: 1375 - continue; 1376 - } 1377 - 1378 - if (func_to_switch != 0xFF) 1379 - break; 1380 - } 1381 - 1382 - dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x", 1383 - func_to_switch); 1384 - 1385 - if (func_to_switch <= CURRENT_LIMIT_800) { 1386 - retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, 1387 - bus_width); 1388 - if (retval != STATUS_SUCCESS) { 1389 - if (sd_check_err_code(chip, SD_NO_CARD)) 1390 - return STATUS_FAIL; 1391 - } 1392 - dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n", 1393 - retval); 1394 - } 1395 - 1396 - if (CHK_SD_DDR50(sd_card)) { 1397 - retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0); 1398 - if (retval) 1399 - return retval; 1400 - } 1401 - 1402 - return STATUS_SUCCESS; 1403 - } 1404 - 1405 - static int sd_wait_data_idle(struct rtsx_chip *chip) 1406 - { 1407 - int retval = STATUS_TIMEDOUT; 1408 - int i; 1409 - u8 val = 0; 1410 - 1411 - for (i = 0; i < 100; i++) { 1412 - retval = rtsx_read_register(chip, SD_DATA_STATE, &val); 1413 - if (retval) 1414 - return retval; 1415 - if (val & SD_DATA_IDLE) { 1416 - retval = STATUS_SUCCESS; 1417 - break; 1418 - } 1419 - udelay(100); 1420 - } 1421 - dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val); 1422 - 1423 - return retval; 1424 - } 1425 - 1426 - static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1427 - { 1428 - int retval; 1429 - u8 cmd[5]; 1430 - 1431 - retval = sd_change_phase(chip, sample_point, TUNE_RX); 1432 - if (retval != STATUS_SUCCESS) 1433 - return STATUS_FAIL; 1434 - 1435 - cmd[0] = 0x40 | SEND_TUNING_PATTERN; 1436 - cmd[1] = 0; 1437 - cmd[2] = 0; 1438 - cmd[3] = 0; 1439 - cmd[4] = 0; 1440 - 1441 - retval = sd_read_data(chip, SD_TM_AUTO_TUNING, cmd, 5, 0x40, 1, 1442 - SD_BUS_WIDTH_4, NULL, 0, 100); 1443 - if (retval != STATUS_SUCCESS) { 1444 - (void)sd_wait_data_idle(chip); 1445 - 1446 - rtsx_clear_sd_error(chip); 1447 - return STATUS_FAIL; 1448 - } 1449 - 1450 - return STATUS_SUCCESS; 1451 - } 1452 - 1453 - static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1454 - { 1455 - struct sd_info *sd_card = &chip->sd_card; 1456 - int retval; 1457 - u8 cmd[5]; 1458 - 1459 - retval = sd_change_phase(chip, sample_point, TUNE_RX); 1460 - if (retval != STATUS_SUCCESS) 1461 - return STATUS_FAIL; 1462 - 1463 - dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n"); 1464 - 1465 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 1466 - SD_RSP_TYPE_R1, NULL, 0); 1467 - if (retval != STATUS_SUCCESS) 1468 - return STATUS_FAIL; 1469 - 1470 - cmd[0] = 0x40 | SD_STATUS; 1471 - cmd[1] = 0; 1472 - cmd[2] = 0; 1473 - cmd[3] = 0; 1474 - cmd[4] = 0; 1475 - 1476 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, 1477 - SD_BUS_WIDTH_4, NULL, 0, 100); 1478 - if (retval != STATUS_SUCCESS) { 1479 - (void)sd_wait_data_idle(chip); 1480 - 1481 - rtsx_clear_sd_error(chip); 1482 - return STATUS_FAIL; 1483 - } 1484 - 1485 - return STATUS_SUCCESS; 1486 - } 1487 - 1488 - static int mmc_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1489 - { 1490 - struct sd_info *sd_card = &chip->sd_card; 1491 - int retval; 1492 - u8 cmd[5], bus_width; 1493 - 1494 - if (CHK_MMC_8BIT(sd_card)) 1495 - bus_width = SD_BUS_WIDTH_8; 1496 - else if (CHK_MMC_4BIT(sd_card)) 1497 - bus_width = SD_BUS_WIDTH_4; 1498 - else 1499 - bus_width = SD_BUS_WIDTH_1; 1500 - 1501 - retval = sd_change_phase(chip, sample_point, TUNE_RX); 1502 - if (retval != STATUS_SUCCESS) 1503 - return STATUS_FAIL; 1504 - 1505 - dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n"); 1506 - 1507 - cmd[0] = 0x40 | SEND_EXT_CSD; 1508 - cmd[1] = 0; 1509 - cmd[2] = 0; 1510 - cmd[3] = 0; 1511 - cmd[4] = 0; 1512 - 1513 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 0x200, 1, 1514 - bus_width, NULL, 0, 100); 1515 - if (retval != STATUS_SUCCESS) { 1516 - (void)sd_wait_data_idle(chip); 1517 - 1518 - rtsx_clear_sd_error(chip); 1519 - return STATUS_FAIL; 1520 - } 1521 - 1522 - return STATUS_SUCCESS; 1523 - } 1524 - 1525 - static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) 1526 - { 1527 - struct sd_info *sd_card = &chip->sd_card; 1528 - int retval; 1529 - 1530 - retval = sd_change_phase(chip, sample_point, TUNE_TX); 1531 - if (retval != STATUS_SUCCESS) 1532 - return STATUS_FAIL; 1533 - 1534 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1535 - SD_RSP_80CLK_TIMEOUT_EN); 1536 - if (retval) 1537 - return retval; 1538 - 1539 - retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 1540 - SD_RSP_TYPE_R1, NULL, 0); 1541 - if (retval != STATUS_SUCCESS) { 1542 - if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) { 1543 - rtsx_write_register(chip, SD_CFG3, 1544 - SD_RSP_80CLK_TIMEOUT_EN, 0); 1545 - return STATUS_FAIL; 1546 - } 1547 - } 1548 - 1549 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1550 - 0); 1551 - if (retval) 1552 - return retval; 1553 - 1554 - return STATUS_SUCCESS; 1555 - } 1556 - 1557 - static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) 1558 - { 1559 - struct sd_info *sd_card = &chip->sd_card; 1560 - int retval; 1561 - u8 cmd[5], bus_width; 1562 - 1563 - retval = sd_change_phase(chip, sample_point, TUNE_TX); 1564 - if (retval != STATUS_SUCCESS) 1565 - return STATUS_FAIL; 1566 - 1567 - if (CHK_SD(sd_card)) { 1568 - bus_width = SD_BUS_WIDTH_4; 1569 - } else { 1570 - if (CHK_MMC_8BIT(sd_card)) 1571 - bus_width = SD_BUS_WIDTH_8; 1572 - else if (CHK_MMC_4BIT(sd_card)) 1573 - bus_width = SD_BUS_WIDTH_4; 1574 - else 1575 - bus_width = SD_BUS_WIDTH_1; 1576 - } 1577 - 1578 - retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 1579 - if (retval != STATUS_SUCCESS) 1580 - return STATUS_FAIL; 1581 - 1582 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1583 - SD_RSP_80CLK_TIMEOUT_EN); 1584 - if (retval) 1585 - return retval; 1586 - 1587 - cmd[0] = 0x40 | PROGRAM_CSD; 1588 - cmd[1] = 0; 1589 - cmd[2] = 0; 1590 - cmd[3] = 0; 1591 - cmd[4] = 0; 1592 - 1593 - retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, cmd, 5, 16, 1, 1594 - bus_width, sd_card->raw_csd, 16, 100); 1595 - if (retval != STATUS_SUCCESS) { 1596 - rtsx_clear_sd_error(chip); 1597 - rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 1598 - return STATUS_FAIL; 1599 - } 1600 - 1601 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1602 - 0); 1603 - if (retval) 1604 - return retval; 1605 - 1606 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, 1607 - NULL, 0); 1608 - 1609 - return STATUS_SUCCESS; 1610 - } 1611 - 1612 - static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, 1613 - u8 tune_dir) 1614 - { 1615 - struct sd_info *sd_card = &chip->sd_card; 1616 - struct timing_phase_path path[MAX_PHASE + 1]; 1617 - int i, j, cont_path_cnt; 1618 - bool new_block; 1619 - int max_len, final_path_idx; 1620 - u8 final_phase = 0xFF; 1621 - 1622 - if (phase_map == 0xFFFFFFFF) { 1623 - if (tune_dir == TUNE_RX) 1624 - final_phase = (u8)chip->sd_default_rx_phase; 1625 - else 1626 - final_phase = (u8)chip->sd_default_tx_phase; 1627 - 1628 - goto search_finish; 1629 - } 1630 - 1631 - cont_path_cnt = 0; 1632 - new_block = true; 1633 - j = 0; 1634 - for (i = 0; i < MAX_PHASE + 1; i++) { 1635 - if (phase_map & (1 << i)) { 1636 - if (new_block) { 1637 - new_block = false; 1638 - j = cont_path_cnt++; 1639 - path[j].start = i; 1640 - path[j].end = i; 1641 - } else { 1642 - path[j].end = i; 1643 - } 1644 - } else { 1645 - new_block = true; 1646 - if (cont_path_cnt) { 1647 - int idx = cont_path_cnt - 1; 1648 - 1649 - path[idx].len = path[idx].end - 1650 - path[idx].start + 1; 1651 - path[idx].mid = path[idx].start + 1652 - path[idx].len / 2; 1653 - } 1654 - } 1655 - } 1656 - 1657 - if (cont_path_cnt == 0) { 1658 - dev_dbg(rtsx_dev(chip), "No continuous phase path\n"); 1659 - goto search_finish; 1660 - } else { 1661 - int idx = cont_path_cnt - 1; 1662 - 1663 - path[idx].len = path[idx].end - path[idx].start + 1; 1664 - path[idx].mid = path[idx].start + path[idx].len / 2; 1665 - } 1666 - 1667 - if (path[0].start == 0 && 1668 - path[cont_path_cnt - 1].end == MAX_PHASE) { 1669 - path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; 1670 - path[0].len += path[cont_path_cnt - 1].len; 1671 - path[0].mid = path[0].start + path[0].len / 2; 1672 - if (path[0].mid < 0) 1673 - path[0].mid += MAX_PHASE + 1; 1674 - 1675 - cont_path_cnt--; 1676 - } 1677 - 1678 - max_len = 0; 1679 - final_phase = 0; 1680 - final_path_idx = 0; 1681 - for (i = 0; i < cont_path_cnt; i++) { 1682 - if (path[i].len > max_len) { 1683 - max_len = path[i].len; 1684 - final_phase = (u8)path[i].mid; 1685 - final_path_idx = i; 1686 - } 1687 - 1688 - dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n", 1689 - i, path[i].start); 1690 - dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end); 1691 - dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len); 1692 - dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid); 1693 - dev_dbg(rtsx_dev(chip), "\n"); 1694 - } 1695 - 1696 - if (tune_dir == TUNE_TX) { 1697 - if (CHK_SD_SDR104(sd_card)) { 1698 - if (max_len > 15) { 1699 - int temp_mid = (max_len - 16) / 2; 1700 - int temp_final_phase = 1701 - path[final_path_idx].end - 1702 - (max_len - (6 + temp_mid)); 1703 - 1704 - if (temp_final_phase < 0) 1705 - final_phase = (u8)(temp_final_phase + 1706 - MAX_PHASE + 1); 1707 - else 1708 - final_phase = (u8)temp_final_phase; 1709 - } 1710 - } else if (CHK_SD_SDR50(sd_card)) { 1711 - if (max_len > 12) { 1712 - int temp_mid = (max_len - 13) / 2; 1713 - int temp_final_phase = 1714 - path[final_path_idx].end - 1715 - (max_len - (3 + temp_mid)); 1716 - 1717 - if (temp_final_phase < 0) 1718 - final_phase = (u8)(temp_final_phase + 1719 - MAX_PHASE + 1); 1720 - else 1721 - final_phase = (u8)temp_final_phase; 1722 - } 1723 - } 1724 - } 1725 - 1726 - search_finish: 1727 - dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase); 1728 - return final_phase; 1729 - } 1730 - 1731 - static int sd_tuning_rx(struct rtsx_chip *chip) 1732 - { 1733 - struct sd_info *sd_card = &chip->sd_card; 1734 - int retval; 1735 - int i, j; 1736 - u32 raw_phase_map[3], phase_map; 1737 - u8 final_phase; 1738 - int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); 1739 - 1740 - if (CHK_SD(sd_card)) { 1741 - if (CHK_SD_DDR50(sd_card)) 1742 - tuning_cmd = sd_ddr_tuning_rx_cmd; 1743 - else 1744 - tuning_cmd = sd_sdr_tuning_rx_cmd; 1745 - 1746 - } else { 1747 - if (CHK_MMC_DDR52(sd_card)) 1748 - tuning_cmd = mmc_ddr_tuning_rx_cmd; 1749 - else 1750 - return STATUS_FAIL; 1751 - } 1752 - 1753 - for (i = 0; i < 3; i++) { 1754 - raw_phase_map[i] = 0; 1755 - for (j = MAX_PHASE; j >= 0; j--) { 1756 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1757 - sd_set_err_code(chip, SD_NO_CARD); 1758 - return STATUS_FAIL; 1759 - } 1760 - 1761 - retval = tuning_cmd(chip, (u8)j); 1762 - if (retval == STATUS_SUCCESS) 1763 - raw_phase_map[i] |= 1 << j; 1764 - } 1765 - } 1766 - 1767 - phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; 1768 - for (i = 0; i < 3; i++) 1769 - dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n", 1770 - i, raw_phase_map[i]); 1771 - 1772 - dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map); 1773 - 1774 - final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX); 1775 - if (final_phase == 0xFF) 1776 - return STATUS_FAIL; 1777 - 1778 - retval = sd_change_phase(chip, final_phase, TUNE_RX); 1779 - if (retval != STATUS_SUCCESS) 1780 - return STATUS_FAIL; 1781 - 1782 - return STATUS_SUCCESS; 1783 - } 1784 - 1785 - static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) 1786 - { 1787 - struct sd_info *sd_card = &chip->sd_card; 1788 - int retval; 1789 - int i; 1790 - u32 phase_map; 1791 - u8 final_phase; 1792 - 1793 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1794 - SD_RSP_80CLK_TIMEOUT_EN); 1795 - if (retval) 1796 - return retval; 1797 - 1798 - phase_map = 0; 1799 - for (i = MAX_PHASE; i >= 0; i--) { 1800 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1801 - sd_set_err_code(chip, SD_NO_CARD); 1802 - rtsx_write_register(chip, SD_CFG3, 1803 - SD_RSP_80CLK_TIMEOUT_EN, 0); 1804 - return STATUS_FAIL; 1805 - } 1806 - 1807 - retval = sd_change_phase(chip, (u8)i, TUNE_TX); 1808 - if (retval != STATUS_SUCCESS) 1809 - continue; 1810 - 1811 - retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 1812 - sd_card->sd_addr, SD_RSP_TYPE_R1, 1813 - NULL, 0); 1814 - if (retval == STATUS_SUCCESS || 1815 - !sd_check_err_code(chip, SD_RSP_TIMEOUT)) 1816 - phase_map |= 1 << i; 1817 - } 1818 - 1819 - retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1820 - 0); 1821 - if (retval) 1822 - return retval; 1823 - 1824 - dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n", 1825 - phase_map); 1826 - 1827 - final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); 1828 - if (final_phase == 0xFF) 1829 - return STATUS_FAIL; 1830 - 1831 - retval = sd_change_phase(chip, final_phase, TUNE_TX); 1832 - if (retval != STATUS_SUCCESS) 1833 - return STATUS_FAIL; 1834 - 1835 - dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n", 1836 - (int)final_phase); 1837 - 1838 - return STATUS_SUCCESS; 1839 - } 1840 - 1841 - static int sd_tuning_tx(struct rtsx_chip *chip) 1842 - { 1843 - struct sd_info *sd_card = &chip->sd_card; 1844 - int retval; 1845 - int i, j; 1846 - u32 raw_phase_map[3], phase_map; 1847 - u8 final_phase; 1848 - int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); 1849 - 1850 - if (CHK_SD(sd_card)) { 1851 - if (CHK_SD_DDR50(sd_card)) 1852 - tuning_cmd = sd_ddr_tuning_tx_cmd; 1853 - else 1854 - tuning_cmd = sd_sdr_tuning_tx_cmd; 1855 - 1856 - } else { 1857 - if (CHK_MMC_DDR52(sd_card)) 1858 - tuning_cmd = sd_ddr_tuning_tx_cmd; 1859 - else 1860 - return STATUS_FAIL; 1861 - } 1862 - 1863 - for (i = 0; i < 3; i++) { 1864 - raw_phase_map[i] = 0; 1865 - for (j = MAX_PHASE; j >= 0; j--) { 1866 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1867 - sd_set_err_code(chip, SD_NO_CARD); 1868 - rtsx_write_register(chip, SD_CFG3, 1869 - SD_RSP_80CLK_TIMEOUT_EN, 0); 1870 - return STATUS_FAIL; 1871 - } 1872 - 1873 - retval = tuning_cmd(chip, (u8)j); 1874 - if (retval == STATUS_SUCCESS) 1875 - raw_phase_map[i] |= 1 << j; 1876 - } 1877 - } 1878 - 1879 - phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; 1880 - for (i = 0; i < 3; i++) 1881 - dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n", 1882 - i, raw_phase_map[i]); 1883 - 1884 - dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map); 1885 - 1886 - final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); 1887 - if (final_phase == 0xFF) 1888 - return STATUS_FAIL; 1889 - 1890 - retval = sd_change_phase(chip, final_phase, TUNE_TX); 1891 - if (retval != STATUS_SUCCESS) 1892 - return STATUS_FAIL; 1893 - 1894 - return STATUS_SUCCESS; 1895 - } 1896 - 1897 - static int sd_sdr_tuning(struct rtsx_chip *chip) 1898 - { 1899 - int retval; 1900 - 1901 - retval = sd_tuning_tx(chip); 1902 - if (retval != STATUS_SUCCESS) 1903 - return STATUS_FAIL; 1904 - 1905 - retval = sd_tuning_rx(chip); 1906 - if (retval != STATUS_SUCCESS) 1907 - return STATUS_FAIL; 1908 - 1909 - return STATUS_SUCCESS; 1910 - } 1911 - 1912 - static int sd_ddr_tuning(struct rtsx_chip *chip) 1913 - { 1914 - int retval; 1915 - 1916 - if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { 1917 - retval = sd_ddr_pre_tuning_tx(chip); 1918 - if (retval != STATUS_SUCCESS) 1919 - return STATUS_FAIL; 1920 - } else { 1921 - retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, 1922 - TUNE_TX); 1923 - if (retval != STATUS_SUCCESS) 1924 - return STATUS_FAIL; 1925 - } 1926 - 1927 - retval = sd_tuning_rx(chip); 1928 - if (retval != STATUS_SUCCESS) 1929 - return STATUS_FAIL; 1930 - 1931 - if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { 1932 - retval = sd_tuning_tx(chip); 1933 - if (retval != STATUS_SUCCESS) 1934 - return STATUS_FAIL; 1935 - } 1936 - 1937 - return STATUS_SUCCESS; 1938 - } 1939 - 1940 - static int mmc_ddr_tuning(struct rtsx_chip *chip) 1941 - { 1942 - int retval; 1943 - 1944 - if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { 1945 - retval = sd_ddr_pre_tuning_tx(chip); 1946 - if (retval != STATUS_SUCCESS) 1947 - return STATUS_FAIL; 1948 - } else { 1949 - retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, 1950 - TUNE_TX); 1951 - if (retval != STATUS_SUCCESS) 1952 - return STATUS_FAIL; 1953 - } 1954 - 1955 - retval = sd_tuning_rx(chip); 1956 - if (retval != STATUS_SUCCESS) 1957 - return STATUS_FAIL; 1958 - 1959 - if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { 1960 - retval = sd_tuning_tx(chip); 1961 - if (retval != STATUS_SUCCESS) 1962 - return STATUS_FAIL; 1963 - } 1964 - 1965 - return STATUS_SUCCESS; 1966 - } 1967 - 1968 - int sd_switch_clock(struct rtsx_chip *chip) 1969 - { 1970 - struct sd_info *sd_card = &chip->sd_card; 1971 - int retval; 1972 - int re_tuning = 0; 1973 - 1974 - retval = select_card(chip, SD_CARD); 1975 - if (retval != STATUS_SUCCESS) 1976 - return STATUS_FAIL; 1977 - 1978 - retval = switch_clock(chip, sd_card->sd_clock); 1979 - if (retval != STATUS_SUCCESS) 1980 - return STATUS_FAIL; 1981 - 1982 - if (re_tuning) { 1983 - if (CHK_SD(sd_card)) { 1984 - if (CHK_SD_DDR50(sd_card)) 1985 - retval = sd_ddr_tuning(chip); 1986 - else 1987 - retval = sd_sdr_tuning(chip); 1988 - } else { 1989 - if (CHK_MMC_DDR52(sd_card)) 1990 - retval = mmc_ddr_tuning(chip); 1991 - } 1992 - 1993 - if (retval != STATUS_SUCCESS) 1994 - return STATUS_FAIL; 1995 - } 1996 - 1997 - return STATUS_SUCCESS; 1998 - } 1999 - 2000 - static int sd_prepare_reset(struct rtsx_chip *chip) 2001 - { 2002 - struct sd_info *sd_card = &chip->sd_card; 2003 - int retval; 2004 - 2005 - if (chip->asic_code) 2006 - sd_card->sd_clock = 29; 2007 - else 2008 - sd_card->sd_clock = CLK_30; 2009 - 2010 - sd_card->sd_type = 0; 2011 - sd_card->seq_mode = 0; 2012 - sd_card->sd_data_buf_ready = 0; 2013 - sd_card->capacity = 0; 2014 - 2015 - #ifdef SUPPORT_SD_LOCK 2016 - sd_card->sd_lock_status = 0; 2017 - sd_card->sd_erase_status = 0; 2018 - #endif 2019 - 2020 - chip->capacity[chip->card2lun[SD_CARD]] = 0; 2021 - chip->sd_io = 0; 2022 - 2023 - retval = sd_set_init_para(chip); 2024 - if (retval != STATUS_SUCCESS) 2025 - return retval; 2026 - 2027 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40); 2028 - if (retval) 2029 - return retval; 2030 - 2031 - retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 2032 - SD_STOP | SD_CLR_ERR); 2033 - if (retval) 2034 - return retval; 2035 - 2036 - retval = select_card(chip, SD_CARD); 2037 - if (retval != STATUS_SUCCESS) 2038 - return STATUS_FAIL; 2039 - 2040 - return STATUS_SUCCESS; 2041 - } 2042 - 2043 - static int sd_pull_ctl_disable(struct rtsx_chip *chip) 2044 - { 2045 - int retval; 2046 - 2047 - if (CHECK_PID(chip, 0x5208)) { 2048 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 2049 - XD_D3_PD | SD_D7_PD | SD_CLK_PD | 2050 - SD_D5_PD); 2051 - if (retval) 2052 - return retval; 2053 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 2054 - SD_D6_PD | SD_D0_PD | SD_D1_PD | 2055 - XD_D5_PD); 2056 - if (retval) 2057 - return retval; 2058 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 2059 - SD_D4_PD | XD_CE_PD | XD_CLE_PD | 2060 - XD_CD_PU); 2061 - if (retval) 2062 - return retval; 2063 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 2064 - XD_RDY_PD | SD_D3_PD | SD_D2_PD | 2065 - XD_ALE_PD); 2066 - if (retval) 2067 - return retval; 2068 - retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 2069 - MS_INS_PU | SD_WP_PD | SD_CD_PU | 2070 - SD_CMD_PD); 2071 - if (retval) 2072 - return retval; 2073 - retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 2074 - MS_D5_PD | MS_D4_PD); 2075 - if (retval) 2076 - return retval; 2077 - } else if (CHECK_PID(chip, 0x5288)) { 2078 - if (CHECK_BARO_PKG(chip, QFN)) { 2079 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 2080 - 0xFF, 0x55); 2081 - if (retval) 2082 - return retval; 2083 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 2084 - 0xFF, 0x55); 2085 - if (retval) 2086 - return retval; 2087 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 2088 - 0xFF, 0x4B); 2089 - if (retval) 2090 - return retval; 2091 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 2092 - 0xFF, 0x69); 2093 - if (retval) 2094 - return retval; 2095 - } 2096 - } 2097 - 2098 - return STATUS_SUCCESS; 2099 - } 2100 - 2101 - int sd_pull_ctl_enable(struct rtsx_chip *chip) 2102 - { 2103 - int retval; 2104 - 2105 - rtsx_init_cmd(chip); 2106 - 2107 - if (CHECK_PID(chip, 0x5208)) { 2108 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 2109 - XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU); 2110 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 2111 - SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD); 2112 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 2113 - SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 2114 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 2115 - XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD); 2116 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 2117 - MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); 2118 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 2119 - MS_D5_PD | MS_D4_PD); 2120 - } else if (CHECK_PID(chip, 0x5288)) { 2121 - if (CHECK_BARO_PKG(chip, QFN)) { 2122 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 2123 - 0xA8); 2124 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 2125 - 0x5A); 2126 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 2127 - 0x95); 2128 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 2129 - 0xAA); 2130 - } 2131 - } 2132 - 2133 - retval = rtsx_send_cmd(chip, SD_CARD, 100); 2134 - if (retval < 0) 2135 - return STATUS_FAIL; 2136 - 2137 - return STATUS_SUCCESS; 2138 - } 2139 - 2140 - static int sd_init_power(struct rtsx_chip *chip) 2141 - { 2142 - int retval; 2143 - 2144 - retval = sd_power_off_card3v3(chip); 2145 - if (retval != STATUS_SUCCESS) 2146 - return STATUS_FAIL; 2147 - 2148 - if (!chip->ft2_fast_mode) 2149 - wait_timeout(250); 2150 - 2151 - retval = enable_card_clock(chip, SD_CARD); 2152 - if (retval != STATUS_SUCCESS) 2153 - return STATUS_FAIL; 2154 - 2155 - if (chip->asic_code) { 2156 - retval = sd_pull_ctl_enable(chip); 2157 - if (retval != STATUS_SUCCESS) 2158 - return STATUS_FAIL; 2159 - } else { 2160 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 2161 - FPGA_SD_PULL_CTL_BIT | 0x20, 0); 2162 - if (retval) 2163 - return retval; 2164 - } 2165 - 2166 - if (!chip->ft2_fast_mode) { 2167 - retval = card_power_on(chip, SD_CARD); 2168 - if (retval != STATUS_SUCCESS) 2169 - return STATUS_FAIL; 2170 - 2171 - wait_timeout(260); 2172 - 2173 - #ifdef SUPPORT_OCP 2174 - if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 2175 - dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 2176 - chip->ocp_stat); 2177 - return STATUS_FAIL; 2178 - } 2179 - #endif 2180 - } 2181 - 2182 - retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 2183 - SD_OUTPUT_EN); 2184 - if (retval) 2185 - return retval; 2186 - 2187 - return STATUS_SUCCESS; 2188 - } 2189 - 2190 - static int sd_dummy_clock(struct rtsx_chip *chip) 2191 - { 2192 - int retval; 2193 - 2194 - retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01); 2195 - if (retval) 2196 - return retval; 2197 - wait_timeout(5); 2198 - retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0); 2199 - if (retval) 2200 - return retval; 2201 - 2202 - return STATUS_SUCCESS; 2203 - } 2204 - 2205 - static int sd_read_lba0(struct rtsx_chip *chip) 2206 - { 2207 - struct sd_info *sd_card = &chip->sd_card; 2208 - int retval; 2209 - u8 cmd[5], bus_width; 2210 - 2211 - cmd[0] = 0x40 | READ_SINGLE_BLOCK; 2212 - cmd[1] = 0; 2213 - cmd[2] = 0; 2214 - cmd[3] = 0; 2215 - cmd[4] = 0; 2216 - 2217 - if (CHK_SD(sd_card)) { 2218 - bus_width = SD_BUS_WIDTH_4; 2219 - } else { 2220 - if (CHK_MMC_8BIT(sd_card)) 2221 - bus_width = SD_BUS_WIDTH_8; 2222 - else if (CHK_MMC_4BIT(sd_card)) 2223 - bus_width = SD_BUS_WIDTH_4; 2224 - else 2225 - bus_width = SD_BUS_WIDTH_1; 2226 - } 2227 - 2228 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512, 1, 2229 - bus_width, NULL, 0, 100); 2230 - if (retval != STATUS_SUCCESS) { 2231 - rtsx_clear_sd_error(chip); 2232 - return STATUS_FAIL; 2233 - } 2234 - 2235 - return STATUS_SUCCESS; 2236 - } 2237 - 2238 - static int sd_check_wp_state(struct rtsx_chip *chip) 2239 - { 2240 - struct sd_info *sd_card = &chip->sd_card; 2241 - int retval; 2242 - u32 val; 2243 - u16 sd_card_type; 2244 - u8 cmd[5], buf[64]; 2245 - 2246 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2247 - SD_RSP_TYPE_R1, NULL, 0); 2248 - if (retval != STATUS_SUCCESS) 2249 - return STATUS_FAIL; 2250 - 2251 - cmd[0] = 0x40 | SD_STATUS; 2252 - cmd[1] = 0; 2253 - cmd[2] = 0; 2254 - cmd[3] = 0; 2255 - cmd[4] = 0; 2256 - 2257 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, 2258 - SD_BUS_WIDTH_4, buf, 64, 250); 2259 - if (retval != STATUS_SUCCESS) { 2260 - rtsx_clear_sd_error(chip); 2261 - 2262 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2263 - SD_RSP_TYPE_R1, NULL, 0); 2264 - return STATUS_FAIL; 2265 - } 2266 - 2267 - dev_dbg(rtsx_dev(chip), "ACMD13:\n"); 2268 - dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf); 2269 - 2270 - sd_card_type = ((u16)buf[2] << 8) | buf[3]; 2271 - dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type); 2272 - if (sd_card_type == 0x0001 || sd_card_type == 0x0002) { 2273 - /* ROM card or OTP */ 2274 - chip->card_wp |= SD_CARD; 2275 - } 2276 - 2277 - /* Check SD Machanical Write-Protect Switch */ 2278 - val = rtsx_readl(chip, RTSX_BIPR); 2279 - if (val & SD_WRITE_PROTECT) 2280 - chip->card_wp |= SD_CARD; 2281 - 2282 - return STATUS_SUCCESS; 2283 - } 2284 - 2285 - static int reset_sd(struct rtsx_chip *chip) 2286 - { 2287 - struct sd_info *sd_card = &chip->sd_card; 2288 - bool hi_cap_flow = false; 2289 - int retval, i = 0, j = 0, k = 0; 2290 - bool sd_dont_switch = false; 2291 - bool support_1v8 = false; 2292 - bool try_sdio = true; 2293 - u8 rsp[16]; 2294 - u8 switch_bus_width; 2295 - u32 voltage = 0; 2296 - bool sd20_mode = false; 2297 - 2298 - SET_SD(sd_card); 2299 - 2300 - switch_fail: 2301 - 2302 - i = 0; 2303 - j = 0; 2304 - k = 0; 2305 - hi_cap_flow = false; 2306 - 2307 - #ifdef SUPPORT_SD_LOCK 2308 - if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) 2309 - goto SD_UNLOCK_ENTRY; 2310 - #endif 2311 - 2312 - retval = sd_prepare_reset(chip); 2313 - if (retval != STATUS_SUCCESS) 2314 - goto status_fail; 2315 - 2316 - retval = sd_dummy_clock(chip); 2317 - if (retval != STATUS_SUCCESS) 2318 - goto status_fail; 2319 - 2320 - if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) { 2321 - int rty_cnt = 0; 2322 - 2323 - for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) { 2324 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2325 - sd_set_err_code(chip, SD_NO_CARD); 2326 - goto status_fail; 2327 - } 2328 - 2329 - retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, 2330 - SD_RSP_TYPE_R4, rsp, 5); 2331 - if (retval == STATUS_SUCCESS) { 2332 - int func_num = (rsp[1] >> 4) & 0x07; 2333 - 2334 - if (func_num) { 2335 - dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n", 2336 - func_num); 2337 - chip->sd_io = 1; 2338 - goto status_fail; 2339 - } 2340 - 2341 - break; 2342 - } 2343 - 2344 - sd_init_power(chip); 2345 - 2346 - sd_dummy_clock(chip); 2347 - } 2348 - 2349 - dev_dbg(rtsx_dev(chip), "Normal card!\n"); 2350 - } 2351 - 2352 - /* Start Initialization Process of SD Card */ 2353 - RTY_SD_RST: 2354 - retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, 2355 - NULL, 0); 2356 - if (retval != STATUS_SUCCESS) 2357 - goto status_fail; 2358 - 2359 - wait_timeout(20); 2360 - 2361 - retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, 2362 - SD_RSP_TYPE_R7, rsp, 5); 2363 - if (retval == STATUS_SUCCESS) { 2364 - if (rsp[4] == 0xAA && ((rsp[3] & 0x0f) == 0x01)) { 2365 - hi_cap_flow = true; 2366 - voltage = SUPPORT_VOLTAGE | 0x40000000; 2367 - } 2368 - } 2369 - 2370 - if (!hi_cap_flow) { 2371 - voltage = SUPPORT_VOLTAGE; 2372 - 2373 - retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, 2374 - SD_RSP_TYPE_R0, NULL, 0); 2375 - if (retval != STATUS_SUCCESS) 2376 - goto status_fail; 2377 - 2378 - wait_timeout(20); 2379 - } 2380 - 2381 - do { 2382 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, 2383 - NULL, 0); 2384 - if (retval != STATUS_SUCCESS) { 2385 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2386 - sd_set_err_code(chip, SD_NO_CARD); 2387 - goto status_fail; 2388 - } 2389 - 2390 - j++; 2391 - if (j < 3) 2392 - goto RTY_SD_RST; 2393 - else 2394 - goto status_fail; 2395 - } 2396 - 2397 - retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, 2398 - SD_RSP_TYPE_R3, rsp, 5); 2399 - if (retval != STATUS_SUCCESS) { 2400 - k++; 2401 - if (k < 3) 2402 - goto RTY_SD_RST; 2403 - else 2404 - goto status_fail; 2405 - } 2406 - 2407 - i++; 2408 - wait_timeout(20); 2409 - } while (!(rsp[1] & 0x80) && (i < 255)); 2410 - 2411 - if (i == 255) 2412 - goto status_fail; 2413 - 2414 - if (hi_cap_flow) { 2415 - if (rsp[1] & 0x40) 2416 - SET_SD_HCXC(sd_card); 2417 - else 2418 - CLR_SD_HCXC(sd_card); 2419 - 2420 - support_1v8 = false; 2421 - } else { 2422 - CLR_SD_HCXC(sd_card); 2423 - support_1v8 = false; 2424 - } 2425 - dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8); 2426 - 2427 - if (support_1v8) { 2428 - retval = sd_voltage_switch(chip); 2429 - if (retval != STATUS_SUCCESS) 2430 - goto status_fail; 2431 - } 2432 - 2433 - retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, 2434 - NULL, 0); 2435 - if (retval != STATUS_SUCCESS) 2436 - goto status_fail; 2437 - 2438 - for (i = 0; i < 3; i++) { 2439 - retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, 2440 - SD_RSP_TYPE_R6, rsp, 5); 2441 - if (retval != STATUS_SUCCESS) 2442 - goto status_fail; 2443 - 2444 - sd_card->sd_addr = (u32)rsp[1] << 24; 2445 - sd_card->sd_addr += (u32)rsp[2] << 16; 2446 - 2447 - if (sd_card->sd_addr) 2448 - break; 2449 - } 2450 - 2451 - retval = sd_check_csd(chip, 1); 2452 - if (retval != STATUS_SUCCESS) 2453 - goto status_fail; 2454 - 2455 - retval = sd_select_card(chip, 1); 2456 - if (retval != STATUS_SUCCESS) 2457 - goto status_fail; 2458 - 2459 - #ifdef SUPPORT_SD_LOCK 2460 - SD_UNLOCK_ENTRY: 2461 - retval = sd_update_lock_status(chip); 2462 - if (retval != STATUS_SUCCESS) 2463 - goto status_fail; 2464 - 2465 - if (sd_card->sd_lock_status & SD_LOCKED) { 2466 - sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST); 2467 - return STATUS_SUCCESS; 2468 - } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) { 2469 - sd_card->sd_lock_status &= ~SD_PWD_EXIST; 2470 - } 2471 - #endif 2472 - 2473 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2474 - SD_RSP_TYPE_R1, NULL, 0); 2475 - if (retval != STATUS_SUCCESS) 2476 - goto status_fail; 2477 - 2478 - retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, 2479 - SD_RSP_TYPE_R1, NULL, 0); 2480 - if (retval != STATUS_SUCCESS) 2481 - goto status_fail; 2482 - 2483 - if (support_1v8) { 2484 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2485 - SD_RSP_TYPE_R1, NULL, 0); 2486 - if (retval != STATUS_SUCCESS) 2487 - goto status_fail; 2488 - 2489 - retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, 2490 - SD_RSP_TYPE_R1, NULL, 0); 2491 - if (retval != STATUS_SUCCESS) 2492 - goto status_fail; 2493 - 2494 - switch_bus_width = SD_BUS_WIDTH_4; 2495 - } else { 2496 - switch_bus_width = SD_BUS_WIDTH_1; 2497 - } 2498 - 2499 - retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, 2500 - NULL, 0); 2501 - if (retval != STATUS_SUCCESS) 2502 - goto status_fail; 2503 - 2504 - retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 2505 - if (retval != STATUS_SUCCESS) 2506 - goto status_fail; 2507 - 2508 - if (!(sd_card->raw_csd[4] & 0x40)) 2509 - sd_dont_switch = true; 2510 - 2511 - if (!sd_dont_switch) { 2512 - if (sd20_mode) { 2513 - /* Set sd_switch_fail here, because we needn't 2514 - * switch to UHS mode 2515 - */ 2516 - sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 2517 - DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; 2518 - } 2519 - 2520 - /* Check the card whether follow SD1.1 spec or higher */ 2521 - retval = sd_check_spec(chip, switch_bus_width); 2522 - if (retval == STATUS_SUCCESS) { 2523 - retval = sd_switch_function(chip, switch_bus_width); 2524 - if (retval != STATUS_SUCCESS) { 2525 - sd_init_power(chip); 2526 - sd_dont_switch = true; 2527 - try_sdio = false; 2528 - 2529 - goto switch_fail; 2530 - } 2531 - } else { 2532 - if (support_1v8) { 2533 - sd_init_power(chip); 2534 - sd_dont_switch = true; 2535 - try_sdio = false; 2536 - 2537 - goto switch_fail; 2538 - } 2539 - } 2540 - } 2541 - 2542 - if (!support_1v8) { 2543 - retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2544 - SD_RSP_TYPE_R1, NULL, 0); 2545 - if (retval != STATUS_SUCCESS) 2546 - goto status_fail; 2547 - 2548 - retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, 2549 - SD_RSP_TYPE_R1, NULL, 0); 2550 - if (retval != STATUS_SUCCESS) 2551 - goto status_fail; 2552 - } 2553 - 2554 - #ifdef SUPPORT_SD_LOCK 2555 - sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 2556 - #endif 2557 - 2558 - if (!sd20_mode && CHK_SD30_SPEED(sd_card)) { 2559 - int read_lba0 = 1; 2560 - 2561 - retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07, 2562 - chip->sd30_drive_sel_1v8); 2563 - if (retval) 2564 - return retval; 2565 - 2566 - retval = sd_set_init_para(chip); 2567 - if (retval != STATUS_SUCCESS) 2568 - goto status_fail; 2569 - 2570 - if (CHK_SD_DDR50(sd_card)) 2571 - retval = sd_ddr_tuning(chip); 2572 - else 2573 - retval = sd_sdr_tuning(chip); 2574 - 2575 - if (retval != STATUS_SUCCESS) { 2576 - retval = sd_init_power(chip); 2577 - if (retval != STATUS_SUCCESS) 2578 - goto status_fail; 2579 - 2580 - try_sdio = false; 2581 - sd20_mode = true; 2582 - goto switch_fail; 2583 - } 2584 - 2585 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2586 - SD_RSP_TYPE_R1, NULL, 0); 2587 - 2588 - if (CHK_SD_DDR50(sd_card)) { 2589 - retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 2590 - if (retval != STATUS_SUCCESS) 2591 - read_lba0 = 0; 2592 - } 2593 - 2594 - if (read_lba0) { 2595 - retval = sd_read_lba0(chip); 2596 - if (retval != STATUS_SUCCESS) { 2597 - retval = sd_init_power(chip); 2598 - if (retval != STATUS_SUCCESS) 2599 - goto status_fail; 2600 - 2601 - try_sdio = false; 2602 - sd20_mode = true; 2603 - goto switch_fail; 2604 - } 2605 - } 2606 - } 2607 - 2608 - retval = sd_check_wp_state(chip); 2609 - if (retval != STATUS_SUCCESS) 2610 - goto status_fail; 2611 - 2612 - chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; 2613 - 2614 - #ifdef SUPPORT_SD_LOCK 2615 - if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { 2616 - retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, 2617 - 0x02); 2618 - if (retval) 2619 - return retval; 2620 - retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, 2621 - 0x00); 2622 - if (retval) 2623 - return retval; 2624 - } 2625 - #endif 2626 - 2627 - return STATUS_SUCCESS; 2628 - 2629 - status_fail: 2630 - return STATUS_FAIL; 2631 - } 2632 - 2633 - static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width) 2634 - { 2635 - struct sd_info *sd_card = &chip->sd_card; 2636 - int retval; 2637 - u8 buf[8] = {0}, bus_width, *ptr; 2638 - u16 byte_cnt; 2639 - int len; 2640 - 2641 - retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 2642 - 0); 2643 - if (retval != STATUS_SUCCESS) 2644 - return SWITCH_FAIL; 2645 - 2646 - if (width == MMC_8BIT_BUS) { 2647 - buf[0] = 0x55; 2648 - buf[1] = 0xAA; 2649 - len = 8; 2650 - byte_cnt = 8; 2651 - bus_width = SD_BUS_WIDTH_8; 2652 - } else { 2653 - buf[0] = 0x5A; 2654 - len = 4; 2655 - byte_cnt = 4; 2656 - bus_width = SD_BUS_WIDTH_4; 2657 - } 2658 - 2659 - retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02); 2660 - if (retval != STATUS_SUCCESS) 2661 - return SWITCH_ERR; 2662 - 2663 - retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, NULL, 0, byte_cnt, 1, 2664 - bus_width, buf, len, 100); 2665 - if (retval != STATUS_SUCCESS) { 2666 - rtsx_clear_sd_error(chip); 2667 - rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); 2668 - return SWITCH_ERR; 2669 - } 2670 - 2671 - retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); 2672 - if (retval != STATUS_SUCCESS) 2673 - return SWITCH_ERR; 2674 - 2675 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R); 2676 - 2677 - rtsx_init_cmd(chip); 2678 - 2679 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R); 2680 - 2681 - if (width == MMC_8BIT_BUS) 2682 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 2683 - 0xFF, 0x08); 2684 - else 2685 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 2686 - 0xFF, 0x04); 2687 - 2688 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); 2689 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); 2690 - 2691 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, SD_CALCULATE_CRC7 | 2692 - SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | 2693 - SD_CHECK_CRC7 | SD_RSP_LEN_6); 2694 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 2695 - PINGPONG_BUFFER); 2696 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 2697 - SD_TM_NORMAL_READ | SD_TRANSFER_START); 2698 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 2699 - SD_TRANSFER_END); 2700 - 2701 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0); 2702 - if (width == MMC_8BIT_BUS) 2703 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0); 2704 - 2705 - retval = rtsx_send_cmd(chip, SD_CARD, 100); 2706 - if (retval < 0) { 2707 - rtsx_clear_sd_error(chip); 2708 - return SWITCH_ERR; 2709 - } 2710 - 2711 - ptr = rtsx_get_cmd_data(chip) + 1; 2712 - 2713 - if (width == MMC_8BIT_BUS) { 2714 - dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n", 2715 - ptr[0], ptr[1]); 2716 - if (ptr[0] == 0xAA && ptr[1] == 0x55) { 2717 - u8 rsp[5]; 2718 - u32 arg; 2719 - 2720 - if (CHK_MMC_DDR52(sd_card)) 2721 - arg = 0x03B70600; 2722 - else 2723 - arg = 0x03B70200; 2724 - 2725 - retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, 2726 - SD_RSP_TYPE_R1b, rsp, 5); 2727 - if (retval == STATUS_SUCCESS && 2728 - !(rsp[4] & MMC_SWITCH_ERR)) 2729 - return SWITCH_SUCCESS; 2730 - } 2731 - } else { 2732 - dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]); 2733 - if (ptr[0] == 0xA5) { 2734 - u8 rsp[5]; 2735 - u32 arg; 2736 - 2737 - if (CHK_MMC_DDR52(sd_card)) 2738 - arg = 0x03B70500; 2739 - else 2740 - arg = 0x03B70100; 2741 - 2742 - retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, 2743 - SD_RSP_TYPE_R1b, rsp, 5); 2744 - if (retval == STATUS_SUCCESS && 2745 - !(rsp[4] & MMC_SWITCH_ERR)) 2746 - return SWITCH_SUCCESS; 2747 - } 2748 - } 2749 - 2750 - return SWITCH_FAIL; 2751 - } 2752 - 2753 - static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr) 2754 - { 2755 - struct sd_info *sd_card = &chip->sd_card; 2756 - int retval; 2757 - u8 *ptr, card_type, card_type_mask = 0; 2758 - 2759 - CLR_MMC_HS(sd_card); 2760 - 2761 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD); 2762 - 2763 - rtsx_init_cmd(chip); 2764 - 2765 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 2766 - 0x40 | SEND_EXT_CSD); 2767 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0); 2768 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0); 2769 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0); 2770 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0); 2771 - 2772 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0); 2773 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2); 2774 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); 2775 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); 2776 - 2777 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 2778 - SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | 2779 - SD_CHECK_CRC7 | SD_RSP_LEN_6); 2780 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 2781 - PINGPONG_BUFFER); 2782 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 2783 - SD_TM_NORMAL_READ | SD_TRANSFER_START); 2784 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 2785 - SD_TRANSFER_END); 2786 - 2787 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0); 2788 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0); 2789 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0); 2790 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0); 2791 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0); 2792 - 2793 - retval = rtsx_send_cmd(chip, SD_CARD, 1000); 2794 - if (retval < 0) { 2795 - if (retval == -ETIMEDOUT) { 2796 - rtsx_clear_sd_error(chip); 2797 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2798 - SD_RSP_TYPE_R1, NULL, 0); 2799 - } 2800 - return STATUS_FAIL; 2801 - } 2802 - 2803 - ptr = rtsx_get_cmd_data(chip); 2804 - if (ptr[0] & SD_TRANSFER_ERR) { 2805 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2806 - SD_RSP_TYPE_R1, NULL, 0); 2807 - return STATUS_FAIL; 2808 - } 2809 - 2810 - if (CHK_MMC_SECTOR_MODE(sd_card)) { 2811 - sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) | 2812 - ((u32)ptr[3] << 8) | ((u32)ptr[2]); 2813 - } 2814 - 2815 - card_type_mask = 0x03; 2816 - card_type = ptr[1] & card_type_mask; 2817 - if (card_type) { 2818 - u8 rsp[5]; 2819 - 2820 - if (card_type & 0x04) { 2821 - if (switch_ddr) 2822 - SET_MMC_DDR52(sd_card); 2823 - else 2824 - SET_MMC_52M(sd_card); 2825 - } else if (card_type & 0x02) { 2826 - SET_MMC_52M(sd_card); 2827 - } else { 2828 - SET_MMC_26M(sd_card); 2829 - } 2830 - 2831 - retval = sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100, 2832 - SD_RSP_TYPE_R1b, rsp, 5); 2833 - if (retval != STATUS_SUCCESS || (rsp[4] & MMC_SWITCH_ERR)) 2834 - CLR_MMC_HS(sd_card); 2835 - } 2836 - 2837 - sd_choose_proper_clock(chip); 2838 - retval = switch_clock(chip, sd_card->sd_clock); 2839 - if (retval != STATUS_SUCCESS) 2840 - return STATUS_FAIL; 2841 - 2842 - /* Test Bus Procedure */ 2843 - retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS); 2844 - if (retval == SWITCH_SUCCESS) { 2845 - SET_MMC_8BIT(sd_card); 2846 - chip->card_bus_width[chip->card2lun[SD_CARD]] = 8; 2847 - #ifdef SUPPORT_SD_LOCK 2848 - sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 2849 - #endif 2850 - } else if (retval == SWITCH_FAIL) { 2851 - retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS); 2852 - if (retval == SWITCH_SUCCESS) { 2853 - SET_MMC_4BIT(sd_card); 2854 - chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; 2855 - #ifdef SUPPORT_SD_LOCK 2856 - sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 2857 - #endif 2858 - } else if (retval == SWITCH_FAIL) { 2859 - CLR_MMC_8BIT(sd_card); 2860 - CLR_MMC_4BIT(sd_card); 2861 - } else { 2862 - return STATUS_FAIL; 2863 - } 2864 - } else { 2865 - return STATUS_FAIL; 2866 - } 2867 - 2868 - return STATUS_SUCCESS; 2869 - } 2870 - 2871 - static int reset_mmc(struct rtsx_chip *chip) 2872 - { 2873 - struct sd_info *sd_card = &chip->sd_card; 2874 - int retval, i = 0, j = 0, k = 0; 2875 - bool switch_ddr = true; 2876 - u8 rsp[16]; 2877 - u8 spec_ver = 0; 2878 - u32 temp; 2879 - 2880 - #ifdef SUPPORT_SD_LOCK 2881 - if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) 2882 - goto MMC_UNLOCK_ENTRY; 2883 - #endif 2884 - 2885 - switch_fail: 2886 - retval = sd_prepare_reset(chip); 2887 - if (retval != STATUS_SUCCESS) 2888 - return retval; 2889 - 2890 - SET_MMC(sd_card); 2891 - 2892 - RTY_MMC_RST: 2893 - retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, 2894 - NULL, 0); 2895 - if (retval != STATUS_SUCCESS) 2896 - return STATUS_FAIL; 2897 - 2898 - do { 2899 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2900 - sd_set_err_code(chip, SD_NO_CARD); 2901 - return STATUS_FAIL; 2902 - } 2903 - 2904 - retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND, 2905 - (SUPPORT_VOLTAGE | 0x40000000), 2906 - SD_RSP_TYPE_R3, rsp, 5); 2907 - if (retval != STATUS_SUCCESS) { 2908 - if (sd_check_err_code(chip, SD_BUSY) || 2909 - sd_check_err_code(chip, SD_TO_ERR)) { 2910 - k++; 2911 - if (k < 20) { 2912 - sd_clr_err_code(chip); 2913 - goto RTY_MMC_RST; 2914 - } else { 2915 - return STATUS_FAIL; 2916 - } 2917 - } else { 2918 - j++; 2919 - if (j < 100) { 2920 - sd_clr_err_code(chip); 2921 - goto RTY_MMC_RST; 2922 - } else { 2923 - return STATUS_FAIL; 2924 - } 2925 - } 2926 - } 2927 - 2928 - wait_timeout(20); 2929 - i++; 2930 - } while (!(rsp[1] & 0x80) && (i < 255)); 2931 - 2932 - if (i == 255) 2933 - return STATUS_FAIL; 2934 - 2935 - if ((rsp[1] & 0x60) == 0x40) 2936 - SET_MMC_SECTOR_MODE(sd_card); 2937 - else 2938 - CLR_MMC_SECTOR_MODE(sd_card); 2939 - 2940 - retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, 2941 - NULL, 0); 2942 - if (retval != STATUS_SUCCESS) 2943 - return STATUS_FAIL; 2944 - 2945 - sd_card->sd_addr = 0x00100000; 2946 - retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, 2947 - SD_RSP_TYPE_R6, rsp, 5); 2948 - if (retval != STATUS_SUCCESS) 2949 - return STATUS_FAIL; 2950 - 2951 - retval = sd_check_csd(chip, 1); 2952 - if (retval != STATUS_SUCCESS) 2953 - return STATUS_FAIL; 2954 - 2955 - spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2; 2956 - 2957 - retval = sd_select_card(chip, 1); 2958 - if (retval != STATUS_SUCCESS) 2959 - return STATUS_FAIL; 2960 - 2961 - retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, 2962 - NULL, 0); 2963 - if (retval != STATUS_SUCCESS) 2964 - return STATUS_FAIL; 2965 - 2966 - #ifdef SUPPORT_SD_LOCK 2967 - MMC_UNLOCK_ENTRY: 2968 - retval = sd_update_lock_status(chip); 2969 - if (retval != STATUS_SUCCESS) 2970 - return STATUS_FAIL; 2971 - #endif 2972 - 2973 - retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 2974 - if (retval != STATUS_SUCCESS) 2975 - return STATUS_FAIL; 2976 - 2977 - chip->card_bus_width[chip->card2lun[SD_CARD]] = 1; 2978 - 2979 - if (!sd_card->mmc_dont_switch_bus) { 2980 - if (spec_ver == 4) { 2981 - /* MMC 4.x Cards */ 2982 - retval = mmc_switch_timing_bus(chip, switch_ddr); 2983 - if (retval != STATUS_SUCCESS) { 2984 - retval = sd_init_power(chip); 2985 - if (retval != STATUS_SUCCESS) 2986 - return STATUS_FAIL; 2987 - sd_card->mmc_dont_switch_bus = 1; 2988 - goto switch_fail; 2989 - } 2990 - } 2991 - 2992 - if (CHK_MMC_SECTOR_MODE(sd_card) && sd_card->capacity == 0) 2993 - return STATUS_FAIL; 2994 - 2995 - if (switch_ddr && CHK_MMC_DDR52(sd_card)) { 2996 - retval = sd_set_init_para(chip); 2997 - if (retval != STATUS_SUCCESS) 2998 - return STATUS_FAIL; 2999 - 3000 - retval = mmc_ddr_tuning(chip); 3001 - if (retval != STATUS_SUCCESS) { 3002 - retval = sd_init_power(chip); 3003 - if (retval != STATUS_SUCCESS) 3004 - return STATUS_FAIL; 3005 - 3006 - switch_ddr = false; 3007 - goto switch_fail; 3008 - } 3009 - 3010 - retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 3011 - if (retval == STATUS_SUCCESS) { 3012 - retval = sd_read_lba0(chip); 3013 - if (retval != STATUS_SUCCESS) { 3014 - retval = sd_init_power(chip); 3015 - if (retval != STATUS_SUCCESS) 3016 - return STATUS_FAIL; 3017 - 3018 - switch_ddr = false; 3019 - goto switch_fail; 3020 - } 3021 - } 3022 - } 3023 - } 3024 - 3025 - #ifdef SUPPORT_SD_LOCK 3026 - if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { 3027 - retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, 3028 - 0x02); 3029 - if (retval) 3030 - return retval; 3031 - retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, 3032 - 0x00); 3033 - if (retval) 3034 - return retval; 3035 - } 3036 - #endif 3037 - 3038 - temp = rtsx_readl(chip, RTSX_BIPR); 3039 - if (temp & SD_WRITE_PROTECT) 3040 - chip->card_wp |= SD_CARD; 3041 - 3042 - return STATUS_SUCCESS; 3043 - } 3044 - 3045 - int reset_sd_card(struct rtsx_chip *chip) 3046 - { 3047 - struct sd_info *sd_card = &chip->sd_card; 3048 - int retval; 3049 - 3050 - sd_init_reg_addr(chip); 3051 - 3052 - memset(sd_card, 0, sizeof(struct sd_info)); 3053 - chip->capacity[chip->card2lun[SD_CARD]] = 0; 3054 - 3055 - retval = enable_card_clock(chip, SD_CARD); 3056 - if (retval != STATUS_SUCCESS) 3057 - return STATUS_FAIL; 3058 - 3059 - if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && 3060 - !CHK_SDIO_IGNORED(chip)) { 3061 - if (chip->asic_code) { 3062 - retval = sd_pull_ctl_enable(chip); 3063 - if (retval != STATUS_SUCCESS) 3064 - return STATUS_FAIL; 3065 - } else { 3066 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 3067 - FPGA_SD_PULL_CTL_BIT | 3068 - 0x20, 0); 3069 - if (retval != STATUS_SUCCESS) 3070 - return STATUS_FAIL; 3071 - } 3072 - retval = card_share_mode(chip, SD_CARD); 3073 - if (retval != STATUS_SUCCESS) 3074 - return STATUS_FAIL; 3075 - 3076 - chip->sd_io = 1; 3077 - return STATUS_FAIL; 3078 - } 3079 - 3080 - retval = sd_init_power(chip); 3081 - if (retval != STATUS_SUCCESS) 3082 - return STATUS_FAIL; 3083 - 3084 - if (chip->sd_ctl & RESET_MMC_FIRST) { 3085 - retval = reset_mmc(chip); 3086 - if (retval != STATUS_SUCCESS) { 3087 - if (sd_check_err_code(chip, SD_NO_CARD)) 3088 - return STATUS_FAIL; 3089 - 3090 - retval = reset_sd(chip); 3091 - if (retval != STATUS_SUCCESS) 3092 - return STATUS_FAIL; 3093 - } 3094 - } else { 3095 - retval = reset_sd(chip); 3096 - if (retval != STATUS_SUCCESS) { 3097 - if (sd_check_err_code(chip, SD_NO_CARD)) 3098 - return STATUS_FAIL; 3099 - 3100 - if (chip->sd_io) 3101 - return STATUS_FAIL; 3102 - retval = reset_mmc(chip); 3103 - if (retval != STATUS_SUCCESS) 3104 - return STATUS_FAIL; 3105 - } 3106 - } 3107 - 3108 - retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 3109 - if (retval != STATUS_SUCCESS) 3110 - return STATUS_FAIL; 3111 - 3112 - retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); 3113 - if (retval) 3114 - return retval; 3115 - retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); 3116 - if (retval) 3117 - return retval; 3118 - 3119 - chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; 3120 - 3121 - retval = sd_set_init_para(chip); 3122 - if (retval != STATUS_SUCCESS) 3123 - return STATUS_FAIL; 3124 - 3125 - dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type); 3126 - 3127 - return STATUS_SUCCESS; 3128 - } 3129 - 3130 - static int reset_mmc_only(struct rtsx_chip *chip) 3131 - { 3132 - struct sd_info *sd_card = &chip->sd_card; 3133 - int retval; 3134 - 3135 - sd_card->sd_type = 0; 3136 - sd_card->seq_mode = 0; 3137 - sd_card->sd_data_buf_ready = 0; 3138 - sd_card->capacity = 0; 3139 - sd_card->sd_switch_fail = 0; 3140 - 3141 - #ifdef SUPPORT_SD_LOCK 3142 - sd_card->sd_lock_status = 0; 3143 - sd_card->sd_erase_status = 0; 3144 - #endif 3145 - 3146 - chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0; 3147 - 3148 - retval = enable_card_clock(chip, SD_CARD); 3149 - if (retval != STATUS_SUCCESS) 3150 - return STATUS_FAIL; 3151 - 3152 - retval = sd_init_power(chip); 3153 - if (retval != STATUS_SUCCESS) 3154 - return STATUS_FAIL; 3155 - 3156 - retval = reset_mmc(chip); 3157 - if (retval != STATUS_SUCCESS) 3158 - return STATUS_FAIL; 3159 - 3160 - retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 3161 - if (retval != STATUS_SUCCESS) 3162 - return STATUS_FAIL; 3163 - 3164 - retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); 3165 - if (retval) 3166 - return retval; 3167 - retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); 3168 - if (retval) 3169 - return retval; 3170 - 3171 - chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; 3172 - 3173 - retval = sd_set_init_para(chip); 3174 - if (retval != STATUS_SUCCESS) 3175 - return STATUS_FAIL; 3176 - 3177 - dev_dbg(rtsx_dev(chip), "In %s, sd_card->sd_type = 0x%x\n", 3178 - __func__, sd_card->sd_type); 3179 - 3180 - return STATUS_SUCCESS; 3181 - } 3182 - 3183 - #define WAIT_DATA_READY_RTY_CNT 255 3184 - 3185 - static int wait_data_buf_ready(struct rtsx_chip *chip) 3186 - { 3187 - struct sd_info *sd_card = &chip->sd_card; 3188 - int i, retval; 3189 - 3190 - for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) { 3191 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3192 - sd_set_err_code(chip, SD_NO_CARD); 3193 - return STATUS_FAIL; 3194 - } 3195 - 3196 - sd_card->sd_data_buf_ready = 0; 3197 - 3198 - retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 3199 - sd_card->sd_addr, SD_RSP_TYPE_R1, 3200 - NULL, 0); 3201 - if (retval != STATUS_SUCCESS) 3202 - return STATUS_FAIL; 3203 - 3204 - if (sd_card->sd_data_buf_ready) { 3205 - return sd_send_cmd_get_rsp(chip, SEND_STATUS, 3206 - sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); 3207 - } 3208 - } 3209 - 3210 - sd_set_err_code(chip, SD_TO_ERR); 3211 - 3212 - return STATUS_FAIL; 3213 - } 3214 - 3215 - void sd_stop_seq_mode(struct rtsx_chip *chip) 3216 - { 3217 - struct sd_info *sd_card = &chip->sd_card; 3218 - int retval; 3219 - 3220 - if (sd_card->seq_mode) { 3221 - retval = sd_switch_clock(chip); 3222 - if (retval != STATUS_SUCCESS) 3223 - return; 3224 - 3225 - retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 3226 - SD_RSP_TYPE_R1b, NULL, 0); 3227 - if (retval != STATUS_SUCCESS) 3228 - sd_set_err_code(chip, SD_STS_ERR); 3229 - 3230 - retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 3231 - if (retval != STATUS_SUCCESS) 3232 - sd_set_err_code(chip, SD_STS_ERR); 3233 - 3234 - sd_card->seq_mode = 0; 3235 - 3236 - rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3237 - } 3238 - } 3239 - 3240 - static inline int sd_auto_tune_clock(struct rtsx_chip *chip) 3241 - { 3242 - struct sd_info *sd_card = &chip->sd_card; 3243 - int retval; 3244 - 3245 - if (chip->asic_code) { 3246 - if (sd_card->sd_clock > 30) 3247 - sd_card->sd_clock -= 20; 3248 - } else { 3249 - switch (sd_card->sd_clock) { 3250 - case CLK_200: 3251 - sd_card->sd_clock = CLK_150; 3252 - break; 3253 - 3254 - case CLK_150: 3255 - sd_card->sd_clock = CLK_120; 3256 - break; 3257 - 3258 - case CLK_120: 3259 - sd_card->sd_clock = CLK_100; 3260 - break; 3261 - 3262 - case CLK_100: 3263 - sd_card->sd_clock = CLK_80; 3264 - break; 3265 - 3266 - case CLK_80: 3267 - sd_card->sd_clock = CLK_60; 3268 - break; 3269 - 3270 - case CLK_60: 3271 - sd_card->sd_clock = CLK_50; 3272 - break; 3273 - 3274 - default: 3275 - break; 3276 - } 3277 - } 3278 - 3279 - retval = sd_switch_clock(chip); 3280 - if (retval != STATUS_SUCCESS) 3281 - return STATUS_FAIL; 3282 - 3283 - return STATUS_SUCCESS; 3284 - } 3285 - 3286 - int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, 3287 - u16 sector_cnt) 3288 - { 3289 - struct sd_info *sd_card = &chip->sd_card; 3290 - u32 data_addr; 3291 - u8 cfg2; 3292 - int retval; 3293 - 3294 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3295 - dev_dbg(rtsx_dev(chip), "%s: Read %d %s from 0x%x\n", __func__, 3296 - sector_cnt, (sector_cnt > 1) ? "sectors" : "sector", 3297 - start_sector); 3298 - } else { 3299 - dev_dbg(rtsx_dev(chip), "%s: Write %d %s to 0x%x\n", __func__, 3300 - sector_cnt, (sector_cnt > 1) ? "sectors" : "sector", 3301 - start_sector); 3302 - } 3303 - 3304 - sd_card->cleanup_counter = 0; 3305 - 3306 - if (!(chip->card_ready & SD_CARD)) { 3307 - sd_card->seq_mode = 0; 3308 - 3309 - retval = reset_sd_card(chip); 3310 - if (retval == STATUS_SUCCESS) { 3311 - chip->card_ready |= SD_CARD; 3312 - chip->card_fail &= ~SD_CARD; 3313 - } else { 3314 - chip->card_ready &= ~SD_CARD; 3315 - chip->card_fail |= SD_CARD; 3316 - chip->capacity[chip->card2lun[SD_CARD]] = 0; 3317 - chip->rw_need_retry = 1; 3318 - return STATUS_FAIL; 3319 - } 3320 - } 3321 - 3322 - if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) 3323 - data_addr = start_sector << 9; 3324 - else 3325 - data_addr = start_sector; 3326 - 3327 - sd_clr_err_code(chip); 3328 - 3329 - retval = sd_switch_clock(chip); 3330 - if (retval != STATUS_SUCCESS) { 3331 - sd_set_err_code(chip, SD_IO_ERR); 3332 - goto RW_FAIL; 3333 - } 3334 - 3335 - if (sd_card->seq_mode && 3336 - (sd_card->pre_dir != srb->sc_data_direction || 3337 - ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != 3338 - start_sector))) { 3339 - if (sd_card->pre_sec_cnt < 0x80 && 3340 - sd_card->pre_dir == DMA_FROM_DEVICE && 3341 - !CHK_SD30_SPEED(sd_card) && 3342 - !CHK_SD_HS(sd_card) && 3343 - !CHK_MMC_HS(sd_card)) { 3344 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3345 - SD_RSP_TYPE_R1, NULL, 0); 3346 - } 3347 - 3348 - retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 3349 - SD_RSP_TYPE_R1b, NULL, 0); 3350 - if (retval != STATUS_SUCCESS) { 3351 - chip->rw_need_retry = 1; 3352 - sd_set_err_code(chip, SD_STS_ERR); 3353 - goto RW_FAIL; 3354 - } 3355 - 3356 - sd_card->seq_mode = 0; 3357 - 3358 - retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3359 - if (retval != STATUS_SUCCESS) { 3360 - sd_set_err_code(chip, SD_IO_ERR); 3361 - goto RW_FAIL; 3362 - } 3363 - 3364 - if (sd_card->pre_sec_cnt < 0x80 && 3365 - !CHK_SD30_SPEED(sd_card) && 3366 - !CHK_SD_HS(sd_card) && 3367 - !CHK_MMC_HS(sd_card)) { 3368 - sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3369 - SD_RSP_TYPE_R1, NULL, 0); 3370 - } 3371 - } 3372 - 3373 - rtsx_init_cmd(chip); 3374 - 3375 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); 3376 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); 3377 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 3378 - (u8)sector_cnt); 3379 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 3380 - (u8)(sector_cnt >> 8)); 3381 - 3382 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 3383 - 3384 - if (CHK_MMC_8BIT(sd_card)) 3385 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3386 - 0x03, SD_BUS_WIDTH_8); 3387 - else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) 3388 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3389 - 0x03, SD_BUS_WIDTH_4); 3390 - else 3391 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3392 - 0x03, SD_BUS_WIDTH_1); 3393 - 3394 - if (sd_card->seq_mode) { 3395 - cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 3396 - SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | 3397 - SD_RSP_LEN_0; 3398 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); 3399 - 3400 - trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, 3401 - DMA_512); 3402 - 3403 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3404 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3405 - SD_TM_AUTO_READ_3 | SD_TRANSFER_START); 3406 - } else { 3407 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3408 - SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 3409 - } 3410 - 3411 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3412 - SD_TRANSFER_END, SD_TRANSFER_END); 3413 - 3414 - rtsx_send_cmd_no_wait(chip); 3415 - } else { 3416 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3417 - dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", 3418 - READ_MULTIPLE_BLOCK); 3419 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 3420 - 0x40 | READ_MULTIPLE_BLOCK); 3421 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 3422 - (u8)(data_addr >> 24)); 3423 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 3424 - (u8)(data_addr >> 16)); 3425 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 3426 - (u8)(data_addr >> 8)); 3427 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 3428 - (u8)data_addr); 3429 - 3430 - cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 3431 - SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | 3432 - SD_RSP_LEN_6; 3433 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3434 - cfg2); 3435 - 3436 - trans_dma_enable(srb->sc_data_direction, chip, 3437 - sector_cnt * 512, DMA_512); 3438 - 3439 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3440 - SD_TM_AUTO_READ_2 | SD_TRANSFER_START); 3441 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3442 - SD_TRANSFER_END, SD_TRANSFER_END); 3443 - 3444 - rtsx_send_cmd_no_wait(chip); 3445 - } else { 3446 - retval = rtsx_send_cmd(chip, SD_CARD, 50); 3447 - if (retval < 0) { 3448 - rtsx_clear_sd_error(chip); 3449 - 3450 - chip->rw_need_retry = 1; 3451 - sd_set_err_code(chip, SD_TO_ERR); 3452 - goto RW_FAIL; 3453 - } 3454 - 3455 - retval = wait_data_buf_ready(chip); 3456 - if (retval != STATUS_SUCCESS) { 3457 - chip->rw_need_retry = 1; 3458 - sd_set_err_code(chip, SD_TO_ERR); 3459 - goto RW_FAIL; 3460 - } 3461 - 3462 - retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK, 3463 - data_addr, SD_RSP_TYPE_R1, 3464 - NULL, 0); 3465 - if (retval != STATUS_SUCCESS) { 3466 - chip->rw_need_retry = 1; 3467 - goto RW_FAIL; 3468 - } 3469 - 3470 - rtsx_init_cmd(chip); 3471 - 3472 - cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 3473 - SD_NO_WAIT_BUSY_END | 3474 - SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 3475 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3476 - cfg2); 3477 - 3478 - trans_dma_enable(srb->sc_data_direction, chip, 3479 - sector_cnt * 512, DMA_512); 3480 - 3481 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3482 - SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 3483 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3484 - SD_TRANSFER_END, SD_TRANSFER_END); 3485 - 3486 - rtsx_send_cmd_no_wait(chip); 3487 - } 3488 - 3489 - sd_card->seq_mode = 1; 3490 - } 3491 - 3492 - retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 3493 - scsi_bufflen(srb), scsi_sg_count(srb), 3494 - srb->sc_data_direction, chip->sd_timeout); 3495 - if (retval < 0) { 3496 - u8 stat = 0; 3497 - int err; 3498 - 3499 - sd_card->seq_mode = 0; 3500 - 3501 - if (retval == -ETIMEDOUT) 3502 - err = STATUS_TIMEDOUT; 3503 - else 3504 - err = STATUS_FAIL; 3505 - 3506 - rtsx_read_register(chip, REG_SD_STAT1, &stat); 3507 - rtsx_clear_sd_error(chip); 3508 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3509 - chip->rw_need_retry = 0; 3510 - dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", 3511 - __func__); 3512 - return STATUS_FAIL; 3513 - } 3514 - 3515 - chip->rw_need_retry = 1; 3516 - 3517 - retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 3518 - SD_RSP_TYPE_R1b, NULL, 0); 3519 - if (retval != STATUS_SUCCESS) { 3520 - sd_set_err_code(chip, SD_STS_ERR); 3521 - goto RW_FAIL; 3522 - } 3523 - 3524 - if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) { 3525 - dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n"); 3526 - sd_set_err_code(chip, SD_CRC_ERR); 3527 - goto RW_FAIL; 3528 - } 3529 - 3530 - if (err == STATUS_TIMEDOUT) { 3531 - sd_set_err_code(chip, SD_TO_ERR); 3532 - goto RW_FAIL; 3533 - } 3534 - 3535 - return err; 3536 - } 3537 - 3538 - sd_card->pre_sec_addr = start_sector; 3539 - sd_card->pre_sec_cnt = sector_cnt; 3540 - sd_card->pre_dir = srb->sc_data_direction; 3541 - 3542 - return STATUS_SUCCESS; 3543 - 3544 - RW_FAIL: 3545 - sd_card->seq_mode = 0; 3546 - 3547 - if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3548 - chip->rw_need_retry = 0; 3549 - dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", __func__); 3550 - return STATUS_FAIL; 3551 - } 3552 - 3553 - if (sd_check_err_code(chip, SD_CRC_ERR)) { 3554 - if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) { 3555 - sd_card->mmc_dont_switch_bus = 1; 3556 - reset_mmc_only(chip); 3557 - sd_card->mmc_dont_switch_bus = 0; 3558 - } else { 3559 - sd_card->need_retune = 1; 3560 - sd_auto_tune_clock(chip); 3561 - } 3562 - } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) { 3563 - retval = reset_sd_card(chip); 3564 - if (retval != STATUS_SUCCESS) { 3565 - chip->card_ready &= ~SD_CARD; 3566 - chip->card_fail |= SD_CARD; 3567 - chip->capacity[chip->card2lun[SD_CARD]] = 0; 3568 - } 3569 - } 3570 - 3571 - return STATUS_FAIL; 3572 - } 3573 - 3574 - #ifdef SUPPORT_CPRM 3575 - int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg, 3576 - u8 rsp_type, u8 *rsp, int rsp_len, 3577 - bool special_check) 3578 - { 3579 - int retval; 3580 - int timeout = 100; 3581 - u16 reg_addr; 3582 - u8 *ptr; 3583 - int stat_idx = 0; 3584 - int rty_cnt = 0; 3585 - 3586 - dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx); 3587 - 3588 - if (rsp_type == SD_RSP_TYPE_R1b) 3589 - timeout = 3000; 3590 - 3591 - RTY_SEND_CMD: 3592 - 3593 - rtsx_init_cmd(chip); 3594 - 3595 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); 3596 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); 3597 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); 3598 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); 3599 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); 3600 - 3601 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 3602 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3603 - 0x01, PINGPONG_BUFFER); 3604 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 3605 - 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 3606 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 3607 - SD_TRANSFER_END); 3608 - 3609 - if (rsp_type == SD_RSP_TYPE_R2) { 3610 - for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 3611 - reg_addr++) 3612 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 3613 - 3614 - stat_idx = 17; 3615 - } else if (rsp_type != SD_RSP_TYPE_R0) { 3616 - for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 3617 - reg_addr++) 3618 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 3619 - 3620 - stat_idx = 6; 3621 - } 3622 - rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0); 3623 - 3624 - rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); 3625 - 3626 - retval = rtsx_send_cmd(chip, SD_CARD, timeout); 3627 - if (retval < 0) { 3628 - if (retval == -ETIMEDOUT) { 3629 - rtsx_clear_sd_error(chip); 3630 - 3631 - if (rsp_type & SD_WAIT_BUSY_END) { 3632 - retval = sd_check_data0_status(chip); 3633 - if (retval != STATUS_SUCCESS) 3634 - return retval; 3635 - } else { 3636 - sd_set_err_code(chip, SD_TO_ERR); 3637 - } 3638 - } 3639 - return STATUS_FAIL; 3640 - } 3641 - 3642 - if (rsp_type == SD_RSP_TYPE_R0) 3643 - return STATUS_SUCCESS; 3644 - 3645 - ptr = rtsx_get_cmd_data(chip) + 1; 3646 - 3647 - if ((ptr[0] & 0xC0) != 0) { 3648 - sd_set_err_code(chip, SD_STS_ERR); 3649 - return STATUS_FAIL; 3650 - } 3651 - 3652 - if (!(rsp_type & SD_NO_CHECK_CRC7)) { 3653 - if (ptr[stat_idx] & SD_CRC7_ERR) { 3654 - if (cmd_idx == WRITE_MULTIPLE_BLOCK) { 3655 - sd_set_err_code(chip, SD_CRC_ERR); 3656 - return STATUS_FAIL; 3657 - } 3658 - if (rty_cnt < SD_MAX_RETRY_COUNT) { 3659 - wait_timeout(20); 3660 - rty_cnt++; 3661 - goto RTY_SEND_CMD; 3662 - } else { 3663 - sd_set_err_code(chip, SD_CRC_ERR); 3664 - return STATUS_FAIL; 3665 - } 3666 - } 3667 - } 3668 - 3669 - if (cmd_idx == SELECT_CARD || cmd_idx == APP_CMD || 3670 - cmd_idx == SEND_STATUS || cmd_idx == STOP_TRANSMISSION) { 3671 - if (cmd_idx != STOP_TRANSMISSION && !special_check) { 3672 - if (ptr[1] & 0x80) 3673 - return STATUS_FAIL; 3674 - } 3675 - #ifdef SUPPORT_SD_LOCK 3676 - if (ptr[1] & 0x7D) { 3677 - #else 3678 - if (ptr[1] & 0x7F) { 3679 - #endif 3680 - return STATUS_FAIL; 3681 - } 3682 - if (ptr[2] & 0xF8) 3683 - return STATUS_FAIL; 3684 - 3685 - if (cmd_idx == SELECT_CARD) { 3686 - if (rsp_type == SD_RSP_TYPE_R2) { 3687 - if ((ptr[3] & 0x1E) != 0x04) 3688 - return STATUS_FAIL; 3689 - } 3690 - } 3691 - } 3692 - 3693 - if (rsp && rsp_len) 3694 - memcpy(rsp, ptr, rsp_len); 3695 - 3696 - return STATUS_SUCCESS; 3697 - } 3698 - 3699 - int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type) 3700 - { 3701 - int retval, rsp_len; 3702 - u16 reg_addr; 3703 - 3704 - if (rsp_type == SD_RSP_TYPE_R0) 3705 - return STATUS_SUCCESS; 3706 - 3707 - rtsx_init_cmd(chip); 3708 - 3709 - if (rsp_type == SD_RSP_TYPE_R2) { 3710 - for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 3711 - reg_addr++) 3712 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); 3713 - 3714 - rsp_len = 17; 3715 - } else if (rsp_type != SD_RSP_TYPE_R0) { 3716 - for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 3717 - reg_addr++) 3718 - rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); 3719 - 3720 - rsp_len = 6; 3721 - } 3722 - rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0); 3723 - 3724 - retval = rtsx_send_cmd(chip, SD_CARD, 100); 3725 - if (retval != STATUS_SUCCESS) 3726 - return STATUS_FAIL; 3727 - 3728 - if (rsp) { 3729 - int min_len = (rsp_len < len) ? rsp_len : len; 3730 - 3731 - memcpy(rsp, rtsx_get_cmd_data(chip), min_len); 3732 - 3733 - dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len); 3734 - dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n", 3735 - rsp[0], rsp[1], rsp[2], rsp[3]); 3736 - } 3737 - 3738 - return STATUS_SUCCESS; 3739 - } 3740 - 3741 - int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3742 - { 3743 - struct sd_info *sd_card = &chip->sd_card; 3744 - unsigned int lun = SCSI_LUN(srb); 3745 - int len; 3746 - u8 buf[18] = { 3747 - 0x00, 3748 - 0x00, 3749 - 0x00, 3750 - 0x0E, 3751 - 0x00, 3752 - 0x00, 3753 - 0x00, 3754 - 0x00, 3755 - 0x53, 3756 - 0x44, 3757 - 0x20, 3758 - 0x43, 3759 - 0x61, 3760 - 0x72, 3761 - 0x64, 3762 - 0x00, 3763 - 0x00, 3764 - 0x00, 3765 - }; 3766 - 3767 - sd_card->pre_cmd_err = 0; 3768 - 3769 - if (!(CHK_BIT(chip->lun_mc, lun))) { 3770 - SET_BIT(chip->lun_mc, lun); 3771 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 3772 - return TRANSPORT_FAILED; 3773 - } 3774 - 3775 - if (srb->cmnd[2] != 0x53 || srb->cmnd[3] != 0x44 || 3776 - srb->cmnd[4] != 0x20 || srb->cmnd[5] != 0x43 || 3777 - srb->cmnd[6] != 0x61 || srb->cmnd[7] != 0x72 || 3778 - srb->cmnd[8] != 0x64) { 3779 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3780 - return TRANSPORT_FAILED; 3781 - } 3782 - 3783 - switch (srb->cmnd[1] & 0x0F) { 3784 - case 0: 3785 - sd_card->sd_pass_thru_en = 0; 3786 - break; 3787 - 3788 - case 1: 3789 - sd_card->sd_pass_thru_en = 1; 3790 - break; 3791 - 3792 - default: 3793 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3794 - return TRANSPORT_FAILED; 3795 - } 3796 - 3797 - buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02; 3798 - if (chip->card_wp & SD_CARD) 3799 - buf[5] |= 0x80; 3800 - 3801 - buf[6] = (u8)(sd_card->sd_addr >> 16); 3802 - buf[7] = (u8)(sd_card->sd_addr >> 24); 3803 - 3804 - buf[15] = chip->max_lun; 3805 - 3806 - len = min_t(int, 18, scsi_bufflen(srb)); 3807 - rtsx_stor_set_xfer_buf(buf, len, srb); 3808 - 3809 - return TRANSPORT_GOOD; 3810 - } 3811 - 3812 - static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, 3813 - int *rsp_len) 3814 - { 3815 - if (!rsp_type || !rsp_len) 3816 - return STATUS_FAIL; 3817 - 3818 - switch (srb->cmnd[10]) { 3819 - case 0x03: 3820 - *rsp_type = SD_RSP_TYPE_R0; 3821 - *rsp_len = 0; 3822 - break; 3823 - 3824 - case 0x04: 3825 - *rsp_type = SD_RSP_TYPE_R1; 3826 - *rsp_len = 6; 3827 - break; 3828 - 3829 - case 0x05: 3830 - *rsp_type = SD_RSP_TYPE_R1b; 3831 - *rsp_len = 6; 3832 - break; 3833 - 3834 - case 0x06: 3835 - *rsp_type = SD_RSP_TYPE_R2; 3836 - *rsp_len = 17; 3837 - break; 3838 - 3839 - case 0x07: 3840 - *rsp_type = SD_RSP_TYPE_R3; 3841 - *rsp_len = 6; 3842 - break; 3843 - 3844 - default: 3845 - return STATUS_FAIL; 3846 - } 3847 - 3848 - return STATUS_SUCCESS; 3849 - } 3850 - 3851 - int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3852 - { 3853 - struct sd_info *sd_card = &chip->sd_card; 3854 - unsigned int lun = SCSI_LUN(srb); 3855 - int retval, rsp_len; 3856 - u8 cmd_idx, rsp_type; 3857 - bool standby = false, acmd = false; 3858 - u32 arg; 3859 - 3860 - if (!sd_card->sd_pass_thru_en) { 3861 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3862 - return TRANSPORT_FAILED; 3863 - } 3864 - 3865 - retval = sd_switch_clock(chip); 3866 - if (retval != STATUS_SUCCESS) 3867 - return TRANSPORT_FAILED; 3868 - 3869 - if (sd_card->pre_cmd_err) { 3870 - sd_card->pre_cmd_err = 0; 3871 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 3872 - return TRANSPORT_FAILED; 3873 - } 3874 - 3875 - cmd_idx = srb->cmnd[2] & 0x3F; 3876 - if (srb->cmnd[1] & 0x02) 3877 - standby = true; 3878 - 3879 - if (srb->cmnd[1] & 0x01) 3880 - acmd = true; 3881 - 3882 - arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | 3883 - ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; 3884 - 3885 - retval = get_rsp_type(srb, &rsp_type, &rsp_len); 3886 - if (retval != STATUS_SUCCESS) { 3887 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3888 - return TRANSPORT_FAILED; 3889 - } 3890 - sd_card->last_rsp_type = rsp_type; 3891 - 3892 - retval = sd_switch_clock(chip); 3893 - if (retval != STATUS_SUCCESS) 3894 - return TRANSPORT_FAILED; 3895 - 3896 - #ifdef SUPPORT_SD_LOCK 3897 - if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 3898 - if (CHK_MMC_8BIT(sd_card)) { 3899 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 3900 - SD_BUS_WIDTH_8); 3901 - if (retval != STATUS_SUCCESS) 3902 - return TRANSPORT_FAILED; 3903 - 3904 - } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { 3905 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 3906 - SD_BUS_WIDTH_4); 3907 - if (retval != STATUS_SUCCESS) 3908 - return TRANSPORT_FAILED; 3909 - } 3910 - } 3911 - #else 3912 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); 3913 - if (retval != STATUS_SUCCESS) 3914 - return TRANSPORT_FAILED; 3915 - #endif 3916 - 3917 - if (standby) { 3918 - retval = sd_select_card(chip, 0); 3919 - if (retval != STATUS_SUCCESS) 3920 - goto sd_execute_cmd_failed; 3921 - } 3922 - 3923 - if (acmd) { 3924 - retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 3925 - sd_card->sd_addr, 3926 - SD_RSP_TYPE_R1, NULL, 0, 3927 - false); 3928 - if (retval != STATUS_SUCCESS) 3929 - goto sd_execute_cmd_failed; 3930 - } 3931 - 3932 - retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, 3933 - sd_card->rsp, rsp_len, false); 3934 - if (retval != STATUS_SUCCESS) 3935 - goto sd_execute_cmd_failed; 3936 - 3937 - if (standby) { 3938 - retval = sd_select_card(chip, 1); 3939 - if (retval != STATUS_SUCCESS) 3940 - goto sd_execute_cmd_failed; 3941 - } 3942 - 3943 - #ifdef SUPPORT_SD_LOCK 3944 - retval = sd_update_lock_status(chip); 3945 - if (retval != STATUS_SUCCESS) 3946 - goto sd_execute_cmd_failed; 3947 - #endif 3948 - 3949 - scsi_set_resid(srb, 0); 3950 - return TRANSPORT_GOOD; 3951 - 3952 - sd_execute_cmd_failed: 3953 - sd_card->pre_cmd_err = 1; 3954 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 3955 - release_sd_card(chip); 3956 - do_reset_sd_card(chip); 3957 - if (!(chip->card_ready & SD_CARD)) 3958 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3959 - 3960 - return TRANSPORT_FAILED; 3961 - } 3962 - 3963 - int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3964 - { 3965 - struct sd_info *sd_card = &chip->sd_card; 3966 - unsigned int lun = SCSI_LUN(srb); 3967 - int retval, rsp_len, i; 3968 - bool read_err = false, cmd13_checkbit = false; 3969 - u8 cmd_idx, rsp_type, bus_width; 3970 - bool standby = false, send_cmd12 = false, acmd = false; 3971 - u32 data_len; 3972 - 3973 - if (!sd_card->sd_pass_thru_en) { 3974 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3975 - return TRANSPORT_FAILED; 3976 - } 3977 - 3978 - if (sd_card->pre_cmd_err) { 3979 - sd_card->pre_cmd_err = 0; 3980 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 3981 - return TRANSPORT_FAILED; 3982 - } 3983 - 3984 - retval = sd_switch_clock(chip); 3985 - if (retval != STATUS_SUCCESS) 3986 - return TRANSPORT_FAILED; 3987 - 3988 - cmd_idx = srb->cmnd[2] & 0x3F; 3989 - if (srb->cmnd[1] & 0x04) 3990 - send_cmd12 = true; 3991 - 3992 - if (srb->cmnd[1] & 0x02) 3993 - standby = true; 3994 - 3995 - if (srb->cmnd[1] & 0x01) 3996 - acmd = true; 3997 - 3998 - data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] 3999 - << 8) | srb->cmnd[9]; 4000 - 4001 - retval = get_rsp_type(srb, &rsp_type, &rsp_len); 4002 - if (retval != STATUS_SUCCESS) { 4003 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4004 - return TRANSPORT_FAILED; 4005 - } 4006 - sd_card->last_rsp_type = rsp_type; 4007 - 4008 - retval = sd_switch_clock(chip); 4009 - if (retval != STATUS_SUCCESS) 4010 - return TRANSPORT_FAILED; 4011 - 4012 - #ifdef SUPPORT_SD_LOCK 4013 - if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 4014 - if (CHK_MMC_8BIT(sd_card)) 4015 - bus_width = SD_BUS_WIDTH_8; 4016 - else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) 4017 - bus_width = SD_BUS_WIDTH_4; 4018 - else 4019 - bus_width = SD_BUS_WIDTH_1; 4020 - } else { 4021 - bus_width = SD_BUS_WIDTH_4; 4022 - } 4023 - dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width); 4024 - #else 4025 - bus_width = SD_BUS_WIDTH_4; 4026 - #endif 4027 - 4028 - if (data_len < 512) { 4029 - retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, 4030 - SD_RSP_TYPE_R1, NULL, 0, 4031 - false); 4032 - if (retval != STATUS_SUCCESS) 4033 - goto sd_execute_read_cmd_failed; 4034 - } 4035 - 4036 - if (standby) { 4037 - retval = sd_select_card(chip, 0); 4038 - if (retval != STATUS_SUCCESS) 4039 - goto sd_execute_read_cmd_failed; 4040 - } 4041 - 4042 - if (acmd) { 4043 - retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 4044 - sd_card->sd_addr, 4045 - SD_RSP_TYPE_R1, NULL, 0, 4046 - false); 4047 - if (retval != STATUS_SUCCESS) 4048 - goto sd_execute_read_cmd_failed; 4049 - } 4050 - 4051 - if (data_len <= 512) { 4052 - int min_len; 4053 - u8 *buf; 4054 - u16 byte_cnt, blk_cnt; 4055 - u8 cmd[5]; 4056 - 4057 - byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9]; 4058 - blk_cnt = 1; 4059 - 4060 - cmd[0] = 0x40 | cmd_idx; 4061 - cmd[1] = srb->cmnd[3]; 4062 - cmd[2] = srb->cmnd[4]; 4063 - cmd[3] = srb->cmnd[5]; 4064 - cmd[4] = srb->cmnd[6]; 4065 - 4066 - buf = kmalloc(data_len, GFP_KERNEL); 4067 - if (!buf) 4068 - return TRANSPORT_ERROR; 4069 - 4070 - retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt, 4071 - blk_cnt, bus_width, buf, data_len, 2000); 4072 - if (retval != STATUS_SUCCESS) { 4073 - read_err = true; 4074 - kfree(buf); 4075 - rtsx_clear_sd_error(chip); 4076 - goto sd_execute_read_cmd_failed; 4077 - } 4078 - 4079 - min_len = min(data_len, scsi_bufflen(srb)); 4080 - rtsx_stor_set_xfer_buf(buf, min_len, srb); 4081 - 4082 - kfree(buf); 4083 - } else if (!(data_len & 0x1FF)) { 4084 - rtsx_init_cmd(chip); 4085 - 4086 - trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512); 4087 - 4088 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4089 - 0x02); 4090 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4091 - 0x00); 4092 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 4093 - 0xFF, (srb->cmnd[7] & 0xFE) >> 1); 4094 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 4095 - 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); 4096 - 4097 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 4098 - 0x40 | cmd_idx); 4099 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 4100 - srb->cmnd[3]); 4101 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 4102 - srb->cmnd[4]); 4103 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 4104 - srb->cmnd[5]); 4105 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 4106 - srb->cmnd[6]); 4107 - 4108 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 4109 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 4110 - 4111 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 4112 - 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START); 4113 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4114 - SD_TRANSFER_END, SD_TRANSFER_END); 4115 - 4116 - rtsx_send_cmd_no_wait(chip); 4117 - 4118 - retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 4119 - scsi_bufflen(srb), 4120 - scsi_sg_count(srb), 4121 - DMA_FROM_DEVICE, 10000); 4122 - if (retval < 0) { 4123 - read_err = true; 4124 - rtsx_clear_sd_error(chip); 4125 - goto sd_execute_read_cmd_failed; 4126 - } 4127 - 4128 - } else { 4129 - goto sd_execute_read_cmd_failed; 4130 - } 4131 - 4132 - retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type); 4133 - if (retval != STATUS_SUCCESS) 4134 - goto sd_execute_read_cmd_failed; 4135 - 4136 - if (standby) { 4137 - retval = sd_select_card(chip, 1); 4138 - if (retval != STATUS_SUCCESS) 4139 - goto sd_execute_read_cmd_failed; 4140 - } 4141 - 4142 - if (send_cmd12) { 4143 - retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 4144 - SD_RSP_TYPE_R1b, NULL, 0, 4145 - false); 4146 - if (retval != STATUS_SUCCESS) 4147 - goto sd_execute_read_cmd_failed; 4148 - } 4149 - 4150 - if (data_len < 512) { 4151 - retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, 4152 - SD_RSP_TYPE_R1, NULL, 0, 4153 - false); 4154 - if (retval != STATUS_SUCCESS) 4155 - goto sd_execute_read_cmd_failed; 4156 - 4157 - retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); 4158 - if (retval != STATUS_SUCCESS) 4159 - goto sd_execute_read_cmd_failed; 4160 - 4161 - retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); 4162 - if (retval != STATUS_SUCCESS) 4163 - goto sd_execute_read_cmd_failed; 4164 - } 4165 - 4166 - if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) 4167 - cmd13_checkbit = true; 4168 - 4169 - for (i = 0; i < 3; i++) { 4170 - retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, 4171 - sd_card->sd_addr, 4172 - SD_RSP_TYPE_R1, NULL, 0, 4173 - cmd13_checkbit); 4174 - if (retval == STATUS_SUCCESS) 4175 - break; 4176 - } 4177 - if (retval != STATUS_SUCCESS) 4178 - goto sd_execute_read_cmd_failed; 4179 - 4180 - scsi_set_resid(srb, 0); 4181 - return TRANSPORT_GOOD; 4182 - 4183 - sd_execute_read_cmd_failed: 4184 - sd_card->pre_cmd_err = 1; 4185 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 4186 - if (read_err) 4187 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4188 - 4189 - release_sd_card(chip); 4190 - do_reset_sd_card(chip); 4191 - if (!(chip->card_ready & SD_CARD)) 4192 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4193 - 4194 - return TRANSPORT_FAILED; 4195 - } 4196 - 4197 - int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4198 - { 4199 - struct sd_info *sd_card = &chip->sd_card; 4200 - unsigned int lun = SCSI_LUN(srb); 4201 - int retval, rsp_len, i; 4202 - bool write_err = false, cmd13_checkbit = false; 4203 - u8 cmd_idx, rsp_type; 4204 - bool standby = false, send_cmd12 = false, acmd = false; 4205 - u32 data_len, arg; 4206 - #ifdef SUPPORT_SD_LOCK 4207 - int lock_cmd_fail = 0; 4208 - u8 sd_lock_state = 0; 4209 - u8 lock_cmd_type = 0; 4210 - #endif 4211 - 4212 - if (!sd_card->sd_pass_thru_en) { 4213 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4214 - return TRANSPORT_FAILED; 4215 - } 4216 - 4217 - if (sd_card->pre_cmd_err) { 4218 - sd_card->pre_cmd_err = 0; 4219 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4220 - return TRANSPORT_FAILED; 4221 - } 4222 - 4223 - retval = sd_switch_clock(chip); 4224 - if (retval != STATUS_SUCCESS) 4225 - return TRANSPORT_FAILED; 4226 - 4227 - cmd_idx = srb->cmnd[2] & 0x3F; 4228 - if (srb->cmnd[1] & 0x04) 4229 - send_cmd12 = true; 4230 - 4231 - if (srb->cmnd[1] & 0x02) 4232 - standby = true; 4233 - 4234 - if (srb->cmnd[1] & 0x01) 4235 - acmd = true; 4236 - 4237 - data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] 4238 - << 8) | srb->cmnd[9]; 4239 - arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | 4240 - ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; 4241 - 4242 - #ifdef SUPPORT_SD_LOCK 4243 - if (cmd_idx == LOCK_UNLOCK) { 4244 - sd_lock_state = sd_card->sd_lock_status; 4245 - sd_lock_state &= SD_LOCKED; 4246 - } 4247 - #endif 4248 - 4249 - retval = get_rsp_type(srb, &rsp_type, &rsp_len); 4250 - if (retval != STATUS_SUCCESS) { 4251 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4252 - return TRANSPORT_FAILED; 4253 - } 4254 - sd_card->last_rsp_type = rsp_type; 4255 - 4256 - retval = sd_switch_clock(chip); 4257 - if (retval != STATUS_SUCCESS) 4258 - return TRANSPORT_FAILED; 4259 - 4260 - #ifdef SUPPORT_SD_LOCK 4261 - if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 4262 - if (CHK_MMC_8BIT(sd_card)) { 4263 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4264 - SD_BUS_WIDTH_8); 4265 - if (retval != STATUS_SUCCESS) 4266 - return TRANSPORT_FAILED; 4267 - 4268 - } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { 4269 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4270 - SD_BUS_WIDTH_4); 4271 - if (retval != STATUS_SUCCESS) 4272 - return TRANSPORT_FAILED; 4273 - } 4274 - } 4275 - #else 4276 - retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); 4277 - if (retval != STATUS_SUCCESS) 4278 - return TRANSPORT_FAILED; 4279 - #endif 4280 - 4281 - if (data_len < 512) { 4282 - retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, 4283 - SD_RSP_TYPE_R1, NULL, 0, 4284 - false); 4285 - if (retval != STATUS_SUCCESS) 4286 - goto sd_execute_write_cmd_failed; 4287 - } 4288 - 4289 - if (standby) { 4290 - retval = sd_select_card(chip, 0); 4291 - if (retval != STATUS_SUCCESS) 4292 - goto sd_execute_write_cmd_failed; 4293 - } 4294 - 4295 - if (acmd) { 4296 - retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 4297 - sd_card->sd_addr, 4298 - SD_RSP_TYPE_R1, NULL, 0, 4299 - false); 4300 - if (retval != STATUS_SUCCESS) 4301 - goto sd_execute_write_cmd_failed; 4302 - } 4303 - 4304 - retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, 4305 - sd_card->rsp, rsp_len, false); 4306 - if (retval != STATUS_SUCCESS) 4307 - goto sd_execute_write_cmd_failed; 4308 - 4309 - if (data_len <= 512) { 4310 - u16 i; 4311 - u8 *buf; 4312 - 4313 - buf = kmalloc(data_len, GFP_KERNEL); 4314 - if (!buf) 4315 - return TRANSPORT_ERROR; 4316 - 4317 - rtsx_stor_get_xfer_buf(buf, data_len, srb); 4318 - 4319 - #ifdef SUPPORT_SD_LOCK 4320 - if (cmd_idx == LOCK_UNLOCK) 4321 - lock_cmd_type = buf[0] & 0x0F; 4322 - #endif 4323 - 4324 - if (data_len > 256) { 4325 - rtsx_init_cmd(chip); 4326 - for (i = 0; i < 256; i++) { 4327 - rtsx_add_cmd(chip, WRITE_REG_CMD, 4328 - PPBUF_BASE2 + i, 0xFF, buf[i]); 4329 - } 4330 - retval = rtsx_send_cmd(chip, 0, 250); 4331 - if (retval != STATUS_SUCCESS) { 4332 - kfree(buf); 4333 - goto sd_execute_write_cmd_failed; 4334 - } 4335 - 4336 - rtsx_init_cmd(chip); 4337 - for (i = 256; i < data_len; i++) { 4338 - rtsx_add_cmd(chip, WRITE_REG_CMD, 4339 - PPBUF_BASE2 + i, 0xFF, buf[i]); 4340 - } 4341 - retval = rtsx_send_cmd(chip, 0, 250); 4342 - if (retval != STATUS_SUCCESS) { 4343 - kfree(buf); 4344 - goto sd_execute_write_cmd_failed; 4345 - } 4346 - } else { 4347 - rtsx_init_cmd(chip); 4348 - for (i = 0; i < data_len; i++) { 4349 - rtsx_add_cmd(chip, WRITE_REG_CMD, 4350 - PPBUF_BASE2 + i, 0xFF, buf[i]); 4351 - } 4352 - retval = rtsx_send_cmd(chip, 0, 250); 4353 - if (retval != STATUS_SUCCESS) { 4354 - kfree(buf); 4355 - goto sd_execute_write_cmd_failed; 4356 - } 4357 - } 4358 - 4359 - kfree(buf); 4360 - 4361 - rtsx_init_cmd(chip); 4362 - 4363 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4364 - srb->cmnd[8] & 0x03); 4365 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4366 - srb->cmnd[9]); 4367 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 4368 - 0x00); 4369 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 4370 - 0x01); 4371 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 4372 - PINGPONG_BUFFER); 4373 - 4374 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 4375 - SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 4376 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4377 - SD_TRANSFER_END, SD_TRANSFER_END); 4378 - 4379 - retval = rtsx_send_cmd(chip, SD_CARD, 250); 4380 - } else if (!(data_len & 0x1FF)) { 4381 - rtsx_init_cmd(chip); 4382 - 4383 - trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512); 4384 - 4385 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4386 - 0x02); 4387 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4388 - 0x00); 4389 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 4390 - 0xFF, (srb->cmnd[7] & 0xFE) >> 1); 4391 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 4392 - 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); 4393 - 4394 - rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 4395 - SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 4396 - rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4397 - SD_TRANSFER_END, SD_TRANSFER_END); 4398 - 4399 - rtsx_send_cmd_no_wait(chip); 4400 - 4401 - retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 4402 - scsi_bufflen(srb), 4403 - scsi_sg_count(srb), 4404 - DMA_TO_DEVICE, 10000); 4405 - 4406 - } else { 4407 - goto sd_execute_write_cmd_failed; 4408 - } 4409 - 4410 - if (retval < 0) { 4411 - write_err = true; 4412 - rtsx_clear_sd_error(chip); 4413 - goto sd_execute_write_cmd_failed; 4414 - } 4415 - 4416 - #ifdef SUPPORT_SD_LOCK 4417 - if (cmd_idx == LOCK_UNLOCK) { 4418 - if (lock_cmd_type == SD_ERASE) { 4419 - sd_card->sd_erase_status = SD_UNDER_ERASING; 4420 - scsi_set_resid(srb, 0); 4421 - return TRANSPORT_GOOD; 4422 - } 4423 - 4424 - rtsx_init_cmd(chip); 4425 - rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02); 4426 - 4427 - retval = rtsx_send_cmd(chip, SD_CARD, 250); 4428 - if (retval < 0) { 4429 - write_err = true; 4430 - rtsx_clear_sd_error(chip); 4431 - goto sd_execute_write_cmd_failed; 4432 - } 4433 - 4434 - retval = sd_update_lock_status(chip); 4435 - if (retval != STATUS_SUCCESS) { 4436 - dev_dbg(rtsx_dev(chip), "Lock command fail!\n"); 4437 - lock_cmd_fail = 1; 4438 - } 4439 - } 4440 - #endif /* SUPPORT_SD_LOCK */ 4441 - 4442 - if (standby) { 4443 - retval = sd_select_card(chip, 1); 4444 - if (retval != STATUS_SUCCESS) 4445 - goto sd_execute_write_cmd_failed; 4446 - } 4447 - 4448 - if (send_cmd12) { 4449 - retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 4450 - SD_RSP_TYPE_R1b, NULL, 0, 4451 - false); 4452 - if (retval != STATUS_SUCCESS) 4453 - goto sd_execute_write_cmd_failed; 4454 - } 4455 - 4456 - if (data_len < 512) { 4457 - retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, 4458 - SD_RSP_TYPE_R1, NULL, 0, 4459 - false); 4460 - if (retval != STATUS_SUCCESS) 4461 - goto sd_execute_write_cmd_failed; 4462 - 4463 - retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); 4464 - if (retval != STATUS_SUCCESS) 4465 - goto sd_execute_write_cmd_failed; 4466 - 4467 - retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); 4468 - if (retval != STATUS_SUCCESS) 4469 - goto sd_execute_write_cmd_failed; 4470 - } 4471 - 4472 - if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) 4473 - cmd13_checkbit = true; 4474 - 4475 - for (i = 0; i < 3; i++) { 4476 - retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, 4477 - sd_card->sd_addr, 4478 - SD_RSP_TYPE_R1, NULL, 0, 4479 - cmd13_checkbit); 4480 - if (retval == STATUS_SUCCESS) 4481 - break; 4482 - } 4483 - if (retval != STATUS_SUCCESS) 4484 - goto sd_execute_write_cmd_failed; 4485 - 4486 - #ifdef SUPPORT_SD_LOCK 4487 - if (cmd_idx == LOCK_UNLOCK) { 4488 - if (!lock_cmd_fail) { 4489 - dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n", 4490 - lock_cmd_type); 4491 - if (lock_cmd_type & SD_CLR_PWD) 4492 - sd_card->sd_lock_status &= ~SD_PWD_EXIST; 4493 - 4494 - if (lock_cmd_type & SD_SET_PWD) 4495 - sd_card->sd_lock_status |= SD_PWD_EXIST; 4496 - } 4497 - 4498 - dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n", 4499 - sd_lock_state, sd_card->sd_lock_status); 4500 - if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) { 4501 - sd_card->sd_lock_notify = 1; 4502 - if (sd_lock_state && 4503 - (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE)) { 4504 - sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST); 4505 - if (CHK_SD(sd_card)) { 4506 - retval = reset_sd(chip); 4507 - if (retval != STATUS_SUCCESS) { 4508 - sd_card->sd_lock_status &= 4509 - ~(SD_UNLOCK_POW_ON | SD_SDR_RST); 4510 - goto sd_execute_write_cmd_failed; 4511 - } 4512 - } 4513 - 4514 - sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); 4515 - } 4516 - } 4517 - } 4518 - 4519 - if (lock_cmd_fail) { 4520 - scsi_set_resid(srb, 0); 4521 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 4522 - return TRANSPORT_FAILED; 4523 - } 4524 - #endif /* SUPPORT_SD_LOCK */ 4525 - 4526 - scsi_set_resid(srb, 0); 4527 - return TRANSPORT_GOOD; 4528 - 4529 - sd_execute_write_cmd_failed: 4530 - sd_card->pre_cmd_err = 1; 4531 - set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 4532 - if (write_err) 4533 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 4534 - 4535 - release_sd_card(chip); 4536 - do_reset_sd_card(chip); 4537 - if (!(chip->card_ready & SD_CARD)) 4538 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4539 - 4540 - return TRANSPORT_FAILED; 4541 - } 4542 - 4543 - int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4544 - { 4545 - struct sd_info *sd_card = &chip->sd_card; 4546 - unsigned int lun = SCSI_LUN(srb); 4547 - int count; 4548 - u16 data_len; 4549 - 4550 - if (!sd_card->sd_pass_thru_en) { 4551 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4552 - return TRANSPORT_FAILED; 4553 - } 4554 - 4555 - if (sd_card->pre_cmd_err) { 4556 - sd_card->pre_cmd_err = 0; 4557 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4558 - return TRANSPORT_FAILED; 4559 - } 4560 - 4561 - data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8]; 4562 - 4563 - if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) { 4564 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4565 - return TRANSPORT_FAILED; 4566 - } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) { 4567 - count = (data_len < 17) ? data_len : 17; 4568 - } else { 4569 - count = (data_len < 6) ? data_len : 6; 4570 - } 4571 - rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb); 4572 - 4573 - dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len); 4574 - dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n", 4575 - sd_card->rsp[0], sd_card->rsp[1], 4576 - sd_card->rsp[2], sd_card->rsp[3]); 4577 - 4578 - scsi_set_resid(srb, 0); 4579 - return TRANSPORT_GOOD; 4580 - } 4581 - 4582 - int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4583 - { 4584 - struct sd_info *sd_card = &chip->sd_card; 4585 - unsigned int lun = SCSI_LUN(srb); 4586 - int retval; 4587 - 4588 - if (!sd_card->sd_pass_thru_en) { 4589 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4590 - return TRANSPORT_FAILED; 4591 - } 4592 - 4593 - if (sd_card->pre_cmd_err) { 4594 - sd_card->pre_cmd_err = 0; 4595 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4596 - return TRANSPORT_FAILED; 4597 - } 4598 - 4599 - if (srb->cmnd[2] != 0x53 || srb->cmnd[3] != 0x44 || 4600 - srb->cmnd[4] != 0x20 || srb->cmnd[5] != 0x43 || 4601 - srb->cmnd[6] != 0x61 || srb->cmnd[7] != 0x72 || 4602 - srb->cmnd[8] != 0x64) { 4603 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4604 - return TRANSPORT_FAILED; 4605 - } 4606 - 4607 - switch (srb->cmnd[1] & 0x0F) { 4608 - case 0: 4609 - #ifdef SUPPORT_SD_LOCK 4610 - if (srb->cmnd[9] == 0x64) 4611 - sd_card->sd_lock_status |= SD_SDR_RST; 4612 - #endif 4613 - retval = reset_sd_card(chip); 4614 - if (retval != STATUS_SUCCESS) { 4615 - #ifdef SUPPORT_SD_LOCK 4616 - sd_card->sd_lock_status &= ~SD_SDR_RST; 4617 - #endif 4618 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4619 - sd_card->pre_cmd_err = 1; 4620 - return TRANSPORT_FAILED; 4621 - } 4622 - #ifdef SUPPORT_SD_LOCK 4623 - sd_card->sd_lock_status &= ~SD_SDR_RST; 4624 - #endif 4625 - break; 4626 - 4627 - case 1: 4628 - retval = reset_sd(chip); 4629 - if (retval != STATUS_SUCCESS) { 4630 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4631 - sd_card->pre_cmd_err = 1; 4632 - return TRANSPORT_FAILED; 4633 - } 4634 - break; 4635 - 4636 - default: 4637 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4638 - return TRANSPORT_FAILED; 4639 - } 4640 - 4641 - scsi_set_resid(srb, 0); 4642 - return TRANSPORT_GOOD; 4643 - } 4644 - #endif 4645 - 4646 - void sd_cleanup_work(struct rtsx_chip *chip) 4647 - { 4648 - struct sd_info *sd_card = &chip->sd_card; 4649 - 4650 - if (sd_card->seq_mode) { 4651 - dev_dbg(rtsx_dev(chip), "SD: stop transmission\n"); 4652 - sd_stop_seq_mode(chip); 4653 - sd_card->cleanup_counter = 0; 4654 - } 4655 - } 4656 - 4657 - int sd_power_off_card3v3(struct rtsx_chip *chip) 4658 - { 4659 - int retval; 4660 - 4661 - retval = disable_card_clock(chip, SD_CARD); 4662 - if (retval != STATUS_SUCCESS) 4663 - return STATUS_FAIL; 4664 - 4665 - retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 4666 - if (retval) 4667 - return retval; 4668 - 4669 - if (!chip->ft2_fast_mode) { 4670 - retval = card_power_off(chip, SD_CARD); 4671 - if (retval != STATUS_SUCCESS) 4672 - return STATUS_FAIL; 4673 - 4674 - mdelay(50); 4675 - } 4676 - 4677 - if (chip->asic_code) { 4678 - retval = sd_pull_ctl_disable(chip); 4679 - if (retval != STATUS_SUCCESS) 4680 - return STATUS_FAIL; 4681 - } else { 4682 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4683 - FPGA_SD_PULL_CTL_BIT | 0x20, 4684 - FPGA_SD_PULL_CTL_BIT); 4685 - if (retval) 4686 - return retval; 4687 - } 4688 - 4689 - return STATUS_SUCCESS; 4690 - } 4691 - 4692 - int release_sd_card(struct rtsx_chip *chip) 4693 - { 4694 - struct sd_info *sd_card = &chip->sd_card; 4695 - int retval; 4696 - 4697 - chip->card_ready &= ~SD_CARD; 4698 - chip->card_fail &= ~SD_CARD; 4699 - chip->card_wp &= ~SD_CARD; 4700 - 4701 - chip->sd_io = 0; 4702 - chip->sd_int = 0; 4703 - 4704 - #ifdef SUPPORT_SD_LOCK 4705 - sd_card->sd_lock_status = 0; 4706 - sd_card->sd_erase_status = 0; 4707 - #endif 4708 - 4709 - memset(sd_card->raw_csd, 0, 16); 4710 - memset(sd_card->raw_scr, 0, 8); 4711 - 4712 - retval = sd_power_off_card3v3(chip); 4713 - if (retval != STATUS_SUCCESS) 4714 - return STATUS_FAIL; 4715 - 4716 - return STATUS_SUCCESS; 4717 - }
-289
drivers/staging/rts5208/sd.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_SD_H 13 - #define __REALTEK_RTSX_SD_H 14 - 15 - #include "rtsx_chip.h" 16 - 17 - #define SUPPORT_VOLTAGE 0x003C0000 18 - 19 - /* Error Code */ 20 - #define SD_NO_ERROR 0x0 21 - #define SD_CRC_ERR 0x80 22 - #define SD_TO_ERR 0x40 23 - #define SD_NO_CARD 0x20 24 - #define SD_BUSY 0x10 25 - #define SD_STS_ERR 0x08 26 - #define SD_RSP_TIMEOUT 0x04 27 - #define SD_IO_ERR 0x02 28 - 29 - /* Return code for MMC switch bus */ 30 - #define SWITCH_SUCCESS 0 31 - #define SWITCH_ERR 1 32 - #define SWITCH_FAIL 2 33 - 34 - /* MMC/SD Command Index */ 35 - /* Basic command (class 0) */ 36 - #define GO_IDLE_STATE 0 37 - #define SEND_OP_COND 1 38 - #define ALL_SEND_CID 2 39 - #define SET_RELATIVE_ADDR 3 40 - #define SEND_RELATIVE_ADDR 3 41 - #define SET_DSR 4 42 - #define IO_SEND_OP_COND 5 43 - #define SWITCH 6 44 - #define SELECT_CARD 7 45 - #define DESELECT_CARD 7 46 - /* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec 47 - * while is "SEND_IF_COND" for SD 2.0 48 - */ 49 - #define SEND_EXT_CSD 8 50 - #define SEND_IF_COND 8 51 - 52 - #define SEND_CSD 9 53 - #define SEND_CID 10 54 - #define VOLTAGE_SWITCH 11 55 - #define READ_DAT_UTIL_STOP 11 56 - #define STOP_TRANSMISSION 12 57 - #define SEND_STATUS 13 58 - #define GO_INACTIVE_STATE 15 59 - 60 - #define SET_BLOCKLEN 16 61 - #define READ_SINGLE_BLOCK 17 62 - #define READ_MULTIPLE_BLOCK 18 63 - #define SEND_TUNING_PATTERN 19 64 - 65 - #define BUSTEST_R 14 66 - #define BUSTEST_W 19 67 - 68 - #define WRITE_BLOCK 24 69 - #define WRITE_MULTIPLE_BLOCK 25 70 - #define PROGRAM_CSD 27 71 - 72 - #define ERASE_WR_BLK_START 32 73 - #define ERASE_WR_BLK_END 33 74 - #define ERASE_CMD 38 75 - 76 - #define LOCK_UNLOCK 42 77 - #define IO_RW_DIRECT 52 78 - 79 - #define APP_CMD 55 80 - #define GEN_CMD 56 81 - 82 - #define SET_BUS_WIDTH 6 83 - #define SD_STATUS 13 84 - #define SEND_NUM_WR_BLOCKS 22 85 - #define SET_WR_BLK_ERASE_COUNT 23 86 - #define SD_APP_OP_COND 41 87 - #define SET_CLR_CARD_DETECT 42 88 - #define SEND_SCR 51 89 - 90 - #define SD_READ_COMPLETE 0x00 91 - #define SD_READ_TO 0x01 92 - #define SD_READ_ADVENCE 0x02 93 - 94 - #define SD_CHECK_MODE 0x00 95 - #define SD_SWITCH_MODE 0x80 96 - #define SD_FUNC_GROUP_1 0x01 97 - #define SD_FUNC_GROUP_2 0x02 98 - #define SD_FUNC_GROUP_3 0x03 99 - #define SD_FUNC_GROUP_4 0x04 100 - #define SD_CHECK_SPEC_V1_1 0xFF 101 - 102 - #define NO_ARGUMENT 0x00 103 - #define CHECK_PATTERN 0x000000AA 104 - #define VOLTAGE_SUPPLY_RANGE 0x00000100 105 - #define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000 106 - #define SUPPORT_MAX_POWER_PERMANCE 0x10000000 107 - #define SUPPORT_1V8 0x01000000 108 - 109 - #define SWITCH_NO_ERR 0x00 110 - #define CARD_NOT_EXIST 0x01 111 - #define SPEC_NOT_SUPPORT 0x02 112 - #define CHECK_MODE_ERR 0x03 113 - #define CHECK_NOT_READY 0x04 114 - #define SWITCH_CRC_ERR 0x05 115 - #define SWITCH_MODE_ERR 0x06 116 - #define SWITCH_PASS 0x07 117 - 118 - #ifdef SUPPORT_SD_LOCK 119 - #define SD_ERASE 0x08 120 - #define SD_LOCK 0x04 121 - #define SD_UNLOCK 0x00 122 - #define SD_CLR_PWD 0x02 123 - #define SD_SET_PWD 0x01 124 - 125 - #define SD_PWD_LEN 0x10 126 - 127 - #define SD_LOCKED 0x80 128 - #define SD_LOCK_1BIT_MODE 0x40 129 - #define SD_PWD_EXIST 0x20 130 - #define SD_UNLOCK_POW_ON 0x01 131 - #define SD_SDR_RST 0x02 132 - 133 - #define SD_NOT_ERASE 0x00 134 - #define SD_UNDER_ERASING 0x01 135 - #define SD_COMPLETE_ERASE 0x02 136 - 137 - #define SD_RW_FORBIDDEN 0x0F 138 - 139 - #endif 140 - 141 - #define HS_SUPPORT 0x01 142 - #define SDR50_SUPPORT 0x02 143 - #define SDR104_SUPPORT 0x03 144 - #define DDR50_SUPPORT 0x04 145 - 146 - #define HS_SUPPORT_MASK 0x02 147 - #define SDR50_SUPPORT_MASK 0x04 148 - #define SDR104_SUPPORT_MASK 0x08 149 - #define DDR50_SUPPORT_MASK 0x10 150 - 151 - #define HS_QUERY_SWITCH_OK 0x01 152 - #define SDR50_QUERY_SWITCH_OK 0x02 153 - #define SDR104_QUERY_SWITCH_OK 0x03 154 - #define DDR50_QUERY_SWITCH_OK 0x04 155 - 156 - #define HS_SWITCH_BUSY 0x02 157 - #define SDR50_SWITCH_BUSY 0x04 158 - #define SDR104_SWITCH_BUSY 0x08 159 - #define DDR50_SWITCH_BUSY 0x10 160 - 161 - #define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D 162 - #define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10 163 - #define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D 164 - 165 - #define DRIVING_TYPE_A 0x01 166 - #define DRIVING_TYPE_B 0x00 167 - #define DRIVING_TYPE_C 0x02 168 - #define DRIVING_TYPE_D 0x03 169 - 170 - #define DRIVING_TYPE_A_MASK 0x02 171 - #define DRIVING_TYPE_B_MASK 0x01 172 - #define DRIVING_TYPE_C_MASK 0x04 173 - #define DRIVING_TYPE_D_MASK 0x08 174 - 175 - #define TYPE_A_QUERY_SWITCH_OK 0x01 176 - #define TYPE_B_QUERY_SWITCH_OK 0x00 177 - #define TYPE_C_QUERY_SWITCH_OK 0x02 178 - #define TYPE_D_QUERY_SWITCH_OK 0x03 179 - 180 - #define TYPE_A_SWITCH_BUSY 0x02 181 - #define TYPE_B_SWITCH_BUSY 0x01 182 - #define TYPE_C_SWITCH_BUSY 0x04 183 - #define TYPE_D_SWITCH_BUSY 0x08 184 - 185 - #define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09 186 - #define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F 187 - #define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19 188 - 189 - #define CURRENT_LIMIT_200 0x00 190 - #define CURRENT_LIMIT_400 0x01 191 - #define CURRENT_LIMIT_600 0x02 192 - #define CURRENT_LIMIT_800 0x03 193 - 194 - #define CURRENT_LIMIT_200_MASK 0x01 195 - #define CURRENT_LIMIT_400_MASK 0x02 196 - #define CURRENT_LIMIT_600_MASK 0x04 197 - #define CURRENT_LIMIT_800_MASK 0x08 198 - 199 - #define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00 200 - #define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01 201 - #define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02 202 - #define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03 203 - 204 - #define CURRENT_LIMIT_200_SWITCH_BUSY 0x01 205 - #define CURRENT_LIMIT_400_SWITCH_BUSY 0x02 206 - #define CURRENT_LIMIT_600_SWITCH_BUSY 0x04 207 - #define CURRENT_LIMIT_800_SWITCH_BUSY 0x08 208 - 209 - #define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07 210 - #define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F 211 - #define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17 212 - 213 - #define DATA_STRUCTURE_VER_OFFSET 0x11 214 - 215 - #define MAX_PHASE 31 216 - 217 - #define MMC_8BIT_BUS 0x0010 218 - #define MMC_4BIT_BUS 0x0020 219 - 220 - #define MMC_SWITCH_ERR 0x80 221 - 222 - #define SD_IO_3V3 0 223 - #define SD_IO_1V8 1 224 - 225 - #define TUNE_TX 0x00 226 - #define TUNE_RX 0x01 227 - 228 - #define CHANGE_TX 0x00 229 - #define CHANGE_RX 0x01 230 - 231 - #define DCM_HIGH_FREQUENCY_MODE 0x00 232 - #define DCM_LOW_FREQUENCY_MODE 0x01 233 - 234 - #define DCM_HIGH_FREQUENCY_MODE_SET 0x0C 235 - #define DCM_LOW_FREQUENCY_MODE_SET 0x00 236 - 237 - #define MULTIPLY_BY_1 0x00 238 - #define MULTIPLY_BY_2 0x01 239 - #define MULTIPLY_BY_3 0x02 240 - #define MULTIPLY_BY_4 0x03 241 - #define MULTIPLY_BY_5 0x04 242 - #define MULTIPLY_BY_6 0x05 243 - #define MULTIPLY_BY_7 0x06 244 - #define MULTIPLY_BY_8 0x07 245 - #define MULTIPLY_BY_9 0x08 246 - #define MULTIPLY_BY_10 0x09 247 - 248 - #define DIVIDE_BY_2 0x01 249 - #define DIVIDE_BY_3 0x02 250 - #define DIVIDE_BY_4 0x03 251 - #define DIVIDE_BY_5 0x04 252 - #define DIVIDE_BY_6 0x05 253 - #define DIVIDE_BY_7 0x06 254 - #define DIVIDE_BY_8 0x07 255 - #define DIVIDE_BY_9 0x08 256 - #define DIVIDE_BY_10 0x09 257 - 258 - struct timing_phase_path { 259 - int start; 260 - int end; 261 - int mid; 262 - int len; 263 - }; 264 - 265 - int sd_select_card(struct rtsx_chip *chip, int select); 266 - int sd_pull_ctl_enable(struct rtsx_chip *chip); 267 - int reset_sd_card(struct rtsx_chip *chip); 268 - int sd_switch_clock(struct rtsx_chip *chip); 269 - void sd_stop_seq_mode(struct rtsx_chip *chip); 270 - int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 271 - u32 start_sector, u16 sector_cnt); 272 - void sd_cleanup_work(struct rtsx_chip *chip); 273 - int sd_power_off_card3v3(struct rtsx_chip *chip); 274 - int release_sd_card(struct rtsx_chip *chip); 275 - #ifdef SUPPORT_CPRM 276 - int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 277 - u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, 278 - bool special_check); 279 - int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type); 280 - 281 - int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip); 282 - int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 283 - int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 284 - int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip); 285 - int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip); 286 - int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip); 287 - #endif 288 - 289 - #endif /* __REALTEK_RTSX_SD_H */
-906
drivers/staging/rts5208/spi.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - 16 - #include "rtsx.h" 17 - #include "spi.h" 18 - 19 - static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) 20 - { 21 - struct spi_info *spi = &chip->spi; 22 - 23 - spi->err_code = err_code; 24 - } 25 - 26 - static int spi_init(struct rtsx_chip *chip) 27 - { 28 - int retval; 29 - 30 - retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 31 - CS_POLARITY_LOW | DTO_MSB_FIRST 32 - | SPI_MASTER | SPI_MODE0 | SPI_AUTO); 33 - if (retval) 34 - return retval; 35 - retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 36 - SAMPLE_DELAY_HALF); 37 - if (retval) 38 - return retval; 39 - 40 - return STATUS_SUCCESS; 41 - } 42 - 43 - static int spi_set_init_para(struct rtsx_chip *chip) 44 - { 45 - struct spi_info *spi = &chip->spi; 46 - int retval; 47 - 48 - retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 49 - (u8)(spi->clk_div >> 8)); 50 - if (retval) 51 - return retval; 52 - retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 53 - (u8)(spi->clk_div)); 54 - if (retval) 55 - return retval; 56 - 57 - retval = switch_clock(chip, spi->spi_clock); 58 - if (retval != STATUS_SUCCESS) 59 - return STATUS_FAIL; 60 - 61 - retval = select_card(chip, SPI_CARD); 62 - if (retval != STATUS_SUCCESS) 63 - return STATUS_FAIL; 64 - 65 - retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 66 - SPI_CLK_EN); 67 - if (retval) 68 - return retval; 69 - retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 70 - SPI_OUTPUT_EN); 71 - if (retval) 72 - return retval; 73 - 74 - wait_timeout(10); 75 - 76 - retval = spi_init(chip); 77 - if (retval != STATUS_SUCCESS) 78 - return STATUS_FAIL; 79 - 80 - return STATUS_SUCCESS; 81 - } 82 - 83 - static int sf_polling_status(struct rtsx_chip *chip, int msec) 84 - { 85 - int retval; 86 - 87 - rtsx_init_cmd(chip); 88 - 89 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); 90 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 91 - SPI_TRANSFER0_START | SPI_POLLING_MODE0); 92 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 93 - SPI_TRANSFER0_END); 94 - 95 - retval = rtsx_send_cmd(chip, 0, msec); 96 - if (retval < 0) { 97 - rtsx_clear_spi_error(chip); 98 - spi_set_err_code(chip, SPI_BUSY_ERR); 99 - return STATUS_FAIL; 100 - } 101 - 102 - return STATUS_SUCCESS; 103 - } 104 - 105 - static int sf_enable_write(struct rtsx_chip *chip, u8 ins) 106 - { 107 - struct spi_info *spi = &chip->spi; 108 - int retval; 109 - 110 - if (!spi->write_en) 111 - return STATUS_SUCCESS; 112 - 113 - rtsx_init_cmd(chip); 114 - 115 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 116 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 117 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 118 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 119 - SPI_TRANSFER0_START | SPI_C_MODE0); 120 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 121 - SPI_TRANSFER0_END); 122 - 123 - retval = rtsx_send_cmd(chip, 0, 100); 124 - if (retval < 0) { 125 - rtsx_clear_spi_error(chip); 126 - spi_set_err_code(chip, SPI_HW_ERR); 127 - return STATUS_FAIL; 128 - } 129 - 130 - return STATUS_SUCCESS; 131 - } 132 - 133 - static int sf_disable_write(struct rtsx_chip *chip, u8 ins) 134 - { 135 - struct spi_info *spi = &chip->spi; 136 - int retval; 137 - 138 - if (!spi->write_en) 139 - return STATUS_SUCCESS; 140 - 141 - rtsx_init_cmd(chip); 142 - 143 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 144 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 145 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 146 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 147 - SPI_TRANSFER0_START | SPI_C_MODE0); 148 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 149 - SPI_TRANSFER0_END); 150 - 151 - retval = rtsx_send_cmd(chip, 0, 100); 152 - if (retval < 0) { 153 - rtsx_clear_spi_error(chip); 154 - spi_set_err_code(chip, SPI_HW_ERR); 155 - return STATUS_FAIL; 156 - } 157 - 158 - return STATUS_SUCCESS; 159 - } 160 - 161 - static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr, 162 - u16 len) 163 - { 164 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 165 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 166 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 167 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len); 168 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8)); 169 - if (addr_mode) { 170 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 171 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 172 - (u8)(addr >> 8)); 173 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 174 - (u8)(addr >> 16)); 175 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 176 - SPI_TRANSFER0_START | SPI_CADO_MODE0); 177 - } else { 178 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 179 - SPI_TRANSFER0_START | SPI_CDO_MODE0); 180 - } 181 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 182 - SPI_TRANSFER0_END); 183 - } 184 - 185 - static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr) 186 - { 187 - int retval; 188 - 189 - rtsx_init_cmd(chip); 190 - 191 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 192 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 193 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 194 - if (addr_mode) { 195 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 196 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 197 - (u8)(addr >> 8)); 198 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 199 - (u8)(addr >> 16)); 200 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 201 - SPI_TRANSFER0_START | SPI_CA_MODE0); 202 - } else { 203 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 204 - SPI_TRANSFER0_START | SPI_C_MODE0); 205 - } 206 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 207 - SPI_TRANSFER0_END); 208 - 209 - retval = rtsx_send_cmd(chip, 0, 100); 210 - if (retval < 0) { 211 - rtsx_clear_spi_error(chip); 212 - spi_set_err_code(chip, SPI_HW_ERR); 213 - return STATUS_FAIL; 214 - } 215 - 216 - return STATUS_SUCCESS; 217 - } 218 - 219 - static int spi_init_eeprom(struct rtsx_chip *chip) 220 - { 221 - int retval; 222 - int clk; 223 - 224 - if (chip->asic_code) 225 - clk = 30; 226 - else 227 - clk = CLK_30; 228 - 229 - retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); 230 - if (retval) 231 - return retval; 232 - retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); 233 - if (retval) 234 - return retval; 235 - 236 - retval = switch_clock(chip, clk); 237 - if (retval != STATUS_SUCCESS) 238 - return STATUS_FAIL; 239 - 240 - retval = select_card(chip, SPI_CARD); 241 - if (retval != STATUS_SUCCESS) 242 - return STATUS_FAIL; 243 - 244 - retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 245 - SPI_CLK_EN); 246 - if (retval) 247 - return retval; 248 - retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 249 - SPI_OUTPUT_EN); 250 - if (retval) 251 - return retval; 252 - 253 - wait_timeout(10); 254 - 255 - retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 256 - CS_POLARITY_HIGH | SPI_EEPROM_AUTO); 257 - if (retval) 258 - return retval; 259 - retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 260 - SAMPLE_DELAY_HALF); 261 - if (retval) 262 - return retval; 263 - 264 - return STATUS_SUCCESS; 265 - } 266 - 267 - static int spi_eeprom_program_enable(struct rtsx_chip *chip) 268 - { 269 - int retval; 270 - 271 - rtsx_init_cmd(chip); 272 - 273 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86); 274 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13); 275 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 276 - SPI_TRANSFER0_START | SPI_CA_MODE0); 277 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 278 - SPI_TRANSFER0_END); 279 - 280 - retval = rtsx_send_cmd(chip, 0, 100); 281 - if (retval < 0) 282 - return STATUS_FAIL; 283 - 284 - return STATUS_SUCCESS; 285 - } 286 - 287 - int spi_erase_eeprom_chip(struct rtsx_chip *chip) 288 - { 289 - int retval; 290 - 291 - retval = spi_init_eeprom(chip); 292 - if (retval != STATUS_SUCCESS) 293 - return STATUS_FAIL; 294 - 295 - retval = spi_eeprom_program_enable(chip); 296 - if (retval != STATUS_SUCCESS) 297 - return STATUS_FAIL; 298 - 299 - rtsx_init_cmd(chip); 300 - 301 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 302 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 303 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12); 304 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84); 305 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 306 - SPI_TRANSFER0_START | SPI_CA_MODE0); 307 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 308 - SPI_TRANSFER0_END); 309 - 310 - retval = rtsx_send_cmd(chip, 0, 100); 311 - if (retval < 0) 312 - return STATUS_FAIL; 313 - 314 - retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 315 - if (retval) 316 - return retval; 317 - 318 - return STATUS_SUCCESS; 319 - } 320 - 321 - int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) 322 - { 323 - int retval; 324 - 325 - retval = spi_init_eeprom(chip); 326 - if (retval != STATUS_SUCCESS) 327 - return STATUS_FAIL; 328 - 329 - retval = spi_eeprom_program_enable(chip); 330 - if (retval != STATUS_SUCCESS) 331 - return STATUS_FAIL; 332 - 333 - rtsx_init_cmd(chip); 334 - 335 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 336 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 337 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07); 338 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 339 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 340 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 341 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 342 - SPI_TRANSFER0_START | SPI_CA_MODE0); 343 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 344 - SPI_TRANSFER0_END); 345 - 346 - retval = rtsx_send_cmd(chip, 0, 100); 347 - if (retval < 0) 348 - return STATUS_FAIL; 349 - 350 - retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 351 - if (retval) 352 - return retval; 353 - 354 - return STATUS_SUCCESS; 355 - } 356 - 357 - int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) 358 - { 359 - int retval; 360 - u8 data; 361 - 362 - retval = spi_init_eeprom(chip); 363 - if (retval != STATUS_SUCCESS) 364 - return STATUS_FAIL; 365 - 366 - rtsx_init_cmd(chip); 367 - 368 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 369 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 370 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06); 371 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 372 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 373 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 374 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 375 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 376 - SPI_TRANSFER0_START | SPI_CADI_MODE0); 377 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 378 - SPI_TRANSFER0_END); 379 - 380 - retval = rtsx_send_cmd(chip, 0, 100); 381 - if (retval < 0) 382 - return STATUS_FAIL; 383 - 384 - wait_timeout(5); 385 - retval = rtsx_read_register(chip, SPI_DATA, &data); 386 - if (retval) 387 - return retval; 388 - 389 - if (val) 390 - *val = data; 391 - 392 - retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 393 - if (retval) 394 - return retval; 395 - 396 - return STATUS_SUCCESS; 397 - } 398 - 399 - int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) 400 - { 401 - int retval; 402 - 403 - retval = spi_init_eeprom(chip); 404 - if (retval != STATUS_SUCCESS) 405 - return STATUS_FAIL; 406 - 407 - retval = spi_eeprom_program_enable(chip); 408 - if (retval != STATUS_SUCCESS) 409 - return STATUS_FAIL; 410 - 411 - rtsx_init_cmd(chip); 412 - 413 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 414 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 415 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05); 416 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); 417 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr); 418 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8)); 419 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E); 420 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 421 - SPI_TRANSFER0_START | SPI_CA_MODE0); 422 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 423 - SPI_TRANSFER0_END); 424 - 425 - retval = rtsx_send_cmd(chip, 0, 100); 426 - if (retval < 0) 427 - return STATUS_FAIL; 428 - 429 - retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 430 - if (retval) 431 - return retval; 432 - 433 - return STATUS_SUCCESS; 434 - } 435 - 436 - int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 437 - { 438 - struct spi_info *spi = &chip->spi; 439 - 440 - dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__, 441 - spi->err_code); 442 - rtsx_stor_set_xfer_buf(&spi->err_code, 443 - min_t(int, scsi_bufflen(srb), 1), srb); 444 - scsi_set_resid(srb, scsi_bufflen(srb) - 1); 445 - 446 - return STATUS_SUCCESS; 447 - } 448 - 449 - int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) 450 - { 451 - struct spi_info *spi = &chip->spi; 452 - 453 - spi_set_err_code(chip, SPI_NO_ERR); 454 - 455 - if (chip->asic_code) 456 - spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; 457 - else 458 - spi->spi_clock = srb->cmnd[3]; 459 - 460 - spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 461 - spi->write_en = srb->cmnd[6]; 462 - 463 - dev_dbg(rtsx_dev(chip), "spi_clock = %d, clk_div = %d, write_en = %d\n", 464 - spi->spi_clock, spi->clk_div, spi->write_en); 465 - 466 - return STATUS_SUCCESS; 467 - } 468 - 469 - int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 470 - { 471 - int retval; 472 - u16 len; 473 - u8 *buf; 474 - 475 - spi_set_err_code(chip, SPI_NO_ERR); 476 - 477 - len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 478 - if (len > 512) { 479 - spi_set_err_code(chip, SPI_INVALID_COMMAND); 480 - return STATUS_FAIL; 481 - } 482 - 483 - retval = spi_set_init_para(chip); 484 - if (retval != STATUS_SUCCESS) { 485 - spi_set_err_code(chip, SPI_HW_ERR); 486 - return STATUS_FAIL; 487 - } 488 - 489 - rtsx_init_cmd(chip); 490 - 491 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 492 - PINGPONG_BUFFER); 493 - 494 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]); 495 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]); 496 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]); 497 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]); 498 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 499 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 500 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]); 501 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]); 502 - 503 - if (len == 0) { 504 - if (srb->cmnd[9]) { 505 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 506 - 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0); 507 - } else { 508 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 509 - 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); 510 - } 511 - } else { 512 - if (srb->cmnd[9]) { 513 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 514 - SPI_TRANSFER0_START | SPI_CADI_MODE0); 515 - } else { 516 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 517 - SPI_TRANSFER0_START | SPI_CDI_MODE0); 518 - } 519 - } 520 - 521 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 522 - SPI_TRANSFER0_END); 523 - 524 - retval = rtsx_send_cmd(chip, 0, 100); 525 - if (retval < 0) { 526 - rtsx_clear_spi_error(chip); 527 - spi_set_err_code(chip, SPI_HW_ERR); 528 - return STATUS_FAIL; 529 - } 530 - 531 - if (len) { 532 - buf = kmalloc(len, GFP_KERNEL); 533 - if (!buf) 534 - return STATUS_ERROR; 535 - 536 - retval = rtsx_read_ppbuf(chip, buf, len); 537 - if (retval != STATUS_SUCCESS) { 538 - spi_set_err_code(chip, SPI_READ_ERR); 539 - kfree(buf); 540 - return STATUS_FAIL; 541 - } 542 - 543 - rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 544 - scsi_set_resid(srb, 0); 545 - 546 - kfree(buf); 547 - } 548 - 549 - return STATUS_SUCCESS; 550 - } 551 - 552 - int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 553 - { 554 - int retval; 555 - unsigned int index = 0, offset = 0; 556 - u8 ins, slow_read; 557 - u32 addr; 558 - u16 len; 559 - u8 *buf; 560 - 561 - spi_set_err_code(chip, SPI_NO_ERR); 562 - 563 - ins = srb->cmnd[3]; 564 - addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 565 - << 8) | srb->cmnd[6]; 566 - len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 567 - slow_read = srb->cmnd[9]; 568 - 569 - retval = spi_set_init_para(chip); 570 - if (retval != STATUS_SUCCESS) { 571 - spi_set_err_code(chip, SPI_HW_ERR); 572 - return STATUS_FAIL; 573 - } 574 - 575 - buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 576 - if (!buf) 577 - return STATUS_ERROR; 578 - 579 - while (len) { 580 - u16 pagelen = SF_PAGE_LEN - (u8)addr; 581 - 582 - if (pagelen > len) 583 - pagelen = len; 584 - 585 - rtsx_init_cmd(chip); 586 - 587 - trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256); 588 - 589 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 590 - 591 - if (slow_read) { 592 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, 593 - (u8)addr); 594 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 595 - (u8)(addr >> 8)); 596 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 597 - (u8)(addr >> 16)); 598 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 599 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 600 - } else { 601 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 602 - (u8)addr); 603 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 604 - (u8)(addr >> 8)); 605 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF, 606 - (u8)(addr >> 16)); 607 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 608 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32); 609 - } 610 - 611 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 612 - (u8)(pagelen >> 8)); 613 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 614 - (u8)pagelen); 615 - 616 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 617 - SPI_TRANSFER0_START | SPI_CADI_MODE0); 618 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, 619 - SPI_TRANSFER0_END, SPI_TRANSFER0_END); 620 - 621 - rtsx_send_cmd_no_wait(chip); 622 - 623 - retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 624 - DMA_FROM_DEVICE, 10000); 625 - if (retval < 0) { 626 - kfree(buf); 627 - rtsx_clear_spi_error(chip); 628 - spi_set_err_code(chip, SPI_HW_ERR); 629 - return STATUS_FAIL; 630 - } 631 - 632 - rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset, 633 - TO_XFER_BUF); 634 - 635 - addr += pagelen; 636 - len -= pagelen; 637 - } 638 - 639 - scsi_set_resid(srb, 0); 640 - kfree(buf); 641 - 642 - return STATUS_SUCCESS; 643 - } 644 - 645 - int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 646 - { 647 - int retval; 648 - u8 ins, program_mode; 649 - u32 addr; 650 - u16 len; 651 - u8 *buf; 652 - unsigned int index = 0, offset = 0; 653 - 654 - spi_set_err_code(chip, SPI_NO_ERR); 655 - 656 - ins = srb->cmnd[3]; 657 - addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 658 - << 8) | srb->cmnd[6]; 659 - len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 660 - program_mode = srb->cmnd[9]; 661 - 662 - retval = spi_set_init_para(chip); 663 - if (retval != STATUS_SUCCESS) { 664 - spi_set_err_code(chip, SPI_HW_ERR); 665 - return STATUS_FAIL; 666 - } 667 - 668 - if (program_mode == BYTE_PROGRAM) { 669 - buf = kmalloc(4, GFP_KERNEL); 670 - if (!buf) 671 - return STATUS_ERROR; 672 - 673 - while (len) { 674 - retval = sf_enable_write(chip, SPI_WREN); 675 - if (retval != STATUS_SUCCESS) { 676 - kfree(buf); 677 - return STATUS_FAIL; 678 - } 679 - 680 - rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 681 - FROM_XFER_BUF); 682 - 683 - rtsx_init_cmd(chip); 684 - 685 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 686 - 0x01, PINGPONG_BUFFER); 687 - rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 688 - buf[0]); 689 - sf_program(chip, ins, 1, addr, 1); 690 - 691 - retval = rtsx_send_cmd(chip, 0, 100); 692 - if (retval < 0) { 693 - kfree(buf); 694 - rtsx_clear_spi_error(chip); 695 - spi_set_err_code(chip, SPI_HW_ERR); 696 - return STATUS_FAIL; 697 - } 698 - 699 - retval = sf_polling_status(chip, 100); 700 - if (retval != STATUS_SUCCESS) { 701 - kfree(buf); 702 - return STATUS_FAIL; 703 - } 704 - 705 - addr++; 706 - len--; 707 - } 708 - 709 - kfree(buf); 710 - 711 - } else if (program_mode == AAI_PROGRAM) { 712 - int first_byte = 1; 713 - 714 - retval = sf_enable_write(chip, SPI_WREN); 715 - if (retval != STATUS_SUCCESS) 716 - return STATUS_FAIL; 717 - 718 - buf = kmalloc(4, GFP_KERNEL); 719 - if (!buf) 720 - return STATUS_ERROR; 721 - 722 - while (len) { 723 - rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 724 - FROM_XFER_BUF); 725 - 726 - rtsx_init_cmd(chip); 727 - 728 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 729 - 0x01, PINGPONG_BUFFER); 730 - rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 731 - buf[0]); 732 - if (first_byte) { 733 - sf_program(chip, ins, 1, addr, 1); 734 - first_byte = 0; 735 - } else { 736 - sf_program(chip, ins, 0, 0, 1); 737 - } 738 - 739 - retval = rtsx_send_cmd(chip, 0, 100); 740 - if (retval < 0) { 741 - kfree(buf); 742 - rtsx_clear_spi_error(chip); 743 - spi_set_err_code(chip, SPI_HW_ERR); 744 - return STATUS_FAIL; 745 - } 746 - 747 - retval = sf_polling_status(chip, 100); 748 - if (retval != STATUS_SUCCESS) { 749 - kfree(buf); 750 - return STATUS_FAIL; 751 - } 752 - 753 - len--; 754 - } 755 - 756 - kfree(buf); 757 - 758 - retval = sf_disable_write(chip, SPI_WRDI); 759 - if (retval != STATUS_SUCCESS) 760 - return STATUS_FAIL; 761 - 762 - retval = sf_polling_status(chip, 100); 763 - if (retval != STATUS_SUCCESS) 764 - return STATUS_FAIL; 765 - } else if (program_mode == PAGE_PROGRAM) { 766 - buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 767 - if (!buf) 768 - return STATUS_NOMEM; 769 - 770 - while (len) { 771 - u16 pagelen = SF_PAGE_LEN - (u8)addr; 772 - 773 - if (pagelen > len) 774 - pagelen = len; 775 - 776 - retval = sf_enable_write(chip, SPI_WREN); 777 - if (retval != STATUS_SUCCESS) { 778 - kfree(buf); 779 - return STATUS_FAIL; 780 - } 781 - 782 - rtsx_init_cmd(chip); 783 - 784 - trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256); 785 - sf_program(chip, ins, 1, addr, pagelen); 786 - 787 - rtsx_send_cmd_no_wait(chip); 788 - 789 - rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, 790 - &offset, FROM_XFER_BUF); 791 - 792 - retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 793 - DMA_TO_DEVICE, 100); 794 - if (retval < 0) { 795 - kfree(buf); 796 - rtsx_clear_spi_error(chip); 797 - spi_set_err_code(chip, SPI_HW_ERR); 798 - return STATUS_FAIL; 799 - } 800 - 801 - retval = sf_polling_status(chip, 100); 802 - if (retval != STATUS_SUCCESS) { 803 - kfree(buf); 804 - return STATUS_FAIL; 805 - } 806 - 807 - addr += pagelen; 808 - len -= pagelen; 809 - } 810 - 811 - kfree(buf); 812 - } else { 813 - spi_set_err_code(chip, SPI_INVALID_COMMAND); 814 - return STATUS_FAIL; 815 - } 816 - 817 - return STATUS_SUCCESS; 818 - } 819 - 820 - int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 821 - { 822 - int retval; 823 - u8 ins, erase_mode; 824 - u32 addr; 825 - 826 - spi_set_err_code(chip, SPI_NO_ERR); 827 - 828 - ins = srb->cmnd[3]; 829 - addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 830 - << 8) | srb->cmnd[6]; 831 - erase_mode = srb->cmnd[9]; 832 - 833 - retval = spi_set_init_para(chip); 834 - if (retval != STATUS_SUCCESS) { 835 - spi_set_err_code(chip, SPI_HW_ERR); 836 - return STATUS_FAIL; 837 - } 838 - 839 - if (erase_mode == PAGE_ERASE) { 840 - retval = sf_enable_write(chip, SPI_WREN); 841 - if (retval != STATUS_SUCCESS) 842 - return STATUS_FAIL; 843 - 844 - retval = sf_erase(chip, ins, 1, addr); 845 - if (retval != STATUS_SUCCESS) 846 - return STATUS_FAIL; 847 - } else if (erase_mode == CHIP_ERASE) { 848 - retval = sf_enable_write(chip, SPI_WREN); 849 - if (retval != STATUS_SUCCESS) 850 - return STATUS_FAIL; 851 - 852 - retval = sf_erase(chip, ins, 0, 0); 853 - if (retval != STATUS_SUCCESS) 854 - return STATUS_FAIL; 855 - } else { 856 - spi_set_err_code(chip, SPI_INVALID_COMMAND); 857 - return STATUS_FAIL; 858 - } 859 - 860 - return STATUS_SUCCESS; 861 - } 862 - 863 - int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 864 - { 865 - int retval; 866 - u8 ins, status, ewsr; 867 - 868 - ins = srb->cmnd[3]; 869 - status = srb->cmnd[4]; 870 - ewsr = srb->cmnd[5]; 871 - 872 - retval = spi_set_init_para(chip); 873 - if (retval != STATUS_SUCCESS) { 874 - spi_set_err_code(chip, SPI_HW_ERR); 875 - return STATUS_FAIL; 876 - } 877 - 878 - retval = sf_enable_write(chip, ewsr); 879 - if (retval != STATUS_SUCCESS) 880 - return STATUS_FAIL; 881 - 882 - rtsx_init_cmd(chip); 883 - 884 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 885 - PINGPONG_BUFFER); 886 - 887 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 888 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 889 - SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 890 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0); 891 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 892 - rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); 893 - rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 894 - SPI_TRANSFER0_START | SPI_CDO_MODE0); 895 - rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 896 - SPI_TRANSFER0_END); 897 - 898 - retval = rtsx_send_cmd(chip, 0, 100); 899 - if (retval != STATUS_SUCCESS) { 900 - rtsx_clear_spi_error(chip); 901 - spi_set_err_code(chip, SPI_HW_ERR); 902 - return STATUS_FAIL; 903 - } 904 - 905 - return STATUS_SUCCESS; 906 - }
-52
drivers/staging/rts5208/spi.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_SPI_H 13 - #define __REALTEK_RTSX_SPI_H 14 - 15 - /* SPI operation error */ 16 - #define SPI_NO_ERR 0x00 17 - #define SPI_HW_ERR 0x01 18 - #define SPI_INVALID_COMMAND 0x02 19 - #define SPI_READ_ERR 0x03 20 - #define SPI_WRITE_ERR 0x04 21 - #define SPI_ERASE_ERR 0x05 22 - #define SPI_BUSY_ERR 0x06 23 - 24 - /* Serial flash instruction */ 25 - #define SPI_READ 0x03 26 - #define SPI_FAST_READ 0x0B 27 - #define SPI_WREN 0x06 28 - #define SPI_WRDI 0x04 29 - #define SPI_RDSR 0x05 30 - 31 - #define SF_PAGE_LEN 256 32 - 33 - #define BYTE_PROGRAM 0 34 - #define AAI_PROGRAM 1 35 - #define PAGE_PROGRAM 2 36 - 37 - #define PAGE_ERASE 0 38 - #define CHIP_ERASE 1 39 - 40 - int spi_erase_eeprom_chip(struct rtsx_chip *chip); 41 - int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr); 42 - int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val); 43 - int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val); 44 - int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip); 45 - int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip); 46 - int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip); 47 - int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip); 48 - int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip); 49 - int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip); 50 - int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip); 51 - 52 - #endif /* __REALTEK_RTSX_SPI_H */
-2145
drivers/staging/rts5208/xd.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #include <linux/blkdev.h> 13 - #include <linux/kthread.h> 14 - #include <linux/sched.h> 15 - #include <linux/vmalloc.h> 16 - 17 - #include "rtsx.h" 18 - #include "rtsx_transport.h" 19 - #include "rtsx_scsi.h" 20 - #include "rtsx_card.h" 21 - #include "xd.h" 22 - 23 - static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no); 24 - static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, 25 - u8 start_page, u8 end_page); 26 - 27 - static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code) 28 - { 29 - struct xd_info *xd_card = &chip->xd_card; 30 - 31 - xd_card->err_code = err_code; 32 - } 33 - 34 - static int xd_set_init_para(struct rtsx_chip *chip) 35 - { 36 - struct xd_info *xd_card = &chip->xd_card; 37 - int retval; 38 - 39 - if (chip->asic_code) 40 - xd_card->xd_clock = 47; 41 - else 42 - xd_card->xd_clock = CLK_50; 43 - 44 - retval = switch_clock(chip, xd_card->xd_clock); 45 - if (retval != STATUS_SUCCESS) 46 - return STATUS_FAIL; 47 - 48 - return STATUS_SUCCESS; 49 - } 50 - 51 - static int xd_switch_clock(struct rtsx_chip *chip) 52 - { 53 - struct xd_info *xd_card = &chip->xd_card; 54 - int retval; 55 - 56 - retval = select_card(chip, XD_CARD); 57 - if (retval != STATUS_SUCCESS) 58 - return STATUS_FAIL; 59 - 60 - retval = switch_clock(chip, xd_card->xd_clock); 61 - if (retval != STATUS_SUCCESS) 62 - return STATUS_FAIL; 63 - 64 - return STATUS_SUCCESS; 65 - } 66 - 67 - static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) 68 - { 69 - int retval, i; 70 - u8 *ptr; 71 - 72 - rtsx_init_cmd(chip); 73 - 74 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); 75 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 76 - XD_TRANSFER_START | XD_READ_ID); 77 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 78 - XD_TRANSFER_END); 79 - 80 - for (i = 0; i < 4; i++) 81 - rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); 82 - 83 - retval = rtsx_send_cmd(chip, XD_CARD, 20); 84 - if (retval < 0) 85 - return STATUS_FAIL; 86 - 87 - ptr = rtsx_get_cmd_data(chip) + 1; 88 - if (id_buf && buf_len) { 89 - if (buf_len > 4) 90 - buf_len = 4; 91 - memcpy(id_buf, ptr, buf_len); 92 - } 93 - 94 - return STATUS_SUCCESS; 95 - } 96 - 97 - static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode) 98 - { 99 - struct xd_info *xd_card = &chip->xd_card; 100 - 101 - switch (mode) { 102 - case XD_RW_ADDR: 103 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); 104 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); 105 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 106 - 0xFF, (u8)(addr >> 8)); 107 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 108 - 0xFF, (u8)(addr >> 16)); 109 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 110 - xd_card->addr_cycle | 111 - XD_CALC_ECC | 112 - XD_BA_NO_TRANSFORM); 113 - break; 114 - 115 - case XD_ERASE_ADDR: 116 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); 117 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 118 - 0xFF, (u8)(addr >> 8)); 119 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 120 - 0xFF, (u8)(addr >> 16)); 121 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 122 - (xd_card->addr_cycle - 1) | XD_CALC_ECC | 123 - XD_BA_NO_TRANSFORM); 124 - break; 125 - 126 - default: 127 - break; 128 - } 129 - } 130 - 131 - static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, 132 - u8 *buf, int buf_len) 133 - { 134 - int retval, i; 135 - 136 - rtsx_init_cmd(chip); 137 - 138 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 139 - 140 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 141 - 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); 142 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 143 - XD_TRANSFER_END, XD_TRANSFER_END); 144 - 145 - for (i = 0; i < 6; i++) 146 - rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 147 - 0, 0); 148 - for (i = 0; i < 4; i++) 149 - rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 150 - 0, 0); 151 - rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); 152 - 153 - retval = rtsx_send_cmd(chip, XD_CARD, 500); 154 - if (retval < 0) 155 - return STATUS_FAIL; 156 - 157 - if (buf && buf_len) { 158 - u8 *ptr = rtsx_get_cmd_data(chip) + 1; 159 - 160 - if (buf_len > 11) 161 - buf_len = 11; 162 - memcpy(buf, ptr, buf_len); 163 - } 164 - 165 - return STATUS_SUCCESS; 166 - } 167 - 168 - static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, 169 - u8 *buf, int buf_len) 170 - { 171 - int retval, i; 172 - 173 - if (!buf || buf_len < 0) 174 - return STATUS_FAIL; 175 - 176 - rtsx_init_cmd(chip); 177 - 178 - for (i = 0; i < buf_len; i++) 179 - rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 180 - 0, 0); 181 - 182 - retval = rtsx_send_cmd(chip, 0, 250); 183 - if (retval < 0) { 184 - rtsx_clear_xd_error(chip); 185 - return STATUS_FAIL; 186 - } 187 - 188 - memcpy(buf, rtsx_get_cmd_data(chip), buf_len); 189 - 190 - return STATUS_SUCCESS; 191 - } 192 - 193 - static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, 194 - int buf_len) 195 - { 196 - int retval; 197 - u8 reg; 198 - 199 - if (!buf || buf_len < 10) 200 - return STATUS_FAIL; 201 - 202 - rtsx_init_cmd(chip); 203 - 204 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 205 - 206 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 207 - 0x01, PINGPONG_BUFFER); 208 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 209 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 210 - XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 211 - 212 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 213 - XD_TRANSFER_START | XD_READ_PAGES); 214 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 215 - XD_TRANSFER_END); 216 - 217 - retval = rtsx_send_cmd(chip, XD_CARD, 250); 218 - if (retval == -ETIMEDOUT) { 219 - rtsx_clear_xd_error(chip); 220 - return STATUS_FAIL; 221 - } 222 - 223 - retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg); 224 - if (retval) 225 - return retval; 226 - if (reg != XD_GPG) { 227 - rtsx_clear_xd_error(chip); 228 - return STATUS_FAIL; 229 - } 230 - 231 - retval = rtsx_read_register(chip, XD_CTL, &reg); 232 - if (retval) 233 - return retval; 234 - if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { 235 - retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); 236 - if (retval != STATUS_SUCCESS) 237 - return STATUS_FAIL; 238 - if (reg & XD_ECC1_ERROR) { 239 - u8 ecc_bit, ecc_byte; 240 - 241 - retval = rtsx_read_register(chip, XD_ECC_BIT1, 242 - &ecc_bit); 243 - if (retval) 244 - return retval; 245 - retval = rtsx_read_register(chip, XD_ECC_BYTE1, 246 - &ecc_byte); 247 - if (retval) 248 - return retval; 249 - 250 - dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", 251 - ecc_bit, ecc_byte); 252 - if (ecc_byte < buf_len) { 253 - dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 254 - buf[ecc_byte]); 255 - buf[ecc_byte] ^= (1 << ecc_bit); 256 - dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 257 - buf[ecc_byte]); 258 - } 259 - } 260 - } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { 261 - rtsx_clear_xd_error(chip); 262 - 263 - retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); 264 - if (retval != STATUS_SUCCESS) 265 - return STATUS_FAIL; 266 - if (reg & XD_ECC2_ERROR) { 267 - u8 ecc_bit, ecc_byte; 268 - 269 - retval = rtsx_read_register(chip, XD_ECC_BIT2, 270 - &ecc_bit); 271 - if (retval) 272 - return retval; 273 - retval = rtsx_read_register(chip, XD_ECC_BYTE2, 274 - &ecc_byte); 275 - if (retval) 276 - return retval; 277 - 278 - dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", 279 - ecc_bit, ecc_byte); 280 - if (ecc_byte < buf_len) { 281 - dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 282 - buf[ecc_byte]); 283 - buf[ecc_byte] ^= (1 << ecc_bit); 284 - dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 285 - buf[ecc_byte]); 286 - } 287 - } 288 - } else { 289 - rtsx_clear_xd_error(chip); 290 - return STATUS_FAIL; 291 - } 292 - 293 - return STATUS_SUCCESS; 294 - } 295 - 296 - static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip) 297 - { 298 - if (CHECK_PID(chip, 0x5208)) { 299 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 300 - XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 301 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 302 - XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 303 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 304 - XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 305 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 306 - XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); 307 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 308 - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 309 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 310 - MS_D5_PD | MS_D4_PD); 311 - } else if (CHECK_PID(chip, 0x5288)) { 312 - if (CHECK_BARO_PKG(chip, QFN)) { 313 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 314 - 0xFF, 0x55); 315 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 316 - 0xFF, 0x55); 317 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 318 - 0xFF, 0x4B); 319 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 320 - 0xFF, 0x69); 321 - } 322 - } 323 - } 324 - 325 - static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip) 326 - { 327 - if (CHECK_BARO_PKG(chip, QFN)) { 328 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55); 329 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55); 330 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B); 331 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55); 332 - } 333 - } 334 - 335 - static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) 336 - { 337 - if (CHECK_PID(chip, 0x5208)) { 338 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 339 - XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 340 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 341 - XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 342 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 343 - XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU); 344 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 345 - XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD); 346 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 347 - MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 348 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 349 - MS_D5_PD | MS_D4_PD); 350 - } else if (CHECK_PID(chip, 0x5288)) { 351 - if (CHECK_BARO_PKG(chip, QFN)) { 352 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 353 - 0xFF, 0x55); 354 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 355 - 0xFF, 0x55); 356 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 357 - 0xFF, 0x53); 358 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 359 - 0xFF, 0xA9); 360 - } 361 - } 362 - } 363 - 364 - static int xd_pull_ctl_disable(struct rtsx_chip *chip) 365 - { 366 - int retval; 367 - 368 - if (CHECK_PID(chip, 0x5208)) { 369 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 370 - XD_D3_PD | 371 - XD_D2_PD | 372 - XD_D1_PD | 373 - XD_D0_PD); 374 - if (retval) 375 - return retval; 376 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 377 - XD_D7_PD | 378 - XD_D6_PD | 379 - XD_D5_PD | 380 - XD_D4_PD); 381 - if (retval) 382 - return retval; 383 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 384 - XD_WP_PD | 385 - XD_CE_PD | 386 - XD_CLE_PD | 387 - XD_CD_PU); 388 - if (retval) 389 - return retval; 390 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 391 - XD_RDY_PD | 392 - XD_WE_PD | 393 - XD_RE_PD | 394 - XD_ALE_PD); 395 - if (retval) 396 - return retval; 397 - retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 398 - MS_INS_PU | 399 - SD_WP_PD | 400 - SD_CD_PU | 401 - SD_CMD_PD); 402 - if (retval) 403 - return retval; 404 - retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 405 - MS_D5_PD | MS_D4_PD); 406 - if (retval) 407 - return retval; 408 - } else if (CHECK_PID(chip, 0x5288)) { 409 - if (CHECK_BARO_PKG(chip, QFN)) { 410 - retval = rtsx_write_register(chip, CARD_PULL_CTL1, 411 - 0xFF, 0x55); 412 - if (retval) 413 - return retval; 414 - retval = rtsx_write_register(chip, CARD_PULL_CTL2, 415 - 0xFF, 0x55); 416 - if (retval) 417 - return retval; 418 - retval = rtsx_write_register(chip, CARD_PULL_CTL3, 419 - 0xFF, 0x4B); 420 - if (retval) 421 - return retval; 422 - retval = rtsx_write_register(chip, CARD_PULL_CTL4, 423 - 0xFF, 0x69); 424 - if (retval) 425 - return retval; 426 - } 427 - } 428 - 429 - return STATUS_SUCCESS; 430 - } 431 - 432 - static int reset_xd(struct rtsx_chip *chip) 433 - { 434 - struct xd_info *xd_card = &chip->xd_card; 435 - int retval, i, j; 436 - u8 *ptr, id_buf[4], redunt[11]; 437 - 438 - retval = select_card(chip, XD_CARD); 439 - if (retval != STATUS_SUCCESS) 440 - return STATUS_FAIL; 441 - 442 - rtsx_init_cmd(chip); 443 - 444 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, 445 - XD_PGSTS_NOT_FF); 446 - if (chip->asic_code) { 447 - if (!CHECK_PID(chip, 0x5288)) 448 - xd_fill_pull_ctl_disable(chip); 449 - else 450 - xd_fill_pull_ctl_stage1_barossa(chip); 451 - } else { 452 - rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 453 - (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 454 - 0x20); 455 - } 456 - 457 - if (!chip->ft2_fast_mode) 458 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, 459 - XD_NO_AUTO_PWR_OFF, 0); 460 - 461 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); 462 - 463 - retval = rtsx_send_cmd(chip, XD_CARD, 100); 464 - if (retval < 0) 465 - return STATUS_FAIL; 466 - 467 - if (!chip->ft2_fast_mode) { 468 - retval = card_power_off(chip, XD_CARD); 469 - if (retval != STATUS_SUCCESS) 470 - return STATUS_FAIL; 471 - 472 - wait_timeout(250); 473 - 474 - rtsx_init_cmd(chip); 475 - 476 - if (chip->asic_code) { 477 - xd_fill_pull_ctl_enable(chip); 478 - } else { 479 - rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 480 - (FPGA_XD_PULL_CTL_EN1 & 481 - FPGA_XD_PULL_CTL_EN2) | 482 - 0x20); 483 - } 484 - 485 - retval = rtsx_send_cmd(chip, XD_CARD, 100); 486 - if (retval < 0) 487 - return STATUS_FAIL; 488 - 489 - retval = card_power_on(chip, XD_CARD); 490 - if (retval != STATUS_SUCCESS) 491 - return STATUS_FAIL; 492 - 493 - #ifdef SUPPORT_OCP 494 - wait_timeout(50); 495 - if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 496 - dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 497 - chip->ocp_stat); 498 - return STATUS_FAIL; 499 - } 500 - #endif 501 - } 502 - 503 - rtsx_init_cmd(chip); 504 - 505 - if (chip->ft2_fast_mode) { 506 - if (chip->asic_code) { 507 - xd_fill_pull_ctl_enable(chip); 508 - } else { 509 - rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 510 - (FPGA_XD_PULL_CTL_EN1 & 511 - FPGA_XD_PULL_CTL_EN2) | 512 - 0x20); 513 - } 514 - } 515 - 516 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN); 517 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); 518 - 519 - retval = rtsx_send_cmd(chip, XD_CARD, 100); 520 - if (retval < 0) 521 - return STATUS_FAIL; 522 - 523 - if (!chip->ft2_fast_mode) 524 - wait_timeout(200); 525 - 526 - retval = xd_set_init_para(chip); 527 - if (retval != STATUS_SUCCESS) 528 - return STATUS_FAIL; 529 - 530 - /* Read ID to check if the timing setting is right */ 531 - for (i = 0; i < 4; i++) { 532 - rtsx_init_cmd(chip); 533 - 534 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF, 535 - XD_TIME_SETUP_STEP * 3 + 536 - XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i); 537 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF, 538 - XD_TIME_SETUP_STEP * 3 + 539 - XD_TIME_RW_STEP * (4 + i) + 540 - XD_TIME_RWN_STEP * (3 + i)); 541 - 542 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 543 - XD_TRANSFER_START | XD_RESET); 544 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 545 - XD_TRANSFER_END, XD_TRANSFER_END); 546 - 547 - rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 548 - rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 549 - 550 - retval = rtsx_send_cmd(chip, XD_CARD, 100); 551 - if (retval < 0) 552 - return STATUS_FAIL; 553 - 554 - ptr = rtsx_get_cmd_data(chip) + 1; 555 - 556 - dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n", 557 - ptr[0], ptr[1]); 558 - 559 - if (((ptr[0] & READY_FLAG) != READY_STATE) || 560 - !(ptr[1] & XD_RDY)) 561 - continue; 562 - 563 - retval = xd_read_id(chip, READ_ID, id_buf, 4); 564 - if (retval != STATUS_SUCCESS) 565 - return STATUS_FAIL; 566 - 567 - dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n", 568 - id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 569 - 570 - xd_card->device_code = id_buf[1]; 571 - 572 - /* Check if the xD card is supported */ 573 - switch (xd_card->device_code) { 574 - case XD_4M_X8_512_1: 575 - case XD_4M_X8_512_2: 576 - xd_card->block_shift = 4; 577 - xd_card->page_off = 0x0F; 578 - xd_card->addr_cycle = 3; 579 - xd_card->zone_cnt = 1; 580 - xd_card->capacity = 8000; 581 - XD_SET_4MB(xd_card); 582 - break; 583 - case XD_8M_X8_512: 584 - xd_card->block_shift = 4; 585 - xd_card->page_off = 0x0F; 586 - xd_card->addr_cycle = 3; 587 - xd_card->zone_cnt = 1; 588 - xd_card->capacity = 16000; 589 - break; 590 - case XD_16M_X8_512: 591 - XD_PAGE_512(xd_card); 592 - xd_card->addr_cycle = 3; 593 - xd_card->zone_cnt = 1; 594 - xd_card->capacity = 32000; 595 - break; 596 - case XD_32M_X8_512: 597 - XD_PAGE_512(xd_card); 598 - xd_card->addr_cycle = 3; 599 - xd_card->zone_cnt = 2; 600 - xd_card->capacity = 64000; 601 - break; 602 - case XD_64M_X8_512: 603 - XD_PAGE_512(xd_card); 604 - xd_card->addr_cycle = 4; 605 - xd_card->zone_cnt = 4; 606 - xd_card->capacity = 128000; 607 - break; 608 - case XD_128M_X8_512: 609 - XD_PAGE_512(xd_card); 610 - xd_card->addr_cycle = 4; 611 - xd_card->zone_cnt = 8; 612 - xd_card->capacity = 256000; 613 - break; 614 - case XD_256M_X8_512: 615 - XD_PAGE_512(xd_card); 616 - xd_card->addr_cycle = 4; 617 - xd_card->zone_cnt = 16; 618 - xd_card->capacity = 512000; 619 - break; 620 - case XD_512M_X8: 621 - XD_PAGE_512(xd_card); 622 - xd_card->addr_cycle = 4; 623 - xd_card->zone_cnt = 32; 624 - xd_card->capacity = 1024000; 625 - break; 626 - case XD_1G_X8_512: 627 - XD_PAGE_512(xd_card); 628 - xd_card->addr_cycle = 4; 629 - xd_card->zone_cnt = 64; 630 - xd_card->capacity = 2048000; 631 - break; 632 - case XD_2G_X8_512: 633 - XD_PAGE_512(xd_card); 634 - xd_card->addr_cycle = 4; 635 - xd_card->zone_cnt = 128; 636 - xd_card->capacity = 4096000; 637 - break; 638 - default: 639 - continue; 640 - } 641 - 642 - /* Confirm timing setting */ 643 - for (j = 0; j < 10; j++) { 644 - retval = xd_read_id(chip, READ_ID, id_buf, 4); 645 - if (retval != STATUS_SUCCESS) 646 - return STATUS_FAIL; 647 - 648 - if (id_buf[1] != xd_card->device_code) 649 - break; 650 - } 651 - 652 - if (j == 10) 653 - break; 654 - } 655 - 656 - if (i == 4) { 657 - xd_card->block_shift = 0; 658 - xd_card->page_off = 0; 659 - xd_card->addr_cycle = 0; 660 - xd_card->capacity = 0; 661 - 662 - return STATUS_FAIL; 663 - } 664 - 665 - retval = xd_read_id(chip, READ_XD_ID, id_buf, 4); 666 - if (retval != STATUS_SUCCESS) 667 - return STATUS_FAIL; 668 - dev_dbg(rtsx_dev(chip), "READ_XD_ID: 0x%x 0x%x 0x%x 0x%x\n", 669 - id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 670 - if (id_buf[2] != XD_ID_CODE) 671 - return STATUS_FAIL; 672 - 673 - /* Search CIS block */ 674 - for (i = 0; i < 24; i++) { 675 - u32 page_addr; 676 - 677 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) 678 - return STATUS_FAIL; 679 - 680 - page_addr = (u32)i << xd_card->block_shift; 681 - 682 - for (j = 0; j < 3; j++) { 683 - retval = xd_read_redundant(chip, page_addr, redunt, 11); 684 - if (retval == STATUS_SUCCESS) 685 - break; 686 - } 687 - if (j == 3) 688 - continue; 689 - 690 - if (redunt[BLOCK_STATUS] != XD_GBLK) 691 - continue; 692 - 693 - j = 0; 694 - if (redunt[PAGE_STATUS] != XD_GPG) { 695 - for (j = 1; j <= 8; j++) { 696 - retval = xd_read_redundant(chip, page_addr + j, 697 - redunt, 11); 698 - if (retval == STATUS_SUCCESS) { 699 - if (redunt[PAGE_STATUS] == XD_GPG) 700 - break; 701 - } 702 - } 703 - 704 - if (j == 9) 705 - break; 706 - } 707 - 708 - /* Check CIS data */ 709 - if (redunt[BLOCK_STATUS] == XD_GBLK && 710 - (redunt[PARITY] & XD_BA1_ALL0)) { 711 - u8 buf[10]; 712 - 713 - page_addr += j; 714 - 715 - retval = xd_read_cis(chip, page_addr, buf, 10); 716 - if (retval != STATUS_SUCCESS) 717 - return STATUS_FAIL; 718 - 719 - if (buf[0] == 0x01 && buf[1] == 0x03 && 720 - buf[2] == 0xD9 && 721 - buf[3] == 0x01 && buf[4] == 0xFF && 722 - buf[5] == 0x18 && buf[6] == 0x02 && 723 - buf[7] == 0xDF && buf[8] == 0x01 && 724 - buf[9] == 0x20) { 725 - xd_card->cis_block = (u16)i; 726 - } 727 - } 728 - 729 - break; 730 - } 731 - 732 - dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block); 733 - if (xd_card->cis_block == 0xFFFF) 734 - return STATUS_FAIL; 735 - 736 - chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; 737 - 738 - return STATUS_SUCCESS; 739 - } 740 - 741 - static int xd_check_data_blank(u8 *redunt) 742 - { 743 - int i; 744 - 745 - for (i = 0; i < 6; i++) { 746 - if (redunt[PAGE_STATUS + i] != 0xFF) 747 - return 0; 748 - } 749 - 750 - if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 751 - != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 752 - return 0; 753 - 754 - for (i = 0; i < 4; i++) { 755 - if (redunt[RESERVED0 + i] != 0xFF) 756 - return 0; 757 - } 758 - 759 - return 1; 760 - } 761 - 762 - static u16 xd_load_log_block_addr(u8 *redunt) 763 - { 764 - u16 addr = 0xFFFF; 765 - 766 - if (redunt[PARITY] & XD_BA1_BA2_EQL) 767 - addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 768 - redunt[BLOCK_ADDR1_L]; 769 - else if (redunt[PARITY] & XD_BA1_VALID) 770 - addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 771 - redunt[BLOCK_ADDR1_L]; 772 - else if (redunt[PARITY] & XD_BA2_VALID) 773 - addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | 774 - redunt[BLOCK_ADDR2_L]; 775 - 776 - return addr; 777 - } 778 - 779 - static int xd_init_l2p_tbl(struct rtsx_chip *chip) 780 - { 781 - struct xd_info *xd_card = &chip->xd_card; 782 - int size, i; 783 - 784 - dev_dbg(rtsx_dev(chip), "%s: zone_cnt = %d\n", __func__, 785 - xd_card->zone_cnt); 786 - 787 - if (xd_card->zone_cnt < 1) 788 - return STATUS_FAIL; 789 - 790 - size = xd_card->zone_cnt * sizeof(struct zone_entry); 791 - dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size); 792 - 793 - xd_card->zone = vmalloc(size); 794 - if (!xd_card->zone) 795 - return STATUS_ERROR; 796 - 797 - for (i = 0; i < xd_card->zone_cnt; i++) { 798 - xd_card->zone[i].build_flag = 0; 799 - xd_card->zone[i].l2p_table = NULL; 800 - xd_card->zone[i].free_table = NULL; 801 - xd_card->zone[i].get_index = 0; 802 - xd_card->zone[i].set_index = 0; 803 - xd_card->zone[i].unused_blk_cnt = 0; 804 - } 805 - 806 - return STATUS_SUCCESS; 807 - } 808 - 809 - static inline void free_zone(struct zone_entry *zone) 810 - { 811 - if (!zone) 812 - return; 813 - 814 - zone->build_flag = 0; 815 - zone->set_index = 0; 816 - zone->get_index = 0; 817 - zone->unused_blk_cnt = 0; 818 - vfree(zone->l2p_table); 819 - zone->l2p_table = NULL; 820 - vfree(zone->free_table); 821 - zone->free_table = NULL; 822 - } 823 - 824 - static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) 825 - { 826 - struct xd_info *xd_card = &chip->xd_card; 827 - struct zone_entry *zone; 828 - int zone_no; 829 - 830 - zone_no = (int)phy_blk >> 10; 831 - if (zone_no >= xd_card->zone_cnt) { 832 - dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n", 833 - zone_no, xd_card->zone_cnt); 834 - return; 835 - } 836 - zone = &xd_card->zone[zone_no]; 837 - 838 - if (!zone->free_table) { 839 - if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) 840 - return; 841 - } 842 - 843 - if (zone->set_index >= XD_FREE_TABLE_CNT || 844 - zone->set_index < 0) { 845 - free_zone(zone); 846 - dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n"); 847 - return; 848 - } 849 - 850 - dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n", 851 - zone->set_index); 852 - 853 - zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff); 854 - if (zone->set_index >= XD_FREE_TABLE_CNT) 855 - zone->set_index = 0; 856 - zone->unused_blk_cnt++; 857 - } 858 - 859 - static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) 860 - { 861 - struct xd_info *xd_card = &chip->xd_card; 862 - struct zone_entry *zone; 863 - u32 phy_blk; 864 - 865 - if (zone_no >= xd_card->zone_cnt) { 866 - dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n", 867 - zone_no, xd_card->zone_cnt); 868 - return BLK_NOT_FOUND; 869 - } 870 - zone = &xd_card->zone[zone_no]; 871 - 872 - if (zone->unused_blk_cnt == 0 || 873 - zone->set_index == zone->get_index) { 874 - free_zone(zone); 875 - dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n"); 876 - return BLK_NOT_FOUND; 877 - } 878 - if (zone->get_index >= XD_FREE_TABLE_CNT || zone->get_index < 0) { 879 - free_zone(zone); 880 - dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n"); 881 - return BLK_NOT_FOUND; 882 - } 883 - 884 - dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n", 885 - zone->get_index); 886 - 887 - phy_blk = zone->free_table[zone->get_index]; 888 - zone->free_table[zone->get_index++] = 0xFFFF; 889 - if (zone->get_index >= XD_FREE_TABLE_CNT) 890 - zone->get_index = 0; 891 - zone->unused_blk_cnt--; 892 - 893 - phy_blk += ((u32)(zone_no) << 10); 894 - return phy_blk; 895 - } 896 - 897 - static void xd_set_l2p_tbl(struct rtsx_chip *chip, 898 - int zone_no, u16 log_off, u16 phy_off) 899 - { 900 - struct xd_info *xd_card = &chip->xd_card; 901 - struct zone_entry *zone; 902 - 903 - zone = &xd_card->zone[zone_no]; 904 - zone->l2p_table[log_off] = phy_off; 905 - } 906 - 907 - static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off) 908 - { 909 - struct xd_info *xd_card = &chip->xd_card; 910 - struct zone_entry *zone; 911 - int retval; 912 - 913 - zone = &xd_card->zone[zone_no]; 914 - if (zone->l2p_table[log_off] == 0xFFFF) { 915 - u32 phy_blk = 0; 916 - int i; 917 - 918 - #ifdef XD_DELAY_WRITE 919 - retval = xd_delay_write(chip); 920 - if (retval != STATUS_SUCCESS) { 921 - dev_dbg(rtsx_dev(chip), "In %s, delay write fail!\n", 922 - __func__); 923 - return BLK_NOT_FOUND; 924 - } 925 - #endif 926 - 927 - if (zone->unused_blk_cnt <= 0) { 928 - dev_dbg(rtsx_dev(chip), "No unused block!\n"); 929 - return BLK_NOT_FOUND; 930 - } 931 - 932 - for (i = 0; i < zone->unused_blk_cnt; i++) { 933 - phy_blk = xd_get_unused_block(chip, zone_no); 934 - if (phy_blk == BLK_NOT_FOUND) { 935 - dev_dbg(rtsx_dev(chip), "No unused block available!\n"); 936 - return BLK_NOT_FOUND; 937 - } 938 - 939 - retval = xd_init_page(chip, phy_blk, log_off, 940 - 0, xd_card->page_off + 1); 941 - if (retval == STATUS_SUCCESS) 942 - break; 943 - } 944 - if (i >= zone->unused_blk_cnt) { 945 - dev_dbg(rtsx_dev(chip), "No good unused block available!\n"); 946 - return BLK_NOT_FOUND; 947 - } 948 - 949 - xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF)); 950 - return phy_blk; 951 - } 952 - 953 - return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10); 954 - } 955 - 956 - int reset_xd_card(struct rtsx_chip *chip) 957 - { 958 - struct xd_info *xd_card = &chip->xd_card; 959 - int retval; 960 - 961 - memset(xd_card, 0, sizeof(struct xd_info)); 962 - 963 - xd_card->block_shift = 0; 964 - xd_card->page_off = 0; 965 - xd_card->addr_cycle = 0; 966 - xd_card->capacity = 0; 967 - xd_card->zone_cnt = 0; 968 - xd_card->cis_block = 0xFFFF; 969 - xd_card->delay_write.delay_write_flag = 0; 970 - 971 - retval = enable_card_clock(chip, XD_CARD); 972 - if (retval != STATUS_SUCCESS) 973 - return STATUS_FAIL; 974 - 975 - retval = reset_xd(chip); 976 - if (retval != STATUS_SUCCESS) 977 - return STATUS_FAIL; 978 - 979 - retval = xd_init_l2p_tbl(chip); 980 - if (retval != STATUS_SUCCESS) 981 - return STATUS_FAIL; 982 - 983 - return STATUS_SUCCESS; 984 - } 985 - 986 - static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) 987 - { 988 - struct xd_info *xd_card = &chip->xd_card; 989 - int retval; 990 - u32 page_addr; 991 - u8 reg = 0; 992 - 993 - dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk); 994 - 995 - if (phy_blk == BLK_NOT_FOUND) 996 - return STATUS_FAIL; 997 - 998 - rtsx_init_cmd(chip); 999 - 1000 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1001 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK); 1002 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF); 1003 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF); 1004 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF); 1005 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF); 1006 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF); 1007 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF); 1008 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF); 1009 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF); 1010 - 1011 - page_addr = phy_blk << xd_card->block_shift; 1012 - 1013 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1014 - 1015 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1016 - xd_card->page_off + 1); 1017 - 1018 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1019 - XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1020 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1021 - XD_TRANSFER_END, XD_TRANSFER_END); 1022 - 1023 - retval = rtsx_send_cmd(chip, XD_CARD, 500); 1024 - if (retval < 0) { 1025 - rtsx_clear_xd_error(chip); 1026 - rtsx_read_register(chip, XD_DAT, &reg); 1027 - if (reg & PROGRAM_ERROR) 1028 - xd_set_err_code(chip, XD_PRG_ERROR); 1029 - else 1030 - xd_set_err_code(chip, XD_TO_ERROR); 1031 - return STATUS_FAIL; 1032 - } 1033 - 1034 - return STATUS_SUCCESS; 1035 - } 1036 - 1037 - static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, 1038 - u16 logoff, u8 start_page, u8 end_page) 1039 - { 1040 - struct xd_info *xd_card = &chip->xd_card; 1041 - int retval; 1042 - u32 page_addr; 1043 - u8 reg = 0; 1044 - 1045 - dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk); 1046 - 1047 - if (start_page > end_page) 1048 - return STATUS_FAIL; 1049 - if (phy_blk == BLK_NOT_FOUND) 1050 - return STATUS_FAIL; 1051 - 1052 - rtsx_init_cmd(chip); 1053 - 1054 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF); 1055 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF); 1056 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1057 - 0xFF, (u8)(logoff >> 8)); 1058 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff); 1059 - 1060 - page_addr = (phy_blk << xd_card->block_shift) + start_page; 1061 - 1062 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1063 - 1064 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 1065 - XD_BA_TRANSFORM, XD_BA_TRANSFORM); 1066 - 1067 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 1068 - 0xFF, (end_page - start_page)); 1069 - 1070 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1071 - 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1072 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1073 - XD_TRANSFER_END, XD_TRANSFER_END); 1074 - 1075 - retval = rtsx_send_cmd(chip, XD_CARD, 500); 1076 - if (retval < 0) { 1077 - rtsx_clear_xd_error(chip); 1078 - rtsx_read_register(chip, XD_DAT, &reg); 1079 - if (reg & PROGRAM_ERROR) { 1080 - xd_mark_bad_block(chip, phy_blk); 1081 - xd_set_err_code(chip, XD_PRG_ERROR); 1082 - } else { 1083 - xd_set_err_code(chip, XD_TO_ERROR); 1084 - } 1085 - return STATUS_FAIL; 1086 - } 1087 - 1088 - return STATUS_SUCCESS; 1089 - } 1090 - 1091 - static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, 1092 - u8 start_page, u8 end_page) 1093 - { 1094 - struct xd_info *xd_card = &chip->xd_card; 1095 - u32 old_page, new_page; 1096 - u8 i, reg = 0; 1097 - int retval; 1098 - 1099 - dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n", 1100 - old_blk, new_blk); 1101 - 1102 - if (start_page > end_page) 1103 - return STATUS_FAIL; 1104 - 1105 - if (old_blk == BLK_NOT_FOUND || new_blk == BLK_NOT_FOUND) 1106 - return STATUS_FAIL; 1107 - 1108 - old_page = (old_blk << xd_card->block_shift) + start_page; 1109 - new_page = (new_blk << xd_card->block_shift) + start_page; 1110 - 1111 - XD_CLR_BAD_NEWBLK(xd_card); 1112 - 1113 - retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, 1114 - PINGPONG_BUFFER); 1115 - if (retval) 1116 - return retval; 1117 - 1118 - for (i = start_page; i < end_page; i++) { 1119 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1120 - rtsx_clear_xd_error(chip); 1121 - xd_set_err_code(chip, XD_NO_CARD); 1122 - return STATUS_FAIL; 1123 - } 1124 - 1125 - rtsx_init_cmd(chip); 1126 - 1127 - xd_assign_phy_addr(chip, old_page, XD_RW_ADDR); 1128 - 1129 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1130 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1131 - XD_AUTO_CHK_DATA_STATUS, 0); 1132 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1133 - XD_TRANSFER_START | XD_READ_PAGES); 1134 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1135 - XD_TRANSFER_END, XD_TRANSFER_END); 1136 - 1137 - retval = rtsx_send_cmd(chip, XD_CARD, 500); 1138 - if (retval < 0) { 1139 - rtsx_clear_xd_error(chip); 1140 - reg = 0; 1141 - rtsx_read_register(chip, XD_CTL, &reg); 1142 - if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { 1143 - mdelay(100); 1144 - 1145 - if (detect_card_cd(chip, 1146 - XD_CARD) != STATUS_SUCCESS) { 1147 - xd_set_err_code(chip, XD_NO_CARD); 1148 - return STATUS_FAIL; 1149 - } 1150 - 1151 - if (((reg & XD_ECC1_ERROR) && 1152 - (reg & XD_ECC1_UNCORRECTABLE)) || 1153 - ((reg & XD_ECC2_ERROR) && 1154 - (reg & XD_ECC2_UNCORRECTABLE))) { 1155 - rtsx_write_register(chip, 1156 - XD_PAGE_STATUS, 1157 - 0xFF, 1158 - XD_BPG); 1159 - rtsx_write_register(chip, 1160 - XD_BLOCK_STATUS, 1161 - 0xFF, 1162 - XD_GBLK); 1163 - XD_SET_BAD_OLDBLK(xd_card); 1164 - dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n", 1165 - old_blk); 1166 - } 1167 - } else { 1168 - xd_set_err_code(chip, XD_TO_ERROR); 1169 - return STATUS_FAIL; 1170 - } 1171 - } 1172 - 1173 - if (XD_CHK_BAD_OLDBLK(xd_card)) 1174 - rtsx_clear_xd_error(chip); 1175 - 1176 - rtsx_init_cmd(chip); 1177 - 1178 - xd_assign_phy_addr(chip, new_page, XD_RW_ADDR); 1179 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1180 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1181 - XD_TRANSFER_START | XD_WRITE_PAGES); 1182 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1183 - XD_TRANSFER_END, XD_TRANSFER_END); 1184 - 1185 - retval = rtsx_send_cmd(chip, XD_CARD, 300); 1186 - if (retval < 0) { 1187 - rtsx_clear_xd_error(chip); 1188 - reg = 0; 1189 - rtsx_read_register(chip, XD_DAT, &reg); 1190 - if (reg & PROGRAM_ERROR) { 1191 - xd_mark_bad_block(chip, new_blk); 1192 - xd_set_err_code(chip, XD_PRG_ERROR); 1193 - XD_SET_BAD_NEWBLK(xd_card); 1194 - } else { 1195 - xd_set_err_code(chip, XD_TO_ERROR); 1196 - } 1197 - return STATUS_FAIL; 1198 - } 1199 - 1200 - old_page++; 1201 - new_page++; 1202 - } 1203 - 1204 - return STATUS_SUCCESS; 1205 - } 1206 - 1207 - static int xd_reset_cmd(struct rtsx_chip *chip) 1208 - { 1209 - int retval; 1210 - u8 *ptr; 1211 - 1212 - rtsx_init_cmd(chip); 1213 - 1214 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1215 - 0xFF, XD_TRANSFER_START | XD_RESET); 1216 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1217 - XD_TRANSFER_END, XD_TRANSFER_END); 1218 - rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1219 - rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 1220 - 1221 - retval = rtsx_send_cmd(chip, XD_CARD, 100); 1222 - if (retval < 0) 1223 - return STATUS_FAIL; 1224 - 1225 - ptr = rtsx_get_cmd_data(chip) + 1; 1226 - if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) 1227 - return STATUS_SUCCESS; 1228 - 1229 - return STATUS_FAIL; 1230 - } 1231 - 1232 - static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) 1233 - { 1234 - struct xd_info *xd_card = &chip->xd_card; 1235 - u32 page_addr; 1236 - u8 reg = 0, *ptr; 1237 - int i, retval; 1238 - 1239 - if (phy_blk == BLK_NOT_FOUND) 1240 - return STATUS_FAIL; 1241 - 1242 - page_addr = phy_blk << xd_card->block_shift; 1243 - 1244 - for (i = 0; i < 3; i++) { 1245 - rtsx_init_cmd(chip); 1246 - 1247 - xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR); 1248 - 1249 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1250 - XD_TRANSFER_START | XD_ERASE); 1251 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1252 - XD_TRANSFER_END, XD_TRANSFER_END); 1253 - rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1254 - 1255 - retval = rtsx_send_cmd(chip, XD_CARD, 250); 1256 - if (retval < 0) { 1257 - rtsx_clear_xd_error(chip); 1258 - rtsx_read_register(chip, XD_DAT, &reg); 1259 - if (reg & PROGRAM_ERROR) { 1260 - xd_mark_bad_block(chip, phy_blk); 1261 - xd_set_err_code(chip, XD_PRG_ERROR); 1262 - return STATUS_FAIL; 1263 - } 1264 - xd_set_err_code(chip, XD_ERASE_FAIL); 1265 - retval = xd_reset_cmd(chip); 1266 - if (retval != STATUS_SUCCESS) 1267 - return STATUS_FAIL; 1268 - continue; 1269 - } 1270 - 1271 - ptr = rtsx_get_cmd_data(chip) + 1; 1272 - if (*ptr & PROGRAM_ERROR) { 1273 - xd_mark_bad_block(chip, phy_blk); 1274 - xd_set_err_code(chip, XD_PRG_ERROR); 1275 - return STATUS_FAIL; 1276 - } 1277 - 1278 - return STATUS_SUCCESS; 1279 - } 1280 - 1281 - xd_mark_bad_block(chip, phy_blk); 1282 - xd_set_err_code(chip, XD_ERASE_FAIL); 1283 - return STATUS_FAIL; 1284 - } 1285 - 1286 - static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) 1287 - { 1288 - struct xd_info *xd_card = &chip->xd_card; 1289 - struct zone_entry *zone; 1290 - int retval; 1291 - u32 start, end, i; 1292 - u16 max_logoff, cur_fst_page_logoff; 1293 - u16 cur_lst_page_logoff, ent_lst_page_logoff; 1294 - u8 redunt[11]; 1295 - 1296 - dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, zone_no); 1297 - 1298 - if (!xd_card->zone) { 1299 - retval = xd_init_l2p_tbl(chip); 1300 - if (retval != STATUS_SUCCESS) 1301 - return retval; 1302 - } 1303 - 1304 - if (xd_card->zone[zone_no].build_flag) { 1305 - dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n", 1306 - zone_no); 1307 - return STATUS_SUCCESS; 1308 - } 1309 - 1310 - zone = &xd_card->zone[zone_no]; 1311 - 1312 - if (!zone->l2p_table) { 1313 - zone->l2p_table = vmalloc(2000); 1314 - if (!zone->l2p_table) 1315 - goto build_fail; 1316 - } 1317 - memset((u8 *)(zone->l2p_table), 0xff, 2000); 1318 - 1319 - if (!zone->free_table) { 1320 - zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2); 1321 - if (!zone->free_table) 1322 - goto build_fail; 1323 - } 1324 - memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); 1325 - 1326 - if (zone_no == 0) { 1327 - if (xd_card->cis_block == 0xFFFF) 1328 - start = 0; 1329 - else 1330 - start = xd_card->cis_block + 1; 1331 - if (XD_CHK_4MB(xd_card)) { 1332 - end = 0x200; 1333 - max_logoff = 499; 1334 - } else { 1335 - end = 0x400; 1336 - max_logoff = 999; 1337 - } 1338 - } else { 1339 - start = (u32)(zone_no) << 10; 1340 - end = (u32)(zone_no + 1) << 10; 1341 - max_logoff = 999; 1342 - } 1343 - 1344 - dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n", 1345 - start, end); 1346 - 1347 - zone->set_index = 0; 1348 - zone->get_index = 0; 1349 - zone->unused_blk_cnt = 0; 1350 - 1351 - for (i = start; i < end; i++) { 1352 - u32 page_addr = i << xd_card->block_shift; 1353 - u32 phy_block; 1354 - 1355 - retval = xd_read_redundant(chip, page_addr, redunt, 11); 1356 - if (retval != STATUS_SUCCESS) 1357 - continue; 1358 - 1359 - if (redunt[BLOCK_STATUS] != 0xFF) { 1360 - dev_dbg(rtsx_dev(chip), "bad block\n"); 1361 - continue; 1362 - } 1363 - 1364 - if (xd_check_data_blank(redunt)) { 1365 - dev_dbg(rtsx_dev(chip), "blank block\n"); 1366 - xd_set_unused_block(chip, i); 1367 - continue; 1368 - } 1369 - 1370 - cur_fst_page_logoff = xd_load_log_block_addr(redunt); 1371 - if (cur_fst_page_logoff == 0xFFFF || 1372 - cur_fst_page_logoff > max_logoff) { 1373 - retval = xd_erase_block(chip, i); 1374 - if (retval == STATUS_SUCCESS) 1375 - xd_set_unused_block(chip, i); 1376 - continue; 1377 - } 1378 - 1379 - if (zone_no == 0 && cur_fst_page_logoff == 0 && 1380 - redunt[PAGE_STATUS] != XD_GPG) 1381 - XD_SET_MBR_FAIL(xd_card); 1382 - 1383 - if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { 1384 - zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); 1385 - continue; 1386 - } 1387 - 1388 - phy_block = zone->l2p_table[cur_fst_page_logoff] + 1389 - ((u32)((zone_no) << 10)); 1390 - 1391 - page_addr = ((i + 1) << xd_card->block_shift) - 1; 1392 - 1393 - retval = xd_read_redundant(chip, page_addr, redunt, 11); 1394 - if (retval != STATUS_SUCCESS) 1395 - continue; 1396 - 1397 - cur_lst_page_logoff = xd_load_log_block_addr(redunt); 1398 - if (cur_lst_page_logoff == cur_fst_page_logoff) { 1399 - int m; 1400 - 1401 - page_addr = ((phy_block + 1) << 1402 - xd_card->block_shift) - 1; 1403 - 1404 - for (m = 0; m < 3; m++) { 1405 - retval = xd_read_redundant(chip, page_addr, 1406 - redunt, 11); 1407 - if (retval == STATUS_SUCCESS) 1408 - break; 1409 - } 1410 - 1411 - if (m == 3) { 1412 - zone->l2p_table[cur_fst_page_logoff] = 1413 - (u16)(i & 0x3FF); 1414 - retval = xd_erase_block(chip, phy_block); 1415 - if (retval == STATUS_SUCCESS) 1416 - xd_set_unused_block(chip, phy_block); 1417 - continue; 1418 - } 1419 - 1420 - ent_lst_page_logoff = xd_load_log_block_addr(redunt); 1421 - if (ent_lst_page_logoff != cur_fst_page_logoff) { 1422 - zone->l2p_table[cur_fst_page_logoff] = 1423 - (u16)(i & 0x3FF); 1424 - retval = xd_erase_block(chip, phy_block); 1425 - if (retval == STATUS_SUCCESS) 1426 - xd_set_unused_block(chip, phy_block); 1427 - continue; 1428 - } else { 1429 - retval = xd_erase_block(chip, i); 1430 - if (retval == STATUS_SUCCESS) 1431 - xd_set_unused_block(chip, i); 1432 - } 1433 - } else { 1434 - retval = xd_erase_block(chip, i); 1435 - if (retval == STATUS_SUCCESS) 1436 - xd_set_unused_block(chip, i); 1437 - } 1438 - } 1439 - 1440 - if (XD_CHK_4MB(xd_card)) 1441 - end = 500; 1442 - else 1443 - end = 1000; 1444 - 1445 - i = 0; 1446 - for (start = 0; start < end; start++) { 1447 - if (zone->l2p_table[start] == 0xFFFF) 1448 - i++; 1449 - } 1450 - 1451 - dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n", 1452 - end, i); 1453 - dev_dbg(rtsx_dev(chip), "Total unused block: %d\n", 1454 - zone->unused_blk_cnt); 1455 - 1456 - if ((zone->unused_blk_cnt - i) < 1) 1457 - chip->card_wp |= XD_CARD; 1458 - 1459 - zone->build_flag = 1; 1460 - 1461 - return STATUS_SUCCESS; 1462 - 1463 - build_fail: 1464 - vfree(zone->l2p_table); 1465 - zone->l2p_table = NULL; 1466 - vfree(zone->free_table); 1467 - zone->free_table = NULL; 1468 - 1469 - return STATUS_FAIL; 1470 - } 1471 - 1472 - static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) 1473 - { 1474 - int retval; 1475 - 1476 - rtsx_init_cmd(chip); 1477 - 1478 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd); 1479 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1480 - XD_TRANSFER_START | XD_SET_CMD); 1481 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1482 - XD_TRANSFER_END, XD_TRANSFER_END); 1483 - 1484 - retval = rtsx_send_cmd(chip, XD_CARD, 200); 1485 - if (retval < 0) 1486 - return STATUS_FAIL; 1487 - 1488 - return STATUS_SUCCESS; 1489 - } 1490 - 1491 - static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, 1492 - u32 log_blk, u8 start_page, u8 end_page, 1493 - u8 *buf, unsigned int *index, 1494 - unsigned int *offset) 1495 - { 1496 - struct xd_info *xd_card = &chip->xd_card; 1497 - u32 page_addr, new_blk; 1498 - u16 log_off; 1499 - u8 reg_val, page_cnt; 1500 - int zone_no, retval, i; 1501 - 1502 - if (start_page > end_page) 1503 - goto status_fail; 1504 - 1505 - page_cnt = end_page - start_page; 1506 - zone_no = (int)(log_blk / 1000); 1507 - log_off = (u16)(log_blk % 1000); 1508 - 1509 - if ((phy_blk & 0x3FF) == 0x3FF) { 1510 - for (i = 0; i < 256; i++) { 1511 - page_addr = ((u32)i) << xd_card->block_shift; 1512 - 1513 - retval = xd_read_redundant(chip, page_addr, NULL, 0); 1514 - if (retval == STATUS_SUCCESS) 1515 - break; 1516 - 1517 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1518 - xd_set_err_code(chip, XD_NO_CARD); 1519 - goto status_fail; 1520 - } 1521 - } 1522 - } 1523 - 1524 - page_addr = (phy_blk << xd_card->block_shift) + start_page; 1525 - 1526 - rtsx_init_cmd(chip); 1527 - 1528 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1529 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE); 1530 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1531 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1532 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1533 - XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 1534 - 1535 - trans_dma_enable(chip->srb->sc_data_direction, chip, 1536 - page_cnt * 512, DMA_512); 1537 - 1538 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1539 - XD_TRANSFER_START | XD_READ_PAGES); 1540 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1541 - XD_TRANSFER_END | XD_PPB_EMPTY, 1542 - XD_TRANSFER_END | XD_PPB_EMPTY); 1543 - 1544 - rtsx_send_cmd_no_wait(chip); 1545 - 1546 - retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1547 - scsi_sg_count(chip->srb), 1548 - index, offset, DMA_FROM_DEVICE, 1549 - chip->xd_timeout); 1550 - if (retval < 0) { 1551 - rtsx_clear_xd_error(chip); 1552 - 1553 - if (retval == -ETIMEDOUT) { 1554 - xd_set_err_code(chip, XD_TO_ERROR); 1555 - goto status_fail; 1556 - } else { 1557 - goto fail; 1558 - } 1559 - } 1560 - 1561 - return STATUS_SUCCESS; 1562 - 1563 - fail: 1564 - retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg_val); 1565 - if (retval) 1566 - return retval; 1567 - 1568 - if (reg_val != XD_GPG) 1569 - xd_set_err_code(chip, XD_PRG_ERROR); 1570 - 1571 - retval = rtsx_read_register(chip, XD_CTL, &reg_val); 1572 - if (retval) 1573 - return retval; 1574 - 1575 - if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == 1576 - (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) || 1577 - ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == 1578 - (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { 1579 - wait_timeout(100); 1580 - 1581 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1582 - xd_set_err_code(chip, XD_NO_CARD); 1583 - goto status_fail; 1584 - } 1585 - 1586 - xd_set_err_code(chip, XD_ECC_ERROR); 1587 - 1588 - new_blk = xd_get_unused_block(chip, zone_no); 1589 - if (new_blk == NO_NEW_BLK) { 1590 - XD_CLR_BAD_OLDBLK(xd_card); 1591 - goto status_fail; 1592 - } 1593 - 1594 - retval = xd_copy_page(chip, phy_blk, new_blk, 0, 1595 - xd_card->page_off + 1); 1596 - if (retval != STATUS_SUCCESS) { 1597 - if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1598 - retval = xd_erase_block(chip, new_blk); 1599 - if (retval == STATUS_SUCCESS) 1600 - xd_set_unused_block(chip, new_blk); 1601 - } else { 1602 - XD_CLR_BAD_NEWBLK(xd_card); 1603 - } 1604 - XD_CLR_BAD_OLDBLK(xd_card); 1605 - goto status_fail; 1606 - } 1607 - xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1608 - xd_erase_block(chip, phy_blk); 1609 - xd_mark_bad_block(chip, phy_blk); 1610 - XD_CLR_BAD_OLDBLK(xd_card); 1611 - } 1612 - 1613 - status_fail: 1614 - return STATUS_FAIL; 1615 - } 1616 - 1617 - static int xd_finish_write(struct rtsx_chip *chip, 1618 - u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1619 - { 1620 - struct xd_info *xd_card = &chip->xd_card; 1621 - int retval, zone_no; 1622 - u16 log_off; 1623 - 1624 - dev_dbg(rtsx_dev(chip), "old_blk = 0x%x, ", old_blk); 1625 - dev_dbg(rtsx_dev(chip), "new_blk = 0x%x, ", new_blk); 1626 - dev_dbg(rtsx_dev(chip), "log_blk = 0x%x\n", log_blk); 1627 - 1628 - if (page_off > xd_card->page_off) 1629 - return STATUS_FAIL; 1630 - 1631 - zone_no = (int)(log_blk / 1000); 1632 - log_off = (u16)(log_blk % 1000); 1633 - 1634 - if (old_blk == BLK_NOT_FOUND) { 1635 - retval = xd_init_page(chip, new_blk, log_off, 1636 - page_off, xd_card->page_off + 1); 1637 - if (retval != STATUS_SUCCESS) { 1638 - retval = xd_erase_block(chip, new_blk); 1639 - if (retval == STATUS_SUCCESS) 1640 - xd_set_unused_block(chip, new_blk); 1641 - return STATUS_FAIL; 1642 - } 1643 - } else { 1644 - retval = xd_copy_page(chip, old_blk, new_blk, 1645 - page_off, xd_card->page_off + 1); 1646 - if (retval != STATUS_SUCCESS) { 1647 - if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1648 - retval = xd_erase_block(chip, new_blk); 1649 - if (retval == STATUS_SUCCESS) 1650 - xd_set_unused_block(chip, new_blk); 1651 - } 1652 - XD_CLR_BAD_NEWBLK(xd_card); 1653 - return STATUS_FAIL; 1654 - } 1655 - 1656 - retval = xd_erase_block(chip, old_blk); 1657 - if (retval == STATUS_SUCCESS) { 1658 - if (XD_CHK_BAD_OLDBLK(xd_card)) { 1659 - xd_mark_bad_block(chip, old_blk); 1660 - XD_CLR_BAD_OLDBLK(xd_card); 1661 - } else { 1662 - xd_set_unused_block(chip, old_blk); 1663 - } 1664 - } else { 1665 - xd_set_err_code(chip, XD_NO_ERROR); 1666 - XD_CLR_BAD_OLDBLK(xd_card); 1667 - } 1668 - } 1669 - 1670 - xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1671 - 1672 - return STATUS_SUCCESS; 1673 - } 1674 - 1675 - static int xd_prepare_write(struct rtsx_chip *chip, 1676 - u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1677 - { 1678 - int retval; 1679 - 1680 - dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n", 1681 - __func__, old_blk, new_blk, log_blk, (int)page_off); 1682 - 1683 - if (page_off) { 1684 - retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); 1685 - if (retval != STATUS_SUCCESS) 1686 - return STATUS_FAIL; 1687 - } 1688 - 1689 - return STATUS_SUCCESS; 1690 - } 1691 - 1692 - static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, 1693 - u32 new_blk, u32 log_blk, u8 start_page, 1694 - u8 end_page, u8 *buf, unsigned int *index, 1695 - unsigned int *offset) 1696 - { 1697 - struct xd_info *xd_card = &chip->xd_card; 1698 - u32 page_addr; 1699 - int zone_no, retval; 1700 - u16 log_off; 1701 - u8 page_cnt, reg_val; 1702 - 1703 - dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", 1704 - __func__, old_blk, new_blk, log_blk); 1705 - 1706 - if (start_page > end_page) 1707 - goto status_fail; 1708 - 1709 - page_cnt = end_page - start_page; 1710 - zone_no = (int)(log_blk / 1000); 1711 - log_off = (u16)(log_blk % 1000); 1712 - 1713 - page_addr = (new_blk << xd_card->block_shift) + start_page; 1714 - 1715 - retval = xd_send_cmd(chip, READ1_1); 1716 - if (retval != STATUS_SUCCESS) 1717 - goto status_fail; 1718 - 1719 - rtsx_init_cmd(chip); 1720 - 1721 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1722 - 0xFF, (u8)(log_off >> 8)); 1723 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off); 1724 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK); 1725 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1726 - 1727 - xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1728 - 1729 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, 1730 - XD_BA_TRANSFORM); 1731 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1732 - rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1733 - 1734 - trans_dma_enable(chip->srb->sc_data_direction, chip, 1735 - page_cnt * 512, DMA_512); 1736 - 1737 - rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1738 - 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES); 1739 - rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1740 - XD_TRANSFER_END, XD_TRANSFER_END); 1741 - 1742 - rtsx_send_cmd_no_wait(chip); 1743 - 1744 - retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1745 - scsi_sg_count(chip->srb), 1746 - index, offset, DMA_TO_DEVICE, chip->xd_timeout); 1747 - if (retval < 0) { 1748 - rtsx_clear_xd_error(chip); 1749 - 1750 - if (retval == -ETIMEDOUT) { 1751 - xd_set_err_code(chip, XD_TO_ERROR); 1752 - goto status_fail; 1753 - } else { 1754 - goto fail; 1755 - } 1756 - } 1757 - 1758 - if (end_page == (xd_card->page_off + 1)) { 1759 - xd_card->delay_write.delay_write_flag = 0; 1760 - 1761 - if (old_blk != BLK_NOT_FOUND) { 1762 - retval = xd_erase_block(chip, old_blk); 1763 - if (retval == STATUS_SUCCESS) { 1764 - if (XD_CHK_BAD_OLDBLK(xd_card)) { 1765 - xd_mark_bad_block(chip, old_blk); 1766 - XD_CLR_BAD_OLDBLK(xd_card); 1767 - } else { 1768 - xd_set_unused_block(chip, old_blk); 1769 - } 1770 - } else { 1771 - xd_set_err_code(chip, XD_NO_ERROR); 1772 - XD_CLR_BAD_OLDBLK(xd_card); 1773 - } 1774 - } 1775 - xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1776 - } 1777 - 1778 - return STATUS_SUCCESS; 1779 - 1780 - fail: 1781 - retval = rtsx_read_register(chip, XD_DAT, &reg_val); 1782 - if (retval) 1783 - return retval; 1784 - if (reg_val & PROGRAM_ERROR) { 1785 - xd_set_err_code(chip, XD_PRG_ERROR); 1786 - xd_mark_bad_block(chip, new_blk); 1787 - } 1788 - 1789 - status_fail: 1790 - return STATUS_FAIL; 1791 - } 1792 - 1793 - #ifdef XD_DELAY_WRITE 1794 - int xd_delay_write(struct rtsx_chip *chip) 1795 - { 1796 - struct xd_info *xd_card = &chip->xd_card; 1797 - struct xd_delay_write_tag *delay_write = &xd_card->delay_write; 1798 - int retval; 1799 - 1800 - if (delay_write->delay_write_flag) { 1801 - retval = xd_switch_clock(chip); 1802 - if (retval != STATUS_SUCCESS) 1803 - return STATUS_FAIL; 1804 - 1805 - delay_write->delay_write_flag = 0; 1806 - retval = xd_finish_write(chip, 1807 - delay_write->old_phyblock, 1808 - delay_write->new_phyblock, 1809 - delay_write->logblock, 1810 - delay_write->pageoff); 1811 - if (retval != STATUS_SUCCESS) 1812 - return STATUS_FAIL; 1813 - } 1814 - 1815 - return STATUS_SUCCESS; 1816 - } 1817 - #endif 1818 - 1819 - int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 1820 - u32 start_sector, u16 sector_cnt) 1821 - { 1822 - struct xd_info *xd_card = &chip->xd_card; 1823 - unsigned int lun = SCSI_LUN(srb); 1824 - #ifdef XD_DELAY_WRITE 1825 - struct xd_delay_write_tag *delay_write = &xd_card->delay_write; 1826 - #endif 1827 - int retval, zone_no; 1828 - unsigned int index = 0, offset = 0; 1829 - u32 log_blk, old_blk = 0, new_blk = 0; 1830 - u16 log_off, total_sec_cnt = sector_cnt; 1831 - u8 start_page, end_page = 0, page_cnt; 1832 - u8 *ptr; 1833 - 1834 - xd_set_err_code(chip, XD_NO_ERROR); 1835 - 1836 - xd_card->cleanup_counter = 0; 1837 - 1838 - dev_dbg(rtsx_dev(chip), "%s: scsi_sg_count = %d\n", __func__, 1839 - scsi_sg_count(srb)); 1840 - 1841 - ptr = (u8 *)scsi_sglist(srb); 1842 - 1843 - retval = xd_switch_clock(chip); 1844 - if (retval != STATUS_SUCCESS) 1845 - return STATUS_FAIL; 1846 - 1847 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1848 - chip->card_fail |= XD_CARD; 1849 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1850 - return STATUS_FAIL; 1851 - } 1852 - 1853 - log_blk = start_sector >> xd_card->block_shift; 1854 - start_page = (u8)start_sector & xd_card->page_off; 1855 - zone_no = (int)(log_blk / 1000); 1856 - log_off = (u16)(log_blk % 1000); 1857 - 1858 - if (xd_card->zone[zone_no].build_flag == 0) { 1859 - retval = xd_build_l2p_tbl(chip, zone_no); 1860 - if (retval != STATUS_SUCCESS) { 1861 - chip->card_fail |= XD_CARD; 1862 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1863 - return STATUS_FAIL; 1864 - } 1865 - } 1866 - 1867 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 1868 - #ifdef XD_DELAY_WRITE 1869 - if (delay_write->delay_write_flag && 1870 - delay_write->logblock == log_blk && 1871 - start_page > delay_write->pageoff) { 1872 - delay_write->delay_write_flag = 0; 1873 - if (delay_write->old_phyblock != BLK_NOT_FOUND) { 1874 - retval = xd_copy_page(chip, 1875 - delay_write->old_phyblock, 1876 - delay_write->new_phyblock, 1877 - delay_write->pageoff, 1878 - start_page); 1879 - if (retval != STATUS_SUCCESS) { 1880 - set_sense_type(chip, lun, 1881 - SENSE_TYPE_MEDIA_WRITE_ERR); 1882 - return STATUS_FAIL; 1883 - } 1884 - } 1885 - old_blk = delay_write->old_phyblock; 1886 - new_blk = delay_write->new_phyblock; 1887 - } else if (delay_write->delay_write_flag && 1888 - (delay_write->logblock == log_blk) && 1889 - (start_page == delay_write->pageoff)) { 1890 - delay_write->delay_write_flag = 0; 1891 - old_blk = delay_write->old_phyblock; 1892 - new_blk = delay_write->new_phyblock; 1893 - } else { 1894 - retval = xd_delay_write(chip); 1895 - if (retval != STATUS_SUCCESS) { 1896 - set_sense_type(chip, lun, 1897 - SENSE_TYPE_MEDIA_WRITE_ERR); 1898 - return STATUS_FAIL; 1899 - } 1900 - #endif 1901 - old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 1902 - new_blk = xd_get_unused_block(chip, zone_no); 1903 - if (old_blk == BLK_NOT_FOUND || 1904 - new_blk == BLK_NOT_FOUND) { 1905 - set_sense_type(chip, lun, 1906 - SENSE_TYPE_MEDIA_WRITE_ERR); 1907 - return STATUS_FAIL; 1908 - } 1909 - 1910 - retval = xd_prepare_write(chip, old_blk, new_blk, 1911 - log_blk, start_page); 1912 - if (retval != STATUS_SUCCESS) { 1913 - if (detect_card_cd(chip, XD_CARD) != 1914 - STATUS_SUCCESS) { 1915 - set_sense_type(chip, lun, 1916 - SENSE_TYPE_MEDIA_NOT_PRESENT); 1917 - return STATUS_FAIL; 1918 - } 1919 - set_sense_type(chip, lun, 1920 - SENSE_TYPE_MEDIA_WRITE_ERR); 1921 - return STATUS_FAIL; 1922 - } 1923 - #ifdef XD_DELAY_WRITE 1924 - } 1925 - #endif 1926 - } else { 1927 - #ifdef XD_DELAY_WRITE 1928 - retval = xd_delay_write(chip); 1929 - if (retval != STATUS_SUCCESS) { 1930 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1931 - set_sense_type(chip, lun, 1932 - SENSE_TYPE_MEDIA_NOT_PRESENT); 1933 - return STATUS_FAIL; 1934 - } 1935 - set_sense_type(chip, lun, 1936 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1937 - return STATUS_FAIL; 1938 - } 1939 - #endif 1940 - 1941 - old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 1942 - if (old_blk == BLK_NOT_FOUND) { 1943 - set_sense_type(chip, lun, 1944 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1945 - return STATUS_FAIL; 1946 - } 1947 - } 1948 - 1949 - dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk); 1950 - 1951 - while (total_sec_cnt) { 1952 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1953 - chip->card_fail |= XD_CARD; 1954 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1955 - return STATUS_FAIL; 1956 - } 1957 - 1958 - if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) 1959 - end_page = xd_card->page_off + 1; 1960 - else 1961 - end_page = start_page + (u8)total_sec_cnt; 1962 - 1963 - page_cnt = end_page - start_page; 1964 - if (srb->sc_data_direction == DMA_FROM_DEVICE) { 1965 - retval = xd_read_multiple_pages(chip, old_blk, log_blk, 1966 - start_page, end_page, 1967 - ptr, &index, &offset); 1968 - if (retval != STATUS_SUCCESS) { 1969 - set_sense_type(chip, lun, 1970 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 1971 - return STATUS_FAIL; 1972 - } 1973 - } else { 1974 - retval = xd_write_multiple_pages(chip, old_blk, 1975 - new_blk, log_blk, 1976 - start_page, end_page, 1977 - ptr, &index, &offset); 1978 - if (retval != STATUS_SUCCESS) { 1979 - set_sense_type(chip, lun, 1980 - SENSE_TYPE_MEDIA_WRITE_ERR); 1981 - return STATUS_FAIL; 1982 - } 1983 - } 1984 - 1985 - total_sec_cnt -= page_cnt; 1986 - if (scsi_sg_count(srb) == 0) 1987 - ptr += page_cnt * 512; 1988 - 1989 - if (total_sec_cnt == 0) 1990 - break; 1991 - 1992 - log_blk++; 1993 - zone_no = (int)(log_blk / 1000); 1994 - log_off = (u16)(log_blk % 1000); 1995 - 1996 - if (xd_card->zone[zone_no].build_flag == 0) { 1997 - retval = xd_build_l2p_tbl(chip, zone_no); 1998 - if (retval != STATUS_SUCCESS) { 1999 - chip->card_fail |= XD_CARD; 2000 - set_sense_type(chip, lun, 2001 - SENSE_TYPE_MEDIA_NOT_PRESENT); 2002 - return STATUS_FAIL; 2003 - } 2004 - } 2005 - 2006 - old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2007 - if (old_blk == BLK_NOT_FOUND) { 2008 - if (srb->sc_data_direction == DMA_FROM_DEVICE) 2009 - set_sense_type(chip, lun, 2010 - SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2011 - else 2012 - set_sense_type(chip, lun, 2013 - SENSE_TYPE_MEDIA_WRITE_ERR); 2014 - 2015 - return STATUS_FAIL; 2016 - } 2017 - 2018 - if (srb->sc_data_direction == DMA_TO_DEVICE) { 2019 - new_blk = xd_get_unused_block(chip, zone_no); 2020 - if (new_blk == BLK_NOT_FOUND) { 2021 - set_sense_type(chip, lun, 2022 - SENSE_TYPE_MEDIA_WRITE_ERR); 2023 - return STATUS_FAIL; 2024 - } 2025 - } 2026 - 2027 - start_page = 0; 2028 - } 2029 - 2030 - if (srb->sc_data_direction == DMA_TO_DEVICE && 2031 - (end_page != (xd_card->page_off + 1))) { 2032 - #ifdef XD_DELAY_WRITE 2033 - delay_write->delay_write_flag = 1; 2034 - delay_write->old_phyblock = old_blk; 2035 - delay_write->new_phyblock = new_blk; 2036 - delay_write->logblock = log_blk; 2037 - delay_write->pageoff = end_page; 2038 - #else 2039 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2040 - chip->card_fail |= XD_CARD; 2041 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2042 - return STATUS_FAIL; 2043 - } 2044 - 2045 - retval = xd_finish_write(chip, old_blk, new_blk, 2046 - log_blk, end_page); 2047 - if (retval != STATUS_SUCCESS) { 2048 - if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2049 - set_sense_type(chip, lun, 2050 - SENSE_TYPE_MEDIA_NOT_PRESENT); 2051 - return STATUS_FAIL; 2052 - } 2053 - set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 2054 - return STATUS_FAIL; 2055 - } 2056 - #endif 2057 - } 2058 - 2059 - scsi_set_resid(srb, 0); 2060 - 2061 - return STATUS_SUCCESS; 2062 - } 2063 - 2064 - void xd_free_l2p_tbl(struct rtsx_chip *chip) 2065 - { 2066 - struct xd_info *xd_card = &chip->xd_card; 2067 - int i = 0; 2068 - 2069 - if (xd_card->zone) { 2070 - for (i = 0; i < xd_card->zone_cnt; i++) { 2071 - vfree(xd_card->zone[i].l2p_table); 2072 - xd_card->zone[i].l2p_table = NULL; 2073 - vfree(xd_card->zone[i].free_table); 2074 - xd_card->zone[i].free_table = NULL; 2075 - } 2076 - vfree(xd_card->zone); 2077 - xd_card->zone = NULL; 2078 - } 2079 - } 2080 - 2081 - void xd_cleanup_work(struct rtsx_chip *chip) 2082 - { 2083 - #ifdef XD_DELAY_WRITE 2084 - struct xd_info *xd_card = &chip->xd_card; 2085 - 2086 - if (xd_card->delay_write.delay_write_flag) { 2087 - dev_dbg(rtsx_dev(chip), "xD: delay write\n"); 2088 - xd_delay_write(chip); 2089 - xd_card->cleanup_counter = 0; 2090 - } 2091 - #endif 2092 - } 2093 - 2094 - int xd_power_off_card3v3(struct rtsx_chip *chip) 2095 - { 2096 - int retval; 2097 - 2098 - retval = disable_card_clock(chip, XD_CARD); 2099 - if (retval != STATUS_SUCCESS) 2100 - return STATUS_FAIL; 2101 - 2102 - retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 2103 - if (retval) 2104 - return retval; 2105 - 2106 - if (!chip->ft2_fast_mode) { 2107 - retval = card_power_off(chip, XD_CARD); 2108 - if (retval != STATUS_SUCCESS) 2109 - return STATUS_FAIL; 2110 - 2111 - wait_timeout(50); 2112 - } 2113 - 2114 - if (chip->asic_code) { 2115 - retval = xd_pull_ctl_disable(chip); 2116 - if (retval != STATUS_SUCCESS) 2117 - return STATUS_FAIL; 2118 - } else { 2119 - retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); 2120 - if (retval) 2121 - return retval; 2122 - } 2123 - 2124 - return STATUS_SUCCESS; 2125 - } 2126 - 2127 - int release_xd_card(struct rtsx_chip *chip) 2128 - { 2129 - struct xd_info *xd_card = &chip->xd_card; 2130 - int retval; 2131 - 2132 - chip->card_ready &= ~XD_CARD; 2133 - chip->card_fail &= ~XD_CARD; 2134 - chip->card_wp &= ~XD_CARD; 2135 - 2136 - xd_card->delay_write.delay_write_flag = 0; 2137 - 2138 - xd_free_l2p_tbl(chip); 2139 - 2140 - retval = xd_power_off_card3v3(chip); 2141 - if (retval != STATUS_SUCCESS) 2142 - return STATUS_FAIL; 2143 - 2144 - return STATUS_SUCCESS; 2145 - }
-176
drivers/staging/rts5208/xd.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * Driver for Realtek PCI-Express card reader 4 - * 5 - * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 - * 7 - * Author: 8 - * Wei WANG (wei_wang@realsil.com.cn) 9 - * Micky Ching (micky_ching@realsil.com.cn) 10 - */ 11 - 12 - #ifndef __REALTEK_RTSX_XD_H 13 - #define __REALTEK_RTSX_XD_H 14 - 15 - #define XD_DELAY_WRITE 16 - 17 - /* Error Codes */ 18 - #define XD_NO_ERROR 0x00 19 - #define XD_NO_MEMORY 0x80 20 - #define XD_PRG_ERROR 0x40 21 - #define XD_NO_CARD 0x20 22 - #define XD_READ_FAIL 0x10 23 - #define XD_ERASE_FAIL 0x08 24 - #define XD_WRITE_FAIL 0x04 25 - #define XD_ECC_ERROR 0x02 26 - #define XD_TO_ERROR 0x01 27 - 28 - /* XD Commands */ 29 - #define READ1_1 0x00 30 - #define READ1_2 0x01 31 - #define READ2 0x50 32 - #define READ_ID 0x90 33 - #define RESET 0xff 34 - #define PAGE_PRG_1 0x80 35 - #define PAGE_PRG_2 0x10 36 - #define BLK_ERASE_1 0x60 37 - #define BLK_ERASE_2 0xD0 38 - #define READ_STS 0x70 39 - #define READ_XD_ID 0x9A 40 - #define COPY_BACK_512 0x8A 41 - #define COPY_BACK_2K 0x85 42 - #define READ1_1_2 0x30 43 - #define READ1_1_3 0x35 44 - #define CHG_DAT_OUT_1 0x05 45 - #define RDM_DAT_OUT_1 0x05 46 - #define CHG_DAT_OUT_2 0xE0 47 - #define RDM_DAT_OUT_2 0xE0 48 - #define CHG_DAT_OUT_2 0xE0 49 - #define CHG_DAT_IN_1 0x85 50 - #define CACHE_PRG 0x15 51 - 52 - /* Redundant Area Related */ 53 - #define XD_EXTRA_SIZE 0x10 54 - #define XD_2K_EXTRA_SIZE 0x40 55 - 56 - #define NOT_WRITE_PROTECTED 0x80 57 - #define READY_STATE 0x40 58 - #define PROGRAM_ERROR 0x01 59 - #define PROGRAM_ERROR_N_1 0x02 60 - #define INTERNAL_READY 0x20 61 - #define READY_FLAG 0x5F 62 - 63 - #define XD_8M_X8_512 0xE6 64 - #define XD_16M_X8_512 0x73 65 - #define XD_32M_X8_512 0x75 66 - #define XD_64M_X8_512 0x76 67 - #define XD_128M_X8_512 0x79 68 - #define XD_256M_X8_512 0x71 69 - #define XD_128M_X8_2048 0xF1 70 - #define XD_256M_X8_2048 0xDA 71 - #define XD_512M_X8 0xDC 72 - #define XD_128M_X16_2048 0xC1 73 - #define XD_4M_X8_512_1 0xE3 74 - #define XD_4M_X8_512_2 0xE5 75 - #define XD_1G_X8_512 0xD3 76 - #define XD_2G_X8_512 0xD5 77 - 78 - #define XD_ID_CODE 0xB5 79 - 80 - #define VENDOR_BLOCK 0xEFFF 81 - #define CIS_BLOCK 0xDFFF 82 - 83 - #define BLK_NOT_FOUND 0xFFFFFFFF 84 - 85 - #define NO_NEW_BLK 0xFFFFFFFF 86 - 87 - #define PAGE_CORRECTABLE 0x0 88 - #define PAGE_NOTCORRECTABLE 0x1 89 - 90 - #define NO_OFFSET 0x0 91 - #define WITH_OFFSET 0x1 92 - 93 - #define SECT_PER_PAGE 4 94 - #define XD_ADDR_MODE_2C XD_ADDR_MODE_2A 95 - 96 - #define ZONE0_BAD_BLOCK 23 97 - #define NOT_ZONE0_BAD_BLOCK 24 98 - 99 - #define XD_RW_ADDR 0x01 100 - #define XD_ERASE_ADDR 0x02 101 - 102 - #define XD_PAGE_512(xd_card) \ 103 - do { \ 104 - (xd_card)->block_shift = 5; \ 105 - (xd_card)->page_off = 0x1F; \ 106 - } while (0) 107 - 108 - #define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01) 109 - #define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01) 110 - #define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01) 111 - 112 - #define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02) 113 - #define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02) 114 - #define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02) 115 - 116 - #define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04) 117 - #define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04) 118 - #define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04) 119 - 120 - #define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08) 121 - #define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08) 122 - #define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08) 123 - 124 - #define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10) 125 - #define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10) 126 - #define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10) 127 - 128 - #define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40) 129 - #define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40) 130 - #define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40) 131 - 132 - #define PAGE_STATUS 0 133 - #define BLOCK_STATUS 1 134 - #define BLOCK_ADDR1_L 2 135 - #define BLOCK_ADDR1_H 3 136 - #define BLOCK_ADDR2_L 4 137 - #define BLOCK_ADDR2_H 5 138 - #define RESERVED0 6 139 - #define RESERVED1 7 140 - #define RESERVED2 8 141 - #define RESERVED3 9 142 - #define PARITY 10 143 - 144 - #define CIS0_0 0 145 - #define CIS0_1 1 146 - #define CIS0_2 2 147 - #define CIS0_3 3 148 - #define CIS0_4 4 149 - #define CIS0_5 5 150 - #define CIS0_6 6 151 - #define CIS0_7 7 152 - #define CIS0_8 8 153 - #define CIS0_9 9 154 - #define CIS1_0 256 155 - #define CIS1_1 (256 + 1) 156 - #define CIS1_2 (256 + 2) 157 - #define CIS1_3 (256 + 3) 158 - #define CIS1_4 (256 + 4) 159 - #define CIS1_5 (256 + 5) 160 - #define CIS1_6 (256 + 6) 161 - #define CIS1_7 (256 + 7) 162 - #define CIS1_8 (256 + 8) 163 - #define CIS1_9 (256 + 9) 164 - 165 - int reset_xd_card(struct rtsx_chip *chip); 166 - #ifdef XD_DELAY_WRITE 167 - int xd_delay_write(struct rtsx_chip *chip); 168 - #endif 169 - int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 170 - u32 start_sector, u16 sector_cnt); 171 - void xd_free_l2p_tbl(struct rtsx_chip *chip); 172 - void xd_cleanup_work(struct rtsx_chip *chip); 173 - int xd_power_off_card3v3(struct rtsx_chip *chip); 174 - int release_xd_card(struct rtsx_chip *chip); 175 - 176 - #endif /* __REALTEK_RTSX_XD_H */