tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/include:cleanup vega10 nbio header files.

Cleanup asic_reg/vega10/NBIO folder.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Feifei Xu and committed by
Alex Deucher f0a58aa3 65417d9f

+10 -10
+2 -2
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
··· 23 23 24 24 #include "amdgpu.h" 25 25 #include "vega10/soc15ip.h" 26 - #include "vega10/NBIO/nbio_6_1_offset.h" 27 - #include "vega10/NBIO/nbio_6_1_sh_mask.h" 26 + #include "nbio/nbio_6_1_offset.h" 27 + #include "nbio/nbio_6_1_sh_mask.h" 28 28 #include "gc/gc_9_0_offset.h" 29 29 #include "gc/gc_9_0_sh_mask.h" 30 30 #include "soc15.h"
+3 -3
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
··· 25 25 #include "nbio_v6_1.h" 26 26 27 27 #include "vega10/soc15ip.h" 28 - #include "vega10/NBIO/nbio_6_1_default.h" 29 - #include "vega10/NBIO/nbio_6_1_offset.h" 30 - #include "vega10/NBIO/nbio_6_1_sh_mask.h" 28 + #include "nbio/nbio_6_1_default.h" 29 + #include "nbio/nbio_6_1_offset.h" 30 + #include "nbio/nbio_6_1_sh_mask.h" 31 31 #include "vega10/vega10_enum.h" 32 32 33 33 #define smnCPM_CONTROL 0x11180460
+1 -1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
··· 36 36 #include "mp/mp_9_0_sh_mask.h" 37 37 #include "gc/gc_9_0_offset.h" 38 38 #include "sdma0/sdma0_4_0_offset.h" 39 - #include "vega10/NBIO/nbio_6_1_offset.h" 39 + #include "nbio/nbio_6_1_offset.h" 40 40 41 41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 42 42 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
+1 -1
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
··· 57 57 #include "dce/dce_12_0_offset.h" 58 58 #include "dce/dce_12_0_sh_mask.h" 59 59 #include "vega10/soc15ip.h" 60 - #include "vega10/NBIO/nbio_6_1_offset.h" 60 + #include "nbio/nbio_6_1_offset.h" 61 61 #include "reg_helper.h" 62 62 63 63 #include "dce100/dce100_resource.h"
drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_default.h
drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h
drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h
+3 -3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
··· 35 35 #include "asic_reg/gc/gc_9_0_offset.h" 36 36 #include "asic_reg/gc/gc_9_0_sh_mask.h" 37 37 38 - #include "asic_reg/vega10/NBIO/nbio_6_1_default.h" 39 - #include "asic_reg/vega10/NBIO/nbio_6_1_offset.h" 40 - #include "asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h" 38 + #include "asic_reg/nbio/nbio_6_1_default.h" 39 + #include "asic_reg/nbio/nbio_6_1_offset.h" 40 + #include "asic_reg/nbio/nbio_6_1_sh_mask.h" 41 41 42 42 43 43 #endif