···1414 * TODO1515 * Look into engine reset on timeout errors. Should not be required.1616 */1717-1818-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt1919-2017#include <linux/kernel.h>2118#include <linux/module.h>2219#include <linux/pci.h>···228231229232 i = match_string(list, -1, model_num);230233 if (i >= 0) {231231- pr_warn("%s is not supported for %s\n", modestr, list[i]);234234+ ata_dev_warn(dev, "%s is not supported for %s\n",235235+ modestr, list[i]);232236 return 1;233237 }234238 return 0;···862864 chip_table = &hpt372;863865 break;864866 default:865865- pr_err("Unknown HPT366 subtype, please report (%d)\n",867867+ dev_err(&dev->dev,868868+ "Unknown HPT366 subtype, please report (%d)\n",866869 rev);867870 return -ENODEV;868871 }···904905 *ppi = &info_hpt374_fn1;905906 break;906907 default:907907- pr_err("PCI table is bogus, please report (%d)\n", dev->device);908908+ dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n",909909+ dev->device);908910 return -ENODEV;909911 }910912 /* Ok so this is a chip we support */···953953 u8 sr;954954 u32 total = 0;955955956956- pr_warn("BIOS has not set timing clocks\n");956956+ dev_warn(&dev->dev, "BIOS has not set timing clocks\n");957957958958 /* This is the process the HPT371 BIOS is reported to use */959959 for (i = 0; i < 128; i++) {···10091009 (f_high << 16) | f_low | 0x100);10101010 }10111011 if (adjust == 8) {10121012- pr_err("DPLL did not stabilize!\n");10121012+ dev_err(&dev->dev, "DPLL did not stabilize!\n");10131013 return -ENODEV;10141014 }10151015 if (dpll == 3)···10171017 else10181018 private_data = (void *)hpt37x_timings_50;1019101910201020- pr_info("bus clock %dMHz, using %dMHz DPLL\n",10201020+ dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n",10211021 MHz[clock_slot], MHz[dpll]);10221022 } else {10231023 private_data = (void *)chip_table->clocks[clock_slot];···10321032 if (clock_slot < 2 && ppi[0] == &info_hpt370a)10331033 ppi[0] = &info_hpt370a_33;1034103410351035- pr_info("%s using %dMHz bus clock\n",10351035+ dev_info(&dev->dev, "%s using %dMHz bus clock\n",10361036 chip_table->name, MHz[clock_slot]);10371037 }10381038