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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup
Rather than casting and shifting. Fixes sparse cast warnings.
Reviewed-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+14
-14
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
152
152
uint64_t tmr_mc, uint32_t size)
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{
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cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
155
-
cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
156
-
cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
155
+
cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
156
+
cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
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cmd->cmd.cmd_setup_tmr.buf_size = size;
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}
159
159
+6
-6
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+6
-6
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
···
96
96
header = (struct common_firmware_header *)ucode->fw;
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98
98
cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
99
-
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
100
-
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
99
+
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
100
+
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
101
101
cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
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103
103
ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
···
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write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
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/* Update KM RB frame */
175
-
write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
176
-
write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
177
-
write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
178
-
write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
175
+
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
176
+
write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
177
+
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
178
+
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
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write_frame->fence_value = index;
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/* Update the write Pointer in DWORDs */
+6
-6
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+6
-6
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
···
254
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memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
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cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
257
-
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
258
-
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
257
+
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
258
+
cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
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cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
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ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
···
375
375
memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
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/* Update KM RB frame */
378
-
write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
379
-
write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
380
-
write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
381
-
write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
378
+
write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
379
+
write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
380
+
write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
381
+
write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
382
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write_frame->fence_value = index;
383
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384
384
/* Update the write Pointer in DWORDs */