tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soundwire: move intel sdw register definitions to sdw_intel.h
Those Intel sdw registers will be used by ASoC SOF drivers in the
following commits. So move those definitions to sdw_intel.h and it can
be visible to SOF drivers.
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Acked-By: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210723115451.7245-2-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Bard Liao
and committed by
Mark Brown
f0163958
170c0d74
+79
-80
-74
drivers/soundwire/intel.c
-74
drivers/soundwire/intel.c
···
40
40
module_param_named(sdw_md_flags, md_flags, int, 0444);
41
41
MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
42
42
43
-
/* Intel SHIM Registers Definition */
44
-
#define SDW_SHIM_LCAP 0x0
45
-
#define SDW_SHIM_LCTL 0x4
46
-
#define SDW_SHIM_IPPTR 0x8
47
-
#define SDW_SHIM_SYNC 0xC
48
-
49
-
#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
50
-
#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
51
-
#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
52
-
#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
53
-
#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
54
-
#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
55
-
56
-
#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
57
-
#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
58
-
#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
59
-
#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
60
-
#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
61
-
62
-
#define SDW_SHIM_WAKEEN 0x190
63
-
#define SDW_SHIM_WAKESTS 0x192
64
-
65
-
#define SDW_SHIM_LCTL_SPA BIT(0)
66
-
#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
67
-
#define SDW_SHIM_LCTL_CPA BIT(8)
68
-
#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
69
-
70
-
#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
71
-
#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
72
-
#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
73
-
#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
74
-
#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
75
-
#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
76
-
#define SDW_SHIM_SYNC_SYNCGO BIT(24)
77
-
78
-
#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
79
-
#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
80
-
#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
81
-
82
-
#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
83
-
#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
84
-
#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
85
-
#define SDW_SHIM_PCMSYCM_DIR BIT(15)
86
-
87
-
#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
88
-
#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
89
-
#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
90
-
#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
91
-
92
-
#define SDW_SHIM_IOCTL_MIF BIT(0)
93
-
#define SDW_SHIM_IOCTL_CO BIT(1)
94
-
#define SDW_SHIM_IOCTL_COE BIT(2)
95
-
#define SDW_SHIM_IOCTL_DO BIT(3)
96
-
#define SDW_SHIM_IOCTL_DOE BIT(4)
97
-
#define SDW_SHIM_IOCTL_BKE BIT(5)
98
-
#define SDW_SHIM_IOCTL_WPDD BIT(6)
99
-
#define SDW_SHIM_IOCTL_CIBD BIT(8)
100
-
#define SDW_SHIM_IOCTL_DIBD BIT(9)
101
-
102
-
#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
103
-
#define SDW_SHIM_CTMCTL_DODS BIT(1)
104
-
#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
105
-
106
-
#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
107
-
#define SDW_SHIM_WAKESTS_STATUS BIT(0)
108
-
109
-
/* Intel ALH Register definitions */
110
-
#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
111
-
#define SDW_ALH_NUM_STREAMS 64
112
-
113
-
#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
114
-
#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
115
-
#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
116
-
117
43
enum intel_pdi_type {
118
44
INTEL_PDI_IN = 0,
119
45
INTEL_PDI_OUT = 1,
-6
drivers/soundwire/intel_init.c
-6
drivers/soundwire/intel_init.c
···
18
18
#include "cadence_master.h"
19
19
#include "intel.h"
20
20
21
-
#define SDW_SHIM_LCAP 0x0
22
-
#define SDW_SHIM_BASE 0x2C000
23
-
#define SDW_ALH_BASE 0x2C800
24
-
#define SDW_LINK_BASE 0x30000
25
-
#define SDW_LINK_SIZE 0x10000
26
-
27
21
static void intel_link_dev_release(struct device *dev)
28
22
{
29
23
struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
+79
include/linux/soundwire/sdw_intel.h
+79
include/linux/soundwire/sdw_intel.h
···
7
7
#include <linux/irqreturn.h>
8
8
#include <linux/soundwire/sdw.h>
9
9
10
+
#define SDW_SHIM_BASE 0x2C000
11
+
#define SDW_ALH_BASE 0x2C800
12
+
#define SDW_LINK_BASE 0x30000
13
+
#define SDW_LINK_SIZE 0x10000
14
+
15
+
/* Intel SHIM Registers Definition */
16
+
#define SDW_SHIM_LCAP 0x0
17
+
#define SDW_SHIM_LCTL 0x4
18
+
#define SDW_SHIM_IPPTR 0x8
19
+
#define SDW_SHIM_SYNC 0xC
20
+
21
+
#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
22
+
#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
23
+
#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
24
+
#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
25
+
#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
26
+
#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
27
+
28
+
#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
29
+
#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
30
+
#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
31
+
#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
32
+
#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
33
+
34
+
#define SDW_SHIM_WAKEEN 0x190
35
+
#define SDW_SHIM_WAKESTS 0x192
36
+
37
+
#define SDW_SHIM_LCTL_SPA BIT(0)
38
+
#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
39
+
#define SDW_SHIM_LCTL_CPA BIT(8)
40
+
#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
41
+
42
+
#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
43
+
#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
44
+
#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
45
+
#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
46
+
#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
47
+
#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
48
+
#define SDW_SHIM_SYNC_SYNCGO BIT(24)
49
+
50
+
#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
51
+
#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
52
+
#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
53
+
54
+
#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
55
+
#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
56
+
#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
57
+
#define SDW_SHIM_PCMSYCM_DIR BIT(15)
58
+
59
+
#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
60
+
#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
61
+
#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
62
+
#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
63
+
64
+
#define SDW_SHIM_IOCTL_MIF BIT(0)
65
+
#define SDW_SHIM_IOCTL_CO BIT(1)
66
+
#define SDW_SHIM_IOCTL_COE BIT(2)
67
+
#define SDW_SHIM_IOCTL_DO BIT(3)
68
+
#define SDW_SHIM_IOCTL_DOE BIT(4)
69
+
#define SDW_SHIM_IOCTL_BKE BIT(5)
70
+
#define SDW_SHIM_IOCTL_WPDD BIT(6)
71
+
#define SDW_SHIM_IOCTL_CIBD BIT(8)
72
+
#define SDW_SHIM_IOCTL_DIBD BIT(9)
73
+
74
+
#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
75
+
#define SDW_SHIM_CTMCTL_DODS BIT(1)
76
+
#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
77
+
78
+
#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
79
+
#define SDW_SHIM_WAKESTS_STATUS BIT(0)
80
+
81
+
/* Intel ALH Register definitions */
82
+
#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
83
+
#define SDW_ALH_NUM_STREAMS 64
84
+
85
+
#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
86
+
#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
87
+
#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
88
+
10
89
/**
11
90
* struct sdw_intel_stream_params_data: configuration passed during
12
91
* the @params_stream callback, e.g. for interaction with DSP