Merge tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux

Pull parisc architecture fixes from Helge Deller:
"Some reverts of existing patches, which were necessary because of boot
issues due to wrong CPU clock handling and cache issues which led to
userspace segfaults with 32bit kernels. Dave has a whole bunch of
upcoming cache fixes which I then plan to push in the next merge
window.

Other than that just small updates and fixes, e.g. defconfig updates,
spelling fixes, a clocksource fix, boot topology fixes and a fix for
/proc/cpuinfo output to satisfy lscpu"

* tag 'for-5.18/parisc-3' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
Revert "parisc: Increase parisc_cache_flush_threshold setting"
parisc: Mark cr16 clock unstable on all SMP machines
parisc: Fix typos in comments
parisc: Change MAX_ADDRESS to become unsigned long long
parisc: Merge model and model name into one line in /proc/cpuinfo
parisc: Re-enable GENERIC_CPU_DEVICES for !SMP
parisc: Update 32- and 64-bit defconfigs
parisc: Only list existing CPUs in cpu_possible_mask
Revert "parisc: Fix patch code locking and flushing"
Revert "parisc: Mark sched_clock unstable only if clocks are not syncronized"
Revert "parisc: Mark cr16 CPU clocksource unstable on all SMP machines"

+1
arch/parisc/Kconfig
··· 38 38 select ARCH_HAVE_NMI_SAFE_CMPXCHG 39 39 select GENERIC_SMP_IDLE_THREAD 40 40 select GENERIC_ARCH_TOPOLOGY if SMP 41 + select GENERIC_CPU_DEVICES if !SMP 41 42 select GENERIC_LIB_DEVMEM_IS_ALLOWED 42 43 select SYSCTL_ARCH_UNALIGN_ALLOW 43 44 select SYSCTL_EXCEPTION_TRACE
+3 -1
arch/parisc/configs/generic-32bit_defconfig
··· 6 6 CONFIG_IKCONFIG=y 7 7 CONFIG_IKCONFIG_PROC=y 8 8 CONFIG_LOG_BUF_SHIFT=16 9 + CONFIG_CGROUPS=y 10 + CONFIG_NAMESPACES=y 11 + CONFIG_USER_NS=y 9 12 CONFIG_BLK_DEV_INITRD=y 10 13 CONFIG_EXPERT=y 11 14 CONFIG_PERF_EVENTS=y ··· 50 47 CONFIG_PARPORT_PC=m 51 48 CONFIG_PARPORT_1284=y 52 49 CONFIG_BLK_DEV_LOOP=y 53 - CONFIG_BLK_DEV_CRYPTOLOOP=y 54 50 CONFIG_BLK_DEV_RAM=y 55 51 CONFIG_BLK_DEV_RAM_SIZE=6144 56 52 CONFIG_BLK_DEV_SD=y
+2 -1
arch/parisc/configs/generic-64bit_defconfig
··· 16 16 CONFIG_MEMCG=y 17 17 CONFIG_CGROUP_PIDS=y 18 18 CONFIG_CPUSETS=y 19 + CONFIG_USER_NS=y 19 20 CONFIG_RELAY=y 20 21 CONFIG_BLK_DEV_INITRD=y 21 22 CONFIG_CC_OPTIMIZE_FOR_SIZE=y ··· 268 267 CONFIG_CRC_CCITT=m 269 268 CONFIG_LIBCRC32C=y 270 269 CONFIG_PRINTK_TIME=y 270 + CONFIG_DEBUG_KERNEL=y 271 271 CONFIG_STRIP_ASM_SYMS=y 272 272 CONFIG_MAGIC_SYSRQ=y 273 273 CONFIG_DEBUG_FS=y 274 - CONFIG_DEBUG_KERNEL=y 275 274 CONFIG_DEBUG_STACKOVERFLOW=y 276 275 # CONFIG_SCHED_DEBUG is not set
+1 -1
arch/parisc/include/asm/pgtable.h
··· 160 160 #define SPACEID_SHIFT (MAX_ADDRBITS - 32) 161 161 #else 162 162 #define MAX_ADDRBITS (BITS_PER_LONG) 163 - #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 163 + #define MAX_ADDRESS (1ULL << MAX_ADDRBITS) 164 164 #define SPACEID_SHIFT 0 165 165 #endif 166 166
+3 -15
arch/parisc/kernel/cache.c
··· 403 403 { 404 404 unsigned long rangetime, alltime; 405 405 unsigned long size; 406 - unsigned long threshold, threshold2; 406 + unsigned long threshold; 407 407 408 408 alltime = mfctl(16); 409 409 flush_data_cache(); ··· 418 418 alltime, size, rangetime); 419 419 420 420 threshold = L1_CACHE_ALIGN(size * alltime / rangetime); 421 - 422 - /* 423 - * The threshold computed above isn't very reliable since the 424 - * flush times depend greatly on the percentage of dirty lines 425 - * in the flush range. Further, the whole cache time doesn't 426 - * include the time to refill lines that aren't in the mm/vma 427 - * being flushed. By timing glibc build and checks on mako cpus, 428 - * the following formula seems to work reasonably well. The 429 - * value from the timing calculation is too small, and increases 430 - * build and check times by almost a factor two. 431 - */ 432 - threshold2 = cache_info.dc_size * num_online_cpus(); 433 - if (threshold2 > threshold) 434 - threshold = threshold2; 421 + if (threshold > cache_info.dc_size) 422 + threshold = cache_info.dc_size; 435 423 if (threshold) 436 424 parisc_cache_flush_threshold = threshold; 437 425 printk(KERN_INFO "Cache flush threshold set to %lu KiB\n",
+1 -1
arch/parisc/kernel/kprobes.c
··· 152 152 /* for absolute branch instructions we can copy iaoq_b. for relative 153 153 * branch instructions we need to calculate the new address based on the 154 154 * difference between iaoq_f and iaoq_b. We cannot use iaoq_b without 155 - * modificationt because it's based on our ainsn.insn address. 155 + * modifications because it's based on our ainsn.insn address. 156 156 */ 157 157 158 158 if (p->post_handler)
+14 -11
arch/parisc/kernel/patch.c
··· 40 40 41 41 *need_unmap = 1; 42 42 set_fixmap(fixmap, page_to_phys(page)); 43 - raw_spin_lock_irqsave(&patch_lock, *flags); 43 + if (flags) 44 + raw_spin_lock_irqsave(&patch_lock, *flags); 45 + else 46 + __acquire(&patch_lock); 44 47 45 48 return (void *) (__fix_to_virt(fixmap) + (uintaddr & ~PAGE_MASK)); 46 49 } ··· 52 49 { 53 50 clear_fixmap(fixmap); 54 51 55 - raw_spin_unlock_irqrestore(&patch_lock, *flags); 52 + if (flags) 53 + raw_spin_unlock_irqrestore(&patch_lock, *flags); 54 + else 55 + __release(&patch_lock); 56 56 } 57 57 58 58 void __kprobes __patch_text_multiple(void *addr, u32 *insn, unsigned int len) ··· 67 61 int mapped; 68 62 69 63 /* Make sure we don't have any aliases in cache */ 70 - flush_kernel_dcache_range_asm(start, end); 71 - flush_kernel_icache_range_asm(start, end); 72 - flush_tlb_kernel_range(start, end); 64 + flush_kernel_vmap_range(addr, len); 65 + flush_icache_range(start, end); 73 66 74 67 p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags, &mapped); 75 68 ··· 81 76 * We're crossing a page boundary, so 82 77 * need to remap 83 78 */ 84 - flush_kernel_dcache_range_asm((unsigned long)fixmap, 85 - (unsigned long)p); 86 - flush_tlb_kernel_range((unsigned long)fixmap, 87 - (unsigned long)p); 79 + flush_kernel_vmap_range((void *)fixmap, 80 + (p-fixmap) * sizeof(*p)); 88 81 if (mapped) 89 82 patch_unmap(FIX_TEXT_POKE0, &flags); 90 83 p = fixmap = patch_map(addr, FIX_TEXT_POKE0, &flags, ··· 90 87 } 91 88 } 92 89 93 - flush_kernel_dcache_range_asm((unsigned long)fixmap, (unsigned long)p); 94 - flush_tlb_kernel_range((unsigned long)fixmap, (unsigned long)p); 90 + flush_kernel_vmap_range((void *)fixmap, (p-fixmap) * sizeof(*p)); 95 91 if (mapped) 96 92 patch_unmap(FIX_TEXT_POKE0, &flags); 93 + flush_icache_range(start, end); 97 94 } 98 95 99 96 void __kprobes __patch_text(void *addr, u32 insn)
+9 -2
arch/parisc/kernel/processor.c
··· 171 171 p->cpu_num = cpu_info.cpu_num; 172 172 p->cpu_loc = cpu_info.cpu_loc; 173 173 174 + set_cpu_possible(cpuid, true); 174 175 store_cpu_topology(cpuid); 175 176 176 177 #ifdef CONFIG_SMP ··· 420 419 } 421 420 seq_printf(m, " (0x%02lx)\n", boot_cpu_data.pdc.capabilities); 422 421 423 - seq_printf(m, "model\t\t: %s\n" 424 - "model name\t: %s\n", 422 + seq_printf(m, "model\t\t: %s - %s\n", 425 423 boot_cpu_data.pdc.sys_model_name, 426 424 cpuinfo->dev ? 427 425 cpuinfo->dev->name : "Unknown"); ··· 461 461 */ 462 462 void __init processor_init(void) 463 463 { 464 + unsigned int cpu; 465 + 464 466 reset_cpu_topology(); 467 + 468 + /* reset possible mask. We will mark those which are possible. */ 469 + for_each_possible_cpu(cpu) 470 + set_cpu_possible(cpu, false); 471 + 465 472 register_parisc_driver(&cpu_driver); 466 473 }
+2
arch/parisc/kernel/setup.c
··· 161 161 #ifdef CONFIG_PA11 162 162 dma_ops_init(); 163 163 #endif 164 + 165 + clear_sched_clock_stable(); 164 166 } 165 167 166 168 /*
+1 -5
arch/parisc/kernel/time.c
··· 251 251 static int __init init_cr16_clocksource(void) 252 252 { 253 253 /* 254 - * The cr16 interval timers are not syncronized across CPUs, even if 255 - * they share the same socket. 254 + * The cr16 interval timers are not synchronized across CPUs. 256 255 */ 257 256 if (num_online_cpus() > 1 && !running_on_qemu) { 258 - /* mark sched_clock unstable */ 259 - clear_sched_clock_stable(); 260 - 261 257 clocksource_cr16.name = "cr16_unstable"; 262 258 clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; 263 259 clocksource_cr16.rating = 0;
+1 -1
arch/parisc/kernel/traps.c
··· 469 469 * panic notifiers, and we should call panic 470 470 * directly from the location that we wish. 471 471 * e.g. We should not call panic from 472 - * parisc_terminate, but rather the oter way around. 472 + * parisc_terminate, but rather the other way around. 473 473 * This hack works, prints the panic message twice, 474 474 * and it enables reboot timers! 475 475 */
+1 -1
arch/parisc/math-emu/dfadd.c
··· 253 253 return(NOEXCEPTION); 254 254 } 255 255 right_exponent = 1; /* Set exponent to reflect different bias 256 - * with denomalized numbers. */ 256 + * with denormalized numbers. */ 257 257 } 258 258 else 259 259 {
+1 -1
arch/parisc/math-emu/dfsub.c
··· 256 256 return(NOEXCEPTION); 257 257 } 258 258 right_exponent = 1; /* Set exponent to reflect different bias 259 - * with denomalized numbers. */ 259 + * with denormalized numbers. */ 260 260 } 261 261 else 262 262 {
+1 -1
arch/parisc/math-emu/sfadd.c
··· 249 249 return(NOEXCEPTION); 250 250 } 251 251 right_exponent = 1; /* Set exponent to reflect different bias 252 - * with denomalized numbers. */ 252 + * with denormalized numbers. */ 253 253 } 254 254 else 255 255 {
+1 -1
arch/parisc/math-emu/sfsub.c
··· 252 252 return(NOEXCEPTION); 253 253 } 254 254 right_exponent = 1; /* Set exponent to reflect different bias 255 - * with denomalized numbers. */ 255 + * with denormalized numbers. */ 256 256 } 257 257 else 258 258 {