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Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
Driver providing perf backend for the SoC-wide PMU hardware found
in APM X-Gene SoCs.
Signed-off-by: Tai Nguyen <ttnguyen@apm.com>
Acked-by: Rob Herring <robh@kernel.org>
authored by
Tai Nguyen
and committed by
Duc Dang
eef691c8
fd3a628e
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Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
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Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
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* APM X-Gene SoC PMU bindings
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This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
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The following PMU devices are supported:
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L3C - L3 cache controller
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IOB - IO bridge
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MCB - Memory controller bridge
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MC - Memory controller
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The following section describes the SoC PMU DT node binding.
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Required properties:
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- compatible : Shall be "apm,xgene-pmu" for revision 1 or
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"apm,xgene-pmu-v2" for revision 2.
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- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
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- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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- reg : First resource shall be the CPU bus PMU resource.
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- interrupts : Interrupt-specifier for PMU IRQ.
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Required properties for L3C subnode:
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- compatible : Shall be "apm,xgene-pmu-l3c".
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- reg : First resource shall be the L3C PMU resource.
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Required properties for IOB subnode:
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- compatible : Shall be "apm,xgene-pmu-iob".
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- reg : First resource shall be the IOB PMU resource.
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Required properties for MCB subnode:
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- compatible : Shall be "apm,xgene-pmu-mcb".
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- reg : First resource shall be the MCB PMU resource.
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- enable-bit-index : The bit indicates if the according MCB is enabled.
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Required properties for MC subnode:
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- compatible : Shall be "apm,xgene-pmu-mc".
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- reg : First resource shall be the MC PMU resource.
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- enable-bit-index : The bit indicates if the according MC is enabled.
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Example:
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csw: csw@7e200000 {
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compatible = "apm,xgene-csw", "syscon";
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reg = <0x0 0x7e200000 0x0 0x1000>;
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};
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mcba: mcba@7e700000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e700000 0x0 0x1000>;
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};
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mcbb: mcbb@7e720000 {
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compatible = "apm,xgene-mcb", "syscon";
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reg = <0x0 0x7e720000 0x0 0x1000>;
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};
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pmu: pmu@78810000 {
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compatible = "apm,xgene-pmu-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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regmap-csw = <&csw>;
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regmap-mcba = <&mcba>;
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regmap-mcbb = <&mcbb>;
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reg = <0x0 0x78810000 0x0 0x1000>;
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interrupts = <0x0 0x22 0x4>;
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pmul3c@7e610000 {
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compatible = "apm,xgene-pmu-l3c";
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reg = <0x0 0x7e610000 0x0 0x1000>;
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};
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pmuiob@7e940000 {
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compatible = "apm,xgene-pmu-iob";
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reg = <0x0 0x7e940000 0x0 0x1000>;
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};
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pmucmcb@7e710000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e710000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmcb@7e730000 {
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compatible = "apm,xgene-pmu-mcb";
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reg = <0x0 0x7e730000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e810000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e810000 0x0 0x1000>;
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enable-bit-index = <0>;
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};
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pmucmc@7e850000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e850000 0x0 0x1000>;
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enable-bit-index = <1>;
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};
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pmucmc@7e890000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e890000 0x0 0x1000>;
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enable-bit-index = <2>;
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};
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pmucmc@7e8d0000 {
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compatible = "apm,xgene-pmu-mc";
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reg = <0x0 0x7e8d0000 0x0 0x1000>;
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enable-bit-index = <3>;
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};
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};