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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: preserve RSMU UMC index mode state
between UMC RAS err register access restore previous RSMU UMC index mode state
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
John Clements
and committed by
Alex Deucher
eee2eaba
9c8c81fe
+41
-2
+41
-2
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
+41
-2
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c
···
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{9, 25, 0, 16}, {15, 31, 6, 22}
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};
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static void umc_v6_1_enable_umc_index_mode(struct amdgpu_device *adev)
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{
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WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 1);
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}
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static void umc_v6_1_disable_umc_index_mode(struct amdgpu_device *adev)
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{
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WREG32_FIELD15(RSMU, 0, RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN, 0);
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}
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static uint32_t umc_v6_1_get_umc_index_mode_state(struct amdgpu_device *adev)
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{
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uint32_t rsmu_umc_index;
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rsmu_umc_index = RREG32_SOC15(RSMU, 0,
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mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU);
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return REG_GET_FIELD(rsmu_umc_index,
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RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU,
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RSMU_UMC_INDEX_MODE_EN);
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}
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static inline uint32_t get_umc_6_reg_offset(struct amdgpu_device *adev,
···
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);
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if (rsmu_umc_index_state)
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umc_v6_1_disable_umc_index_mode(adev);
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
···
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umc_reg_offset,
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&(err_data->ue_count));
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}
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if (rsmu_umc_index_state)
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umc_v6_1_enable_umc_index_mode(adev);
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}
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static void umc_v6_1_query_error_address(struct amdgpu_device *adev,
···
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
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err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
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err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
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/* the lowest lsb bits should be ignored */
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lsb = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, LSB);
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err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
···
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);
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if (rsmu_umc_index_state)
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umc_v6_1_disable_umc_index_mode(adev);
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
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umc_inst,
···
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umc_inst);
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}
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if (rsmu_umc_index_state)
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umc_v6_1_enable_umc_index_mode(adev);
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}
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static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
···
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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-
umc_v6_1_disable_umc_index_mode(adev);
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uint32_t rsmu_umc_index_state = umc_v6_1_get_umc_index_mode_state(adev);
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if (rsmu_umc_index_state)
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umc_v6_1_disable_umc_index_mode(adev);
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LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
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umc_reg_offset = get_umc_6_reg_offset(adev,
···
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umc_v6_1_err_cnt_init_per_channel(adev, umc_reg_offset);
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}
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if (rsmu_umc_index_state)
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umc_v6_1_enable_umc_index_mode(adev);
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}
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const struct amdgpu_umc_funcs umc_v6_1_funcs = {