drm/amd/display: Enable DCN314 in DC · tjh.dev/kernel@ee7b62e

+1

drivers/gpu/drm/amd/display/dc/Makefile

··· 35 35 DC_LIBS += dcn302 36 36 DC_LIBS += dcn303 37 37 DC_LIBS += dcn31 38 + DC_LIBS += dcn314 38 39 DC_LIBS += dcn315 39 40 DC_LIBS += dcn316 40 41 DC_LIBS += dcn32

+1

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

··· 75 75 case DCN_VERSION_3_02: 76 76 case DCN_VERSION_3_03: 77 77 case DCN_VERSION_3_1: 78 + case DCN_VERSION_3_14: 78 79 case DCN_VERSION_3_15: 79 80 case DCN_VERSION_3_16: 80 81 case DCN_VERSION_3_2:

+9

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

··· 155 155 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31) 156 156 157 157 ############################################################################### 158 + # DCN314 159 + ############################################################################### 160 + CLK_MGR_DCN314 = dcn314_smu.o dcn314_clk_mgr.o 161 + 162 + AMD_DAL_CLK_MGR_DCN314 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn314/,$(CLK_MGR_DCN314)) 163 + 164 + AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN314) 165 + 166 + ############################################################################### 158 167 # DCN315 159 168 ############################################################################### 160 169 CLK_MGR_DCN315 = dcn315_smu.o dcn315_clk_mgr.o

+21 -1

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

··· 43 43 #include "dcn30/dcn30_clk_mgr.h" 44 44 #include "dcn301/vg_clk_mgr.h" 45 45 #include "dcn31/dcn31_clk_mgr.h" 46 + #include "dcn314/dcn314_clk_mgr.h" 46 47 #include "dcn315/dcn315_clk_mgr.h" 47 48 #include "dcn316/dcn316_clk_mgr.h" 48 49 #include "dcn32/dcn32_clk_mgr.h" 49 - 50 50 51 51 int clk_mgr_helper_get_active_display_cnt( 52 52 struct dc *dc, ··· 287 287 return &clk_mgr->base.base; 288 288 } 289 289 break; 290 + 290 291 case FAMILY_YELLOW_CARP: { 291 292 struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); 292 293 ··· 336 335 return &clk_mgr->base; 337 336 break; 338 337 } 338 + 339 + case AMDGPU_FAMILY_GC_11_0_2: { 340 + struct clk_mgr_dcn314 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); 341 + 342 + if (clk_mgr == NULL) { 343 + BREAK_TO_DEBUGGER(); 344 + return NULL; 345 + } 346 + 347 + dcn314_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); 348 + return &clk_mgr->base.base; 349 + } 350 + break; 351 + 339 352 #endif 340 353 default: 341 354 ASSERT(0); /* Unknown Asic */ ··· 396 381 case AMDGPU_FAMILY_GC_11_0_0: 397 382 dcn32_clk_mgr_destroy(clk_mgr); 398 383 break; 384 + 385 + case AMDGPU_FAMILY_GC_11_0_2: 386 + dcn314_clk_mgr_destroy(clk_mgr); 387 + break; 388 + 399 389 default: 400 390 break; 401 391 }

+4

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 4292 4292 !dc->debug.dpia_debug.bits.disable_dpia) 4293 4293 return true; 4294 4294 4295 + if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_2 && 4296 + !dc->debug.dpia_debug.bits.disable_dpia) 4297 + return true; 4298 + 4295 4299 /* dmub aux needs dmub notifications to be enabled */ 4296 4300 return dc->debug.enable_dmub_aux_for_legacy_ddc; 4297 4301 }

+1

drivers/gpu/drm/amd/display/dc/core/dc_link.c

··· 3372 3372 switch(link->ctx->asic_id.chip_family) { 3373 3373 case FAMILY_YELLOW_CARP: 3374 3374 case AMDGPU_FAMILY_GC_10_3_6: 3375 + case AMDGPU_FAMILY_GC_11_0_2: 3375 3376 if(!dc->debug.disable_z10) 3376 3377 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false; 3377 3378 break;

+8

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

··· 63 63 #include "dcn302/dcn302_resource.h" 64 64 #include "dcn303/dcn303_resource.h" 65 65 #include "dcn31/dcn31_resource.h" 66 + #include "dcn314/dcn314_resource.h" 66 67 #include "dcn315/dcn315_resource.h" 67 68 #include "dcn316/dcn316_resource.h" 68 69 #include "../dcn32/dcn32_resource.h" ··· 168 167 if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev)) 169 168 dc_version = DCN_VERSION_3_21; 170 169 break; 170 + case AMDGPU_FAMILY_GC_11_0_2: 171 + if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev)) 172 + dc_version = DCN_VERSION_3_14; 173 + break; 171 174 default: 172 175 dc_version = DCE_VERSION_UNKNOWN; 173 176 break; ··· 260 255 break; 261 256 case DCN_VERSION_3_1: 262 257 res_pool = dcn31_create_resource_pool(init_data, dc); 258 + break; 259 + case DCN_VERSION_3_14: 260 + res_pool = dcn314_create_resource_pool(init_data, dc); 263 261 break; 264 262 case DCN_VERSION_3_15: 265 263 res_pool = dcn315_create_resource_pool(init_data, dc);

+4 -1

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

··· 157 157 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 158 158 SRII(PIXEL_RATE_CNTL, OTG, 1) 159 159 160 - 161 160 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 162 161 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 163 162 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 164 163 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 165 164 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 165 + 166 + #define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\ 167 + CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ 168 + CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh), 166 169 167 170 #define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ 168 171 CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\

+12 -5

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

··· 575 575 PIC_HEIGHT, reg_vals->pps.pic_height); 576 576 577 577 // dscc registers 578 - REG_SET_4(DSCC_CONFIG0, 0, 579 - ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 580 - NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 581 - ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 582 - NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 578 + if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) { 579 + REG_SET_3(DSCC_CONFIG0, 0, 580 + NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 581 + ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 582 + NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 583 + } else { 584 + REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, 585 + reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE, 586 + reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN, 587 + reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, 588 + reg_vals->num_slices_v - 1); 589 + } 583 590 584 591 REG_SET(DSCC_CONFIG1, 0, 585 592 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);

+219

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h

··· 445 445 type DSCRM_DSC_FORWARD_EN; \ 446 446 type DSCRM_DSC_OPP_PIPE_SOURCE 447 447 448 + #define DSC_REG_LIST_DCN314(id) \ 449 + SRI(DSC_TOP_CONTROL, DSC_TOP, id),\ 450 + SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\ 451 + SRI(DSCC_CONFIG0, DSCC, id),\ 452 + SRI(DSCC_CONFIG1, DSCC, id),\ 453 + SRI(DSCC_STATUS, DSCC, id),\ 454 + SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\ 455 + SRI(DSCC_PPS_CONFIG0, DSCC, id),\ 456 + SRI(DSCC_PPS_CONFIG1, DSCC, id),\ 457 + SRI(DSCC_PPS_CONFIG2, DSCC, id),\ 458 + SRI(DSCC_PPS_CONFIG3, DSCC, id),\ 459 + SRI(DSCC_PPS_CONFIG4, DSCC, id),\ 460 + SRI(DSCC_PPS_CONFIG5, DSCC, id),\ 461 + SRI(DSCC_PPS_CONFIG6, DSCC, id),\ 462 + SRI(DSCC_PPS_CONFIG7, DSCC, id),\ 463 + SRI(DSCC_PPS_CONFIG8, DSCC, id),\ 464 + SRI(DSCC_PPS_CONFIG9, DSCC, id),\ 465 + SRI(DSCC_PPS_CONFIG10, DSCC, id),\ 466 + SRI(DSCC_PPS_CONFIG11, DSCC, id),\ 467 + SRI(DSCC_PPS_CONFIG12, DSCC, id),\ 468 + SRI(DSCC_PPS_CONFIG13, DSCC, id),\ 469 + SRI(DSCC_PPS_CONFIG14, DSCC, id),\ 470 + SRI(DSCC_PPS_CONFIG15, DSCC, id),\ 471 + SRI(DSCC_PPS_CONFIG16, DSCC, id),\ 472 + SRI(DSCC_PPS_CONFIG17, DSCC, id),\ 473 + SRI(DSCC_PPS_CONFIG18, DSCC, id),\ 474 + SRI(DSCC_PPS_CONFIG19, DSCC, id),\ 475 + SRI(DSCC_PPS_CONFIG20, DSCC, id),\ 476 + SRI(DSCC_PPS_CONFIG21, DSCC, id),\ 477 + SRI(DSCC_PPS_CONFIG22, DSCC, id),\ 478 + SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\ 479 + SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\ 480 + SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\ 481 + SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\ 482 + SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\ 483 + SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\ 484 + SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\ 485 + SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\ 486 + SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\ 487 + SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\ 488 + SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\ 489 + SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\ 490 + SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\ 491 + SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\ 492 + SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\ 493 + SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\ 494 + SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\ 495 + SRI(DSCCIF_CONFIG0, DSCCIF, id),\ 496 + SRI(DSCCIF_CONFIG1, DSCCIF, id),\ 497 + SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id) 498 + 499 + #define DSC_REG_LIST_SH_MASK_DCN314(mask_sh)\ 500 + DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \ 501 + DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \ 502 + DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \ 503 + DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \ 504 + DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \ 505 + DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \ 506 + DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \ 507 + DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \ 508 + DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \ 509 + /*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \ 510 + DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ 511 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \ 512 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \ 513 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \ 514 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \ 515 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \ 516 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \ 517 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \ 518 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \ 519 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \ 520 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \ 521 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \ 522 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \ 523 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 524 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 525 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 526 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 527 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 528 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 529 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 530 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 531 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 532 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 533 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 534 + DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \ 535 + DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \ 536 + DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \ 537 + DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \ 538 + DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \ 539 + DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ 540 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \ 541 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \ 542 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \ 543 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \ 544 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \ 545 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \ 546 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \ 547 + DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \ 548 + DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \ 549 + DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \ 550 + DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \ 551 + DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \ 552 + DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \ 553 + DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \ 554 + DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \ 555 + DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \ 556 + DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \ 557 + DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \ 558 + DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \ 559 + DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \ 560 + DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \ 561 + DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \ 562 + DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \ 563 + DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \ 564 + DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \ 565 + DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \ 566 + DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \ 567 + DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \ 568 + DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \ 569 + DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \ 570 + DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \ 571 + DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \ 572 + DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \ 573 + DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \ 574 + DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \ 575 + DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \ 576 + DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \ 577 + DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \ 578 + DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \ 579 + DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \ 580 + DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \ 581 + DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \ 582 + DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \ 583 + DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \ 584 + DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \ 585 + DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \ 586 + DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \ 587 + DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \ 588 + DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \ 589 + DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \ 590 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \ 591 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \ 592 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \ 593 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \ 594 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \ 595 + DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \ 596 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \ 597 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \ 598 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \ 599 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \ 600 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \ 601 + DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \ 602 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \ 603 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \ 604 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \ 605 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \ 606 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \ 607 + DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \ 608 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \ 609 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \ 610 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \ 611 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \ 612 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \ 613 + DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \ 614 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \ 615 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \ 616 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \ 617 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \ 618 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \ 619 + DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \ 620 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \ 621 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \ 622 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \ 623 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \ 624 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \ 625 + DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \ 626 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \ 627 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \ 628 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \ 629 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \ 630 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \ 631 + DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \ 632 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \ 633 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \ 634 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \ 635 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \ 636 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \ 637 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \ 638 + DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \ 639 + DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \ 640 + DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \ 641 + DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \ 642 + DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \ 643 + DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \ 644 + DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \ 645 + DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \ 646 + DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \ 647 + DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \ 648 + DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ 649 + DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ 650 + DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ 651 + DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ 652 + DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \ 653 + DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \ 654 + DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \ 655 + DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \ 656 + DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \ 657 + DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \ 658 + DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \ 659 + DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \ 660 + DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \ 661 + DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \ 662 + DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \ 663 + DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \ 664 + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \ 665 + DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh) 666 + 448 667 449 668 struct dcn20_dsc_registers { 450 669 uint32_t DSC_TOP_CONTROL;

+8 -8

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c

··· 43 43 #define DC_LOGGER \ 44 44 dccg->ctx->logger 45 45 46 - static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 46 + void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) 47 47 { 48 48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 49 49 ··· 338 338 } 339 339 } 340 340 341 - static void dccg31_disable_dscclk(struct dccg *dccg, int inst) 341 + void dccg31_disable_dscclk(struct dccg *dccg, int inst) 342 342 { 343 343 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 344 344 ··· 373 373 } 374 374 } 375 375 376 - static void dccg31_enable_dscclk(struct dccg *dccg, int inst) 376 + void dccg31_enable_dscclk(struct dccg *dccg, int inst) 377 377 { 378 378 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); 379 379 ··· 510 510 } 511 511 512 512 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */ 513 - static void dccg31_set_dtbclk_dto( 513 + void dccg31_set_dtbclk_dto( 514 514 struct dccg *dccg, 515 515 const struct dtbclk_dto_params *params) 516 516 { ··· 608 608 } 609 609 } 610 610 611 - static void dccg31_get_dccg_ref_freq(struct dccg *dccg, 611 + void dccg31_get_dccg_ref_freq(struct dccg *dccg, 612 612 unsigned int xtalin_freq_inKhz, 613 613 unsigned int *dccg_ref_freq_inKhz) 614 614 { ··· 620 620 return; 621 621 } 622 622 623 - static void dccg31_set_dispclk_change_mode( 623 + void dccg31_set_dispclk_change_mode( 624 624 struct dccg *dccg, 625 625 enum dentist_dispclk_change_mode change_mode) 626 626 { ··· 662 662 } 663 663 } 664 664 665 - static void dccg31_otg_add_pixel(struct dccg *dccg, 665 + void dccg31_otg_add_pixel(struct dccg *dccg, 666 666 uint32_t otg_inst) 667 667 { 668 668 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); ··· 671 671 OTG_ADD_PIXEL[otg_inst], 1); 672 672 } 673 673 674 - static void dccg31_otg_drop_pixel(struct dccg *dccg, 674 + void dccg31_otg_drop_pixel(struct dccg *dccg, 675 675 uint32_t otg_inst) 676 676 { 677 677 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

+35

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

··· 194 194 struct dccg *dccg, 195 195 const struct dtbclk_dto_params *params); 196 196 197 + void dccg31_update_dpp_dto( 198 + struct dccg *dccg, 199 + int dpp_inst, 200 + int req_dppclk); 201 + 202 + void dccg31_get_dccg_ref_freq( 203 + struct dccg *dccg, 204 + unsigned int xtalin_freq_inKhz, 205 + unsigned int *dccg_ref_freq_inKhz); 206 + 207 + void dccg31_set_dpstreamclk( 208 + struct dccg *dccg, 209 + enum streamclk_source src, 210 + int otg_inst); 211 + 212 + void dccg31_set_dtbclk_dto( 213 + struct dccg *dccg, 214 + const struct dtbclk_dto_params *params); 215 + 216 + void dccg31_otg_add_pixel( 217 + struct dccg *dccg, 218 + uint32_t otg_inst); 219 + 220 + void dccg31_otg_drop_pixel( 221 + struct dccg *dccg, 222 + uint32_t otg_inst); 223 + 224 + void dccg31_set_dispclk_change_mode( 225 + struct dccg *dccg, 226 + enum dentist_dispclk_change_mode change_mode); 227 + 228 + void dccg31_disable_dscclk(struct dccg *dccg, int inst); 229 + 230 + void dccg31_enable_dscclk(struct dccg *dccg, int inst); 231 + 197 232 #endif //__DCN31_DCCG_H__

+28

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h

··· 198 198 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\ 199 199 LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh) 200 200 201 + #define DPCS_DCN314_REG_LIST(id) \ 202 + SRI(TMDS_CTL_BITS, DIG, id), \ 203 + SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \ 204 + SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \ 205 + SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \ 206 + SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \ 207 + SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \ 208 + SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \ 209 + SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \ 210 + SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \ 211 + SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \ 212 + SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \ 213 + SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \ 214 + SRI(RDPCSTX_CNTL, RDPCSTX, id), \ 215 + SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \ 216 + SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \ 217 + SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \ 218 + SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \ 219 + SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \ 220 + SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \ 221 + SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \ 222 + SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \ 223 + SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \ 224 + SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \ 225 + SR(RDPCSTX0_RDPCSTX_SCRATCH), \ 226 + SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\ 227 + SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id) 228 + 201 229 void dcn31_link_encoder_construct( 202 230 struct dcn20_link_encoder *enc20, 203 231 const struct encoder_init_data *init_data,

+3

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

··· 2162 2162 pool->base.usb4_dpia_count = 4; 2163 2163 } 2164 2164 2165 + if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_2) 2166 + pool->base.usb4_dpia_count = 4; 2167 + 2165 2168 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2166 2169 if (!resource_construct(num_virtual_links, dc, &pool->base, 2167 2170 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?

+1

drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c

··· 100 100 case DCN_VERSION_3_02: 101 101 case DCN_VERSION_3_03: 102 102 case DCN_VERSION_3_1: 103 + case DCN_VERSION_3_14: 103 104 case DCN_VERSION_3_16: 104 105 dal_hw_factory_dcn30_init(factory); 105 106 return true;

+1

drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c

··· 101 101 case DCN_VERSION_3_02: 102 102 case DCN_VERSION_3_03: 103 103 case DCN_VERSION_3_1: 104 + case DCN_VERSION_3_14: 104 105 case DCN_VERSION_3_16: 105 106 dal_hw_translate_dcn30_init(translate); 106 107 return true;

+10

drivers/gpu/drm/amd/display/dc/irq/Makefile

··· 135 135 AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31)) 136 136 137 137 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31) 138 + 139 + ############################################################################### 140 + # DCN 314 141 + ############################################################################### 142 + IRQ_DCN314 = irq_service_dcn314.o 143 + 144 + AMD_DAL_IRQ_DCN314= $(addprefix $(AMDDALPATH)/dc/irq/dcn314/,$(IRQ_DCN314)) 145 + 146 + AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN314) 147 + 138 148 ############################################################################### 139 149 # DCN 315 140 150 ###############################################################################