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phy: qcom-qmp: qserdes-txrx: Add v7 register offsets
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE.
Add the new qserdes TX RX offsets in a dedicated header file.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-7-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abel Vesa
and committed by
Vinod Koul
ee6fcc0f
762c3565
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drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
+78
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V7_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_V7_H_
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#define QSERDES_V7_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V7_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V7_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V7_TX_TX_BAND 0x24
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#define QSERDES_V7_TX_INTERFACE_SELECT 0x2c
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#define QSERDES_V7_TX_RES_CODE_LANE_TX 0x34
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#define QSERDES_V7_TX_RES_CODE_LANE_RX 0x38
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#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX 0x3c
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#define QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX 0x40
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#define QSERDES_V7_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
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#define QSERDES_V7_TX_BIST_PATTERN7 0x7c
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#define QSERDES_V7_TX_LANE_MODE_1 0x84
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#define QSERDES_V7_TX_LANE_MODE_2 0x88
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#define QSERDES_V7_TX_LANE_MODE_3 0x8c
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#define QSERDES_V7_TX_LANE_MODE_4 0x90
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#define QSERDES_V7_TX_LANE_MODE_5 0x94
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#define QSERDES_V7_TX_RCV_DETECT_LVL_2 0xa4
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#define QSERDES_V7_TX_TRAN_DRVR_EMP_EN 0xc0
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#define QSERDES_V7_TX_TX_INTERFACE_MODE 0xc4
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#define QSERDES_V7_TX_VMODE_CTRL1 0xc8
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#define QSERDES_V7_TX_PI_QEC_CTRL 0xe4
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#define QSERDES_V7_RX_UCDR_FO_GAIN 0x08
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#define QSERDES_V7_RX_UCDR_SO_GAIN 0x14
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#define QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN 0x30
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#define QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE 0x34
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#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW 0x3c
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#define QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH 0x40
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#define QSERDES_V7_RX_UCDR_PI_CONTROLS 0x44
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#define QSERDES_V7_RX_UCDR_SB2_THRESH1 0x4c
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#define QSERDES_V7_RX_UCDR_SB2_THRESH2 0x50
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#define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54
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#define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58
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#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60
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#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc
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#define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4
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#define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8
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#define QSERDES_V7_RX_GM_CAL 0xdc
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#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2 0xec
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#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3 0xf0
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#define QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4 0xf4
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#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8
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#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc
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#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
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#define QSERDES_V7_RX_SIDGET_ENABLES 0x118
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#define QSERDES_V7_RX_SIGDET_CNTRL 0x11c
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#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124
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#define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c
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#define QSERDES_V7_RX_RX_MODE_00_HIGH 0x160
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#define QSERDES_V7_RX_RX_MODE_00_HIGH2 0x164
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#define QSERDES_V7_RX_RX_MODE_00_HIGH3 0x168
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#define QSERDES_V7_RX_RX_MODE_00_HIGH4 0x16c
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#define QSERDES_V7_RX_RX_MODE_01_LOW 0x170
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#define QSERDES_V7_RX_RX_MODE_01_HIGH 0x174
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#define QSERDES_V7_RX_RX_MODE_01_HIGH2 0x178
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#define QSERDES_V7_RX_RX_MODE_01_HIGH3 0x17c
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#define QSERDES_V7_RX_RX_MODE_01_HIGH4 0x180
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#define QSERDES_V7_RX_RX_MODE_10_LOW 0x184
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#define QSERDES_V7_RX_RX_MODE_10_HIGH 0x188
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#define QSERDES_V7_RX_RX_MODE_10_HIGH2 0x18c
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#define QSERDES_V7_RX_RX_MODE_10_HIGH3 0x190
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#define QSERDES_V7_RX_RX_MODE_10_HIGH4 0x194
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#define QSERDES_V7_RX_DFE_EN_TIMER 0x1a0
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#define QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
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#define QSERDES_V7_RX_DCC_CTRL1 0x1a8
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#define QSERDES_V7_RX_VTH_CODE 0x1b0
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#define QSERDES_V7_RX_SIGDET_CAL_CTRL1 0x1e4
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#define QSERDES_V7_RX_SIGDET_CAL_TRIM 0x1f8
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#endif