Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Lattice ECP3 FPGA: Correct endianness

This code corrects endianness and avoids a sparse error.
Tested with Lattice ECP3-35 with Freescale i.MX6.
It also sends uevent in order to load it.

Signed-off-by: Jean-Michel Hautbois <jean-michel.hautbois@vodalys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Jean-Michel Hautbois and committed by
Greg Kroah-Hartman
ee531142 4dcc2ab3

+9 -7
+9 -7
drivers/misc/lattice-ecp3-config.c
··· 15 15 #include <linux/spi/spi.h> 16 16 #include <linux/platform_device.h> 17 17 #include <linux/delay.h> 18 + #include <asm/unaligned.h> 18 19 19 20 #define FIRMWARE_NAME "lattice-ecp3.bit" 20 21 ··· 92 91 /* Trying to speak with the FPGA via SPI... */ 93 92 txbuf[0] = FPGA_CMD_READ_ID; 94 93 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 95 - dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", *(u32 *)&rxbuf[4]); 96 - jedec_id = *(u32 *)&rxbuf[4]; 94 + jedec_id = get_unaligned_be32(&rxbuf[4]); 95 + dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); 97 96 98 97 for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) { 99 98 if (jedec_id == ecp3_dev[i].jedec_id) ··· 110 109 111 110 txbuf[0] = FPGA_CMD_READ_STATUS; 112 111 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 113 - dev_dbg(&spi->dev, "FPGA Status=%08x\n", *(u32 *)&rxbuf[4]); 112 + status = get_unaligned_be32(&rxbuf[4]); 113 + dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 114 114 115 115 buffer = kzalloc(fw->size + 8, GFP_KERNEL); 116 116 if (!buffer) { ··· 143 141 for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) { 144 142 txbuf[0] = FPGA_CMD_READ_STATUS; 145 143 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 146 - status = *(u32 *)&rxbuf[4]; 144 + status = get_unaligned_be32(&rxbuf[4]); 147 145 if (status == FPGA_STATUS_CLEARED) 148 146 break; 149 147 ··· 166 164 167 165 txbuf[0] = FPGA_CMD_READ_STATUS; 168 166 ret = spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len); 169 - dev_dbg(&spi->dev, "FPGA Status=%08x\n", *(u32 *)&rxbuf[4]); 170 - status = *(u32 *)&rxbuf[4]; 167 + status = get_unaligned_be32(&rxbuf[4]); 168 + dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); 171 169 172 170 /* Check result */ 173 171 if (status & FPGA_STATUS_DONE) ··· 198 196 spi_set_drvdata(spi, data); 199 197 200 198 init_completion(&data->fw_loaded); 201 - err = request_firmware_nowait(THIS_MODULE, FW_ACTION_NOHOTPLUG, 199 + err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, 202 200 FIRMWARE_NAME, &spi->dev, 203 201 GFP_KERNEL, spi, firmware_load); 204 202 if (err) {