dt-bindings: clock: qcom: document the Glymur Global Clock Controller

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add device tree bindings for global clock controller on Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by

Bjorn Andersson 7 months ago ee2d9670 2c7a7fe4

+699

2 changed files

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Documentation

devicetree

bindings

clock

qcom,glymur-gcc.yaml

include

dt-bindings

clock

qcom,glymur-gcc.h

+121

Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on Glymur SoC 8 + 9 + maintainers: 10 + - Taniya Das <taniya.das@oss.qualcomm.com> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and power 14 + domains on Glymur SoC. 15 + 16 + See also: include/dt-bindings/clock/qcom,glymur-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,glymur-gcc 21 + 22 + clocks: 23 + items: 24 + - description: Board XO source 25 + - description: Board XO_A source 26 + - description: Sleep clock source 27 + - description: USB 0 Phy DP0 GMUX clock source 28 + - description: USB 0 Phy DP1 GMUX clock source 29 + - description: USB 0 Phy PCIE PIPEGMUX clock source 30 + - description: USB 0 Phy PIPEGMUX clock source 31 + - description: USB 0 Phy SYS PCIE PIPEGMUX clock source 32 + - description: USB 1 Phy DP0 GMUX 2 clock source 33 + - description: USB 1 Phy DP1 GMUX 2 clock source 34 + - description: USB 1 Phy PCIE PIPEGMUX clock source 35 + - description: USB 1 Phy PIPEGMUX clock source 36 + - description: USB 1 Phy SYS PCIE PIPEGMUX clock source 37 + - description: USB 2 Phy DP0 GMUX 2 clock source 38 + - description: USB 2 Phy DP1 GMUX 2 clock source 39 + - description: USB 2 Phy PCIE PIPEGMUX clock source 40 + - description: USB 2 Phy PIPEGMUX clock source 41 + - description: USB 2 Phy SYS PCIE PIPEGMUX clock source 42 + - description: PCIe 3a pipe clock 43 + - description: PCIe 3b pipe clock 44 + - description: PCIe 4 pipe clock 45 + - description: PCIe 5 pipe clock 46 + - description: PCIe 6 pipe clock 47 + - description: QUSB4 0 PHY RX 0 clock source 48 + - description: QUSB4 0 PHY RX 1 clock source 49 + - description: QUSB4 1 PHY RX 0 clock source 50 + - description: QUSB4 1 PHY RX 1 clock source 51 + - description: QUSB4 2 PHY RX 0 clock source 52 + - description: QUSB4 2 PHY RX 1 clock source 53 + - description: UFS PHY RX Symbol 0 clock source 54 + - description: UFS PHY RX Symbol 1 clock source 55 + - description: UFS PHY TX Symbol 0 clock source 56 + - description: USB3 PHY 0 pipe clock source 57 + - description: USB3 PHY 1 pipe clock source 58 + - description: USB3 PHY 2 pipe clock source 59 + - description: USB3 UNI PHY pipe 0 clock source 60 + - description: USB3 UNI PHY pipe 1 clock source 61 + - description: USB4 PHY 0 pcie pipe clock source 62 + - description: USB4 PHY 0 Max pipe clock source 63 + - description: USB4 PHY 1 pcie pipe clock source 64 + - description: USB4 PHY 1 Max pipe clock source 65 + - description: USB4 PHY 2 pcie pipe clock source 66 + - description: USB4 PHY 2 Max pipe clock source 67 + 68 + required: 69 + - compatible 70 + - clocks 71 + - '#power-domain-cells' 72 + 73 + allOf: 74 + - $ref: qcom,gcc.yaml# 75 + 76 + unevaluatedProperties: false 77 + 78 + examples: 79 + - | 80 + #include <dt-bindings/clock/qcom,rpmh.h> 81 + clock-controller@100000 { 82 + compatible = "qcom,glymur-gcc"; 83 + reg = <0x100000 0x1f9000>; 84 + clocks = <&rpmhcc RPMH_CXO_CLK>, 85 + <&rpmhcc RPMH_CXO_CLK_A>, 86 + <&sleep_clk>, 87 + <&usb_0_phy_dp0_gmux>, 88 + <&usb_0_phy_dp1_gmux>, 89 + <&usb_0_phy_pcie_pipegmux>, 90 + <&usb_0_phy_pipegmux>, 91 + <&usb_0_phy_sys_pcie_pipegmux>, 92 + <&usb_1_phy_dp0_gmux_2>, 93 + <&usb_1_phy_dp1_gmux_2>, 94 + <&usb_1_phy_pcie_pipegmux>, 95 + <&usb_1_phy_pipegmux>, 96 + <&usb_1_phy_sys_pcie_pipegmux>, 97 + <&usb_2_phy_dp0_gmux 2>, 98 + <&usb_2_phy_dp1_gmux 2>, 99 + <&usb_2_phy_pcie_pipegmux>, 100 + <&usb_2_phy_pipegmux>, 101 + <&usb_2_phy_sys_pcie_pipegmux>, 102 + <&pcie_3a_pipe>, <&pcie_3b_pipe>, 103 + <&pcie_4_pipe>, <&pcie_5_pipe>, 104 + <&pcie_6_pipe>, 105 + <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>, 106 + <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>, 107 + <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>, 108 + <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>, 109 + <&ufs_phy_tx_symbol_0>, 110 + <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>, 111 + <&usb3_phy_2_pipe>, 112 + <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>, 113 + <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>, 114 + <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>, 115 + <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>; 116 + #clock-cells = <1>; 117 + #reset-cells = <1>; 118 + #power-domain-cells = <1>; 119 + }; 120 + 121 + ...

+578

include/dt-bindings/clock/qcom,glymur-gcc.h

··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_GLYMUR_H 8 + 9 + /* GCC clocks */ 10 + #define GCC_GPLL0 0 11 + #define GCC_GPLL0_OUT_EVEN 1 12 + #define GCC_GPLL1 2 13 + #define GCC_GPLL14 3 14 + #define GCC_GPLL14_OUT_EVEN 4 15 + #define GCC_GPLL4 5 16 + #define GCC_GPLL5 6 17 + #define GCC_GPLL7 7 18 + #define GCC_GPLL8 8 19 + #define GCC_GPLL9 9 20 + #define GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK 10 21 + #define GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK 11 22 + #define GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK 12 23 + #define GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK 13 24 + #define GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK 14 25 + #define GCC_AGGRE_UFS_PHY_AXI_CLK 15 26 + #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 16 27 + #define GCC_AGGRE_USB2_PRIM_AXI_CLK 17 28 + #define GCC_AGGRE_USB3_MP_AXI_CLK 18 29 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 19 30 + #define GCC_AGGRE_USB3_SEC_AXI_CLK 20 31 + #define GCC_AGGRE_USB3_TERT_AXI_CLK 21 32 + #define GCC_AGGRE_USB4_0_AXI_CLK 22 33 + #define GCC_AGGRE_USB4_1_AXI_CLK 23 34 + #define GCC_AGGRE_USB4_2_AXI_CLK 24 35 + #define GCC_AV1E_AHB_CLK 25 36 + #define GCC_AV1E_AXI_CLK 26 37 + #define GCC_AV1E_XO_CLK 27 38 + #define GCC_BOOT_ROM_AHB_CLK 28 39 + #define GCC_CAMERA_AHB_CLK 29 40 + #define GCC_CAMERA_HF_AXI_CLK 30 41 + #define GCC_CAMERA_SF_AXI_CLK 31 42 + #define GCC_CAMERA_XO_CLK 32 43 + #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 33 44 + #define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 34 45 + #define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 35 46 + #define GCC_CFG_NOC_USB3_MP_AXI_CLK 36 47 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 37 48 + #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 38 49 + #define GCC_CFG_NOC_USB3_TERT_AXI_CLK 39 50 + #define GCC_CFG_NOC_USB_ANOC_AHB_CLK 40 51 + #define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 41 52 + #define GCC_DISP_AHB_CLK 42 53 + #define GCC_DISP_HF_AXI_CLK 43 54 + #define GCC_EVA_AHB_CLK 44 55 + #define GCC_EVA_AXI0_CLK 45 56 + #define GCC_EVA_AXI0C_CLK 46 57 + #define GCC_EVA_XO_CLK 47 58 + #define GCC_GP1_CLK 48 59 + #define GCC_GP1_CLK_SRC 49 60 + #define GCC_GP2_CLK 50 61 + #define GCC_GP2_CLK_SRC 51 62 + #define GCC_GP3_CLK 52 63 + #define GCC_GP3_CLK_SRC 53 64 + #define GCC_GPU_CFG_AHB_CLK 54 65 + #define GCC_GPU_GEMNOC_GFX_CLK 55 66 + #define GCC_GPU_GPLL0_CLK_SRC 56 67 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 57 68 + #define GCC_PCIE_0_AUX_CLK 58 69 + #define GCC_PCIE_0_AUX_CLK_SRC 59 70 + #define GCC_PCIE_0_CFG_AHB_CLK 60 71 + #define GCC_PCIE_0_MSTR_AXI_CLK 61 72 + #define GCC_PCIE_0_PHY_RCHNG_CLK 62 73 + #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 63 74 + #define GCC_PCIE_0_PIPE_CLK 64 75 + #define GCC_PCIE_0_SLV_AXI_CLK 65 76 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 66 77 + #define GCC_PCIE_1_AUX_CLK 67 78 + #define GCC_PCIE_1_AUX_CLK_SRC 68 79 + #define GCC_PCIE_1_CFG_AHB_CLK 69 80 + #define GCC_PCIE_1_MSTR_AXI_CLK 70 81 + #define GCC_PCIE_1_PHY_RCHNG_CLK 71 82 + #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72 83 + #define GCC_PCIE_1_PIPE_CLK 73 84 + #define GCC_PCIE_1_SLV_AXI_CLK 74 85 + #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75 86 + #define GCC_PCIE_2_AUX_CLK 76 87 + #define GCC_PCIE_2_AUX_CLK_SRC 77 88 + #define GCC_PCIE_2_CFG_AHB_CLK 78 89 + #define GCC_PCIE_2_MSTR_AXI_CLK 79 90 + #define GCC_PCIE_2_PHY_RCHNG_CLK 80 91 + #define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 81 92 + #define GCC_PCIE_2_PIPE_CLK 82 93 + #define GCC_PCIE_2_SLV_AXI_CLK 83 94 + #define GCC_PCIE_2_SLV_Q2A_AXI_CLK 84 95 + #define GCC_PCIE_3A_AUX_CLK 85 96 + #define GCC_PCIE_3A_AUX_CLK_SRC 86 97 + #define GCC_PCIE_3A_CFG_AHB_CLK 87 98 + #define GCC_PCIE_3A_MSTR_AXI_CLK 88 99 + #define GCC_PCIE_3A_PHY_RCHNG_CLK 89 100 + #define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 90 101 + #define GCC_PCIE_3A_PIPE_CLK 91 102 + #define GCC_PCIE_3A_PIPE_CLK_SRC 92 103 + #define GCC_PCIE_3A_SLV_AXI_CLK 93 104 + #define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 94 105 + #define GCC_PCIE_3B_AUX_CLK 95 106 + #define GCC_PCIE_3B_AUX_CLK_SRC 96 107 + #define GCC_PCIE_3B_CFG_AHB_CLK 97 108 + #define GCC_PCIE_3B_MSTR_AXI_CLK 98 109 + #define GCC_PCIE_3B_PHY_RCHNG_CLK 99 110 + #define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 100 111 + #define GCC_PCIE_3B_PIPE_CLK 101 112 + #define GCC_PCIE_3B_PIPE_CLK_SRC 102 113 + #define GCC_PCIE_3B_PIPE_DIV2_CLK 103 114 + #define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 104 115 + #define GCC_PCIE_3B_SLV_AXI_CLK 105 116 + #define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 106 117 + #define GCC_PCIE_4_AUX_CLK 107 118 + #define GCC_PCIE_4_AUX_CLK_SRC 108 119 + #define GCC_PCIE_4_CFG_AHB_CLK 109 120 + #define GCC_PCIE_4_MSTR_AXI_CLK 110 121 + #define GCC_PCIE_4_PHY_RCHNG_CLK 111 122 + #define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 112 123 + #define GCC_PCIE_4_PIPE_CLK 113 124 + #define GCC_PCIE_4_PIPE_CLK_SRC 114 125 + #define GCC_PCIE_4_PIPE_DIV2_CLK 115 126 + #define GCC_PCIE_4_PIPE_DIV_CLK_SRC 116 127 + #define GCC_PCIE_4_SLV_AXI_CLK 117 128 + #define GCC_PCIE_4_SLV_Q2A_AXI_CLK 118 129 + #define GCC_PCIE_5_AUX_CLK 119 130 + #define GCC_PCIE_5_AUX_CLK_SRC 120 131 + #define GCC_PCIE_5_CFG_AHB_CLK 121 132 + #define GCC_PCIE_5_MSTR_AXI_CLK 122 133 + #define GCC_PCIE_5_PHY_RCHNG_CLK 123 134 + #define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 124 135 + #define GCC_PCIE_5_PIPE_CLK 125 136 + #define GCC_PCIE_5_PIPE_CLK_SRC 126 137 + #define GCC_PCIE_5_PIPE_DIV2_CLK 127 138 + #define GCC_PCIE_5_PIPE_DIV_CLK_SRC 128 139 + #define GCC_PCIE_5_SLV_AXI_CLK 129 140 + #define GCC_PCIE_5_SLV_Q2A_AXI_CLK 130 141 + #define GCC_PCIE_6_AUX_CLK 131 142 + #define GCC_PCIE_6_AUX_CLK_SRC 132 143 + #define GCC_PCIE_6_CFG_AHB_CLK 133 144 + #define GCC_PCIE_6_MSTR_AXI_CLK 134 145 + #define GCC_PCIE_6_PHY_RCHNG_CLK 135 146 + #define GCC_PCIE_6_PHY_RCHNG_CLK_SRC 136 147 + #define GCC_PCIE_6_PIPE_CLK 137 148 + #define GCC_PCIE_6_PIPE_CLK_SRC 138 149 + #define GCC_PCIE_6_PIPE_DIV2_CLK 139 150 + #define GCC_PCIE_6_PIPE_DIV_CLK_SRC 140 151 + #define GCC_PCIE_6_SLV_AXI_CLK 141 152 + #define GCC_PCIE_6_SLV_Q2A_AXI_CLK 142 153 + #define GCC_PCIE_NOC_PWRCTL_CLK 143 154 + #define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 144 155 + #define GCC_PCIE_NOC_SF_CENTER_CLK 145 156 + #define GCC_PCIE_NOC_SLAVE_SF_EAST_CLK 146 157 + #define GCC_PCIE_NOC_SLAVE_SF_WEST_CLK 147 158 + #define GCC_PCIE_NOC_TSCTR_CLK 148 159 + #define GCC_PCIE_PHY_3A_AUX_CLK 149 160 + #define GCC_PCIE_PHY_3A_AUX_CLK_SRC 150 161 + #define GCC_PCIE_PHY_3B_AUX_CLK 151 162 + #define GCC_PCIE_PHY_3B_AUX_CLK_SRC 152 163 + #define GCC_PCIE_PHY_4_AUX_CLK 153 164 + #define GCC_PCIE_PHY_4_AUX_CLK_SRC 154 165 + #define GCC_PCIE_PHY_5_AUX_CLK 155 166 + #define GCC_PCIE_PHY_5_AUX_CLK_SRC 156 167 + #define GCC_PCIE_PHY_6_AUX_CLK 157 168 + #define GCC_PCIE_PHY_6_AUX_CLK_SRC 158 169 + #define GCC_PCIE_RSCC_CFG_AHB_CLK 159 170 + #define GCC_PCIE_RSCC_XO_CLK 160 171 + #define GCC_PDM2_CLK 161 172 + #define GCC_PDM2_CLK_SRC 162 173 + #define GCC_PDM_AHB_CLK 163 174 + #define GCC_PDM_XO4_CLK 164 175 + #define GCC_QMIP_AV1E_AHB_CLK 165 176 + #define GCC_QMIP_CAMERA_CMD_AHB_CLK 166 177 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 167 178 + #define GCC_QMIP_CAMERA_RT_AHB_CLK 168 179 + #define GCC_QMIP_GPU_AHB_CLK 169 180 + #define GCC_QMIP_PCIE_3A_AHB_CLK 170 181 + #define GCC_QMIP_PCIE_3B_AHB_CLK 171 182 + #define GCC_QMIP_PCIE_4_AHB_CLK 172 183 + #define GCC_QMIP_PCIE_5_AHB_CLK 173 184 + #define GCC_QMIP_PCIE_6_AHB_CLK 174 185 + #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 175 186 + #define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 187 + #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 177 188 + #define GCC_QMIP_VIDEO_VCODEC1_AHB_CLK 178 189 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 179 190 + #define GCC_QUPV3_OOB_CORE_2X_CLK 180 191 + #define GCC_QUPV3_OOB_CORE_CLK 181 192 + #define GCC_QUPV3_OOB_M_AHB_CLK 182 193 + #define GCC_QUPV3_OOB_QSPI_S0_CLK 183 194 + #define GCC_QUPV3_OOB_QSPI_S0_CLK_SRC 184 195 + #define GCC_QUPV3_OOB_QSPI_S1_CLK 185 196 + #define GCC_QUPV3_OOB_QSPI_S1_CLK_SRC 186 197 + #define GCC_QUPV3_OOB_S0_CLK 187 198 + #define GCC_QUPV3_OOB_S0_CLK_SRC 188 199 + #define GCC_QUPV3_OOB_S1_CLK 189 200 + #define GCC_QUPV3_OOB_S1_CLK_SRC 190 201 + #define GCC_QUPV3_OOB_S_AHB_CLK 191 202 + #define GCC_QUPV3_OOB_TCXO_CLK 192 203 + #define GCC_QUPV3_WRAP0_CORE_2X_CLK 193 204 + #define GCC_QUPV3_WRAP0_CORE_CLK 194 205 + #define GCC_QUPV3_WRAP0_QSPI_S2_CLK 195 206 + #define GCC_QUPV3_WRAP0_QSPI_S2_CLK_SRC 196 207 + #define GCC_QUPV3_WRAP0_QSPI_S3_CLK 197 208 + #define GCC_QUPV3_WRAP0_QSPI_S3_CLK_SRC 198 209 + #define GCC_QUPV3_WRAP0_QSPI_S6_CLK 199 210 + #define GCC_QUPV3_WRAP0_QSPI_S6_CLK_SRC 200 211 + #define GCC_QUPV3_WRAP0_S0_CLK 201 212 + #define GCC_QUPV3_WRAP0_S0_CLK_SRC 202 213 + #define GCC_QUPV3_WRAP0_S1_CLK 203 214 + #define GCC_QUPV3_WRAP0_S1_CLK_SRC 204 215 + #define GCC_QUPV3_WRAP0_S2_CLK 205 216 + #define GCC_QUPV3_WRAP0_S2_CLK_SRC 206 217 + #define GCC_QUPV3_WRAP0_S3_CLK 207 218 + #define GCC_QUPV3_WRAP0_S3_CLK_SRC 208 219 + #define GCC_QUPV3_WRAP0_S4_CLK 209 220 + #define GCC_QUPV3_WRAP0_S4_CLK_SRC 210 221 + #define GCC_QUPV3_WRAP0_S5_CLK 211 222 + #define GCC_QUPV3_WRAP0_S5_CLK_SRC 212 223 + #define GCC_QUPV3_WRAP0_S6_CLK 213 224 + #define GCC_QUPV3_WRAP0_S6_CLK_SRC 214 225 + #define GCC_QUPV3_WRAP0_S7_CLK 215 226 + #define GCC_QUPV3_WRAP0_S7_CLK_SRC 216 227 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 217 228 + #define GCC_QUPV3_WRAP1_CORE_CLK 218 229 + #define GCC_QUPV3_WRAP1_QSPI_S2_CLK 219 230 + #define GCC_QUPV3_WRAP1_QSPI_S2_CLK_SRC 220 231 + #define GCC_QUPV3_WRAP1_QSPI_S3_CLK 221 232 + #define GCC_QUPV3_WRAP1_QSPI_S3_CLK_SRC 222 233 + #define GCC_QUPV3_WRAP1_QSPI_S6_CLK 223 234 + #define GCC_QUPV3_WRAP1_QSPI_S6_CLK_SRC 224 235 + #define GCC_QUPV3_WRAP1_S0_CLK 225 236 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 226 237 + #define GCC_QUPV3_WRAP1_S1_CLK 227 238 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 228 239 + #define GCC_QUPV3_WRAP1_S2_CLK 229 240 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 230 241 + #define GCC_QUPV3_WRAP1_S3_CLK 231 242 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 232 243 + #define GCC_QUPV3_WRAP1_S4_CLK 233 244 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 234 245 + #define GCC_QUPV3_WRAP1_S5_CLK 235 246 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 236 247 + #define GCC_QUPV3_WRAP1_S6_CLK 237 248 + #define GCC_QUPV3_WRAP1_S6_CLK_SRC 238 249 + #define GCC_QUPV3_WRAP1_S7_CLK 239 250 + #define GCC_QUPV3_WRAP1_S7_CLK_SRC 240 251 + #define GCC_QUPV3_WRAP2_CORE_2X_CLK 241 252 + #define GCC_QUPV3_WRAP2_CORE_CLK 242 253 + #define GCC_QUPV3_WRAP2_QSPI_S2_CLK 243 254 + #define GCC_QUPV3_WRAP2_QSPI_S2_CLK_SRC 244 255 + #define GCC_QUPV3_WRAP2_QSPI_S3_CLK 245 256 + #define GCC_QUPV3_WRAP2_QSPI_S3_CLK_SRC 246 257 + #define GCC_QUPV3_WRAP2_QSPI_S6_CLK 247 258 + #define GCC_QUPV3_WRAP2_QSPI_S6_CLK_SRC 248 259 + #define GCC_QUPV3_WRAP2_S0_CLK 249 260 + #define GCC_QUPV3_WRAP2_S0_CLK_SRC 250 261 + #define GCC_QUPV3_WRAP2_S1_CLK 251 262 + #define GCC_QUPV3_WRAP2_S1_CLK_SRC 252 263 + #define GCC_QUPV3_WRAP2_S2_CLK 253 264 + #define GCC_QUPV3_WRAP2_S2_CLK_SRC 254 265 + #define GCC_QUPV3_WRAP2_S3_CLK 255 266 + #define GCC_QUPV3_WRAP2_S3_CLK_SRC 256 267 + #define GCC_QUPV3_WRAP2_S4_CLK 257 268 + #define GCC_QUPV3_WRAP2_S4_CLK_SRC 258 269 + #define GCC_QUPV3_WRAP2_S5_CLK 259 270 + #define GCC_QUPV3_WRAP2_S5_CLK_SRC 260 271 + #define GCC_QUPV3_WRAP2_S6_CLK 261 272 + #define GCC_QUPV3_WRAP2_S6_CLK_SRC 262 273 + #define GCC_QUPV3_WRAP2_S7_CLK 263 274 + #define GCC_QUPV3_WRAP2_S7_CLK_SRC 264 275 + #define GCC_QUPV3_WRAP_0_M_AHB_CLK 265 276 + #define GCC_QUPV3_WRAP_0_S_AHB_CLK 266 277 + #define GCC_QUPV3_WRAP_1_M_AHB_CLK 267 278 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 268 279 + #define GCC_QUPV3_WRAP_2_M_AHB_CLK 269 280 + #define GCC_QUPV3_WRAP_2_S_AHB_CLK 270 281 + #define GCC_SDCC2_AHB_CLK 271 282 + #define GCC_SDCC2_APPS_CLK 272 283 + #define GCC_SDCC2_APPS_CLK_SRC 273 284 + #define GCC_SDCC4_AHB_CLK 274 285 + #define GCC_SDCC4_APPS_CLK 275 286 + #define GCC_SDCC4_APPS_CLK_SRC 276 287 + #define GCC_UFS_PHY_AHB_CLK 277 288 + #define GCC_UFS_PHY_AXI_CLK 278 289 + #define GCC_UFS_PHY_AXI_CLK_SRC 279 290 + #define GCC_UFS_PHY_AXI_HW_CTL_CLK 280 291 + #define GCC_UFS_PHY_ICE_CORE_CLK 281 292 + #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 282 293 + #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 283 294 + #define GCC_UFS_PHY_PHY_AUX_CLK 284 295 + #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 285 296 + #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 286 297 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 287 298 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 288 299 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 289 300 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 290 301 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 291 302 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 292 303 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK 293 304 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 294 305 + #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 295 306 + #define GCC_USB20_MASTER_CLK 296 307 + #define GCC_USB20_MASTER_CLK_SRC 297 308 + #define GCC_USB20_MOCK_UTMI_CLK 298 309 + #define GCC_USB20_MOCK_UTMI_CLK_SRC 299 310 + #define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 300 311 + #define GCC_USB20_SLEEP_CLK 301 312 + #define GCC_USB30_MP_MASTER_CLK 302 313 + #define GCC_USB30_MP_MASTER_CLK_SRC 303 314 + #define GCC_USB30_MP_MOCK_UTMI_CLK 304 315 + #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 305 316 + #define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 306 317 + #define GCC_USB30_MP_SLEEP_CLK 307 318 + #define GCC_USB30_PRIM_MASTER_CLK 308 319 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 309 320 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 310 321 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 311 322 + #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 312 323 + #define GCC_USB30_PRIM_SLEEP_CLK 313 324 + #define GCC_USB30_SEC_MASTER_CLK 314 325 + #define GCC_USB30_SEC_MASTER_CLK_SRC 315 326 + #define GCC_USB30_SEC_MOCK_UTMI_CLK 316 327 + #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 317 328 + #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 318 329 + #define GCC_USB30_SEC_SLEEP_CLK 319 330 + #define GCC_USB30_TERT_MASTER_CLK 320 331 + #define GCC_USB30_TERT_MASTER_CLK_SRC 321 332 + #define GCC_USB30_TERT_MOCK_UTMI_CLK 322 333 + #define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 323 334 + #define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 324 335 + #define GCC_USB30_TERT_SLEEP_CLK 325 336 + #define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 326 337 + #define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 327 338 + #define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 328 339 + #define GCC_USB3_MP_PHY_AUX_CLK 329 340 + #define GCC_USB3_MP_PHY_AUX_CLK_SRC 330 341 + #define GCC_USB3_MP_PHY_COM_AUX_CLK 331 342 + #define GCC_USB3_MP_PHY_PIPE_0_CLK 332 343 + #define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 333 344 + #define GCC_USB3_MP_PHY_PIPE_1_CLK 334 345 + #define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 335 346 + #define GCC_USB3_PRIM_PHY_AUX_CLK 336 347 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 337 348 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 338 349 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 339 350 + #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 340 351 + #define GCC_USB3_SEC_PHY_AUX_CLK 341 352 + #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 342 353 + #define GCC_USB3_SEC_PHY_COM_AUX_CLK 343 354 + #define GCC_USB3_SEC_PHY_PIPE_CLK 344 355 + #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 345 356 + #define GCC_USB3_TERT_PHY_AUX_CLK 346 357 + #define GCC_USB3_TERT_PHY_AUX_CLK_SRC 347 358 + #define GCC_USB3_TERT_PHY_COM_AUX_CLK 348 359 + #define GCC_USB3_TERT_PHY_PIPE_CLK 349 360 + #define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 350 361 + #define GCC_USB4_0_CFG_AHB_CLK 351 362 + #define GCC_USB4_0_DP0_CLK 352 363 + #define GCC_USB4_0_DP1_CLK 353 364 + #define GCC_USB4_0_MASTER_CLK 354 365 + #define GCC_USB4_0_MASTER_CLK_SRC 355 366 + #define GCC_USB4_0_PHY_DP0_CLK_SRC 356 367 + #define GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC 357 368 + #define GCC_USB4_0_PHY_DP1_CLK_SRC 358 369 + #define GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC 359 370 + #define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 360 371 + #define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361 372 + #define GCC_USB4_0_PHY_PCIE_PIPE_CLK 362 373 + #define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 363 374 + #define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 364 375 + #define GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC 365 376 + #define GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC 366 377 + #define GCC_USB4_0_PHY_RX0_CLK 367 378 + #define GCC_USB4_0_PHY_RX0_CLK_SRC 368 379 + #define GCC_USB4_0_PHY_RX1_CLK 369 380 + #define GCC_USB4_0_PHY_RX1_CLK_SRC 370 381 + #define GCC_USB4_0_PHY_SYS_CLK_SRC 371 382 + #define GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC 372 383 + #define GCC_USB4_0_PHY_USB_PIPE_CLK 373 384 + #define GCC_USB4_0_SB_IF_CLK 374 385 + #define GCC_USB4_0_SB_IF_CLK_SRC 375 386 + #define GCC_USB4_0_SYS_CLK 376 387 + #define GCC_USB4_0_TMU_CLK 377 388 + #define GCC_USB4_0_TMU_CLK_SRC 378 389 + #define GCC_USB4_0_UC_HRR_CLK 379 390 + #define GCC_USB4_1_CFG_AHB_CLK 380 391 + #define GCC_USB4_1_DP0_CLK 381 392 + #define GCC_USB4_1_DP1_CLK 382 393 + #define GCC_USB4_1_MASTER_CLK 383 394 + #define GCC_USB4_1_MASTER_CLK_SRC 384 395 + #define GCC_USB4_1_PHY_DP0_CLK_SRC 385 396 + #define GCC_USB4_1_PHY_DP0_GMUX_2_CLK_SRC 386 397 + #define GCC_USB4_1_PHY_DP1_CLK_SRC 387 398 + #define GCC_USB4_1_PHY_DP1_GMUX_2_CLK_SRC 388 399 + #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 389 400 + #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 390 401 + #define GCC_USB4_1_PHY_PCIE_PIPE_CLK 391 402 + #define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 392 403 + #define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 393 404 + #define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 394 405 + #define GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC 395 406 + #define GCC_USB4_1_PHY_PLL_PIPE_CLK_SRC 396 407 + #define GCC_USB4_1_PHY_RX0_CLK 397 408 + #define GCC_USB4_1_PHY_RX0_CLK_SRC 398 409 + #define GCC_USB4_1_PHY_RX1_CLK 399 410 + #define GCC_USB4_1_PHY_RX1_CLK_SRC 400 411 + #define GCC_USB4_1_PHY_SYS_CLK_SRC 401 412 + #define GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC 402 413 + #define GCC_USB4_1_PHY_USB_PIPE_CLK 403 414 + #define GCC_USB4_1_SB_IF_CLK 404 415 + #define GCC_USB4_1_SB_IF_CLK_SRC 405 416 + #define GCC_USB4_1_SYS_CLK 406 417 + #define GCC_USB4_1_TMU_CLK 407 418 + #define GCC_USB4_1_TMU_CLK_SRC 408 419 + #define GCC_USB4_1_UC_HRR_CLK 409 420 + #define GCC_USB4_2_CFG_AHB_CLK 410 421 + #define GCC_USB4_2_DP0_CLK 411 422 + #define GCC_USB4_2_DP1_CLK 412 423 + #define GCC_USB4_2_MASTER_CLK 413 424 + #define GCC_USB4_2_MASTER_CLK_SRC 414 425 + #define GCC_USB4_2_PHY_DP0_CLK_SRC 415 426 + #define GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC 416 427 + #define GCC_USB4_2_PHY_DP1_CLK_SRC 417 428 + #define GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC 418 429 + #define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 419 430 + #define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 420 431 + #define GCC_USB4_2_PHY_PCIE_PIPE_CLK 421 432 + #define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 422 433 + #define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 423 434 + #define GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC 424 435 + #define GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC 425 436 + #define GCC_USB4_2_PHY_RX0_CLK 426 437 + #define GCC_USB4_2_PHY_RX0_CLK_SRC 427 438 + #define GCC_USB4_2_PHY_RX1_CLK 428 439 + #define GCC_USB4_2_PHY_RX1_CLK_SRC 429 440 + #define GCC_USB4_2_PHY_SYS_CLK_SRC 430 441 + #define GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC 431 442 + #define GCC_USB4_2_PHY_USB_PIPE_CLK 432 443 + #define GCC_USB4_2_SB_IF_CLK 433 444 + #define GCC_USB4_2_SB_IF_CLK_SRC 434 445 + #define GCC_USB4_2_SYS_CLK 435 446 + #define GCC_USB4_2_TMU_CLK 436 447 + #define GCC_USB4_2_TMU_CLK_SRC 437 448 + #define GCC_USB4_2_UC_HRR_CLK 438 449 + #define GCC_VIDEO_AHB_CLK 439 450 + #define GCC_VIDEO_AXI0_CLK 440 451 + #define GCC_VIDEO_AXI0C_CLK 441 452 + #define GCC_VIDEO_AXI1_CLK 442 453 + #define GCC_VIDEO_XO_CLK 443 454 + 455 + /* GCC power domains */ 456 + #define GCC_PCIE_0_TUNNEL_GDSC 0 457 + #define GCC_PCIE_1_TUNNEL_GDSC 1 458 + #define GCC_PCIE_2_TUNNEL_GDSC 2 459 + #define GCC_PCIE_3A_GDSC 3 460 + #define GCC_PCIE_3A_PHY_GDSC 4 461 + #define GCC_PCIE_3B_GDSC 5 462 + #define GCC_PCIE_3B_PHY_GDSC 6 463 + #define GCC_PCIE_4_GDSC 7 464 + #define GCC_PCIE_4_PHY_GDSC 8 465 + #define GCC_PCIE_5_GDSC 9 466 + #define GCC_PCIE_5_PHY_GDSC 10 467 + #define GCC_PCIE_6_GDSC 11 468 + #define GCC_PCIE_6_PHY_GDSC 12 469 + #define GCC_UFS_PHY_GDSC 13 470 + #define GCC_USB20_PRIM_GDSC 14 471 + #define GCC_USB30_MP_GDSC 15 472 + #define GCC_USB30_PRIM_GDSC 16 473 + #define GCC_USB30_SEC_GDSC 17 474 + #define GCC_USB30_TERT_GDSC 18 475 + #define GCC_USB3_MP_SS0_PHY_GDSC 19 476 + #define GCC_USB3_MP_SS1_PHY_GDSC 20 477 + #define GCC_USB4_0_GDSC 21 478 + #define GCC_USB4_1_GDSC 22 479 + #define GCC_USB4_2_GDSC 23 480 + #define GCC_USB_0_PHY_GDSC 24 481 + #define GCC_USB_1_PHY_GDSC 25 482 + #define GCC_USB_2_PHY_GDSC 26 483 + 484 + /* GCC resets */ 485 + #define GCC_AV1E_BCR 0 486 + #define GCC_CAMERA_BCR 1 487 + #define GCC_DISPLAY_BCR 2 488 + #define GCC_EVA_BCR 3 489 + #define GCC_GPU_BCR 4 490 + #define GCC_PCIE_0_LINK_DOWN_BCR 5 491 + #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 492 + #define GCC_PCIE_0_PHY_BCR 7 493 + #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 494 + #define GCC_PCIE_0_TUNNEL_BCR 9 495 + #define GCC_PCIE_1_LINK_DOWN_BCR 10 496 + #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 497 + #define GCC_PCIE_1_PHY_BCR 12 498 + #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 499 + #define GCC_PCIE_1_TUNNEL_BCR 14 500 + #define GCC_PCIE_2_LINK_DOWN_BCR 15 501 + #define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16 502 + #define GCC_PCIE_2_PHY_BCR 17 503 + #define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18 504 + #define GCC_PCIE_2_TUNNEL_BCR 19 505 + #define GCC_PCIE_3A_BCR 20 506 + #define GCC_PCIE_3A_LINK_DOWN_BCR 21 507 + #define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 22 508 + #define GCC_PCIE_3A_PHY_BCR 23 509 + #define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 24 510 + #define GCC_PCIE_3B_BCR 25 511 + #define GCC_PCIE_3B_LINK_DOWN_BCR 26 512 + #define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 27 513 + #define GCC_PCIE_3B_PHY_BCR 28 514 + #define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 29 515 + #define GCC_PCIE_4_BCR 30 516 + #define GCC_PCIE_4_LINK_DOWN_BCR 31 517 + #define GCC_PCIE_4_NOCSR_COM_PHY_BCR 32 518 + #define GCC_PCIE_4_PHY_BCR 33 519 + #define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 34 520 + #define GCC_PCIE_5_BCR 35 521 + #define GCC_PCIE_5_LINK_DOWN_BCR 36 522 + #define GCC_PCIE_5_NOCSR_COM_PHY_BCR 37 523 + #define GCC_PCIE_5_PHY_BCR 38 524 + #define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 39 525 + #define GCC_PCIE_6_BCR 40 526 + #define GCC_PCIE_6_LINK_DOWN_BCR 41 527 + #define GCC_PCIE_6_NOCSR_COM_PHY_BCR 42 528 + #define GCC_PCIE_6_PHY_BCR 43 529 + #define GCC_PCIE_6_PHY_NOCSR_COM_PHY_BCR 44 530 + #define GCC_PCIE_NOC_BCR 45 531 + #define GCC_PCIE_PHY_BCR 46 532 + #define GCC_PCIE_PHY_CFG_AHB_BCR 47 533 + #define GCC_PCIE_PHY_COM_BCR 48 534 + #define GCC_PCIE_RSCC_BCR 49 535 + #define GCC_PDM_BCR 50 536 + #define GCC_QUPV3_WRAPPER_0_BCR 51 537 + #define GCC_QUPV3_WRAPPER_1_BCR 52 538 + #define GCC_QUPV3_WRAPPER_2_BCR 53 539 + #define GCC_QUPV3_WRAPPER_OOB_BCR 54 540 + #define GCC_QUSB2PHY_HS0_MP_BCR 55 541 + #define GCC_QUSB2PHY_HS1_MP_BCR 56 542 + #define GCC_QUSB2PHY_PRIM_BCR 57 543 + #define GCC_QUSB2PHY_SEC_BCR 58 544 + #define GCC_QUSB2PHY_TERT_BCR 59 545 + #define GCC_QUSB2PHY_USB20_HS_BCR 60 546 + #define GCC_SDCC2_BCR 61 547 + #define GCC_SDCC4_BCR 62 548 + #define GCC_TCSR_PCIE_BCR 63 549 + #define GCC_UFS_PHY_BCR 64 550 + #define GCC_USB20_PRIM_BCR 65 551 + #define GCC_USB30_MP_BCR 66 552 + #define GCC_USB30_PRIM_BCR 67 553 + #define GCC_USB30_SEC_BCR 68 554 + #define GCC_USB30_TERT_BCR 69 555 + #define GCC_USB3_MP_SS0_PHY_BCR 70 556 + #define GCC_USB3_MP_SS1_PHY_BCR 71 557 + #define GCC_USB3_PHY_PRIM_BCR 72 558 + #define GCC_USB3_PHY_SEC_BCR 73 559 + #define GCC_USB3_PHY_TERT_BCR 74 560 + #define GCC_USB3_UNIPHY_MP0_BCR 75 561 + #define GCC_USB3_UNIPHY_MP1_BCR 76 562 + #define GCC_USB3PHY_PHY_PRIM_BCR 77 563 + #define GCC_USB3PHY_PHY_SEC_BCR 78 564 + #define GCC_USB3PHY_PHY_TERT_BCR 79 565 + #define GCC_USB3UNIPHY_PHY_MP0_BCR 80 566 + #define GCC_USB3UNIPHY_PHY_MP1_BCR 81 567 + #define GCC_USB4_0_BCR 82 568 + #define GCC_USB4_0_DP0_PHY_PRIM_BCR 83 569 + #define GCC_USB4_1_BCR 84 570 + #define GCC_USB4_2_BCR 85 571 + #define GCC_USB_0_PHY_BCR 86 572 + #define GCC_USB_1_PHY_BCR 87 573 + #define GCC_USB_2_PHY_BCR 88 574 + #define GCC_VIDEO_AXI0_CLK_ARES 89 575 + #define GCC_VIDEO_AXI1_CLK_ARES 90 576 + #define GCC_VIDEO_BCR 91 577 + 578 + #endif